diff --git a/.gitignore b/.gitignore index fa7bd55..7c8c7ac 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,5 @@ **/*_task/run001 **/*_task/latest **/*_task/skywater +**/*_Verilog/SRC_Skeleton +**/*_Verilog/SRCBackup diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/InstancesMap.txt b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/InstancesMap.txt new file mode 100644 index 0000000..b431eb5 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/InstancesMap.txt @@ -0,0 +1 @@ +{"grid_clb": ["grid_clb_1__1_", "grid_clb_1__2_", "grid_clb_2__1_", "grid_clb_2__2_"], "grid_io_top": ["grid_io_top_1__3_", "grid_io_top_2__3_"], "grid_io_right": ["grid_io_right_3__1_", "grid_io_right_3__2_"], "grid_io_bottom": ["grid_io_bottom_1__0_", "grid_io_bottom_2__0_"], "grid_io_left": ["grid_io_left_0__1_", "grid_io_left_0__2_"], "sb_0__0_": ["sb_0__0_"], "sb_0__1_": ["sb_0__1_"], "sb_0__2_": ["sb_0__2_"], "sb_1__0_": ["sb_1__0_"], "sb_1__1_": ["sb_1__1_"], "sb_1__2_": ["sb_1__2_"], "sb_2__0_": ["sb_2__0_"], "sb_2__1_": ["sb_2__1_"], "sb_2__2_": ["sb_2__2_"], "cbx_1__0_": ["cbx_1__0_", "cbx_2__0_"], "cbx_1__1_": ["cbx_1__1_", "cbx_2__1_"], "cbx_1__2_": ["cbx_1__2_", "cbx_2__2_"], "cby_0__1_": ["cby_0__1_", "cby_0__2_"], "cby_1__1_": ["cby_1__1_", "cby_1__2_"], "cby_2__1_": ["cby_2__1_", "cby_2__2_"], "direct_interc": ["direct_interc_0_", "direct_interc_1_", "direct_interc_2_", "direct_interc_3_", "direct_interc_4_", "direct_interc_5_"]} \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v index 523cc86..d6db793 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v @@ -18,9 +18,9 @@ `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrbp/sky130_fd_sc_hd__dfxbp_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/std_cell_extract.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v" // `include "./SRC/sub_module/inv_buf_passgate.v" `include "./SRC/sub_module/arch_encoder.v" @@ -39,10 +39,10 @@ `include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v" `include "./SRC/lb/logical_tile_clb_mode_default__fle.v" `include "./SRC/lb/logical_tile_clb_mode_clb_.v" -`include "./SRC/lb/grid_io_top.v" -`include "./SRC/lb/grid_io_right.v" -`include "./SRC/lb/grid_io_bottom.v" -`include "./SRC/lb/grid_io_left.v" +`include "./SRC/lb/grid_io_top_top.v" +`include "./SRC/lb/grid_io_right_right.v" +`include "./SRC/lb/grid_io_bottom_bottom.v" +`include "./SRC/lb/grid_io_left_left.v" `include "./SRC/lb/grid_clb.v" // @@ -60,6 +60,7 @@ `include "./SRC/routing/cbx_1__2_.v" `include "./SRC/routing/cby_0__1_.v" `include "./SRC/routing/cby_1__1_.v" +`include "./SRC/routing/cby_2__1_.v" // `include "./SRC/fpga_top.v" diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v index e5e1c6b..49d1358 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v @@ -1,1347 +1,1504 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module fpga_core(prog_clk, - Test_en, - clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, - ccff_head, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] Test_en; -// -input [0:0] clk; -// -output [0:7] gfpga_pad_GPIO_A; -// -output [0:7] gfpga_pad_GPIO_IE; -// -output [0:7] gfpga_pad_GPIO_OE; -// -inout [0:7] gfpga_pad_GPIO_Y; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; - -// -// -// -// +module fpga_core +( + input [0:0] prog_clk, + input [0:0] Test_en, + input [0:0] clk, + input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN, + output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT, + output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR, + input [0:0] ccff_head, + output [0:0] ccff_tail, + input sc_head, + output sc_tail +); + + wire [0:0] cbx_1__0__0_bottom_grid_pin_0_; + wire [0:0] cbx_1__0__0_bottom_grid_pin_10_; + wire [0:0] cbx_1__0__0_bottom_grid_pin_2_; + wire [0:0] cbx_1__0__0_bottom_grid_pin_4_; + wire [0:0] cbx_1__0__0_bottom_grid_pin_6_; + wire [0:0] cbx_1__0__0_bottom_grid_pin_8_; + wire [0:0] cbx_1__0__0_ccff_tail; + wire [0:19] cbx_1__0__0_chanx_left_out; + wire [0:19] cbx_1__0__0_chanx_right_out; + wire [0:0] cbx_1__0__1_bottom_grid_pin_0_; + wire [0:0] cbx_1__0__1_bottom_grid_pin_10_; + wire [0:0] cbx_1__0__1_bottom_grid_pin_2_; + wire [0:0] cbx_1__0__1_bottom_grid_pin_4_; + wire [0:0] cbx_1__0__1_bottom_grid_pin_6_; + wire [0:0] cbx_1__0__1_bottom_grid_pin_8_; + wire [0:0] cbx_1__0__1_ccff_tail; + wire [0:19] cbx_1__0__1_chanx_left_out; + wire [0:19] cbx_1__0__1_chanx_right_out; + wire [0:0] cbx_1__1__0_bottom_grid_pin_0_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_10_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_11_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_12_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_13_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_14_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_15_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_1_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_2_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_3_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_4_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_5_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_6_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_7_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_8_; + wire [0:0] cbx_1__1__0_bottom_grid_pin_9_; + wire [0:0] cbx_1__1__0_ccff_tail; + wire [0:19] cbx_1__1__0_chanx_left_out; + wire [0:19] cbx_1__1__0_chanx_right_out; + wire [0:0] cbx_1__1__1_bottom_grid_pin_0_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_10_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_11_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_12_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_13_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_14_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_15_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_1_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_2_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_3_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_4_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_5_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_6_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_7_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_8_; + wire [0:0] cbx_1__1__1_bottom_grid_pin_9_; + wire [0:0] cbx_1__1__1_ccff_tail; + wire [0:19] cbx_1__1__1_chanx_left_out; + wire [0:19] cbx_1__1__1_chanx_right_out; + wire [0:0] cbx_1__2__0_bottom_grid_pin_0_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_10_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_11_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_12_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_13_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_14_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_15_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_1_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_2_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_3_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_4_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_5_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_6_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_7_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_8_; + wire [0:0] cbx_1__2__0_bottom_grid_pin_9_; + wire [0:0] cbx_1__2__0_ccff_tail; + wire [0:19] cbx_1__2__0_chanx_left_out; + wire [0:19] cbx_1__2__0_chanx_right_out; + wire [0:0] cbx_1__2__0_top_grid_pin_0_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_0_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_10_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_11_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_12_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_13_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_14_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_15_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_1_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_2_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_3_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_4_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_5_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_6_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_7_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_8_; + wire [0:0] cbx_1__2__1_bottom_grid_pin_9_; + wire [0:0] cbx_1__2__1_ccff_tail; + wire [0:19] cbx_1__2__1_chanx_left_out; + wire [0:19] cbx_1__2__1_chanx_right_out; + wire [0:0] cbx_1__2__1_top_grid_pin_0_; + wire [0:0] cby_0__1__0_ccff_tail; + wire [0:19] cby_0__1__0_chany_bottom_out; + wire [0:19] cby_0__1__0_chany_top_out; + wire [0:0] cby_0__1__0_left_grid_pin_0_; + wire [0:0] cby_0__1__1_ccff_tail; + wire [0:19] cby_0__1__1_chany_bottom_out; + wire [0:19] cby_0__1__1_chany_top_out; + wire [0:0] cby_0__1__1_left_grid_pin_0_; + wire [0:0] cby_1__1__0_ccff_tail; + wire [0:19] cby_1__1__0_chany_bottom_out; + wire [0:19] cby_1__1__0_chany_top_out; + wire [0:0] cby_1__1__0_left_grid_pin_16_; + wire [0:0] cby_1__1__0_left_grid_pin_17_; + wire [0:0] cby_1__1__0_left_grid_pin_18_; + wire [0:0] cby_1__1__0_left_grid_pin_19_; + wire [0:0] cby_1__1__0_left_grid_pin_20_; + wire [0:0] cby_1__1__0_left_grid_pin_21_; + wire [0:0] cby_1__1__0_left_grid_pin_22_; + wire [0:0] cby_1__1__0_left_grid_pin_23_; + wire [0:0] cby_1__1__0_left_grid_pin_24_; + wire [0:0] cby_1__1__0_left_grid_pin_25_; + wire [0:0] cby_1__1__0_left_grid_pin_26_; + wire [0:0] cby_1__1__0_left_grid_pin_27_; + wire [0:0] cby_1__1__0_left_grid_pin_28_; + wire [0:0] cby_1__1__0_left_grid_pin_29_; + wire [0:0] cby_1__1__0_left_grid_pin_30_; + wire [0:0] cby_1__1__0_left_grid_pin_31_; + wire [0:0] cby_1__1__1_ccff_tail; + wire [0:19] cby_1__1__1_chany_bottom_out; + wire [0:19] cby_1__1__1_chany_top_out; + wire [0:0] cby_1__1__1_left_grid_pin_16_; + wire [0:0] cby_1__1__1_left_grid_pin_17_; + wire [0:0] cby_1__1__1_left_grid_pin_18_; + wire [0:0] cby_1__1__1_left_grid_pin_19_; + wire [0:0] cby_1__1__1_left_grid_pin_20_; + wire [0:0] cby_1__1__1_left_grid_pin_21_; + wire [0:0] cby_1__1__1_left_grid_pin_22_; + wire [0:0] cby_1__1__1_left_grid_pin_23_; + wire [0:0] cby_1__1__1_left_grid_pin_24_; + wire [0:0] cby_1__1__1_left_grid_pin_25_; + wire [0:0] cby_1__1__1_left_grid_pin_26_; + wire [0:0] cby_1__1__1_left_grid_pin_27_; + wire [0:0] cby_1__1__1_left_grid_pin_28_; + wire [0:0] cby_1__1__1_left_grid_pin_29_; + wire [0:0] cby_1__1__1_left_grid_pin_30_; + wire [0:0] cby_1__1__1_left_grid_pin_31_; + wire [0:0] cby_2__1__0_ccff_tail; + wire [0:19] cby_2__1__0_chany_bottom_out; + wire [0:19] cby_2__1__0_chany_top_out; + wire [0:0] cby_2__1__0_left_grid_pin_16_; + wire [0:0] cby_2__1__0_left_grid_pin_17_; + wire [0:0] cby_2__1__0_left_grid_pin_18_; + wire [0:0] cby_2__1__0_left_grid_pin_19_; + wire [0:0] cby_2__1__0_left_grid_pin_20_; + wire [0:0] cby_2__1__0_left_grid_pin_21_; + wire [0:0] cby_2__1__0_left_grid_pin_22_; + wire [0:0] cby_2__1__0_left_grid_pin_23_; + wire [0:0] cby_2__1__0_left_grid_pin_24_; + wire [0:0] cby_2__1__0_left_grid_pin_25_; + wire [0:0] cby_2__1__0_left_grid_pin_26_; + wire [0:0] cby_2__1__0_left_grid_pin_27_; + wire [0:0] cby_2__1__0_left_grid_pin_28_; + wire [0:0] cby_2__1__0_left_grid_pin_29_; + wire [0:0] cby_2__1__0_left_grid_pin_30_; + wire [0:0] cby_2__1__0_left_grid_pin_31_; + wire [0:0] cby_2__1__0_right_grid_pin_0_; + wire [0:0] cby_2__1__1_ccff_tail; + wire [0:19] cby_2__1__1_chany_bottom_out; + wire [0:19] cby_2__1__1_chany_top_out; + wire [0:0] cby_2__1__1_left_grid_pin_16_; + wire [0:0] cby_2__1__1_left_grid_pin_17_; + wire [0:0] cby_2__1__1_left_grid_pin_18_; + wire [0:0] cby_2__1__1_left_grid_pin_19_; + wire [0:0] cby_2__1__1_left_grid_pin_20_; + wire [0:0] cby_2__1__1_left_grid_pin_21_; + wire [0:0] cby_2__1__1_left_grid_pin_22_; + wire [0:0] cby_2__1__1_left_grid_pin_23_; + wire [0:0] cby_2__1__1_left_grid_pin_24_; + wire [0:0] cby_2__1__1_left_grid_pin_25_; + wire [0:0] cby_2__1__1_left_grid_pin_26_; + wire [0:0] cby_2__1__1_left_grid_pin_27_; + wire [0:0] cby_2__1__1_left_grid_pin_28_; + wire [0:0] cby_2__1__1_left_grid_pin_29_; + wire [0:0] cby_2__1__1_left_grid_pin_30_; + wire [0:0] cby_2__1__1_left_grid_pin_31_; + wire [0:0] cby_2__1__1_right_grid_pin_0_; + wire [0:0] direct_interc_0_out; + wire [0:0] direct_interc_1_out; + wire [0:0] direct_interc_2_out; + wire [0:0] direct_interc_3_out; + wire [0:0] direct_interc_4_out; + wire [0:0] direct_interc_5_out; + wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_; + wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_; + wire [0:0] grid_clb_0_ccff_tail; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower; + wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower; + wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper; + wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_; + wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_; + wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_; + wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_; + wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_; + wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_; + wire [0:0] grid_clb_1_ccff_tail; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower; + wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower; + wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper; + wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_; + wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_; + wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_; + wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_; + wire [0:0] grid_clb_2_ccff_tail; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower; + wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower; + wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper; + wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_; + wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_; + wire [0:0] grid_clb_3_ccff_tail; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower; + wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower; + wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper; + wire [0:0] grid_io_bottom_0_ccff_tail; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower; + wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper; + wire [0:0] grid_io_bottom_1_ccff_tail; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower; + wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper; + wire [0:0] grid_io_left_0_ccff_tail; + wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_left_1_ccff_tail; + wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_right_0_ccff_tail; + wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_right_1_ccff_tail; + wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_top_0_ccff_tail; + wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower; + wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper; + wire [0:0] grid_io_top_1_ccff_tail; + wire [0:19] sb_0__0__0_chanx_right_out; + wire [0:19] sb_0__0__0_chany_top_out; + wire [0:0] sb_0__1__0_ccff_tail; + wire [0:19] sb_0__1__0_chanx_right_out; + wire [0:19] sb_0__1__0_chany_bottom_out; + wire [0:19] sb_0__1__0_chany_top_out; + wire [0:0] sb_0__2__0_ccff_tail; + wire [0:19] sb_0__2__0_chanx_right_out; + wire [0:19] sb_0__2__0_chany_bottom_out; + wire [0:0] sb_1__0__0_ccff_tail; + wire [0:19] sb_1__0__0_chanx_left_out; + wire [0:19] sb_1__0__0_chanx_right_out; + wire [0:19] sb_1__0__0_chany_top_out; + wire [0:0] sb_1__1__0_ccff_tail; + wire [0:19] sb_1__1__0_chanx_left_out; + wire [0:19] sb_1__1__0_chanx_right_out; + wire [0:19] sb_1__1__0_chany_bottom_out; + wire [0:19] sb_1__1__0_chany_top_out; + wire [0:0] sb_1__2__0_ccff_tail; + wire [0:19] sb_1__2__0_chanx_left_out; + wire [0:19] sb_1__2__0_chanx_right_out; + wire [0:19] sb_1__2__0_chany_bottom_out; + wire [0:0] sb_2__0__0_ccff_tail; + wire [0:19] sb_2__0__0_chanx_left_out; + wire [0:19] sb_2__0__0_chany_top_out; + wire [0:0] sb_2__1__0_ccff_tail; + wire [0:19] sb_2__1__0_chanx_left_out; + wire [0:19] sb_2__1__0_chany_bottom_out; + wire [0:19] sb_2__1__0_chany_top_out; + wire [0:0] sb_2__2__0_ccff_tail; + wire [0:19] sb_2__2__0_chanx_left_out; + wire [0:19] sb_2__2__0_chany_bottom_out; + wire [1:0] UNCONN; + wire [2:0] sc_out_wires; + wire [2:0] sc_in_wires; + wire [12:0] scff_Wires; + + grid_clb + grid_clb_1__1_ + ( + .SC_OUT_BOT(scff_Wires[5]), + .SC_IN_TOP(scff_Wires[3]), + .top_width_0_height_0__pin_33_(sc_in_wires[0]), + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__1__0_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__1__0_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__1__0_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__1__0_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__1__0_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__1__0_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__1__0_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__1__0_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__1__0_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__1__0_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__1__0_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__1__0_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__1__0_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__1__0_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__1__0_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__1__0_bottom_grid_pin_15_[0]), + .top_width_0_height_0__pin_32_(direct_interc_0_out[0]), + .right_width_0_height_0__pin_16_(cby_1__1__0_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_1__1__0_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_1__1__0_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_1__1__0_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_1__1__0_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_1__1__0_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_1__1__0_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_1__1__0_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_1__1__0_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_1__1__0_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_1__1__0_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_1__1__0_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_1__1__0_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_1__1__0_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_1__1__0_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_1__1__0_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_1__1__undriven_left_width_0_height_0__pin_52_[0]), + .ccff_head(grid_io_left_0_ccff_tail[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_0_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_0_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_0_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_0_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_0_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_0_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_0_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_0_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_0_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_0_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_0_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_0_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_0_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_0_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_0_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_0_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_0_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_0_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_0_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_0_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_0_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_0_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_0_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_0_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_0_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_0_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_0_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_0_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_0_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_0_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), + .bottom_width_0_height_0__pin_51_(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(grid_clb_0_ccff_tail[0]) + ); -wire [0:0] cbx_1__0__0_bottom_grid_pin_0_; -wire [0:0] cbx_1__0__0_ccff_tail; -wire [0:19] cbx_1__0__0_chanx_left_out; -wire [0:19] cbx_1__0__0_chanx_right_out; -wire [0:0] cbx_1__0__0_top_grid_pin_16_; -wire [0:0] cbx_1__0__0_top_grid_pin_17_; -wire [0:0] cbx_1__0__0_top_grid_pin_18_; -wire [0:0] cbx_1__0__0_top_grid_pin_19_; -wire [0:0] cbx_1__0__0_top_grid_pin_20_; -wire [0:0] cbx_1__0__0_top_grid_pin_21_; -wire [0:0] cbx_1__0__0_top_grid_pin_22_; -wire [0:0] cbx_1__0__0_top_grid_pin_23_; -wire [0:0] cbx_1__0__0_top_grid_pin_24_; -wire [0:0] cbx_1__0__0_top_grid_pin_25_; -wire [0:0] cbx_1__0__0_top_grid_pin_26_; -wire [0:0] cbx_1__0__0_top_grid_pin_27_; -wire [0:0] cbx_1__0__0_top_grid_pin_28_; -wire [0:0] cbx_1__0__0_top_grid_pin_29_; -wire [0:0] cbx_1__0__0_top_grid_pin_30_; -wire [0:0] cbx_1__0__0_top_grid_pin_31_; -wire [0:0] cbx_1__0__1_bottom_grid_pin_0_; -wire [0:0] cbx_1__0__1_ccff_tail; -wire [0:19] cbx_1__0__1_chanx_left_out; -wire [0:19] cbx_1__0__1_chanx_right_out; -wire [0:0] cbx_1__0__1_top_grid_pin_16_; -wire [0:0] cbx_1__0__1_top_grid_pin_17_; -wire [0:0] cbx_1__0__1_top_grid_pin_18_; -wire [0:0] cbx_1__0__1_top_grid_pin_19_; -wire [0:0] cbx_1__0__1_top_grid_pin_20_; -wire [0:0] cbx_1__0__1_top_grid_pin_21_; -wire [0:0] cbx_1__0__1_top_grid_pin_22_; -wire [0:0] cbx_1__0__1_top_grid_pin_23_; -wire [0:0] cbx_1__0__1_top_grid_pin_24_; -wire [0:0] cbx_1__0__1_top_grid_pin_25_; -wire [0:0] cbx_1__0__1_top_grid_pin_26_; -wire [0:0] cbx_1__0__1_top_grid_pin_27_; -wire [0:0] cbx_1__0__1_top_grid_pin_28_; -wire [0:0] cbx_1__0__1_top_grid_pin_29_; -wire [0:0] cbx_1__0__1_top_grid_pin_30_; -wire [0:0] cbx_1__0__1_top_grid_pin_31_; -wire [0:0] cbx_1__1__0_ccff_tail; -wire [0:19] cbx_1__1__0_chanx_left_out; -wire [0:19] cbx_1__1__0_chanx_right_out; -wire [0:0] cbx_1__1__0_top_grid_pin_16_; -wire [0:0] cbx_1__1__0_top_grid_pin_17_; -wire [0:0] cbx_1__1__0_top_grid_pin_18_; -wire [0:0] cbx_1__1__0_top_grid_pin_19_; -wire [0:0] cbx_1__1__0_top_grid_pin_20_; -wire [0:0] cbx_1__1__0_top_grid_pin_21_; -wire [0:0] cbx_1__1__0_top_grid_pin_22_; -wire [0:0] cbx_1__1__0_top_grid_pin_23_; -wire [0:0] cbx_1__1__0_top_grid_pin_24_; -wire [0:0] cbx_1__1__0_top_grid_pin_25_; -wire [0:0] cbx_1__1__0_top_grid_pin_26_; -wire [0:0] cbx_1__1__0_top_grid_pin_27_; -wire [0:0] cbx_1__1__0_top_grid_pin_28_; -wire [0:0] cbx_1__1__0_top_grid_pin_29_; -wire [0:0] cbx_1__1__0_top_grid_pin_30_; -wire [0:0] cbx_1__1__0_top_grid_pin_31_; -wire [0:0] cbx_1__1__1_ccff_tail; -wire [0:19] cbx_1__1__1_chanx_left_out; -wire [0:19] cbx_1__1__1_chanx_right_out; -wire [0:0] cbx_1__1__1_top_grid_pin_16_; -wire [0:0] cbx_1__1__1_top_grid_pin_17_; -wire [0:0] cbx_1__1__1_top_grid_pin_18_; -wire [0:0] cbx_1__1__1_top_grid_pin_19_; -wire [0:0] cbx_1__1__1_top_grid_pin_20_; -wire [0:0] cbx_1__1__1_top_grid_pin_21_; -wire [0:0] cbx_1__1__1_top_grid_pin_22_; -wire [0:0] cbx_1__1__1_top_grid_pin_23_; -wire [0:0] cbx_1__1__1_top_grid_pin_24_; -wire [0:0] cbx_1__1__1_top_grid_pin_25_; -wire [0:0] cbx_1__1__1_top_grid_pin_26_; -wire [0:0] cbx_1__1__1_top_grid_pin_27_; -wire [0:0] cbx_1__1__1_top_grid_pin_28_; -wire [0:0] cbx_1__1__1_top_grid_pin_29_; -wire [0:0] cbx_1__1__1_top_grid_pin_30_; -wire [0:0] cbx_1__1__1_top_grid_pin_31_; -wire [0:0] cbx_1__2__0_ccff_tail; -wire [0:19] cbx_1__2__0_chanx_left_out; -wire [0:19] cbx_1__2__0_chanx_right_out; -wire [0:0] cbx_1__2__0_top_grid_pin_0_; -wire [0:0] cbx_1__2__1_ccff_tail; -wire [0:19] cbx_1__2__1_chanx_left_out; -wire [0:19] cbx_1__2__1_chanx_right_out; -wire [0:0] cbx_1__2__1_top_grid_pin_0_; -wire [0:0] cby_0__1__0_ccff_tail; -wire [0:19] cby_0__1__0_chany_bottom_out; -wire [0:19] cby_0__1__0_chany_top_out; -wire [0:0] cby_0__1__0_left_grid_pin_0_; -wire [0:0] cby_0__1__0_right_grid_pin_52_; -wire [0:0] cby_0__1__1_ccff_tail; -wire [0:19] cby_0__1__1_chany_bottom_out; -wire [0:19] cby_0__1__1_chany_top_out; -wire [0:0] cby_0__1__1_left_grid_pin_0_; -wire [0:0] cby_0__1__1_right_grid_pin_52_; -wire [0:0] cby_1__1__0_ccff_tail; -wire [0:19] cby_1__1__0_chany_bottom_out; -wire [0:19] cby_1__1__0_chany_top_out; -wire [0:0] cby_1__1__0_left_grid_pin_0_; -wire [0:0] cby_1__1__0_left_grid_pin_10_; -wire [0:0] cby_1__1__0_left_grid_pin_11_; -wire [0:0] cby_1__1__0_left_grid_pin_12_; -wire [0:0] cby_1__1__0_left_grid_pin_13_; -wire [0:0] cby_1__1__0_left_grid_pin_14_; -wire [0:0] cby_1__1__0_left_grid_pin_15_; -wire [0:0] cby_1__1__0_left_grid_pin_1_; -wire [0:0] cby_1__1__0_left_grid_pin_2_; -wire [0:0] cby_1__1__0_left_grid_pin_3_; -wire [0:0] cby_1__1__0_left_grid_pin_4_; -wire [0:0] cby_1__1__0_left_grid_pin_5_; -wire [0:0] cby_1__1__0_left_grid_pin_6_; -wire [0:0] cby_1__1__0_left_grid_pin_7_; -wire [0:0] cby_1__1__0_left_grid_pin_8_; -wire [0:0] cby_1__1__0_left_grid_pin_9_; -wire [0:0] cby_1__1__0_right_grid_pin_52_; -wire [0:0] cby_1__1__1_ccff_tail; -wire [0:19] cby_1__1__1_chany_bottom_out; -wire [0:19] cby_1__1__1_chany_top_out; -wire [0:0] cby_1__1__1_left_grid_pin_0_; -wire [0:0] cby_1__1__1_left_grid_pin_10_; -wire [0:0] cby_1__1__1_left_grid_pin_11_; -wire [0:0] cby_1__1__1_left_grid_pin_12_; -wire [0:0] cby_1__1__1_left_grid_pin_13_; -wire [0:0] cby_1__1__1_left_grid_pin_14_; -wire [0:0] cby_1__1__1_left_grid_pin_15_; -wire [0:0] cby_1__1__1_left_grid_pin_1_; -wire [0:0] cby_1__1__1_left_grid_pin_2_; -wire [0:0] cby_1__1__1_left_grid_pin_3_; -wire [0:0] cby_1__1__1_left_grid_pin_4_; -wire [0:0] cby_1__1__1_left_grid_pin_5_; -wire [0:0] cby_1__1__1_left_grid_pin_6_; -wire [0:0] cby_1__1__1_left_grid_pin_7_; -wire [0:0] cby_1__1__1_left_grid_pin_8_; -wire [0:0] cby_1__1__1_left_grid_pin_9_; -wire [0:0] cby_1__1__1_right_grid_pin_52_; -wire [0:0] cby_1__1__2_ccff_tail; -wire [0:19] cby_1__1__2_chany_bottom_out; -wire [0:19] cby_1__1__2_chany_top_out; -wire [0:0] cby_1__1__2_left_grid_pin_0_; -wire [0:0] cby_1__1__2_left_grid_pin_10_; -wire [0:0] cby_1__1__2_left_grid_pin_11_; -wire [0:0] cby_1__1__2_left_grid_pin_12_; -wire [0:0] cby_1__1__2_left_grid_pin_13_; -wire [0:0] cby_1__1__2_left_grid_pin_14_; -wire [0:0] cby_1__1__2_left_grid_pin_15_; -wire [0:0] cby_1__1__2_left_grid_pin_1_; -wire [0:0] cby_1__1__2_left_grid_pin_2_; -wire [0:0] cby_1__1__2_left_grid_pin_3_; -wire [0:0] cby_1__1__2_left_grid_pin_4_; -wire [0:0] cby_1__1__2_left_grid_pin_5_; -wire [0:0] cby_1__1__2_left_grid_pin_6_; -wire [0:0] cby_1__1__2_left_grid_pin_7_; -wire [0:0] cby_1__1__2_left_grid_pin_8_; -wire [0:0] cby_1__1__2_left_grid_pin_9_; -wire [0:0] cby_1__1__2_right_grid_pin_52_; -wire [0:0] cby_1__1__3_ccff_tail; -wire [0:19] cby_1__1__3_chany_bottom_out; -wire [0:19] cby_1__1__3_chany_top_out; -wire [0:0] cby_1__1__3_left_grid_pin_0_; -wire [0:0] cby_1__1__3_left_grid_pin_10_; -wire [0:0] cby_1__1__3_left_grid_pin_11_; -wire [0:0] cby_1__1__3_left_grid_pin_12_; -wire [0:0] cby_1__1__3_left_grid_pin_13_; -wire [0:0] cby_1__1__3_left_grid_pin_14_; -wire [0:0] cby_1__1__3_left_grid_pin_15_; -wire [0:0] cby_1__1__3_left_grid_pin_1_; -wire [0:0] cby_1__1__3_left_grid_pin_2_; -wire [0:0] cby_1__1__3_left_grid_pin_3_; -wire [0:0] cby_1__1__3_left_grid_pin_4_; -wire [0:0] cby_1__1__3_left_grid_pin_5_; -wire [0:0] cby_1__1__3_left_grid_pin_6_; -wire [0:0] cby_1__1__3_left_grid_pin_7_; -wire [0:0] cby_1__1__3_left_grid_pin_8_; -wire [0:0] cby_1__1__3_left_grid_pin_9_; -wire [0:0] cby_1__1__3_right_grid_pin_52_; -wire [0:0] direct_interc_0_out; -wire [0:0] direct_interc_1_out; -wire [0:0] direct_interc_2_out; -wire [0:0] direct_interc_3_out; -wire [0:0] direct_interc_4_out; -wire [0:0] direct_interc_5_out; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_0_ccff_tail; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_upper; -wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_; -wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_1_ccff_tail; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_upper; -wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_; -wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_upper; -wire [0:0] grid_clb_2_ccff_tail; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_3_ccff_tail; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_upper; -wire [0:0] grid_io_bottom_0_ccff_tail; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_bottom_1_ccff_tail; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_left_0_ccff_tail; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_left_1_ccff_tail; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_right_0_ccff_tail; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_right_1_ccff_tail; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_0_ccff_tail; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_1_ccff_tail; -wire [0:19] sb_0__0__0_chanx_right_out; -wire [0:19] sb_0__0__0_chany_top_out; -wire [0:0] sb_0__1__0_ccff_tail; -wire [0:19] sb_0__1__0_chanx_right_out; -wire [0:19] sb_0__1__0_chany_bottom_out; -wire [0:19] sb_0__1__0_chany_top_out; -wire [0:0] sb_0__2__0_ccff_tail; -wire [0:19] sb_0__2__0_chanx_right_out; -wire [0:19] sb_0__2__0_chany_bottom_out; -wire [0:0] sb_1__0__0_ccff_tail; -wire [0:19] sb_1__0__0_chanx_left_out; -wire [0:19] sb_1__0__0_chanx_right_out; -wire [0:19] sb_1__0__0_chany_top_out; -wire [0:0] sb_1__1__0_ccff_tail; -wire [0:19] sb_1__1__0_chanx_left_out; -wire [0:19] sb_1__1__0_chanx_right_out; -wire [0:19] sb_1__1__0_chany_bottom_out; -wire [0:19] sb_1__1__0_chany_top_out; -wire [0:0] sb_1__2__0_ccff_tail; -wire [0:19] sb_1__2__0_chanx_left_out; -wire [0:19] sb_1__2__0_chanx_right_out; -wire [0:19] sb_1__2__0_chany_bottom_out; -wire [0:0] sb_2__0__0_ccff_tail; -wire [0:19] sb_2__0__0_chanx_left_out; -wire [0:19] sb_2__0__0_chany_top_out; -wire [0:0] sb_2__1__0_ccff_tail; -wire [0:19] sb_2__1__0_chanx_left_out; -wire [0:19] sb_2__1__0_chany_bottom_out; -wire [0:19] sb_2__1__0_chany_top_out; -wire [0:0] sb_2__2__0_ccff_tail; -wire [0:19] sb_2__2__0_chanx_left_out; -wire [0:19] sb_2__2__0_chany_bottom_out; + grid_clb + grid_clb_1__2_ + ( + .SC_OUT_BOT(scff_Wires[2]), + .SC_IN_TOP(scff_Wires[1]), + .bottom_width_0_height_0__pin_51_(sc_out_wires[0]), + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__2__0_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__2__0_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__2__0_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__2__0_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__2__0_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__2__0_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__2__0_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__2__0_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__2__0_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__2__0_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__2__0_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__2__0_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__2__0_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__2__0_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), + .top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]), + .top_width_0_height_0__pin_33_(grid_clb_1__2__undriven_top_width_0_height_0__pin_33_[0]), + .right_width_0_height_0__pin_16_(cby_1__1__1_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_1__1__1_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_1__1__1_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_1__1__1_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_1__1__1_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_1__1__1_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_1__1__1_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_1__1__1_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_1__1__1_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_1__1__1_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_1__1__1_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_1__1__1_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_1__1__1_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_1__1__1_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_1__1__1_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_1__1__1_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_1__2__undriven_left_width_0_height_0__pin_52_[0]), + .ccff_head(grid_io_left_1_ccff_tail[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_1_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_1_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_1_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_1_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_1_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_1_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_1_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_1_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_1_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_1_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_1_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_1_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_1_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_1_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_1_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_1_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_1_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_1_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_1_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_1_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_1_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_1_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_1_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_1_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_1_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_1_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_1_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_1_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_1_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_1_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_1_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_1_right_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), + .ccff_tail(grid_clb_1_ccff_tail[0]) + ); -// -// -// -// - grid_clb grid_clb_1__1_ ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_32_(direct_interc_0_out[0]), - .top_width_0_height_0__pin_33_(direct_interc_3_out[0]), - .right_width_0_height_0__pin_0_(cby_1__1__0_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__0_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__0_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__0_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__0_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__0_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__0_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__0_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__0_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__0_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__0_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__0_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__0_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__0_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__0_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__0_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__0__0_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__0__0_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__0__0_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__0__0_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__0__0_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__0__0_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__0__0_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__0__0_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__0__0_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__0__0_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__0__0_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__0__0_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__0__0_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__0__0_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__0__0_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__0__0_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_0__1__0_right_grid_pin_52_[0]), - .ccff_head(grid_io_left_0_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_0_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_0_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_0_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_0_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_0_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_0_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_0_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_0_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_0_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_0_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_0_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_0_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_0_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_0_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_0_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_0_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_0_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_0_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_0_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_0_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_0_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_0_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_0_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_0_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_0_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_0_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_0_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_0_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_0_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_0_bottom_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(grid_clb_0_ccff_tail[0])); + grid_clb + grid_clb_2__1_ + ( + .SC_OUT_TOP(scff_Wires[9]), + .SC_IN_BOT(scff_Wires[8]), + .top_width_0_height_0__pin_33_(sc_in_wires[1]), + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__1__1_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__1__1_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__1__1_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__1__1_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__1__1_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__1__1_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__1__1_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__1__1_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__1__1_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__1__1_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__1__1_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__1__1_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__1__1_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__1__1_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__1__1_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__1__1_bottom_grid_pin_15_[0]), + .top_width_0_height_0__pin_32_(direct_interc_1_out[0]), + .right_width_0_height_0__pin_16_(cby_2__1__0_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_2__1__0_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_2__1__0_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_2__1__0_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_2__1__0_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_2__1__0_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_2__1__0_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_2__1__0_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_2__1__0_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_2__1__0_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_2__1__0_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_2__1__0_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_2__1__0_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_2__1__0_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_2__1__0_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_2__1__0_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_2__1__undriven_left_width_0_height_0__pin_52_[0]), + .ccff_head(cby_1__1__0_ccff_tail[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_2_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_2_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_2_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_2_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_2_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_2_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_2_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_2_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_2_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_2_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_2_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_2_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_2_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_2_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_2_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_2_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_2_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_2_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_2_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_2_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_2_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_2_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_2_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_2_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_2_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_2_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_2_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_2_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_2_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_2_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]), + .bottom_width_0_height_0__pin_51_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(grid_clb_2_ccff_tail[0]) + ); - grid_clb grid_clb_1__2_ ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]), - .top_width_0_height_0__pin_33_(grid_clb_1__2__undriven_top_width_0_height_0__pin_33_[0]), - .right_width_0_height_0__pin_0_(cby_1__1__1_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__1_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__1_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__1_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__1_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__1_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__1_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__1_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__1_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__1_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__1_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__1_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__1_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__1_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__1_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__1_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__1__0_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__1__0_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__1__0_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__1__0_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__1__0_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__1__0_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__1__0_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__1__0_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__1__0_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__1__0_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__1__0_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__1__0_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__1__0_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__1__0_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__1__0_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__1__0_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_0__1__1_right_grid_pin_52_[0]), - .ccff_head(grid_io_left_1_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_1_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_1_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_1_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_1_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_1_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_1_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_1_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_1_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_1_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_1_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_1_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_1_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_1_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_1_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_1_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_1_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_1_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_1_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_1_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_1_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_1_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_1_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_1_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_1_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_1_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_1_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_1_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_1_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_1_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_1_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_1_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_1_bottom_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(grid_clb_1_ccff_tail[0])); - grid_clb grid_clb_2__1_ ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_32_(direct_interc_1_out[0]), - .top_width_0_height_0__pin_33_(direct_interc_4_out[0]), - .right_width_0_height_0__pin_0_(cby_1__1__2_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__2_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__2_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__2_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__2_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__2_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__2_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__2_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__2_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__2_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__2_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__2_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__2_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__2_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__2_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__2_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__0__1_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__0__1_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__0__1_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__0__1_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__0__1_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__0__1_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__0__1_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__0__1_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__0__1_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__0__1_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__0__1_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__0__1_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__0__1_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__0__1_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__0__1_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__0__1_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_1__1__0_right_grid_pin_52_[0]), - .ccff_head(cby_1__1__0_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_2_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_2_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_2_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_2_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_2_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_2_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_2_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_2_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_2_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_2_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_2_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_2_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_2_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_2_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_2_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_2_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_2_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_2_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_2_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_2_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_2_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_2_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_2_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_2_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_2_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_2_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_2_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_2_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_2_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_2_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_2_bottom_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(grid_clb_2_ccff_tail[0])); + grid_clb + grid_clb_2__2_ + ( + .SC_OUT_TOP(scff_Wires[11]), + .SC_IN_BOT(scff_Wires[10]), + .bottom_width_0_height_0__pin_51_(sc_out_wires[1]), + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__2__1_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__2__1_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__2__1_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__2__1_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__2__1_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__2__1_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__2__1_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__2__1_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__2__1_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__2__1_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__2__1_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__2__1_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__2__1_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__2__1_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), + .top_width_0_height_0__pin_32_(direct_interc_2_out[0]), + .top_width_0_height_0__pin_33_(direct_interc_5_out[0]), + .right_width_0_height_0__pin_16_(cby_2__1__1_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_2__1__1_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_2__1__1_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_2__1__1_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_2__1__1_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_2__1__1_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_2__1__1_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_2__1__1_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_2__1__1_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_2__1__1_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_2__1__1_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_2__1__1_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_2__1__1_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_2__1__1_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_2__1__1_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_2__1__1_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_2__2__undriven_left_width_0_height_0__pin_52_[0]), + .ccff_head(cby_1__1__1_ccff_tail[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_3_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_3_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_3_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_3_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_3_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_3_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_3_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_3_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_3_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_3_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_3_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_3_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_3_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_3_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_3_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_3_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_3_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_3_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_3_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_3_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_3_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_3_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_3_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_3_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_3_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_3_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_3_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_3_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_3_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_3_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_3_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_3_right_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), + .ccff_tail(grid_clb_3_ccff_tail[0]) + ); - grid_clb grid_clb_2__2_ ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_32_(direct_interc_2_out[0]), - .top_width_0_height_0__pin_33_(direct_interc_5_out[0]), - .right_width_0_height_0__pin_0_(cby_1__1__3_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__3_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__3_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__3_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__3_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__3_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__3_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__3_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__3_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__3_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__3_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__3_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__3_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__3_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__3_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__3_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__1__1_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__1__1_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__1__1_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__1__1_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__1__1_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__1__1_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__1__1_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__1__1_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__1__1_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__1__1_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__1__1_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__1__1_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__1__1_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__1__1_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__1__1_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__1__1_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_1__1__1_right_grid_pin_52_[0]), - .ccff_head(cby_1__1__1_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_3_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_3_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_3_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_3_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_3_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_3_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_3_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_3_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_3_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_3_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_3_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_3_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_3_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_3_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_3_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_3_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_3_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_3_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_3_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_3_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_3_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_3_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_3_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_3_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_3_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_3_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_3_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_3_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_3_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_3_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_3_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_3_bottom_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(grid_clb_3_ccff_tail[0])); - grid_io_top grid_io_top_1__3_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), - .bottom_width_0_height_0__pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), - .ccff_head(cbx_1__2__0_ccff_tail[0]), - .bottom_width_0_height_0__pin_1_upper(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), - .bottom_width_0_height_0__pin_1_lower(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_top_0_ccff_tail[0])); + sb_0__0_ + sb_0__0_ + ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_0__1__0_chany_bottom_out[0:19]), + .top_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), + .chanx_right_in(cbx_1__0__0_chanx_left_out[0:19]), + .right_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_3_(grid_io_bottom_0_top_width_0_height_0__pin_3_upper[0]), + .right_bottom_grid_pin_5_(grid_io_bottom_0_top_width_0_height_0__pin_5_upper[0]), + .right_bottom_grid_pin_7_(grid_io_bottom_0_top_width_0_height_0__pin_7_upper[0]), + .right_bottom_grid_pin_9_(grid_io_bottom_0_top_width_0_height_0__pin_9_upper[0]), + .right_bottom_grid_pin_11_(grid_io_bottom_0_top_width_0_height_0__pin_11_upper[0]), + .ccff_head(grid_io_bottom_0_ccff_tail[0]), + .chany_top_out(sb_0__0__0_chany_top_out[0:19]), + .chanx_right_out(sb_0__0__0_chanx_right_out[0:19]), + .ccff_tail(ccff_tail[0]) + ); - grid_io_top grid_io_top_2__3_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[1]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[1]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[1]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[1]), - .bottom_width_0_height_0__pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), - .ccff_head(cbx_1__2__1_ccff_tail[0]), - .bottom_width_0_height_0__pin_1_upper(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), - .bottom_width_0_height_0__pin_1_lower(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_top_1_ccff_tail[0])); - grid_io_right grid_io_right_3__1_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[2]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[2]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[2]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[2]), - .left_width_0_height_0__pin_0_(cby_1__1__2_right_grid_pin_52_[0]), - .ccff_head(cby_1__1__2_ccff_tail[0]), - .left_width_0_height_0__pin_1_upper(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), - .left_width_0_height_0__pin_1_lower(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_right_0_ccff_tail[0])); + sb_0__1_ + sb_0__1_ + ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_0__1__1_chany_bottom_out[0:19]), + .top_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), + .chanx_right_in(cbx_1__1__0_chanx_left_out[0:19]), + .right_bottom_grid_pin_34_(grid_clb_0_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_0_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_0_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_0_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_0_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_0_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_0_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_0_top_width_0_height_0__pin_41_upper[0]), + .chany_bottom_in(cby_0__1__0_chany_top_out[0:19]), + .bottom_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), + .ccff_head(cbx_1__1__0_ccff_tail[0]), + .chany_top_out(sb_0__1__0_chany_top_out[0:19]), + .chanx_right_out(sb_0__1__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:19]), + .ccff_tail(sb_0__1__0_ccff_tail[0]) + ); - grid_io_right grid_io_right_3__2_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[3]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[3]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[3]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[3]), - .left_width_0_height_0__pin_0_(cby_1__1__3_right_grid_pin_52_[0]), - .ccff_head(cby_1__1__3_ccff_tail[0]), - .left_width_0_height_0__pin_1_upper(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), - .left_width_0_height_0__pin_1_lower(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_right_1_ccff_tail[0])); - grid_io_bottom grid_io_bottom_1__0_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[4]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[4]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[4]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[4]), - .top_width_0_height_0__pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), - .ccff_head(cbx_1__0__0_ccff_tail[0]), - .top_width_0_height_0__pin_1_upper(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), - .top_width_0_height_0__pin_1_lower(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_bottom_0_ccff_tail[0])); + sb_0__2_ + sb_0__2_ + ( + .SC_OUT_BOT(scff_Wires[0]), + .SC_IN_TOP(sc_head), + .prog_clk(prog_clk[0]), + .chanx_right_in(cbx_1__2__0_chanx_left_out[0:19]), + .right_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_34_(grid_clb_1_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_1_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_1_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_1_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_1_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_1_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_1_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_1_top_width_0_height_0__pin_41_upper[0]), + .chany_bottom_in(cby_0__1__1_chany_top_out[0:19]), + .bottom_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), + .ccff_head(grid_io_top_0_ccff_tail[0]), + .chanx_right_out(sb_0__2__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_0__2__0_chany_bottom_out[0:19]), + .ccff_tail(sb_0__2__0_ccff_tail[0]) + ); - grid_io_bottom grid_io_bottom_2__0_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[5]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[5]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[5]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[5]), - .top_width_0_height_0__pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), - .ccff_head(cbx_1__0__1_ccff_tail[0]), - .top_width_0_height_0__pin_1_upper(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), - .top_width_0_height_0__pin_1_lower(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_bottom_1_ccff_tail[0])); - grid_io_left grid_io_left_0__1_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[6]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[6]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[6]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[6]), - .right_width_0_height_0__pin_0_(cby_0__1__0_left_grid_pin_0_[0]), - .ccff_head(cby_0__1__0_ccff_tail[0]), - .right_width_0_height_0__pin_1_upper(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), - .right_width_0_height_0__pin_1_lower(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_left_0_ccff_tail[0])); + sb_1__0_ + sb_1__0_ + ( + .SC_OUT_BOT(scff_Wires[7]), + .SC_IN_TOP(scff_Wires[6]), + .prog_clk(prog_clk[0]), + .chany_top_in(cby_1__1__0_chany_bottom_out[0:19]), + .top_left_grid_pin_42_(grid_clb_0_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_0_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_0_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_0_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_0_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_0_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_0_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), + .chanx_right_in(cbx_1__0__1_chanx_left_out[0:19]), + .right_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_3_(grid_io_bottom_1_top_width_0_height_0__pin_3_upper[0]), + .right_bottom_grid_pin_5_(grid_io_bottom_1_top_width_0_height_0__pin_5_upper[0]), + .right_bottom_grid_pin_7_(grid_io_bottom_1_top_width_0_height_0__pin_7_upper[0]), + .right_bottom_grid_pin_9_(grid_io_bottom_1_top_width_0_height_0__pin_9_upper[0]), + .right_bottom_grid_pin_11_(grid_io_bottom_1_top_width_0_height_0__pin_11_upper[0]), + .chanx_left_in(cbx_1__0__0_chanx_right_out[0:19]), + .left_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_3_(grid_io_bottom_0_top_width_0_height_0__pin_3_lower[0]), + .left_bottom_grid_pin_5_(grid_io_bottom_0_top_width_0_height_0__pin_5_lower[0]), + .left_bottom_grid_pin_7_(grid_io_bottom_0_top_width_0_height_0__pin_7_lower[0]), + .left_bottom_grid_pin_9_(grid_io_bottom_0_top_width_0_height_0__pin_9_lower[0]), + .left_bottom_grid_pin_11_(grid_io_bottom_0_top_width_0_height_0__pin_11_lower[0]), + .ccff_head(grid_io_bottom_1_ccff_tail[0]), + .chany_top_out(sb_1__0__0_chany_top_out[0:19]), + .chanx_right_out(sb_1__0__0_chanx_right_out[0:19]), + .chanx_left_out(sb_1__0__0_chanx_left_out[0:19]), + .ccff_tail(sb_1__0__0_ccff_tail[0]) + ); - grid_io_left grid_io_left_0__2_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[7]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[7]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[7]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[7]), - .right_width_0_height_0__pin_0_(cby_0__1__1_left_grid_pin_0_[0]), - .ccff_head(cby_0__1__1_ccff_tail[0]), - .right_width_0_height_0__pin_1_upper(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), - .right_width_0_height_0__pin_1_lower(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_left_1_ccff_tail[0])); - sb_0__0_ sb_0__0_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_0__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), - .chanx_right_in(cbx_1__0__0_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_0_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_0_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_0_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_0_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_0_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_0_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_0_bottom_width_0_height_0__pin_49_upper[0]), - .right_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), - .ccff_head(grid_io_bottom_0_ccff_tail[0]), - .chany_top_out(sb_0__0__0_chany_top_out[0:19]), - .chanx_right_out(sb_0__0__0_chanx_right_out[0:19]), - .ccff_tail(ccff_tail[0])); + sb_1__1_ + sb_1__1_ + ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_1__1__1_chany_bottom_out[0:19]), + .top_left_grid_pin_42_(grid_clb_1_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_1_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_1_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_1_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_1_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_1_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_1_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_1_right_width_0_height_0__pin_49_lower[0]), + .chanx_right_in(cbx_1__1__1_chanx_left_out[0:19]), + .right_bottom_grid_pin_34_(grid_clb_2_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_2_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_2_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_2_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_2_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_2_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_2_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_2_top_width_0_height_0__pin_41_upper[0]), + .chany_bottom_in(cby_1__1__0_chany_top_out[0:19]), + .bottom_left_grid_pin_42_(grid_clb_0_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_0_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_0_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_0_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_0_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_0_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_0_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), + .chanx_left_in(cbx_1__1__0_chanx_right_out[0:19]), + .left_bottom_grid_pin_34_(grid_clb_0_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_0_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_0_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_0_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_0_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_0_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_0_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_0_top_width_0_height_0__pin_41_lower[0]), + .ccff_head(cbx_1__1__1_ccff_tail[0]), + .chany_top_out(sb_1__1__0_chany_top_out[0:19]), + .chanx_right_out(sb_1__1__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_1__1__0_chanx_left_out[0:19]), + .ccff_tail(sb_1__1__0_ccff_tail[0]) + ); - sb_0__1_ sb_0__1_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_0__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), - .chanx_right_in(cbx_1__1__0_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_1_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_1_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_1_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_1_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_1_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_1_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_1_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_1_bottom_width_0_height_0__pin_49_upper[0]), - .chany_bottom_in(cby_0__1__0_chany_top_out[0:19]), - .bottom_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), - .ccff_head(cbx_1__1__0_ccff_tail[0]), - .chany_top_out(sb_0__1__0_chany_top_out[0:19]), - .chanx_right_out(sb_0__1__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:19]), - .ccff_tail(sb_0__1__0_ccff_tail[0])); - sb_0__2_ sb_0__2_ ( - .prog_clk(prog_clk[0]), - .chanx_right_in(cbx_1__2__0_chanx_left_out[0:19]), - .right_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), - .chany_bottom_in(cby_0__1__1_chany_top_out[0:19]), - .bottom_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), - .ccff_head(grid_io_top_0_ccff_tail[0]), - .chanx_right_out(sb_0__2__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_0__2__0_chany_bottom_out[0:19]), - .ccff_tail(sb_0__2__0_ccff_tail[0])); + sb_1__2_ + sb_1__2_ + ( + .prog_clk(prog_clk[0]), + .chanx_right_in(cbx_1__2__1_chanx_left_out[0:19]), + .right_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_34_(grid_clb_3_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_3_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_3_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_3_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_3_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_3_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_3_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_3_top_width_0_height_0__pin_41_upper[0]), + .chany_bottom_in(cby_1__1__1_chany_top_out[0:19]), + .bottom_left_grid_pin_42_(grid_clb_1_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_1_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_1_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_1_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_1_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_1_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_1_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_1_right_width_0_height_0__pin_49_upper[0]), + .chanx_left_in(cbx_1__2__0_chanx_right_out[0:19]), + .left_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_34_(grid_clb_1_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_1_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_1_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_1_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_1_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_1_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_1_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_1_top_width_0_height_0__pin_41_lower[0]), + .ccff_head(grid_io_top_1_ccff_tail[0]), + .chanx_right_out(sb_1__2__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_1__2__0_chanx_left_out[0:19]), + .ccff_tail(sb_1__2__0_ccff_tail[0]) + ); - sb_1__0_ sb_1__0_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_0_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_0_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_0_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_0_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_0_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_0_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_0_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_0_right_width_0_height_0__pin_41_lower[0]), - .chanx_right_in(cbx_1__0__1_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_2_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_2_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_2_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_2_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_2_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_2_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_2_bottom_width_0_height_0__pin_49_upper[0]), - .right_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), - .chanx_left_in(cbx_1__0__0_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_0_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_0_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_0_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_0_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_0_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_0_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_0_bottom_width_0_height_0__pin_49_lower[0]), - .left_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), - .ccff_head(grid_io_bottom_1_ccff_tail[0]), - .chany_top_out(sb_1__0__0_chany_top_out[0:19]), - .chanx_right_out(sb_1__0__0_chanx_right_out[0:19]), - .chanx_left_out(sb_1__0__0_chanx_left_out[0:19]), - .ccff_tail(sb_1__0__0_ccff_tail[0])); - sb_1__1_ sb_1__1_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_1_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_1_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_1_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_1_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_1_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_1_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_1_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_1_right_width_0_height_0__pin_41_lower[0]), - .chanx_right_in(cbx_1__1__1_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_3_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_3_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_3_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_3_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_3_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_3_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_3_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_3_bottom_width_0_height_0__pin_49_upper[0]), - .chany_bottom_in(cby_1__1__0_chany_top_out[0:19]), - .bottom_left_grid_pin_34_(grid_clb_0_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_0_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_0_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_0_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_0_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_0_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_0_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_0_right_width_0_height_0__pin_41_upper[0]), - .chanx_left_in(cbx_1__1__0_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_1_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_1_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_1_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_1_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_1_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_1_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_1_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_1_bottom_width_0_height_0__pin_49_lower[0]), - .ccff_head(cbx_1__1__1_ccff_tail[0]), - .chany_top_out(sb_1__1__0_chany_top_out[0:19]), - .chanx_right_out(sb_1__1__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_1__1__0_chanx_left_out[0:19]), - .ccff_tail(sb_1__1__0_ccff_tail[0])); + sb_2__0_ + sb_2__0_ + ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_2__1__0_chany_bottom_out[0:19]), + .top_left_grid_pin_42_(grid_clb_2_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_2_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_2_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_2_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_2_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_2_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_2_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), + .top_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), + .chanx_left_in(cbx_1__0__1_chanx_right_out[0:19]), + .left_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_3_(grid_io_bottom_1_top_width_0_height_0__pin_3_lower[0]), + .left_bottom_grid_pin_5_(grid_io_bottom_1_top_width_0_height_0__pin_5_lower[0]), + .left_bottom_grid_pin_7_(grid_io_bottom_1_top_width_0_height_0__pin_7_lower[0]), + .left_bottom_grid_pin_9_(grid_io_bottom_1_top_width_0_height_0__pin_9_lower[0]), + .left_bottom_grid_pin_11_(grid_io_bottom_1_top_width_0_height_0__pin_11_lower[0]), + .ccff_head(grid_io_right_0_ccff_tail[0]), + .chany_top_out(sb_2__0__0_chany_top_out[0:19]), + .chanx_left_out(sb_2__0__0_chanx_left_out[0:19]), + .ccff_tail(sb_2__0__0_ccff_tail[0]) + ); - sb_1__2_ sb_1__2_ ( - .prog_clk(prog_clk[0]), - .chanx_right_in(cbx_1__2__1_chanx_left_out[0:19]), - .right_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), - .chany_bottom_in(cby_1__1__1_chany_top_out[0:19]), - .bottom_left_grid_pin_34_(grid_clb_1_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_1_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_1_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_1_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_1_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_1_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_1_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_1_right_width_0_height_0__pin_41_upper[0]), - .chanx_left_in(cbx_1__2__0_chanx_right_out[0:19]), - .left_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_head(grid_io_top_1_ccff_tail[0]), - .chanx_right_out(sb_1__2__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_1__2__0_chanx_left_out[0:19]), - .ccff_tail(sb_1__2__0_ccff_tail[0])); - sb_2__0_ sb_2__0_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__2_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_2_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_2_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_2_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_2_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_2_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_2_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_2_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_2_right_width_0_height_0__pin_41_lower[0]), - .top_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), - .chanx_left_in(cbx_1__0__1_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_2_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_2_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_2_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_2_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_2_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_2_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_2_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_2_bottom_width_0_height_0__pin_49_lower[0]), - .left_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), - .ccff_head(grid_io_right_0_ccff_tail[0]), - .chany_top_out(sb_2__0__0_chany_top_out[0:19]), - .chanx_left_out(sb_2__0__0_chanx_left_out[0:19]), - .ccff_tail(sb_2__0__0_ccff_tail[0])); + sb_2__1_ + sb_2__1_ + ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_2__1__1_chany_bottom_out[0:19]), + .top_left_grid_pin_42_(grid_clb_3_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_3_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_3_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_3_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_3_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_3_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_3_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_3_right_width_0_height_0__pin_49_lower[0]), + .top_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), + .chany_bottom_in(cby_2__1__0_chany_top_out[0:19]), + .bottom_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_42_(grid_clb_2_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_2_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_2_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_2_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_2_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_2_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_2_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), + .chanx_left_in(cbx_1__1__1_chanx_right_out[0:19]), + .left_bottom_grid_pin_34_(grid_clb_2_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_2_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_2_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_2_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_2_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_2_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_2_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_2_top_width_0_height_0__pin_41_lower[0]), + .ccff_head(grid_io_right_1_ccff_tail[0]), + .chany_top_out(sb_2__1__0_chany_top_out[0:19]), + .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_2__1__0_chanx_left_out[0:19]), + .ccff_tail(sb_2__1__0_ccff_tail[0]) + ); - sb_2__1_ sb_2__1_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__3_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_3_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_3_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_3_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_3_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_3_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_3_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_3_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_3_right_width_0_height_0__pin_41_lower[0]), - .top_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), - .chany_bottom_in(cby_1__1__2_chany_top_out[0:19]), - .bottom_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), - .bottom_left_grid_pin_34_(grid_clb_2_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_2_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_2_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_2_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_2_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_2_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_2_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_2_right_width_0_height_0__pin_41_upper[0]), - .chanx_left_in(cbx_1__1__1_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_3_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_3_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_3_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_3_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_3_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_3_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_3_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_3_bottom_width_0_height_0__pin_49_lower[0]), - .ccff_head(grid_io_right_1_ccff_tail[0]), - .chany_top_out(sb_2__1__0_chany_top_out[0:19]), - .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_2__1__0_chanx_left_out[0:19]), - .ccff_tail(sb_2__1__0_ccff_tail[0])); - sb_2__2_ sb_2__2_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(cby_1__1__3_chany_top_out[0:19]), - .bottom_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), - .bottom_left_grid_pin_34_(grid_clb_3_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_3_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_3_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_3_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_3_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_3_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_3_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_3_right_width_0_height_0__pin_41_upper[0]), - .chanx_left_in(cbx_1__2__1_chanx_right_out[0:19]), - .left_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_head(ccff_head[0]), - .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_2__2__0_chanx_left_out[0:19]), - .ccff_tail(sb_2__2__0_ccff_tail[0])); + sb_2__2_ + sb_2__2_ + ( + .SC_OUT_TOP(sc_tail), + .SC_IN_TOP(scff_Wires[12]), + .prog_clk(prog_clk[0]), + .chany_bottom_in(cby_2__1__1_chany_top_out[0:19]), + .bottom_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_42_(grid_clb_3_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_3_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_3_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_3_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_3_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_3_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_3_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_3_right_width_0_height_0__pin_49_upper[0]), + .chanx_left_in(cbx_1__2__1_chanx_right_out[0:19]), + .left_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_34_(grid_clb_3_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_3_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_3_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_3_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_3_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_3_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_3_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_3_top_width_0_height_0__pin_41_lower[0]), + .ccff_head(ccff_head[0]), + .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_2__2__0_chanx_left_out[0:19]), + .ccff_tail(sb_2__2__0_ccff_tail[0]) + ); - cbx_1__0_ cbx_1__0_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_0__0__0_chanx_right_out[0:19]), - .chanx_right_in(sb_1__0__0_chanx_left_out[0:19]), - .ccff_head(sb_1__0__0_ccff_tail[0]), - .chanx_left_out(cbx_1__0__0_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__0__0_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__0__0_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__0__0_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__0__0_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__0__0_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__0__0_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__0__0_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__0__0_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__0__0_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__0__0_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__0__0_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__0__0_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__0__0_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__0__0_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__0__0_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__0__0_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__0__0_top_grid_pin_31_[0]), - .bottom_grid_pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), - .ccff_tail(cbx_1__0__0_ccff_tail[0])); - cbx_1__0_ cbx_2__0_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_1__0__0_chanx_right_out[0:19]), - .chanx_right_in(sb_2__0__0_chanx_left_out[0:19]), - .ccff_head(sb_2__0__0_ccff_tail[0]), - .chanx_left_out(cbx_1__0__1_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__0__1_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__0__1_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__0__1_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__0__1_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__0__1_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__0__1_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__0__1_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__0__1_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__0__1_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__0__1_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__0__1_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__0__1_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__0__1_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__0__1_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__0__1_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__0__1_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__0__1_top_grid_pin_31_[0]), - .bottom_grid_pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), - .ccff_tail(cbx_1__0__1_ccff_tail[0])); + cbx_1__0_ + cbx_1__0_ + ( + .SC_OUT_BOT(scff_Wires[6]), + .SC_IN_TOP(scff_Wires[5]), + .top_width_0_height_0__pin_11_lower(grid_io_bottom_0_top_width_0_height_0__pin_11_lower[0]), + .top_width_0_height_0__pin_11_upper(grid_io_bottom_0_top_width_0_height_0__pin_11_upper[0]), + .top_width_0_height_0__pin_9_lower(grid_io_bottom_0_top_width_0_height_0__pin_9_lower[0]), + .top_width_0_height_0__pin_9_upper(grid_io_bottom_0_top_width_0_height_0__pin_9_upper[0]), + .top_width_0_height_0__pin_7_lower(grid_io_bottom_0_top_width_0_height_0__pin_7_lower[0]), + .top_width_0_height_0__pin_7_upper(grid_io_bottom_0_top_width_0_height_0__pin_7_upper[0]), + .top_width_0_height_0__pin_5_lower(grid_io_bottom_0_top_width_0_height_0__pin_5_lower[0]), + .top_width_0_height_0__pin_5_upper(grid_io_bottom_0_top_width_0_height_0__pin_5_upper[0]), + .top_width_0_height_0__pin_3_lower(grid_io_bottom_0_top_width_0_height_0__pin_3_lower[0]), + .top_width_0_height_0__pin_3_upper(grid_io_bottom_0_top_width_0_height_0__pin_3_upper[0]), + .top_width_0_height_0__pin_1_lower(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), + .top_width_0_height_0__pin_1_upper(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), + .top_width_0_height_0__pin_10_(cbx_1__0__0_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_8_(cbx_1__0__0_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_6_(cbx_1__0__0_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_4_(cbx_1__0__0_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_2_(cbx_1__0__0_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4:9]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4:9]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4:9]), + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_0__0__0_chanx_right_out[0:19]), + .chanx_right_in(sb_1__0__0_chanx_left_out[0:19]), + .ccff_head(sb_1__0__0_ccff_tail[0]), + .chanx_left_out(cbx_1__0__0_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__0__0_chanx_right_out[0:19]), + .bottom_grid_pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), + .bottom_grid_pin_2_(cbx_1__0__0_bottom_grid_pin_2_[0]), + .bottom_grid_pin_4_(cbx_1__0__0_bottom_grid_pin_4_[0]), + .bottom_grid_pin_6_(cbx_1__0__0_bottom_grid_pin_6_[0]), + .bottom_grid_pin_8_(cbx_1__0__0_bottom_grid_pin_8_[0]), + .bottom_grid_pin_10_(cbx_1__0__0_bottom_grid_pin_10_[0]), + .ccff_tail(grid_io_bottom_0_ccff_tail[0]) + ); - cbx_1__1_ cbx_1__1_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_0__1__0_chanx_right_out[0:19]), - .chanx_right_in(sb_1__1__0_chanx_left_out[0:19]), - .ccff_head(sb_1__1__0_ccff_tail[0]), - .chanx_left_out(cbx_1__1__0_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__1__0_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__1__0_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__1__0_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__1__0_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__1__0_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__1__0_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__1__0_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__1__0_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__1__0_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__1__0_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__1__0_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__1__0_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__1__0_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__1__0_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__1__0_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__1__0_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__1__0_top_grid_pin_31_[0]), - .ccff_tail(cbx_1__1__0_ccff_tail[0])); - cbx_1__1_ cbx_2__1_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_1__1__0_chanx_right_out[0:19]), - .chanx_right_in(sb_2__1__0_chanx_left_out[0:19]), - .ccff_head(sb_2__1__0_ccff_tail[0]), - .chanx_left_out(cbx_1__1__1_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__1__1_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__1__1_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__1__1_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__1__1_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__1__1_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__1__1_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__1__1_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__1__1_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__1__1_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__1__1_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__1__1_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__1__1_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__1__1_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__1__1_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__1__1_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__1__1_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__1__1_top_grid_pin_31_[0]), - .ccff_tail(cbx_1__1__1_ccff_tail[0])); + cbx_1__0_ + cbx_2__0_ + ( + .SC_OUT_TOP(scff_Wires[8]), + .SC_IN_TOP(scff_Wires[7]), + .top_width_0_height_0__pin_11_lower(grid_io_bottom_1_top_width_0_height_0__pin_11_lower[0]), + .top_width_0_height_0__pin_11_upper(grid_io_bottom_1_top_width_0_height_0__pin_11_upper[0]), + .top_width_0_height_0__pin_9_lower(grid_io_bottom_1_top_width_0_height_0__pin_9_lower[0]), + .top_width_0_height_0__pin_9_upper(grid_io_bottom_1_top_width_0_height_0__pin_9_upper[0]), + .top_width_0_height_0__pin_7_lower(grid_io_bottom_1_top_width_0_height_0__pin_7_lower[0]), + .top_width_0_height_0__pin_7_upper(grid_io_bottom_1_top_width_0_height_0__pin_7_upper[0]), + .top_width_0_height_0__pin_5_lower(grid_io_bottom_1_top_width_0_height_0__pin_5_lower[0]), + .top_width_0_height_0__pin_5_upper(grid_io_bottom_1_top_width_0_height_0__pin_5_upper[0]), + .top_width_0_height_0__pin_3_lower(grid_io_bottom_1_top_width_0_height_0__pin_3_lower[0]), + .top_width_0_height_0__pin_3_upper(grid_io_bottom_1_top_width_0_height_0__pin_3_upper[0]), + .top_width_0_height_0__pin_1_lower(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), + .top_width_0_height_0__pin_1_upper(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .top_width_0_height_0__pin_10_(cbx_1__0__1_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_8_(cbx_1__0__1_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_6_(cbx_1__0__1_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_4_(cbx_1__0__1_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_2_(cbx_1__0__1_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[10:15]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[10:15]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[10:15]), + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_1__0__0_chanx_right_out[0:19]), + .chanx_right_in(sb_2__0__0_chanx_left_out[0:19]), + .ccff_head(sb_2__0__0_ccff_tail[0]), + .chanx_left_out(cbx_1__0__1_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__0__1_chanx_right_out[0:19]), + .bottom_grid_pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), + .bottom_grid_pin_2_(cbx_1__0__1_bottom_grid_pin_2_[0]), + .bottom_grid_pin_4_(cbx_1__0__1_bottom_grid_pin_4_[0]), + .bottom_grid_pin_6_(cbx_1__0__1_bottom_grid_pin_6_[0]), + .bottom_grid_pin_8_(cbx_1__0__1_bottom_grid_pin_8_[0]), + .bottom_grid_pin_10_(cbx_1__0__1_bottom_grid_pin_10_[0]), + .ccff_tail(grid_io_bottom_1_ccff_tail[0]) + ); - cbx_1__2_ cbx_1__2_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_0__2__0_chanx_right_out[0:19]), - .chanx_right_in(sb_1__2__0_chanx_left_out[0:19]), - .ccff_head(sb_1__2__0_ccff_tail[0]), - .chanx_left_out(cbx_1__2__0_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__2__0_chanx_right_out[0:19]), - .top_grid_pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), - .ccff_tail(cbx_1__2__0_ccff_tail[0])); - cbx_1__2_ cbx_2__2_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_1__2__0_chanx_right_out[0:19]), - .chanx_right_in(sb_2__2__0_chanx_left_out[0:19]), - .ccff_head(sb_2__2__0_ccff_tail[0]), - .chanx_left_out(cbx_1__2__1_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__2__1_chanx_right_out[0:19]), - .top_grid_pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), - .ccff_tail(cbx_1__2__1_ccff_tail[0])); + cbx_1__1_ + cbx_1__1_ + ( + .SC_OUT_BOT(scff_Wires[3]), + .SC_IN_TOP(scff_Wires[2]), + .CLB_SC_OUT(sc_in_wires[0]), + .CLB_SC_IN(sc_out_wires[0]), + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_0__1__0_chanx_right_out[0:19]), + .chanx_right_in(sb_1__1__0_chanx_left_out[0:19]), + .ccff_head(sb_1__1__0_ccff_tail[0]), + .chanx_left_out(cbx_1__1__0_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__1__0_chanx_right_out[0:19]), + .bottom_grid_pin_0_(cbx_1__1__0_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__1__0_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__1__0_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__1__0_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__1__0_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__1__0_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__1__0_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__1__0_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__1__0_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__1__0_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__1__0_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__1__0_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__1__0_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__1__0_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__1__0_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__1__0_bottom_grid_pin_15_[0]), + .ccff_tail(cbx_1__1__0_ccff_tail[0]) + ); - cby_0__1_ cby_0__1_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_0__0__0_chany_top_out[0:19]), - .chany_top_in(sb_0__1__0_chany_bottom_out[0:19]), - .ccff_head(sb_0__1__0_ccff_tail[0]), - .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:19]), - .chany_top_out(cby_0__1__0_chany_top_out[0:19]), - .right_grid_pin_52_(cby_0__1__0_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_0__1__0_left_grid_pin_0_[0]), - .ccff_tail(cby_0__1__0_ccff_tail[0])); - cby_0__1_ cby_0__2_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_0__1__0_chany_top_out[0:19]), - .chany_top_in(sb_0__2__0_chany_bottom_out[0:19]), - .ccff_head(sb_0__2__0_ccff_tail[0]), - .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:19]), - .chany_top_out(cby_0__1__1_chany_top_out[0:19]), - .right_grid_pin_52_(cby_0__1__1_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_0__1__1_left_grid_pin_0_[0]), - .ccff_tail(cby_0__1__1_ccff_tail[0])); + cbx_1__1_ + cbx_2__1_ + ( + .SC_OUT_TOP(scff_Wires[10]), + .SC_IN_BOT(scff_Wires[9]), + .CLB_SC_OUT(sc_in_wires[1]), + .CLB_SC_IN(sc_out_wires[1]), + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_1__1__0_chanx_right_out[0:19]), + .chanx_right_in(sb_2__1__0_chanx_left_out[0:19]), + .ccff_head(sb_2__1__0_ccff_tail[0]), + .chanx_left_out(cbx_1__1__1_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__1__1_chanx_right_out[0:19]), + .bottom_grid_pin_0_(cbx_1__1__1_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__1__1_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__1__1_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__1__1_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__1__1_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__1__1_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__1__1_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__1__1_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__1__1_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__1__1_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__1__1_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__1__1_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__1__1_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__1__1_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__1__1_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__1__1_bottom_grid_pin_15_[0]), + .ccff_tail(cbx_1__1__1_ccff_tail[0]) + ); - cby_1__1_ cby_1__1_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_1__0__0_chany_top_out[0:19]), - .chany_top_in(sb_1__1__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_0_ccff_tail[0]), - .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__0_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__0_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__0_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__0_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__0_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__0_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__0_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__0_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__0_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__0_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__0_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__0_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__0_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__0_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__0_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__0_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__0_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__0_left_grid_pin_15_[0]), - .ccff_tail(cby_1__1__0_ccff_tail[0])); - cby_1__1_ cby_1__2_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_1__1__0_chany_top_out[0:19]), - .chany_top_in(sb_1__2__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_1_ccff_tail[0]), - .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__1_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__1_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__1_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__1_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__1_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__1_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__1_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__1_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__1_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__1_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__1_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__1_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__1_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__1_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__1_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__1_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__1_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__1_left_grid_pin_15_[0]), - .ccff_tail(cby_1__1__1_ccff_tail[0])); + cbx_1__2_ + cbx_1__2_ + ( + .SC_OUT_BOT(scff_Wires[1]), + .SC_IN_TOP(scff_Wires[0]), + .bottom_width_0_height_0__pin_1_lower(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), + .bottom_width_0_height_0__pin_1_upper(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .bottom_width_0_height_0__pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_0__2__0_chanx_right_out[0:19]), + .chanx_right_in(sb_1__2__0_chanx_left_out[0:19]), + .ccff_head(sb_1__2__0_ccff_tail[0]), + .chanx_left_out(cbx_1__2__0_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__2__0_chanx_right_out[0:19]), + .top_grid_pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), + .bottom_grid_pin_0_(cbx_1__2__0_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__2__0_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__2__0_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__2__0_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__2__0_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__2__0_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__2__0_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__2__0_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__2__0_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__2__0_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__2__0_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__2__0_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__2__0_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__2__0_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), + .ccff_tail(grid_io_top_0_ccff_tail[0]) + ); - cby_1__1_ cby_2__1_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_2__0__0_chany_top_out[0:19]), - .chany_top_in(sb_2__1__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_2_ccff_tail[0]), - .chany_bottom_out(cby_1__1__2_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__2_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__2_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__2_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__2_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__2_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__2_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__2_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__2_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__2_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__2_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__2_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__2_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__2_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__2_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__2_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__2_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__2_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__2_left_grid_pin_15_[0]), - .ccff_tail(cby_1__1__2_ccff_tail[0])); - cby_1__1_ cby_2__2_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_2__1__0_chany_top_out[0:19]), - .chany_top_in(sb_2__2__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_3_ccff_tail[0]), - .chany_bottom_out(cby_1__1__3_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__3_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__3_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__3_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__3_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__3_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__3_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__3_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__3_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__3_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__3_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__3_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__3_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__3_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__3_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__3_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__3_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__3_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__3_left_grid_pin_15_[0]), - .ccff_tail(cby_1__1__3_ccff_tail[0])); + cbx_1__2_ + cbx_2__2_ + ( + .SC_OUT_BOT(scff_Wires[12]), + .SC_IN_BOT(scff_Wires[11]), + .bottom_width_0_height_0__pin_1_lower(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .bottom_width_0_height_0__pin_1_upper(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .bottom_width_0_height_0__pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]), + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_1__2__0_chanx_right_out[0:19]), + .chanx_right_in(sb_2__2__0_chanx_left_out[0:19]), + .ccff_head(sb_2__2__0_ccff_tail[0]), + .chanx_left_out(cbx_1__2__1_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__2__1_chanx_right_out[0:19]), + .top_grid_pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), + .bottom_grid_pin_0_(cbx_1__2__1_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__2__1_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__2__1_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__2__1_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__2__1_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__2__1_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__2__1_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__2__1_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__2__1_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__2__1_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__2__1_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__2__1_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__2__1_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__2__1_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), + .ccff_tail(grid_io_top_1_ccff_tail[0]) + ); - direct_interc direct_interc_0_ ( - .in(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), - .out(direct_interc_0_out[0])); - direct_interc direct_interc_1_ ( - .in(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), - .out(direct_interc_1_out[0])); + cby_0__1_ + cby_0__1_ + ( + .right_width_0_height_0__pin_1_lower(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), + .right_width_0_height_0__pin_1_upper(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), + .right_width_0_height_0__pin_0_(cby_0__1__0_left_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[16]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[16]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[16]), + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_0__0__0_chany_top_out[0:19]), + .chany_top_in(sb_0__1__0_chany_bottom_out[0:19]), + .ccff_head(sb_0__1__0_ccff_tail[0]), + .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:19]), + .chany_top_out(cby_0__1__0_chany_top_out[0:19]), + .left_grid_pin_0_(cby_0__1__0_left_grid_pin_0_[0]), + .ccff_tail(grid_io_left_0_ccff_tail[0]) + ); - direct_interc direct_interc_2_ ( - .in(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), - .out(direct_interc_2_out[0])); - direct_interc direct_interc_3_ ( - .in(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), - .out(direct_interc_3_out[0])); + cby_0__1_ + cby_0__2_ + ( + .right_width_0_height_0__pin_1_lower(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), + .right_width_0_height_0__pin_1_upper(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), + .right_width_0_height_0__pin_0_(cby_0__1__1_left_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[17]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[17]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[17]), + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_0__1__0_chany_top_out[0:19]), + .chany_top_in(sb_0__2__0_chany_bottom_out[0:19]), + .ccff_head(sb_0__2__0_ccff_tail[0]), + .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:19]), + .chany_top_out(cby_0__1__1_chany_top_out[0:19]), + .left_grid_pin_0_(cby_0__1__1_left_grid_pin_0_[0]), + .ccff_tail(grid_io_left_1_ccff_tail[0]) + ); - direct_interc direct_interc_4_ ( - .in(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), - .out(direct_interc_4_out[0])); - direct_interc direct_interc_5_ ( - .in(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), - .out(direct_interc_5_out[0])); + cby_1__1_ + cby_1__1_ + ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_1__0__0_chany_top_out[0:19]), + .chany_top_in(sb_1__1__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_0_ccff_tail[0]), + .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:19]), + .chany_top_out(cby_1__1__0_chany_top_out[0:19]), + .left_grid_pin_16_(cby_1__1__0_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_1__1__0_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_1__1__0_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_1__1__0_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_1__1__0_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_1__1__0_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_1__1__0_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_1__1__0_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_1__1__0_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_1__1__0_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_1__1__0_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_1__1__0_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_1__1__0_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_1__1__0_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_1__1__0_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_1__1__0_left_grid_pin_31_[0]), + .ccff_tail(cby_1__1__0_ccff_tail[0]) + ); + + + cby_1__1_ + cby_1__2_ + ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_1__1__0_chany_top_out[0:19]), + .chany_top_in(sb_1__2__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_1_ccff_tail[0]), + .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:19]), + .chany_top_out(cby_1__1__1_chany_top_out[0:19]), + .left_grid_pin_16_(cby_1__1__1_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_1__1__1_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_1__1__1_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_1__1__1_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_1__1__1_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_1__1__1_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_1__1__1_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_1__1__1_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_1__1__1_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_1__1__1_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_1__1__1_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_1__1__1_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_1__1__1_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_1__1__1_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_1__1__1_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_1__1__1_left_grid_pin_31_[0]), + .ccff_tail(cby_1__1__1_ccff_tail[0]) + ); + + + cby_2__1_ + cby_2__1_ + ( + .left_width_0_height_0__pin_1_lower(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), + .left_width_0_height_0__pin_1_upper(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), + .left_width_0_height_0__pin_0_(cby_2__1__0_right_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]), + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_2__0__0_chany_top_out[0:19]), + .chany_top_in(sb_2__1__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_2_ccff_tail[0]), + .chany_bottom_out(cby_2__1__0_chany_bottom_out[0:19]), + .chany_top_out(cby_2__1__0_chany_top_out[0:19]), + .right_grid_pin_0_(cby_2__1__0_right_grid_pin_0_[0]), + .left_grid_pin_16_(cby_2__1__0_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_2__1__0_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_2__1__0_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_2__1__0_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_2__1__0_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_2__1__0_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_2__1__0_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_2__1__0_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_2__1__0_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_2__1__0_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_2__1__0_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_2__1__0_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_2__1__0_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_2__1__0_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_2__1__0_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_2__1__0_left_grid_pin_31_[0]), + .ccff_tail(grid_io_right_0_ccff_tail[0]) + ); + + + cby_2__1_ + cby_2__2_ + ( + .left_width_0_height_0__pin_1_lower(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), + .left_width_0_height_0__pin_1_upper(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), + .left_width_0_height_0__pin_0_(cby_2__1__1_right_grid_pin_0_[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]), + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_2__1__0_chany_top_out[0:19]), + .chany_top_in(sb_2__2__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_3_ccff_tail[0]), + .chany_bottom_out(cby_2__1__1_chany_bottom_out[0:19]), + .chany_top_out(cby_2__1__1_chany_top_out[0:19]), + .right_grid_pin_0_(cby_2__1__1_right_grid_pin_0_[0]), + .left_grid_pin_16_(cby_2__1__1_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_2__1__1_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_2__1__1_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_2__1__1_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_2__1__1_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_2__1__1_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_2__1__1_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_2__1__1_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_2__1__1_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_2__1__1_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_2__1__1_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_2__1__1_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_2__1__1_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_2__1__1_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_2__1__1_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_2__1__1_left_grid_pin_31_[0]), + .ccff_tail(grid_io_right_1_ccff_tail[0]) + ); + + + direct_interc + direct_interc_0_ + ( + .in(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), + .out(direct_interc_0_out[0]) + ); + + + direct_interc + direct_interc_1_ + ( + .in(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), + .out(direct_interc_1_out[0]) + ); + + + direct_interc + direct_interc_2_ + ( + .in(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), + .out(direct_interc_2_out[0]) + ); + + + direct_interc + direct_interc_3_ + ( + .in(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), + .out(direct_interc_3_out[0]) + ); + + + direct_interc + direct_interc_4_ + ( + .in(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), + .out(direct_interc_4_out[0]) + ); + + + direct_interc + direct_interc_5_ + ( + .in(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), + .out(direct_interc_5_out[0]) + ); + endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v index 5ccd1a3..b283491 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v @@ -9,14 +9,14 @@ `timescale 1ns / 1ps // -module fpga_topfpga_top(prog_clk, Test_en, clk, gfpga_pad_GPIO_A, gfpga_pad_GPIO_IE, gfpga_pad_GPIO_OE, gfpga_pad_GPIO_Y, ccff_head, ccff_tail); prog_clk; - Test_en; - clk; - gfpga_pad_GPIO_A; - gfpga_pad_GPIO_IE; - gfpga_pad_GPIO_OE; - gfpga_pad_GPIO_Y; - ccff_head;; +module fpga_top(prog_clk, + Test_en, + clk, + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, + ccff_head, + ccff_tail); // input [0:0] prog_clk; // @@ -24,13 +24,11 @@ input [0:0] Test_en; // input [0:0] clk; // -output [0:7] gfpga_pad_GPIO_A; +input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:7] gfpga_pad_GPIO_IE; +output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:7] gfpga_pad_GPIO_OE; -// -inout [0:7] gfpga_pad_GPIO_Y; +output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] ccff_head; // @@ -45,87 +43,97 @@ output [0:0] ccff_tail; wire [0:0] cbx_1__0__0_bottom_grid_pin_0_; +wire [0:0] cbx_1__0__0_bottom_grid_pin_10_; +wire [0:0] cbx_1__0__0_bottom_grid_pin_2_; +wire [0:0] cbx_1__0__0_bottom_grid_pin_4_; +wire [0:0] cbx_1__0__0_bottom_grid_pin_6_; +wire [0:0] cbx_1__0__0_bottom_grid_pin_8_; wire [0:0] cbx_1__0__0_ccff_tail; wire [0:19] cbx_1__0__0_chanx_left_out; wire [0:19] cbx_1__0__0_chanx_right_out; -wire [0:0] cbx_1__0__0_top_grid_pin_16_; -wire [0:0] cbx_1__0__0_top_grid_pin_17_; -wire [0:0] cbx_1__0__0_top_grid_pin_18_; -wire [0:0] cbx_1__0__0_top_grid_pin_19_; -wire [0:0] cbx_1__0__0_top_grid_pin_20_; -wire [0:0] cbx_1__0__0_top_grid_pin_21_; -wire [0:0] cbx_1__0__0_top_grid_pin_22_; -wire [0:0] cbx_1__0__0_top_grid_pin_23_; -wire [0:0] cbx_1__0__0_top_grid_pin_24_; -wire [0:0] cbx_1__0__0_top_grid_pin_25_; -wire [0:0] cbx_1__0__0_top_grid_pin_26_; -wire [0:0] cbx_1__0__0_top_grid_pin_27_; -wire [0:0] cbx_1__0__0_top_grid_pin_28_; -wire [0:0] cbx_1__0__0_top_grid_pin_29_; -wire [0:0] cbx_1__0__0_top_grid_pin_30_; -wire [0:0] cbx_1__0__0_top_grid_pin_31_; wire [0:0] cbx_1__0__1_bottom_grid_pin_0_; +wire [0:0] cbx_1__0__1_bottom_grid_pin_10_; +wire [0:0] cbx_1__0__1_bottom_grid_pin_2_; +wire [0:0] cbx_1__0__1_bottom_grid_pin_4_; +wire [0:0] cbx_1__0__1_bottom_grid_pin_6_; +wire [0:0] cbx_1__0__1_bottom_grid_pin_8_; wire [0:0] cbx_1__0__1_ccff_tail; wire [0:19] cbx_1__0__1_chanx_left_out; wire [0:19] cbx_1__0__1_chanx_right_out; -wire [0:0] cbx_1__0__1_top_grid_pin_16_; -wire [0:0] cbx_1__0__1_top_grid_pin_17_; -wire [0:0] cbx_1__0__1_top_grid_pin_18_; -wire [0:0] cbx_1__0__1_top_grid_pin_19_; -wire [0:0] cbx_1__0__1_top_grid_pin_20_; -wire [0:0] cbx_1__0__1_top_grid_pin_21_; -wire [0:0] cbx_1__0__1_top_grid_pin_22_; -wire [0:0] cbx_1__0__1_top_grid_pin_23_; -wire [0:0] cbx_1__0__1_top_grid_pin_24_; -wire [0:0] cbx_1__0__1_top_grid_pin_25_; -wire [0:0] cbx_1__0__1_top_grid_pin_26_; -wire [0:0] cbx_1__0__1_top_grid_pin_27_; -wire [0:0] cbx_1__0__1_top_grid_pin_28_; -wire [0:0] cbx_1__0__1_top_grid_pin_29_; -wire [0:0] cbx_1__0__1_top_grid_pin_30_; -wire [0:0] cbx_1__0__1_top_grid_pin_31_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_0_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_10_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_11_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_12_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_13_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_14_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_15_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_1_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_2_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_3_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_4_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_5_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_6_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_7_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_8_; +wire [0:0] cbx_1__1__0_bottom_grid_pin_9_; wire [0:0] cbx_1__1__0_ccff_tail; wire [0:19] cbx_1__1__0_chanx_left_out; wire [0:19] cbx_1__1__0_chanx_right_out; -wire [0:0] cbx_1__1__0_top_grid_pin_16_; -wire [0:0] cbx_1__1__0_top_grid_pin_17_; -wire [0:0] cbx_1__1__0_top_grid_pin_18_; -wire [0:0] cbx_1__1__0_top_grid_pin_19_; -wire [0:0] cbx_1__1__0_top_grid_pin_20_; -wire [0:0] cbx_1__1__0_top_grid_pin_21_; -wire [0:0] cbx_1__1__0_top_grid_pin_22_; -wire [0:0] cbx_1__1__0_top_grid_pin_23_; -wire [0:0] cbx_1__1__0_top_grid_pin_24_; -wire [0:0] cbx_1__1__0_top_grid_pin_25_; -wire [0:0] cbx_1__1__0_top_grid_pin_26_; -wire [0:0] cbx_1__1__0_top_grid_pin_27_; -wire [0:0] cbx_1__1__0_top_grid_pin_28_; -wire [0:0] cbx_1__1__0_top_grid_pin_29_; -wire [0:0] cbx_1__1__0_top_grid_pin_30_; -wire [0:0] cbx_1__1__0_top_grid_pin_31_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_0_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_10_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_11_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_12_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_13_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_14_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_15_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_1_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_2_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_3_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_4_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_5_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_6_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_7_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_8_; +wire [0:0] cbx_1__1__1_bottom_grid_pin_9_; wire [0:0] cbx_1__1__1_ccff_tail; wire [0:19] cbx_1__1__1_chanx_left_out; wire [0:19] cbx_1__1__1_chanx_right_out; -wire [0:0] cbx_1__1__1_top_grid_pin_16_; -wire [0:0] cbx_1__1__1_top_grid_pin_17_; -wire [0:0] cbx_1__1__1_top_grid_pin_18_; -wire [0:0] cbx_1__1__1_top_grid_pin_19_; -wire [0:0] cbx_1__1__1_top_grid_pin_20_; -wire [0:0] cbx_1__1__1_top_grid_pin_21_; -wire [0:0] cbx_1__1__1_top_grid_pin_22_; -wire [0:0] cbx_1__1__1_top_grid_pin_23_; -wire [0:0] cbx_1__1__1_top_grid_pin_24_; -wire [0:0] cbx_1__1__1_top_grid_pin_25_; -wire [0:0] cbx_1__1__1_top_grid_pin_26_; -wire [0:0] cbx_1__1__1_top_grid_pin_27_; -wire [0:0] cbx_1__1__1_top_grid_pin_28_; -wire [0:0] cbx_1__1__1_top_grid_pin_29_; -wire [0:0] cbx_1__1__1_top_grid_pin_30_; -wire [0:0] cbx_1__1__1_top_grid_pin_31_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_0_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_10_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_11_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_12_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_13_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_14_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_15_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_1_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_2_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_3_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_4_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_5_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_6_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_7_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_8_; +wire [0:0] cbx_1__2__0_bottom_grid_pin_9_; wire [0:0] cbx_1__2__0_ccff_tail; wire [0:19] cbx_1__2__0_chanx_left_out; wire [0:19] cbx_1__2__0_chanx_right_out; wire [0:0] cbx_1__2__0_top_grid_pin_0_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_0_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_10_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_11_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_12_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_13_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_14_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_15_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_1_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_2_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_3_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_4_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_5_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_6_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_7_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_8_; +wire [0:0] cbx_1__2__1_bottom_grid_pin_9_; wire [0:0] cbx_1__2__1_ccff_tail; wire [0:19] cbx_1__2__1_chanx_left_out; wire [0:19] cbx_1__2__1_chanx_right_out; @@ -134,264 +142,284 @@ wire [0:0] cby_0__1__0_ccff_tail; wire [0:19] cby_0__1__0_chany_bottom_out; wire [0:19] cby_0__1__0_chany_top_out; wire [0:0] cby_0__1__0_left_grid_pin_0_; -wire [0:0] cby_0__1__0_right_grid_pin_52_; wire [0:0] cby_0__1__1_ccff_tail; wire [0:19] cby_0__1__1_chany_bottom_out; wire [0:19] cby_0__1__1_chany_top_out; wire [0:0] cby_0__1__1_left_grid_pin_0_; -wire [0:0] cby_0__1__1_right_grid_pin_52_; wire [0:0] cby_1__1__0_ccff_tail; wire [0:19] cby_1__1__0_chany_bottom_out; wire [0:19] cby_1__1__0_chany_top_out; -wire [0:0] cby_1__1__0_left_grid_pin_0_; -wire [0:0] cby_1__1__0_left_grid_pin_10_; -wire [0:0] cby_1__1__0_left_grid_pin_11_; -wire [0:0] cby_1__1__0_left_grid_pin_12_; -wire [0:0] cby_1__1__0_left_grid_pin_13_; -wire [0:0] cby_1__1__0_left_grid_pin_14_; -wire [0:0] cby_1__1__0_left_grid_pin_15_; -wire [0:0] cby_1__1__0_left_grid_pin_1_; -wire [0:0] cby_1__1__0_left_grid_pin_2_; -wire [0:0] cby_1__1__0_left_grid_pin_3_; -wire [0:0] cby_1__1__0_left_grid_pin_4_; -wire [0:0] cby_1__1__0_left_grid_pin_5_; -wire [0:0] cby_1__1__0_left_grid_pin_6_; -wire [0:0] cby_1__1__0_left_grid_pin_7_; -wire [0:0] cby_1__1__0_left_grid_pin_8_; -wire [0:0] cby_1__1__0_left_grid_pin_9_; -wire [0:0] cby_1__1__0_right_grid_pin_52_; +wire [0:0] cby_1__1__0_left_grid_pin_16_; +wire [0:0] cby_1__1__0_left_grid_pin_17_; +wire [0:0] cby_1__1__0_left_grid_pin_18_; +wire [0:0] cby_1__1__0_left_grid_pin_19_; +wire [0:0] cby_1__1__0_left_grid_pin_20_; +wire [0:0] cby_1__1__0_left_grid_pin_21_; +wire [0:0] cby_1__1__0_left_grid_pin_22_; +wire [0:0] cby_1__1__0_left_grid_pin_23_; +wire [0:0] cby_1__1__0_left_grid_pin_24_; +wire [0:0] cby_1__1__0_left_grid_pin_25_; +wire [0:0] cby_1__1__0_left_grid_pin_26_; +wire [0:0] cby_1__1__0_left_grid_pin_27_; +wire [0:0] cby_1__1__0_left_grid_pin_28_; +wire [0:0] cby_1__1__0_left_grid_pin_29_; +wire [0:0] cby_1__1__0_left_grid_pin_30_; +wire [0:0] cby_1__1__0_left_grid_pin_31_; wire [0:0] cby_1__1__1_ccff_tail; wire [0:19] cby_1__1__1_chany_bottom_out; wire [0:19] cby_1__1__1_chany_top_out; -wire [0:0] cby_1__1__1_left_grid_pin_0_; -wire [0:0] cby_1__1__1_left_grid_pin_10_; -wire [0:0] cby_1__1__1_left_grid_pin_11_; -wire [0:0] cby_1__1__1_left_grid_pin_12_; -wire [0:0] cby_1__1__1_left_grid_pin_13_; -wire [0:0] cby_1__1__1_left_grid_pin_14_; -wire [0:0] cby_1__1__1_left_grid_pin_15_; -wire [0:0] cby_1__1__1_left_grid_pin_1_; -wire [0:0] cby_1__1__1_left_grid_pin_2_; -wire [0:0] cby_1__1__1_left_grid_pin_3_; -wire [0:0] cby_1__1__1_left_grid_pin_4_; -wire [0:0] cby_1__1__1_left_grid_pin_5_; -wire [0:0] cby_1__1__1_left_grid_pin_6_; -wire [0:0] cby_1__1__1_left_grid_pin_7_; -wire [0:0] cby_1__1__1_left_grid_pin_8_; -wire [0:0] cby_1__1__1_left_grid_pin_9_; -wire [0:0] cby_1__1__1_right_grid_pin_52_; -wire [0:0] cby_1__1__2_ccff_tail; -wire [0:19] cby_1__1__2_chany_bottom_out; -wire [0:19] cby_1__1__2_chany_top_out; -wire [0:0] cby_1__1__2_left_grid_pin_0_; -wire [0:0] cby_1__1__2_left_grid_pin_10_; -wire [0:0] cby_1__1__2_left_grid_pin_11_; -wire [0:0] cby_1__1__2_left_grid_pin_12_; -wire [0:0] cby_1__1__2_left_grid_pin_13_; -wire [0:0] cby_1__1__2_left_grid_pin_14_; -wire [0:0] cby_1__1__2_left_grid_pin_15_; -wire [0:0] cby_1__1__2_left_grid_pin_1_; -wire [0:0] cby_1__1__2_left_grid_pin_2_; -wire [0:0] cby_1__1__2_left_grid_pin_3_; -wire [0:0] cby_1__1__2_left_grid_pin_4_; -wire [0:0] cby_1__1__2_left_grid_pin_5_; -wire [0:0] cby_1__1__2_left_grid_pin_6_; -wire [0:0] cby_1__1__2_left_grid_pin_7_; -wire [0:0] cby_1__1__2_left_grid_pin_8_; -wire [0:0] cby_1__1__2_left_grid_pin_9_; -wire [0:0] cby_1__1__2_right_grid_pin_52_; -wire [0:0] cby_1__1__3_ccff_tail; -wire [0:19] cby_1__1__3_chany_bottom_out; -wire [0:19] cby_1__1__3_chany_top_out; -wire [0:0] cby_1__1__3_left_grid_pin_0_; -wire [0:0] cby_1__1__3_left_grid_pin_10_; -wire [0:0] cby_1__1__3_left_grid_pin_11_; -wire [0:0] cby_1__1__3_left_grid_pin_12_; -wire [0:0] cby_1__1__3_left_grid_pin_13_; -wire [0:0] cby_1__1__3_left_grid_pin_14_; -wire [0:0] cby_1__1__3_left_grid_pin_15_; -wire [0:0] cby_1__1__3_left_grid_pin_1_; -wire [0:0] cby_1__1__3_left_grid_pin_2_; -wire [0:0] cby_1__1__3_left_grid_pin_3_; -wire [0:0] cby_1__1__3_left_grid_pin_4_; -wire [0:0] cby_1__1__3_left_grid_pin_5_; -wire [0:0] cby_1__1__3_left_grid_pin_6_; -wire [0:0] cby_1__1__3_left_grid_pin_7_; -wire [0:0] cby_1__1__3_left_grid_pin_8_; -wire [0:0] cby_1__1__3_left_grid_pin_9_; -wire [0:0] cby_1__1__3_right_grid_pin_52_; +wire [0:0] cby_1__1__1_left_grid_pin_16_; +wire [0:0] cby_1__1__1_left_grid_pin_17_; +wire [0:0] cby_1__1__1_left_grid_pin_18_; +wire [0:0] cby_1__1__1_left_grid_pin_19_; +wire [0:0] cby_1__1__1_left_grid_pin_20_; +wire [0:0] cby_1__1__1_left_grid_pin_21_; +wire [0:0] cby_1__1__1_left_grid_pin_22_; +wire [0:0] cby_1__1__1_left_grid_pin_23_; +wire [0:0] cby_1__1__1_left_grid_pin_24_; +wire [0:0] cby_1__1__1_left_grid_pin_25_; +wire [0:0] cby_1__1__1_left_grid_pin_26_; +wire [0:0] cby_1__1__1_left_grid_pin_27_; +wire [0:0] cby_1__1__1_left_grid_pin_28_; +wire [0:0] cby_1__1__1_left_grid_pin_29_; +wire [0:0] cby_1__1__1_left_grid_pin_30_; +wire [0:0] cby_1__1__1_left_grid_pin_31_; +wire [0:0] cby_2__1__0_ccff_tail; +wire [0:19] cby_2__1__0_chany_bottom_out; +wire [0:19] cby_2__1__0_chany_top_out; +wire [0:0] cby_2__1__0_left_grid_pin_16_; +wire [0:0] cby_2__1__0_left_grid_pin_17_; +wire [0:0] cby_2__1__0_left_grid_pin_18_; +wire [0:0] cby_2__1__0_left_grid_pin_19_; +wire [0:0] cby_2__1__0_left_grid_pin_20_; +wire [0:0] cby_2__1__0_left_grid_pin_21_; +wire [0:0] cby_2__1__0_left_grid_pin_22_; +wire [0:0] cby_2__1__0_left_grid_pin_23_; +wire [0:0] cby_2__1__0_left_grid_pin_24_; +wire [0:0] cby_2__1__0_left_grid_pin_25_; +wire [0:0] cby_2__1__0_left_grid_pin_26_; +wire [0:0] cby_2__1__0_left_grid_pin_27_; +wire [0:0] cby_2__1__0_left_grid_pin_28_; +wire [0:0] cby_2__1__0_left_grid_pin_29_; +wire [0:0] cby_2__1__0_left_grid_pin_30_; +wire [0:0] cby_2__1__0_left_grid_pin_31_; +wire [0:0] cby_2__1__0_right_grid_pin_0_; +wire [0:0] cby_2__1__1_ccff_tail; +wire [0:19] cby_2__1__1_chany_bottom_out; +wire [0:19] cby_2__1__1_chany_top_out; +wire [0:0] cby_2__1__1_left_grid_pin_16_; +wire [0:0] cby_2__1__1_left_grid_pin_17_; +wire [0:0] cby_2__1__1_left_grid_pin_18_; +wire [0:0] cby_2__1__1_left_grid_pin_19_; +wire [0:0] cby_2__1__1_left_grid_pin_20_; +wire [0:0] cby_2__1__1_left_grid_pin_21_; +wire [0:0] cby_2__1__1_left_grid_pin_22_; +wire [0:0] cby_2__1__1_left_grid_pin_23_; +wire [0:0] cby_2__1__1_left_grid_pin_24_; +wire [0:0] cby_2__1__1_left_grid_pin_25_; +wire [0:0] cby_2__1__1_left_grid_pin_26_; +wire [0:0] cby_2__1__1_left_grid_pin_27_; +wire [0:0] cby_2__1__1_left_grid_pin_28_; +wire [0:0] cby_2__1__1_left_grid_pin_29_; +wire [0:0] cby_2__1__1_left_grid_pin_30_; +wire [0:0] cby_2__1__1_left_grid_pin_31_; +wire [0:0] cby_2__1__1_right_grid_pin_0_; wire [0:0] direct_interc_0_out; wire [0:0] direct_interc_1_out; wire [0:0] direct_interc_2_out; wire [0:0] direct_interc_3_out; wire [0:0] direct_interc_4_out; wire [0:0] direct_interc_5_out; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_upper; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_; wire [0:0] grid_clb_0_ccff_tail; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper; +wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_; +wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_upper; wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_; wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_; wire [0:0] grid_clb_1_ccff_tail; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_; +wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_; wire [0:0] grid_clb_2_ccff_tail; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper; wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_; wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_; wire [0:0] grid_clb_3_ccff_tail; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_upper; -wire [0:0] grid_io_bottom_0_ccff_tail; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_bottom_1_ccff_tail; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_left_0_ccff_tail; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_left_1_ccff_tail; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_right_0_ccff_tail; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_right_1_ccff_tail; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_0_ccff_tail; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_1_ccff_tail; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper; +wire [0:0] grid_io_bottom_bottom_0_ccff_tail; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_lower; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_upper; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_lower; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_upper; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_lower; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_upper; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_lower; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_upper; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_lower; +wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_upper; +wire [0:0] grid_io_bottom_bottom_1_ccff_tail; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_lower; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_upper; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_lower; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_upper; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_lower; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_upper; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_lower; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_upper; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_lower; +wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_upper; +wire [0:0] grid_io_left_left_0_ccff_tail; +wire [0:0] grid_io_left_left_0_right_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_left_left_0_right_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_left_left_1_ccff_tail; +wire [0:0] grid_io_left_left_1_right_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_left_left_1_right_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_right_right_0_ccff_tail; +wire [0:0] grid_io_right_right_0_left_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_right_right_0_left_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_right_right_1_ccff_tail; +wire [0:0] grid_io_right_right_1_left_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_right_right_1_left_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_top_top_0_bottom_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_top_top_0_bottom_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_top_top_0_ccff_tail; +wire [0:0] grid_io_top_top_1_bottom_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_top_top_1_bottom_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_top_top_1_ccff_tail; wire [0:19] sb_0__0__0_chanx_right_out; wire [0:19] sb_0__0__0_chany_top_out; wire [0:0] sb_0__1__0_ccff_tail; @@ -434,74 +462,74 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__1__0_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__1__0_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__1__0_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__1__0_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__1__0_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__1__0_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__1__0_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__1__0_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__1__0_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__1__0_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__1__0_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__1__0_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__1__0_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__1__0_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__1__0_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__1__0_bottom_grid_pin_15_[0]), .top_width_0_height_0__pin_32_(direct_interc_0_out[0]), .top_width_0_height_0__pin_33_(direct_interc_3_out[0]), - .right_width_0_height_0__pin_0_(cby_1__1__0_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__0_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__0_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__0_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__0_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__0_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__0_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__0_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__0_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__0_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__0_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__0_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__0_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__0_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__0_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__0_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__0__0_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__0__0_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__0__0_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__0__0_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__0__0_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__0__0_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__0__0_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__0__0_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__0__0_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__0__0_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__0__0_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__0__0_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__0__0_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__0__0_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__0__0_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__0__0_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_0__1__0_right_grid_pin_52_[0]), - .ccff_head(grid_io_left_0_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_0_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_0_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_0_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_0_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_0_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_0_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_0_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_0_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_0_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_0_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_0_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_0_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_0_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_0_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_0_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_0_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_0_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_0_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_0_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_0_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_0_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_0_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_0_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_0_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_0_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_0_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_0_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_0_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_0_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_0_bottom_width_0_height_0__pin_49_lower[0]), + .right_width_0_height_0__pin_16_(cby_1__1__0_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_1__1__0_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_1__1__0_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_1__1__0_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_1__1__0_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_1__1__0_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_1__1__0_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_1__1__0_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_1__1__0_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_1__1__0_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_1__1__0_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_1__1__0_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_1__1__0_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_1__1__0_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_1__1__0_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_1__1__0_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_1__1__undriven_left_width_0_height_0__pin_52_[0]), + .ccff_head(grid_io_left_left_0_ccff_tail[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_0_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_0_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_0_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_0_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_0_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_0_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_0_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_0_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_0_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_0_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_0_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_0_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_0_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_0_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_0_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_0_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_0_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_0_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_0_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_0_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_0_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_0_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_0_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_0_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_0_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_0_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_0_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_0_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_0_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_0_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), .bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), .bottom_width_0_height_0__pin_51_(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), .ccff_tail(grid_clb_0_ccff_tail[0])); @@ -510,74 +538,74 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__2__0_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__2__0_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__2__0_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__2__0_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__2__0_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__2__0_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__2__0_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__2__0_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__2__0_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__2__0_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__2__0_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__2__0_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__2__0_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__2__0_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), .top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]), .top_width_0_height_0__pin_33_(grid_clb_1__2__undriven_top_width_0_height_0__pin_33_[0]), - .right_width_0_height_0__pin_0_(cby_1__1__1_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__1_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__1_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__1_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__1_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__1_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__1_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__1_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__1_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__1_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__1_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__1_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__1_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__1_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__1_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__1_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__1__0_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__1__0_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__1__0_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__1__0_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__1__0_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__1__0_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__1__0_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__1__0_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__1__0_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__1__0_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__1__0_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__1__0_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__1__0_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__1__0_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__1__0_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__1__0_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_0__1__1_right_grid_pin_52_[0]), - .ccff_head(grid_io_left_1_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_1_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_1_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_1_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_1_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_1_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_1_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_1_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_1_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_1_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_1_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_1_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_1_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_1_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_1_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_1_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_1_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_1_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_1_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_1_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_1_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_1_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_1_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_1_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_1_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_1_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_1_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_1_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_1_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_1_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_1_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_1_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_1_bottom_width_0_height_0__pin_49_lower[0]), + .right_width_0_height_0__pin_16_(cby_1__1__1_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_1__1__1_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_1__1__1_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_1__1__1_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_1__1__1_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_1__1__1_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_1__1__1_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_1__1__1_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_1__1__1_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_1__1__1_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_1__1__1_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_1__1__1_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_1__1__1_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_1__1__1_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_1__1__1_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_1__1__1_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_1__2__undriven_left_width_0_height_0__pin_52_[0]), + .ccff_head(grid_io_left_left_1_ccff_tail[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_1_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_1_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_1_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_1_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_1_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_1_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_1_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_1_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_1_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_1_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_1_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_1_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_1_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_1_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_1_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_1_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_1_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_1_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_1_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_1_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_1_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_1_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_1_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_1_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_1_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_1_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_1_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_1_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_1_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_1_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_1_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_1_right_width_0_height_0__pin_49_lower[0]), .bottom_width_0_height_0__pin_50_(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), .bottom_width_0_height_0__pin_51_(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), .ccff_tail(grid_clb_1_ccff_tail[0])); @@ -586,74 +614,74 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__1__1_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__1__1_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__1__1_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__1__1_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__1__1_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__1__1_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__1__1_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__1__1_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__1__1_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__1__1_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__1__1_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__1__1_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__1__1_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__1__1_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__1__1_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__1__1_bottom_grid_pin_15_[0]), .top_width_0_height_0__pin_32_(direct_interc_1_out[0]), .top_width_0_height_0__pin_33_(direct_interc_4_out[0]), - .right_width_0_height_0__pin_0_(cby_1__1__2_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__2_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__2_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__2_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__2_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__2_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__2_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__2_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__2_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__2_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__2_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__2_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__2_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__2_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__2_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__2_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__0__1_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__0__1_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__0__1_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__0__1_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__0__1_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__0__1_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__0__1_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__0__1_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__0__1_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__0__1_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__0__1_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__0__1_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__0__1_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__0__1_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__0__1_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__0__1_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_1__1__0_right_grid_pin_52_[0]), + .right_width_0_height_0__pin_16_(cby_2__1__0_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_2__1__0_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_2__1__0_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_2__1__0_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_2__1__0_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_2__1__0_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_2__1__0_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_2__1__0_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_2__1__0_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_2__1__0_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_2__1__0_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_2__1__0_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_2__1__0_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_2__1__0_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_2__1__0_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_2__1__0_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_2__1__undriven_left_width_0_height_0__pin_52_[0]), .ccff_head(cby_1__1__0_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_2_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_2_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_2_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_2_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_2_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_2_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_2_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_2_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_2_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_2_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_2_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_2_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_2_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_2_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_2_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_2_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_2_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_2_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_2_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_2_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_2_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_2_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_2_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_2_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_2_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_2_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_2_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_2_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_2_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_2_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_2_bottom_width_0_height_0__pin_49_lower[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_2_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_2_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_2_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_2_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_2_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_2_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_2_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_2_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_2_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_2_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_2_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_2_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_2_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_2_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_2_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_2_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_2_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_2_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_2_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_2_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_2_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_2_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_2_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_2_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_2_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_2_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_2_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_2_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_2_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_2_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), .bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]), .bottom_width_0_height_0__pin_51_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_[0]), .ccff_tail(grid_clb_2_ccff_tail[0])); @@ -662,189 +690,208 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), + .top_width_0_height_0__pin_0_(cbx_1__2__1_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_1_(cbx_1__2__1_bottom_grid_pin_1_[0]), + .top_width_0_height_0__pin_2_(cbx_1__2__1_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_3_(cbx_1__2__1_bottom_grid_pin_3_[0]), + .top_width_0_height_0__pin_4_(cbx_1__2__1_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_5_(cbx_1__2__1_bottom_grid_pin_5_[0]), + .top_width_0_height_0__pin_6_(cbx_1__2__1_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_7_(cbx_1__2__1_bottom_grid_pin_7_[0]), + .top_width_0_height_0__pin_8_(cbx_1__2__1_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_9_(cbx_1__2__1_bottom_grid_pin_9_[0]), + .top_width_0_height_0__pin_10_(cbx_1__2__1_bottom_grid_pin_10_[0]), + .top_width_0_height_0__pin_11_(cbx_1__2__1_bottom_grid_pin_11_[0]), + .top_width_0_height_0__pin_12_(cbx_1__2__1_bottom_grid_pin_12_[0]), + .top_width_0_height_0__pin_13_(cbx_1__2__1_bottom_grid_pin_13_[0]), + .top_width_0_height_0__pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), + .top_width_0_height_0__pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), .top_width_0_height_0__pin_32_(direct_interc_2_out[0]), .top_width_0_height_0__pin_33_(direct_interc_5_out[0]), - .right_width_0_height_0__pin_0_(cby_1__1__3_left_grid_pin_0_[0]), - .right_width_0_height_0__pin_1_(cby_1__1__3_left_grid_pin_1_[0]), - .right_width_0_height_0__pin_2_(cby_1__1__3_left_grid_pin_2_[0]), - .right_width_0_height_0__pin_3_(cby_1__1__3_left_grid_pin_3_[0]), - .right_width_0_height_0__pin_4_(cby_1__1__3_left_grid_pin_4_[0]), - .right_width_0_height_0__pin_5_(cby_1__1__3_left_grid_pin_5_[0]), - .right_width_0_height_0__pin_6_(cby_1__1__3_left_grid_pin_6_[0]), - .right_width_0_height_0__pin_7_(cby_1__1__3_left_grid_pin_7_[0]), - .right_width_0_height_0__pin_8_(cby_1__1__3_left_grid_pin_8_[0]), - .right_width_0_height_0__pin_9_(cby_1__1__3_left_grid_pin_9_[0]), - .right_width_0_height_0__pin_10_(cby_1__1__3_left_grid_pin_10_[0]), - .right_width_0_height_0__pin_11_(cby_1__1__3_left_grid_pin_11_[0]), - .right_width_0_height_0__pin_12_(cby_1__1__3_left_grid_pin_12_[0]), - .right_width_0_height_0__pin_13_(cby_1__1__3_left_grid_pin_13_[0]), - .right_width_0_height_0__pin_14_(cby_1__1__3_left_grid_pin_14_[0]), - .right_width_0_height_0__pin_15_(cby_1__1__3_left_grid_pin_15_[0]), - .bottom_width_0_height_0__pin_16_(cbx_1__1__1_top_grid_pin_16_[0]), - .bottom_width_0_height_0__pin_17_(cbx_1__1__1_top_grid_pin_17_[0]), - .bottom_width_0_height_0__pin_18_(cbx_1__1__1_top_grid_pin_18_[0]), - .bottom_width_0_height_0__pin_19_(cbx_1__1__1_top_grid_pin_19_[0]), - .bottom_width_0_height_0__pin_20_(cbx_1__1__1_top_grid_pin_20_[0]), - .bottom_width_0_height_0__pin_21_(cbx_1__1__1_top_grid_pin_21_[0]), - .bottom_width_0_height_0__pin_22_(cbx_1__1__1_top_grid_pin_22_[0]), - .bottom_width_0_height_0__pin_23_(cbx_1__1__1_top_grid_pin_23_[0]), - .bottom_width_0_height_0__pin_24_(cbx_1__1__1_top_grid_pin_24_[0]), - .bottom_width_0_height_0__pin_25_(cbx_1__1__1_top_grid_pin_25_[0]), - .bottom_width_0_height_0__pin_26_(cbx_1__1__1_top_grid_pin_26_[0]), - .bottom_width_0_height_0__pin_27_(cbx_1__1__1_top_grid_pin_27_[0]), - .bottom_width_0_height_0__pin_28_(cbx_1__1__1_top_grid_pin_28_[0]), - .bottom_width_0_height_0__pin_29_(cbx_1__1__1_top_grid_pin_29_[0]), - .bottom_width_0_height_0__pin_30_(cbx_1__1__1_top_grid_pin_30_[0]), - .bottom_width_0_height_0__pin_31_(cbx_1__1__1_top_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(cby_1__1__1_right_grid_pin_52_[0]), + .right_width_0_height_0__pin_16_(cby_2__1__1_left_grid_pin_16_[0]), + .right_width_0_height_0__pin_17_(cby_2__1__1_left_grid_pin_17_[0]), + .right_width_0_height_0__pin_18_(cby_2__1__1_left_grid_pin_18_[0]), + .right_width_0_height_0__pin_19_(cby_2__1__1_left_grid_pin_19_[0]), + .right_width_0_height_0__pin_20_(cby_2__1__1_left_grid_pin_20_[0]), + .right_width_0_height_0__pin_21_(cby_2__1__1_left_grid_pin_21_[0]), + .right_width_0_height_0__pin_22_(cby_2__1__1_left_grid_pin_22_[0]), + .right_width_0_height_0__pin_23_(cby_2__1__1_left_grid_pin_23_[0]), + .right_width_0_height_0__pin_24_(cby_2__1__1_left_grid_pin_24_[0]), + .right_width_0_height_0__pin_25_(cby_2__1__1_left_grid_pin_25_[0]), + .right_width_0_height_0__pin_26_(cby_2__1__1_left_grid_pin_26_[0]), + .right_width_0_height_0__pin_27_(cby_2__1__1_left_grid_pin_27_[0]), + .right_width_0_height_0__pin_28_(cby_2__1__1_left_grid_pin_28_[0]), + .right_width_0_height_0__pin_29_(cby_2__1__1_left_grid_pin_29_[0]), + .right_width_0_height_0__pin_30_(cby_2__1__1_left_grid_pin_30_[0]), + .right_width_0_height_0__pin_31_(cby_2__1__1_left_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(grid_clb_2__2__undriven_left_width_0_height_0__pin_52_[0]), .ccff_head(cby_1__1__1_ccff_tail[0]), - .right_width_0_height_0__pin_34_upper(grid_clb_3_right_width_0_height_0__pin_34_upper[0]), - .right_width_0_height_0__pin_34_lower(grid_clb_3_right_width_0_height_0__pin_34_lower[0]), - .right_width_0_height_0__pin_35_upper(grid_clb_3_right_width_0_height_0__pin_35_upper[0]), - .right_width_0_height_0__pin_35_lower(grid_clb_3_right_width_0_height_0__pin_35_lower[0]), - .right_width_0_height_0__pin_36_upper(grid_clb_3_right_width_0_height_0__pin_36_upper[0]), - .right_width_0_height_0__pin_36_lower(grid_clb_3_right_width_0_height_0__pin_36_lower[0]), - .right_width_0_height_0__pin_37_upper(grid_clb_3_right_width_0_height_0__pin_37_upper[0]), - .right_width_0_height_0__pin_37_lower(grid_clb_3_right_width_0_height_0__pin_37_lower[0]), - .right_width_0_height_0__pin_38_upper(grid_clb_3_right_width_0_height_0__pin_38_upper[0]), - .right_width_0_height_0__pin_38_lower(grid_clb_3_right_width_0_height_0__pin_38_lower[0]), - .right_width_0_height_0__pin_39_upper(grid_clb_3_right_width_0_height_0__pin_39_upper[0]), - .right_width_0_height_0__pin_39_lower(grid_clb_3_right_width_0_height_0__pin_39_lower[0]), - .right_width_0_height_0__pin_40_upper(grid_clb_3_right_width_0_height_0__pin_40_upper[0]), - .right_width_0_height_0__pin_40_lower(grid_clb_3_right_width_0_height_0__pin_40_lower[0]), - .right_width_0_height_0__pin_41_upper(grid_clb_3_right_width_0_height_0__pin_41_upper[0]), - .right_width_0_height_0__pin_41_lower(grid_clb_3_right_width_0_height_0__pin_41_lower[0]), - .bottom_width_0_height_0__pin_42_upper(grid_clb_3_bottom_width_0_height_0__pin_42_upper[0]), - .bottom_width_0_height_0__pin_42_lower(grid_clb_3_bottom_width_0_height_0__pin_42_lower[0]), - .bottom_width_0_height_0__pin_43_upper(grid_clb_3_bottom_width_0_height_0__pin_43_upper[0]), - .bottom_width_0_height_0__pin_43_lower(grid_clb_3_bottom_width_0_height_0__pin_43_lower[0]), - .bottom_width_0_height_0__pin_44_upper(grid_clb_3_bottom_width_0_height_0__pin_44_upper[0]), - .bottom_width_0_height_0__pin_44_lower(grid_clb_3_bottom_width_0_height_0__pin_44_lower[0]), - .bottom_width_0_height_0__pin_45_upper(grid_clb_3_bottom_width_0_height_0__pin_45_upper[0]), - .bottom_width_0_height_0__pin_45_lower(grid_clb_3_bottom_width_0_height_0__pin_45_lower[0]), - .bottom_width_0_height_0__pin_46_upper(grid_clb_3_bottom_width_0_height_0__pin_46_upper[0]), - .bottom_width_0_height_0__pin_46_lower(grid_clb_3_bottom_width_0_height_0__pin_46_lower[0]), - .bottom_width_0_height_0__pin_47_upper(grid_clb_3_bottom_width_0_height_0__pin_47_upper[0]), - .bottom_width_0_height_0__pin_47_lower(grid_clb_3_bottom_width_0_height_0__pin_47_lower[0]), - .bottom_width_0_height_0__pin_48_upper(grid_clb_3_bottom_width_0_height_0__pin_48_upper[0]), - .bottom_width_0_height_0__pin_48_lower(grid_clb_3_bottom_width_0_height_0__pin_48_lower[0]), - .bottom_width_0_height_0__pin_49_upper(grid_clb_3_bottom_width_0_height_0__pin_49_upper[0]), - .bottom_width_0_height_0__pin_49_lower(grid_clb_3_bottom_width_0_height_0__pin_49_lower[0]), + .top_width_0_height_0__pin_34_upper(grid_clb_3_top_width_0_height_0__pin_34_upper[0]), + .top_width_0_height_0__pin_34_lower(grid_clb_3_top_width_0_height_0__pin_34_lower[0]), + .top_width_0_height_0__pin_35_upper(grid_clb_3_top_width_0_height_0__pin_35_upper[0]), + .top_width_0_height_0__pin_35_lower(grid_clb_3_top_width_0_height_0__pin_35_lower[0]), + .top_width_0_height_0__pin_36_upper(grid_clb_3_top_width_0_height_0__pin_36_upper[0]), + .top_width_0_height_0__pin_36_lower(grid_clb_3_top_width_0_height_0__pin_36_lower[0]), + .top_width_0_height_0__pin_37_upper(grid_clb_3_top_width_0_height_0__pin_37_upper[0]), + .top_width_0_height_0__pin_37_lower(grid_clb_3_top_width_0_height_0__pin_37_lower[0]), + .top_width_0_height_0__pin_38_upper(grid_clb_3_top_width_0_height_0__pin_38_upper[0]), + .top_width_0_height_0__pin_38_lower(grid_clb_3_top_width_0_height_0__pin_38_lower[0]), + .top_width_0_height_0__pin_39_upper(grid_clb_3_top_width_0_height_0__pin_39_upper[0]), + .top_width_0_height_0__pin_39_lower(grid_clb_3_top_width_0_height_0__pin_39_lower[0]), + .top_width_0_height_0__pin_40_upper(grid_clb_3_top_width_0_height_0__pin_40_upper[0]), + .top_width_0_height_0__pin_40_lower(grid_clb_3_top_width_0_height_0__pin_40_lower[0]), + .top_width_0_height_0__pin_41_upper(grid_clb_3_top_width_0_height_0__pin_41_upper[0]), + .top_width_0_height_0__pin_41_lower(grid_clb_3_top_width_0_height_0__pin_41_lower[0]), + .right_width_0_height_0__pin_42_upper(grid_clb_3_right_width_0_height_0__pin_42_upper[0]), + .right_width_0_height_0__pin_42_lower(grid_clb_3_right_width_0_height_0__pin_42_lower[0]), + .right_width_0_height_0__pin_43_upper(grid_clb_3_right_width_0_height_0__pin_43_upper[0]), + .right_width_0_height_0__pin_43_lower(grid_clb_3_right_width_0_height_0__pin_43_lower[0]), + .right_width_0_height_0__pin_44_upper(grid_clb_3_right_width_0_height_0__pin_44_upper[0]), + .right_width_0_height_0__pin_44_lower(grid_clb_3_right_width_0_height_0__pin_44_lower[0]), + .right_width_0_height_0__pin_45_upper(grid_clb_3_right_width_0_height_0__pin_45_upper[0]), + .right_width_0_height_0__pin_45_lower(grid_clb_3_right_width_0_height_0__pin_45_lower[0]), + .right_width_0_height_0__pin_46_upper(grid_clb_3_right_width_0_height_0__pin_46_upper[0]), + .right_width_0_height_0__pin_46_lower(grid_clb_3_right_width_0_height_0__pin_46_lower[0]), + .right_width_0_height_0__pin_47_upper(grid_clb_3_right_width_0_height_0__pin_47_upper[0]), + .right_width_0_height_0__pin_47_lower(grid_clb_3_right_width_0_height_0__pin_47_lower[0]), + .right_width_0_height_0__pin_48_upper(grid_clb_3_right_width_0_height_0__pin_48_upper[0]), + .right_width_0_height_0__pin_48_lower(grid_clb_3_right_width_0_height_0__pin_48_lower[0]), + .right_width_0_height_0__pin_49_upper(grid_clb_3_right_width_0_height_0__pin_49_upper[0]), + .right_width_0_height_0__pin_49_lower(grid_clb_3_right_width_0_height_0__pin_49_lower[0]), .bottom_width_0_height_0__pin_50_(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), .bottom_width_0_height_0__pin_51_(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), .ccff_tail(grid_clb_3_ccff_tail[0])); - grid_io_top grid_io_top_1__3_ ( + grid_io_top_top grid_io_top_top_1__3_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), .bottom_width_0_height_0__pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), .ccff_head(cbx_1__2__0_ccff_tail[0]), - .bottom_width_0_height_0__pin_1_upper(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), - .bottom_width_0_height_0__pin_1_lower(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_top_0_ccff_tail[0])); + .bottom_width_0_height_0__pin_1_upper(grid_io_top_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .bottom_width_0_height_0__pin_1_lower(grid_io_top_top_0_bottom_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_top_top_0_ccff_tail[0])); - grid_io_top grid_io_top_2__3_ ( + grid_io_top_top grid_io_top_top_2__3_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[1]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[1]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[1]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[1]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), .bottom_width_0_height_0__pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), .ccff_head(cbx_1__2__1_ccff_tail[0]), - .bottom_width_0_height_0__pin_1_upper(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), - .bottom_width_0_height_0__pin_1_lower(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_top_1_ccff_tail[0])); + .bottom_width_0_height_0__pin_1_upper(grid_io_top_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .bottom_width_0_height_0__pin_1_lower(grid_io_top_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_top_top_1_ccff_tail[0])); - grid_io_right grid_io_right_3__1_ ( + grid_io_right_right grid_io_right_right_3__1_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[2]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[2]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[2]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[2]), - .left_width_0_height_0__pin_0_(cby_1__1__2_right_grid_pin_52_[0]), - .ccff_head(cby_1__1__2_ccff_tail[0]), - .left_width_0_height_0__pin_1_upper(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), - .left_width_0_height_0__pin_1_lower(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_right_0_ccff_tail[0])); + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), + .left_width_0_height_0__pin_0_(cby_2__1__0_right_grid_pin_0_[0]), + .ccff_head(cby_2__1__0_ccff_tail[0]), + .left_width_0_height_0__pin_1_upper(grid_io_right_right_0_left_width_0_height_0__pin_1_upper[0]), + .left_width_0_height_0__pin_1_lower(grid_io_right_right_0_left_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_right_right_0_ccff_tail[0])); - grid_io_right grid_io_right_3__2_ ( + grid_io_right_right grid_io_right_right_3__2_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[3]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[3]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[3]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[3]), - .left_width_0_height_0__pin_0_(cby_1__1__3_right_grid_pin_52_[0]), - .ccff_head(cby_1__1__3_ccff_tail[0]), - .left_width_0_height_0__pin_1_upper(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), - .left_width_0_height_0__pin_1_lower(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_right_1_ccff_tail[0])); + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), + .left_width_0_height_0__pin_0_(cby_2__1__1_right_grid_pin_0_[0]), + .ccff_head(cby_2__1__1_ccff_tail[0]), + .left_width_0_height_0__pin_1_upper(grid_io_right_right_1_left_width_0_height_0__pin_1_upper[0]), + .left_width_0_height_0__pin_1_lower(grid_io_right_right_1_left_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_right_right_1_ccff_tail[0])); - grid_io_bottom grid_io_bottom_1__0_ ( + grid_io_bottom_bottom grid_io_bottom_bottom_1__0_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[4]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[4]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[4]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[4]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4:9]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4:9]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4:9]), .top_width_0_height_0__pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_2_(cbx_1__0__0_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_4_(cbx_1__0__0_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_6_(cbx_1__0__0_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_8_(cbx_1__0__0_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_10_(cbx_1__0__0_bottom_grid_pin_10_[0]), .ccff_head(cbx_1__0__0_ccff_tail[0]), - .top_width_0_height_0__pin_1_upper(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), - .top_width_0_height_0__pin_1_lower(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_bottom_0_ccff_tail[0])); + .top_width_0_height_0__pin_1_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_upper[0]), + .top_width_0_height_0__pin_1_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_lower[0]), + .top_width_0_height_0__pin_3_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_upper[0]), + .top_width_0_height_0__pin_3_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_lower[0]), + .top_width_0_height_0__pin_5_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_upper[0]), + .top_width_0_height_0__pin_5_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_lower[0]), + .top_width_0_height_0__pin_7_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_upper[0]), + .top_width_0_height_0__pin_7_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_lower[0]), + .top_width_0_height_0__pin_9_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_upper[0]), + .top_width_0_height_0__pin_9_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_lower[0]), + .top_width_0_height_0__pin_11_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_upper[0]), + .top_width_0_height_0__pin_11_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_lower[0]), + .ccff_tail(grid_io_bottom_bottom_0_ccff_tail[0])); - grid_io_bottom grid_io_bottom_2__0_ ( + grid_io_bottom_bottom grid_io_bottom_bottom_2__0_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[5]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[5]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[5]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[5]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[10:15]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[10:15]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[10:15]), .top_width_0_height_0__pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), + .top_width_0_height_0__pin_2_(cbx_1__0__1_bottom_grid_pin_2_[0]), + .top_width_0_height_0__pin_4_(cbx_1__0__1_bottom_grid_pin_4_[0]), + .top_width_0_height_0__pin_6_(cbx_1__0__1_bottom_grid_pin_6_[0]), + .top_width_0_height_0__pin_8_(cbx_1__0__1_bottom_grid_pin_8_[0]), + .top_width_0_height_0__pin_10_(cbx_1__0__1_bottom_grid_pin_10_[0]), .ccff_head(cbx_1__0__1_ccff_tail[0]), - .top_width_0_height_0__pin_1_upper(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), - .top_width_0_height_0__pin_1_lower(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_bottom_1_ccff_tail[0])); + .top_width_0_height_0__pin_1_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .top_width_0_height_0__pin_1_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_lower[0]), + .top_width_0_height_0__pin_3_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_upper[0]), + .top_width_0_height_0__pin_3_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_lower[0]), + .top_width_0_height_0__pin_5_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_upper[0]), + .top_width_0_height_0__pin_5_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_lower[0]), + .top_width_0_height_0__pin_7_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_upper[0]), + .top_width_0_height_0__pin_7_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_lower[0]), + .top_width_0_height_0__pin_9_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_upper[0]), + .top_width_0_height_0__pin_9_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_lower[0]), + .top_width_0_height_0__pin_11_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_upper[0]), + .top_width_0_height_0__pin_11_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_lower[0]), + .ccff_tail(grid_io_bottom_bottom_1_ccff_tail[0])); - grid_io_left grid_io_left_0__1_ ( + grid_io_left_left grid_io_left_left_0__1_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[6]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[6]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[6]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[6]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[16]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[16]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[16]), .right_width_0_height_0__pin_0_(cby_0__1__0_left_grid_pin_0_[0]), .ccff_head(cby_0__1__0_ccff_tail[0]), - .right_width_0_height_0__pin_1_upper(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), - .right_width_0_height_0__pin_1_lower(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_left_0_ccff_tail[0])); + .right_width_0_height_0__pin_1_upper(grid_io_left_left_0_right_width_0_height_0__pin_1_upper[0]), + .right_width_0_height_0__pin_1_lower(grid_io_left_left_0_right_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_left_left_0_ccff_tail[0])); - grid_io_left grid_io_left_0__2_ ( + grid_io_left_left grid_io_left_left_0__2_ ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[7]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[7]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[7]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[7]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[17]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[17]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[17]), .right_width_0_height_0__pin_0_(cby_0__1__1_left_grid_pin_0_[0]), .ccff_head(cby_0__1__1_ccff_tail[0]), - .right_width_0_height_0__pin_1_upper(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), - .right_width_0_height_0__pin_1_lower(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_left_1_ccff_tail[0])); + .right_width_0_height_0__pin_1_upper(grid_io_left_left_1_right_width_0_height_0__pin_1_upper[0]), + .right_width_0_height_0__pin_1_lower(grid_io_left_left_1_right_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_left_left_1_ccff_tail[0])); sb_0__0_ sb_0__0_ ( .prog_clk(prog_clk[0]), .chany_top_in(cby_0__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), + .top_left_grid_pin_1_(grid_io_left_left_0_right_width_0_height_0__pin_1_lower[0]), .chanx_right_in(cbx_1__0__0_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_0_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_0_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_0_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_0_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_0_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_0_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_0_bottom_width_0_height_0__pin_49_upper[0]), - .right_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), - .ccff_head(grid_io_bottom_0_ccff_tail[0]), + .right_bottom_grid_pin_1_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_3_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_upper[0]), + .right_bottom_grid_pin_5_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_upper[0]), + .right_bottom_grid_pin_7_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_upper[0]), + .right_bottom_grid_pin_9_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_upper[0]), + .right_bottom_grid_pin_11_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_upper[0]), + .ccff_head(grid_io_bottom_bottom_0_ccff_tail[0]), .chany_top_out(sb_0__0__0_chany_top_out[0:19]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:19]), .ccff_tail(ccff_tail[0])); @@ -852,18 +899,18 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_0__1_ sb_0__1_ ( .prog_clk(prog_clk[0]), .chany_top_in(cby_0__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), + .top_left_grid_pin_1_(grid_io_left_left_1_right_width_0_height_0__pin_1_lower[0]), .chanx_right_in(cbx_1__1__0_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_1_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_1_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_1_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_1_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_1_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_1_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_1_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_1_bottom_width_0_height_0__pin_49_upper[0]), + .right_bottom_grid_pin_34_(grid_clb_0_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_0_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_0_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_0_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_0_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_0_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_0_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_0_top_width_0_height_0__pin_41_upper[0]), .chany_bottom_in(cby_0__1__0_chany_top_out[0:19]), - .bottom_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_1_(grid_io_left_left_0_right_width_0_height_0__pin_1_upper[0]), .ccff_head(cbx_1__1__0_ccff_tail[0]), .chany_top_out(sb_0__1__0_chany_top_out[0:19]), .chanx_right_out(sb_0__1__0_chanx_right_out[0:19]), @@ -873,10 +920,18 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_0__2_ sb_0__2_ ( .prog_clk(prog_clk[0]), .chanx_right_in(cbx_1__2__0_chanx_left_out[0:19]), - .right_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .right_top_grid_pin_1_(grid_io_top_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_34_(grid_clb_1_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_1_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_1_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_1_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_1_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_1_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_1_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_1_top_width_0_height_0__pin_41_upper[0]), .chany_bottom_in(cby_0__1__1_chany_top_out[0:19]), - .bottom_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), - .ccff_head(grid_io_top_0_ccff_tail[0]), + .bottom_left_grid_pin_1_(grid_io_left_left_1_right_width_0_height_0__pin_1_upper[0]), + .ccff_head(grid_io_top_top_0_ccff_tail[0]), .chanx_right_out(sb_0__2__0_chanx_right_out[0:19]), .chany_bottom_out(sb_0__2__0_chany_bottom_out[0:19]), .ccff_tail(sb_0__2__0_ccff_tail[0])); @@ -884,35 +939,29 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_1__0_ sb_1__0_ ( .prog_clk(prog_clk[0]), .chany_top_in(cby_1__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_0_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_0_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_0_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_0_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_0_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_0_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_0_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_0_right_width_0_height_0__pin_41_lower[0]), + .top_left_grid_pin_42_(grid_clb_0_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_0_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_0_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_0_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_0_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_0_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_0_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), .chanx_right_in(cbx_1__0__1_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_2_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_2_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_2_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_2_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_2_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_2_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_2_bottom_width_0_height_0__pin_49_upper[0]), - .right_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_1_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_3_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_upper[0]), + .right_bottom_grid_pin_5_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_upper[0]), + .right_bottom_grid_pin_7_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_upper[0]), + .right_bottom_grid_pin_9_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_upper[0]), + .right_bottom_grid_pin_11_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_upper[0]), .chanx_left_in(cbx_1__0__0_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_0_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_0_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_0_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_0_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_0_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_0_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_0_bottom_width_0_height_0__pin_49_lower[0]), - .left_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), - .ccff_head(grid_io_bottom_1_ccff_tail[0]), + .left_bottom_grid_pin_1_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_3_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_lower[0]), + .left_bottom_grid_pin_5_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_lower[0]), + .left_bottom_grid_pin_7_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_lower[0]), + .left_bottom_grid_pin_9_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_lower[0]), + .left_bottom_grid_pin_11_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_lower[0]), + .ccff_head(grid_io_bottom_bottom_1_ccff_tail[0]), .chany_top_out(sb_1__0__0_chany_top_out[0:19]), .chanx_right_out(sb_1__0__0_chanx_right_out[0:19]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:19]), @@ -921,41 +970,41 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_1__1_ sb_1__1_ ( .prog_clk(prog_clk[0]), .chany_top_in(cby_1__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_1_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_1_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_1_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_1_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_1_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_1_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_1_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_1_right_width_0_height_0__pin_41_lower[0]), + .top_left_grid_pin_42_(grid_clb_1_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_1_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_1_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_1_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_1_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_1_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_1_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_1_right_width_0_height_0__pin_49_lower[0]), .chanx_right_in(cbx_1__1__1_chanx_left_out[0:19]), - .right_top_grid_pin_42_(grid_clb_3_bottom_width_0_height_0__pin_42_upper[0]), - .right_top_grid_pin_43_(grid_clb_3_bottom_width_0_height_0__pin_43_upper[0]), - .right_top_grid_pin_44_(grid_clb_3_bottom_width_0_height_0__pin_44_upper[0]), - .right_top_grid_pin_45_(grid_clb_3_bottom_width_0_height_0__pin_45_upper[0]), - .right_top_grid_pin_46_(grid_clb_3_bottom_width_0_height_0__pin_46_upper[0]), - .right_top_grid_pin_47_(grid_clb_3_bottom_width_0_height_0__pin_47_upper[0]), - .right_top_grid_pin_48_(grid_clb_3_bottom_width_0_height_0__pin_48_upper[0]), - .right_top_grid_pin_49_(grid_clb_3_bottom_width_0_height_0__pin_49_upper[0]), + .right_bottom_grid_pin_34_(grid_clb_2_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_2_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_2_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_2_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_2_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_2_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_2_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_2_top_width_0_height_0__pin_41_upper[0]), .chany_bottom_in(cby_1__1__0_chany_top_out[0:19]), - .bottom_left_grid_pin_34_(grid_clb_0_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_0_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_0_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_0_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_0_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_0_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_0_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_0_right_width_0_height_0__pin_41_upper[0]), + .bottom_left_grid_pin_42_(grid_clb_0_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_0_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_0_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_0_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_0_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_0_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_0_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), .chanx_left_in(cbx_1__1__0_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_1_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_1_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_1_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_1_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_1_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_1_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_1_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_1_bottom_width_0_height_0__pin_49_lower[0]), + .left_bottom_grid_pin_34_(grid_clb_0_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_0_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_0_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_0_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_0_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_0_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_0_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_0_top_width_0_height_0__pin_41_lower[0]), .ccff_head(cbx_1__1__1_ccff_tail[0]), .chany_top_out(sb_1__1__0_chany_top_out[0:19]), .chanx_right_out(sb_1__1__0_chanx_right_out[0:19]), @@ -966,19 +1015,35 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_1__2_ sb_1__2_ ( .prog_clk(prog_clk[0]), .chanx_right_in(cbx_1__2__1_chanx_left_out[0:19]), - .right_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .right_top_grid_pin_1_(grid_io_top_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .right_bottom_grid_pin_34_(grid_clb_3_top_width_0_height_0__pin_34_upper[0]), + .right_bottom_grid_pin_35_(grid_clb_3_top_width_0_height_0__pin_35_upper[0]), + .right_bottom_grid_pin_36_(grid_clb_3_top_width_0_height_0__pin_36_upper[0]), + .right_bottom_grid_pin_37_(grid_clb_3_top_width_0_height_0__pin_37_upper[0]), + .right_bottom_grid_pin_38_(grid_clb_3_top_width_0_height_0__pin_38_upper[0]), + .right_bottom_grid_pin_39_(grid_clb_3_top_width_0_height_0__pin_39_upper[0]), + .right_bottom_grid_pin_40_(grid_clb_3_top_width_0_height_0__pin_40_upper[0]), + .right_bottom_grid_pin_41_(grid_clb_3_top_width_0_height_0__pin_41_upper[0]), .chany_bottom_in(cby_1__1__1_chany_top_out[0:19]), - .bottom_left_grid_pin_34_(grid_clb_1_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_1_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_1_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_1_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_1_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_1_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_1_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_1_right_width_0_height_0__pin_41_upper[0]), + .bottom_left_grid_pin_42_(grid_clb_1_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_1_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_1_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_1_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_1_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_1_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_1_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_1_right_width_0_height_0__pin_49_upper[0]), .chanx_left_in(cbx_1__2__0_chanx_right_out[0:19]), - .left_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_head(grid_io_top_1_ccff_tail[0]), + .left_top_grid_pin_1_(grid_io_top_top_0_bottom_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_34_(grid_clb_1_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_1_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_1_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_1_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_1_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_1_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_1_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_1_top_width_0_height_0__pin_41_lower[0]), + .ccff_head(grid_io_top_top_1_ccff_tail[0]), .chanx_right_out(sb_1__2__0_chanx_right_out[0:19]), .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:19]), .chanx_left_out(sb_1__2__0_chanx_left_out[0:19]), @@ -986,63 +1051,60 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_2__0_ sb_2__0_ ( .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__2_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_2_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_2_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_2_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_2_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_2_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_2_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_2_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_2_right_width_0_height_0__pin_41_lower[0]), - .top_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), + .chany_top_in(cby_2__1__0_chany_bottom_out[0:19]), + .top_left_grid_pin_42_(grid_clb_2_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_2_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_2_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_2_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_2_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_2_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_2_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), + .top_right_grid_pin_1_(grid_io_right_right_0_left_width_0_height_0__pin_1_lower[0]), .chanx_left_in(cbx_1__0__1_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_2_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_2_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_2_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_2_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_2_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_2_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_2_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_2_bottom_width_0_height_0__pin_49_lower[0]), - .left_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), - .ccff_head(grid_io_right_0_ccff_tail[0]), + .left_bottom_grid_pin_1_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_3_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_lower[0]), + .left_bottom_grid_pin_5_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_lower[0]), + .left_bottom_grid_pin_7_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_lower[0]), + .left_bottom_grid_pin_9_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_lower[0]), + .left_bottom_grid_pin_11_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_lower[0]), + .ccff_head(grid_io_right_right_0_ccff_tail[0]), .chany_top_out(sb_2__0__0_chany_top_out[0:19]), .chanx_left_out(sb_2__0__0_chanx_left_out[0:19]), .ccff_tail(sb_2__0__0_ccff_tail[0])); sb_2__1_ sb_2__1_ ( .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__3_chany_bottom_out[0:19]), - .top_left_grid_pin_34_(grid_clb_3_right_width_0_height_0__pin_34_lower[0]), - .top_left_grid_pin_35_(grid_clb_3_right_width_0_height_0__pin_35_lower[0]), - .top_left_grid_pin_36_(grid_clb_3_right_width_0_height_0__pin_36_lower[0]), - .top_left_grid_pin_37_(grid_clb_3_right_width_0_height_0__pin_37_lower[0]), - .top_left_grid_pin_38_(grid_clb_3_right_width_0_height_0__pin_38_lower[0]), - .top_left_grid_pin_39_(grid_clb_3_right_width_0_height_0__pin_39_lower[0]), - .top_left_grid_pin_40_(grid_clb_3_right_width_0_height_0__pin_40_lower[0]), - .top_left_grid_pin_41_(grid_clb_3_right_width_0_height_0__pin_41_lower[0]), - .top_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), - .chany_bottom_in(cby_1__1__2_chany_top_out[0:19]), - .bottom_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), - .bottom_left_grid_pin_34_(grid_clb_2_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_2_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_2_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_2_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_2_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_2_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_2_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_2_right_width_0_height_0__pin_41_upper[0]), + .chany_top_in(cby_2__1__1_chany_bottom_out[0:19]), + .top_left_grid_pin_42_(grid_clb_3_right_width_0_height_0__pin_42_lower[0]), + .top_left_grid_pin_43_(grid_clb_3_right_width_0_height_0__pin_43_lower[0]), + .top_left_grid_pin_44_(grid_clb_3_right_width_0_height_0__pin_44_lower[0]), + .top_left_grid_pin_45_(grid_clb_3_right_width_0_height_0__pin_45_lower[0]), + .top_left_grid_pin_46_(grid_clb_3_right_width_0_height_0__pin_46_lower[0]), + .top_left_grid_pin_47_(grid_clb_3_right_width_0_height_0__pin_47_lower[0]), + .top_left_grid_pin_48_(grid_clb_3_right_width_0_height_0__pin_48_lower[0]), + .top_left_grid_pin_49_(grid_clb_3_right_width_0_height_0__pin_49_lower[0]), + .top_right_grid_pin_1_(grid_io_right_right_1_left_width_0_height_0__pin_1_lower[0]), + .chany_bottom_in(cby_2__1__0_chany_top_out[0:19]), + .bottom_right_grid_pin_1_(grid_io_right_right_0_left_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_42_(grid_clb_2_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_2_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_2_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_2_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_2_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_2_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_2_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), .chanx_left_in(cbx_1__1__1_chanx_right_out[0:19]), - .left_top_grid_pin_42_(grid_clb_3_bottom_width_0_height_0__pin_42_lower[0]), - .left_top_grid_pin_43_(grid_clb_3_bottom_width_0_height_0__pin_43_lower[0]), - .left_top_grid_pin_44_(grid_clb_3_bottom_width_0_height_0__pin_44_lower[0]), - .left_top_grid_pin_45_(grid_clb_3_bottom_width_0_height_0__pin_45_lower[0]), - .left_top_grid_pin_46_(grid_clb_3_bottom_width_0_height_0__pin_46_lower[0]), - .left_top_grid_pin_47_(grid_clb_3_bottom_width_0_height_0__pin_47_lower[0]), - .left_top_grid_pin_48_(grid_clb_3_bottom_width_0_height_0__pin_48_lower[0]), - .left_top_grid_pin_49_(grid_clb_3_bottom_width_0_height_0__pin_49_lower[0]), - .ccff_head(grid_io_right_1_ccff_tail[0]), + .left_bottom_grid_pin_34_(grid_clb_2_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_2_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_2_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_2_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_2_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_2_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_2_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_2_top_width_0_height_0__pin_41_lower[0]), + .ccff_head(grid_io_right_right_1_ccff_tail[0]), .chany_top_out(sb_2__1__0_chany_top_out[0:19]), .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:19]), .chanx_left_out(sb_2__1__0_chanx_left_out[0:19]), @@ -1050,18 +1112,26 @@ wire [0:19] sb_2__2__0_chany_bottom_out; sb_2__2_ sb_2__2_ ( .prog_clk(prog_clk[0]), - .chany_bottom_in(cby_1__1__3_chany_top_out[0:19]), - .bottom_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), - .bottom_left_grid_pin_34_(grid_clb_3_right_width_0_height_0__pin_34_upper[0]), - .bottom_left_grid_pin_35_(grid_clb_3_right_width_0_height_0__pin_35_upper[0]), - .bottom_left_grid_pin_36_(grid_clb_3_right_width_0_height_0__pin_36_upper[0]), - .bottom_left_grid_pin_37_(grid_clb_3_right_width_0_height_0__pin_37_upper[0]), - .bottom_left_grid_pin_38_(grid_clb_3_right_width_0_height_0__pin_38_upper[0]), - .bottom_left_grid_pin_39_(grid_clb_3_right_width_0_height_0__pin_39_upper[0]), - .bottom_left_grid_pin_40_(grid_clb_3_right_width_0_height_0__pin_40_upper[0]), - .bottom_left_grid_pin_41_(grid_clb_3_right_width_0_height_0__pin_41_upper[0]), + .chany_bottom_in(cby_2__1__1_chany_top_out[0:19]), + .bottom_right_grid_pin_1_(grid_io_right_right_1_left_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_42_(grid_clb_3_right_width_0_height_0__pin_42_upper[0]), + .bottom_left_grid_pin_43_(grid_clb_3_right_width_0_height_0__pin_43_upper[0]), + .bottom_left_grid_pin_44_(grid_clb_3_right_width_0_height_0__pin_44_upper[0]), + .bottom_left_grid_pin_45_(grid_clb_3_right_width_0_height_0__pin_45_upper[0]), + .bottom_left_grid_pin_46_(grid_clb_3_right_width_0_height_0__pin_46_upper[0]), + .bottom_left_grid_pin_47_(grid_clb_3_right_width_0_height_0__pin_47_upper[0]), + .bottom_left_grid_pin_48_(grid_clb_3_right_width_0_height_0__pin_48_upper[0]), + .bottom_left_grid_pin_49_(grid_clb_3_right_width_0_height_0__pin_49_upper[0]), .chanx_left_in(cbx_1__2__1_chanx_right_out[0:19]), - .left_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .left_top_grid_pin_1_(grid_io_top_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .left_bottom_grid_pin_34_(grid_clb_3_top_width_0_height_0__pin_34_lower[0]), + .left_bottom_grid_pin_35_(grid_clb_3_top_width_0_height_0__pin_35_lower[0]), + .left_bottom_grid_pin_36_(grid_clb_3_top_width_0_height_0__pin_36_lower[0]), + .left_bottom_grid_pin_37_(grid_clb_3_top_width_0_height_0__pin_37_lower[0]), + .left_bottom_grid_pin_38_(grid_clb_3_top_width_0_height_0__pin_38_lower[0]), + .left_bottom_grid_pin_39_(grid_clb_3_top_width_0_height_0__pin_39_lower[0]), + .left_bottom_grid_pin_40_(grid_clb_3_top_width_0_height_0__pin_40_lower[0]), + .left_bottom_grid_pin_41_(grid_clb_3_top_width_0_height_0__pin_41_lower[0]), .ccff_head(ccff_head[0]), .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:19]), .chanx_left_out(sb_2__2__0_chanx_left_out[0:19]), @@ -1074,23 +1144,12 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(sb_1__0__0_ccff_tail[0]), .chanx_left_out(cbx_1__0__0_chanx_left_out[0:19]), .chanx_right_out(cbx_1__0__0_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__0__0_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__0__0_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__0__0_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__0__0_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__0__0_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__0__0_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__0__0_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__0__0_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__0__0_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__0__0_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__0__0_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__0__0_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__0__0_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__0__0_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__0__0_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__0__0_top_grid_pin_31_[0]), .bottom_grid_pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), + .bottom_grid_pin_2_(cbx_1__0__0_bottom_grid_pin_2_[0]), + .bottom_grid_pin_4_(cbx_1__0__0_bottom_grid_pin_4_[0]), + .bottom_grid_pin_6_(cbx_1__0__0_bottom_grid_pin_6_[0]), + .bottom_grid_pin_8_(cbx_1__0__0_bottom_grid_pin_8_[0]), + .bottom_grid_pin_10_(cbx_1__0__0_bottom_grid_pin_10_[0]), .ccff_tail(cbx_1__0__0_ccff_tail[0])); cbx_1__0_ cbx_2__0_ ( @@ -1100,23 +1159,12 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(sb_2__0__0_ccff_tail[0]), .chanx_left_out(cbx_1__0__1_chanx_left_out[0:19]), .chanx_right_out(cbx_1__0__1_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__0__1_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__0__1_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__0__1_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__0__1_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__0__1_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__0__1_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__0__1_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__0__1_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__0__1_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__0__1_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__0__1_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__0__1_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__0__1_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__0__1_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__0__1_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__0__1_top_grid_pin_31_[0]), .bottom_grid_pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), + .bottom_grid_pin_2_(cbx_1__0__1_bottom_grid_pin_2_[0]), + .bottom_grid_pin_4_(cbx_1__0__1_bottom_grid_pin_4_[0]), + .bottom_grid_pin_6_(cbx_1__0__1_bottom_grid_pin_6_[0]), + .bottom_grid_pin_8_(cbx_1__0__1_bottom_grid_pin_8_[0]), + .bottom_grid_pin_10_(cbx_1__0__1_bottom_grid_pin_10_[0]), .ccff_tail(cbx_1__0__1_ccff_tail[0])); cbx_1__1_ cbx_1__1_ ( @@ -1126,22 +1174,22 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(sb_1__1__0_ccff_tail[0]), .chanx_left_out(cbx_1__1__0_chanx_left_out[0:19]), .chanx_right_out(cbx_1__1__0_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__1__0_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__1__0_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__1__0_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__1__0_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__1__0_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__1__0_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__1__0_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__1__0_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__1__0_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__1__0_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__1__0_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__1__0_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__1__0_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__1__0_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__1__0_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__1__0_top_grid_pin_31_[0]), + .bottom_grid_pin_0_(cbx_1__1__0_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__1__0_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__1__0_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__1__0_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__1__0_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__1__0_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__1__0_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__1__0_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__1__0_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__1__0_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__1__0_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__1__0_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__1__0_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__1__0_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__1__0_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__1__0_bottom_grid_pin_15_[0]), .ccff_tail(cbx_1__1__0_ccff_tail[0])); cbx_1__1_ cbx_2__1_ ( @@ -1151,22 +1199,22 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(sb_2__1__0_ccff_tail[0]), .chanx_left_out(cbx_1__1__1_chanx_left_out[0:19]), .chanx_right_out(cbx_1__1__1_chanx_right_out[0:19]), - .top_grid_pin_16_(cbx_1__1__1_top_grid_pin_16_[0]), - .top_grid_pin_17_(cbx_1__1__1_top_grid_pin_17_[0]), - .top_grid_pin_18_(cbx_1__1__1_top_grid_pin_18_[0]), - .top_grid_pin_19_(cbx_1__1__1_top_grid_pin_19_[0]), - .top_grid_pin_20_(cbx_1__1__1_top_grid_pin_20_[0]), - .top_grid_pin_21_(cbx_1__1__1_top_grid_pin_21_[0]), - .top_grid_pin_22_(cbx_1__1__1_top_grid_pin_22_[0]), - .top_grid_pin_23_(cbx_1__1__1_top_grid_pin_23_[0]), - .top_grid_pin_24_(cbx_1__1__1_top_grid_pin_24_[0]), - .top_grid_pin_25_(cbx_1__1__1_top_grid_pin_25_[0]), - .top_grid_pin_26_(cbx_1__1__1_top_grid_pin_26_[0]), - .top_grid_pin_27_(cbx_1__1__1_top_grid_pin_27_[0]), - .top_grid_pin_28_(cbx_1__1__1_top_grid_pin_28_[0]), - .top_grid_pin_29_(cbx_1__1__1_top_grid_pin_29_[0]), - .top_grid_pin_30_(cbx_1__1__1_top_grid_pin_30_[0]), - .top_grid_pin_31_(cbx_1__1__1_top_grid_pin_31_[0]), + .bottom_grid_pin_0_(cbx_1__1__1_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__1__1_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__1__1_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__1__1_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__1__1_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__1__1_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__1__1_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__1__1_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__1__1_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__1__1_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__1__1_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__1__1_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__1__1_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__1__1_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__1__1_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__1__1_bottom_grid_pin_15_[0]), .ccff_tail(cbx_1__1__1_ccff_tail[0])); cbx_1__2_ cbx_1__2_ ( @@ -1177,6 +1225,22 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .chanx_left_out(cbx_1__2__0_chanx_left_out[0:19]), .chanx_right_out(cbx_1__2__0_chanx_right_out[0:19]), .top_grid_pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), + .bottom_grid_pin_0_(cbx_1__2__0_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__2__0_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__2__0_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__2__0_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__2__0_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__2__0_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__2__0_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__2__0_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__2__0_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__2__0_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__2__0_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__2__0_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__2__0_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__2__0_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), .ccff_tail(cbx_1__2__0_ccff_tail[0])); cbx_1__2_ cbx_2__2_ ( @@ -1187,6 +1251,22 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .chanx_left_out(cbx_1__2__1_chanx_left_out[0:19]), .chanx_right_out(cbx_1__2__1_chanx_right_out[0:19]), .top_grid_pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), + .bottom_grid_pin_0_(cbx_1__2__1_bottom_grid_pin_0_[0]), + .bottom_grid_pin_1_(cbx_1__2__1_bottom_grid_pin_1_[0]), + .bottom_grid_pin_2_(cbx_1__2__1_bottom_grid_pin_2_[0]), + .bottom_grid_pin_3_(cbx_1__2__1_bottom_grid_pin_3_[0]), + .bottom_grid_pin_4_(cbx_1__2__1_bottom_grid_pin_4_[0]), + .bottom_grid_pin_5_(cbx_1__2__1_bottom_grid_pin_5_[0]), + .bottom_grid_pin_6_(cbx_1__2__1_bottom_grid_pin_6_[0]), + .bottom_grid_pin_7_(cbx_1__2__1_bottom_grid_pin_7_[0]), + .bottom_grid_pin_8_(cbx_1__2__1_bottom_grid_pin_8_[0]), + .bottom_grid_pin_9_(cbx_1__2__1_bottom_grid_pin_9_[0]), + .bottom_grid_pin_10_(cbx_1__2__1_bottom_grid_pin_10_[0]), + .bottom_grid_pin_11_(cbx_1__2__1_bottom_grid_pin_11_[0]), + .bottom_grid_pin_12_(cbx_1__2__1_bottom_grid_pin_12_[0]), + .bottom_grid_pin_13_(cbx_1__2__1_bottom_grid_pin_13_[0]), + .bottom_grid_pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), + .bottom_grid_pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), .ccff_tail(cbx_1__2__1_ccff_tail[0])); cby_0__1_ cby_0__1_ ( @@ -1196,7 +1276,6 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(sb_0__1__0_ccff_tail[0]), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:19]), .chany_top_out(cby_0__1__0_chany_top_out[0:19]), - .right_grid_pin_52_(cby_0__1__0_right_grid_pin_52_[0]), .left_grid_pin_0_(cby_0__1__0_left_grid_pin_0_[0]), .ccff_tail(cby_0__1__0_ccff_tail[0])); @@ -1207,7 +1286,6 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(sb_0__2__0_ccff_tail[0]), .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:19]), .chany_top_out(cby_0__1__1_chany_top_out[0:19]), - .right_grid_pin_52_(cby_0__1__1_right_grid_pin_52_[0]), .left_grid_pin_0_(cby_0__1__1_left_grid_pin_0_[0]), .ccff_tail(cby_0__1__1_ccff_tail[0])); @@ -1218,23 +1296,22 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(grid_clb_0_ccff_tail[0]), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:19]), .chany_top_out(cby_1__1__0_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__0_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__0_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__0_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__0_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__0_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__0_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__0_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__0_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__0_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__0_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__0_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__0_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__0_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__0_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__0_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__0_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__0_left_grid_pin_15_[0]), + .left_grid_pin_16_(cby_1__1__0_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_1__1__0_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_1__1__0_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_1__1__0_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_1__1__0_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_1__1__0_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_1__1__0_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_1__1__0_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_1__1__0_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_1__1__0_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_1__1__0_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_1__1__0_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_1__1__0_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_1__1__0_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_1__1__0_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_1__1__0_left_grid_pin_31_[0]), .ccff_tail(cby_1__1__0_ccff_tail[0])); cby_1__1_ cby_1__2_ ( @@ -1244,76 +1321,75 @@ wire [0:19] sb_2__2__0_chany_bottom_out; .ccff_head(grid_clb_1_ccff_tail[0]), .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:19]), .chany_top_out(cby_1__1__1_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__1_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__1_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__1_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__1_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__1_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__1_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__1_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__1_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__1_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__1_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__1_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__1_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__1_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__1_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__1_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__1_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__1_left_grid_pin_15_[0]), + .left_grid_pin_16_(cby_1__1__1_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_1__1__1_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_1__1__1_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_1__1__1_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_1__1__1_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_1__1__1_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_1__1__1_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_1__1__1_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_1__1__1_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_1__1__1_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_1__1__1_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_1__1__1_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_1__1__1_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_1__1__1_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_1__1__1_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_1__1__1_left_grid_pin_31_[0]), .ccff_tail(cby_1__1__1_ccff_tail[0])); - cby_1__1_ cby_2__1_ ( + cby_2__1_ cby_2__1_ ( .prog_clk(prog_clk[0]), .chany_bottom_in(sb_2__0__0_chany_top_out[0:19]), .chany_top_in(sb_2__1__0_chany_bottom_out[0:19]), .ccff_head(grid_clb_2_ccff_tail[0]), - .chany_bottom_out(cby_1__1__2_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__2_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__2_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__2_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__2_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__2_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__2_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__2_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__2_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__2_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__2_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__2_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__2_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__2_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__2_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__2_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__2_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__2_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__2_left_grid_pin_15_[0]), - .ccff_tail(cby_1__1__2_ccff_tail[0])); + .chany_bottom_out(cby_2__1__0_chany_bottom_out[0:19]), + .chany_top_out(cby_2__1__0_chany_top_out[0:19]), + .right_grid_pin_0_(cby_2__1__0_right_grid_pin_0_[0]), + .left_grid_pin_16_(cby_2__1__0_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_2__1__0_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_2__1__0_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_2__1__0_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_2__1__0_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_2__1__0_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_2__1__0_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_2__1__0_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_2__1__0_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_2__1__0_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_2__1__0_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_2__1__0_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_2__1__0_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_2__1__0_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_2__1__0_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_2__1__0_left_grid_pin_31_[0]), + .ccff_tail(cby_2__1__0_ccff_tail[0])); - cby_1__1_ cby_2__2_ ( + cby_2__1_ cby_2__2_ ( .prog_clk(prog_clk[0]), .chany_bottom_in(sb_2__1__0_chany_top_out[0:19]), .chany_top_in(sb_2__2__0_chany_bottom_out[0:19]), .ccff_head(grid_clb_3_ccff_tail[0]), - .chany_bottom_out(cby_1__1__3_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__3_chany_top_out[0:19]), - .right_grid_pin_52_(cby_1__1__3_right_grid_pin_52_[0]), - .left_grid_pin_0_(cby_1__1__3_left_grid_pin_0_[0]), - .left_grid_pin_1_(cby_1__1__3_left_grid_pin_1_[0]), - .left_grid_pin_2_(cby_1__1__3_left_grid_pin_2_[0]), - .left_grid_pin_3_(cby_1__1__3_left_grid_pin_3_[0]), - .left_grid_pin_4_(cby_1__1__3_left_grid_pin_4_[0]), - .left_grid_pin_5_(cby_1__1__3_left_grid_pin_5_[0]), - .left_grid_pin_6_(cby_1__1__3_left_grid_pin_6_[0]), - .left_grid_pin_7_(cby_1__1__3_left_grid_pin_7_[0]), - .left_grid_pin_8_(cby_1__1__3_left_grid_pin_8_[0]), - .left_grid_pin_9_(cby_1__1__3_left_grid_pin_9_[0]), - .left_grid_pin_10_(cby_1__1__3_left_grid_pin_10_[0]), - .left_grid_pin_11_(cby_1__1__3_left_grid_pin_11_[0]), - .left_grid_pin_12_(cby_1__1__3_left_grid_pin_12_[0]), - .left_grid_pin_13_(cby_1__1__3_left_grid_pin_13_[0]), - .left_grid_pin_14_(cby_1__1__3_left_grid_pin_14_[0]), - .left_grid_pin_15_(cby_1__1__3_left_grid_pin_15_[0]), - .ccff_tail(cby_1__1__3_ccff_tail[0])); + .chany_bottom_out(cby_2__1__1_chany_bottom_out[0:19]), + .chany_top_out(cby_2__1__1_chany_top_out[0:19]), + .right_grid_pin_0_(cby_2__1__1_right_grid_pin_0_[0]), + .left_grid_pin_16_(cby_2__1__1_left_grid_pin_16_[0]), + .left_grid_pin_17_(cby_2__1__1_left_grid_pin_17_[0]), + .left_grid_pin_18_(cby_2__1__1_left_grid_pin_18_[0]), + .left_grid_pin_19_(cby_2__1__1_left_grid_pin_19_[0]), + .left_grid_pin_20_(cby_2__1__1_left_grid_pin_20_[0]), + .left_grid_pin_21_(cby_2__1__1_left_grid_pin_21_[0]), + .left_grid_pin_22_(cby_2__1__1_left_grid_pin_22_[0]), + .left_grid_pin_23_(cby_2__1__1_left_grid_pin_23_[0]), + .left_grid_pin_24_(cby_2__1__1_left_grid_pin_24_[0]), + .left_grid_pin_25_(cby_2__1__1_left_grid_pin_25_[0]), + .left_grid_pin_26_(cby_2__1__1_left_grid_pin_26_[0]), + .left_grid_pin_27_(cby_2__1__1_left_grid_pin_27_[0]), + .left_grid_pin_28_(cby_2__1__1_left_grid_pin_28_[0]), + .left_grid_pin_29_(cby_2__1__1_left_grid_pin_29_[0]), + .left_grid_pin_30_(cby_2__1__1_left_grid_pin_30_[0]), + .left_grid_pin_31_(cby_2__1__1_left_grid_pin_31_[0]), + .ccff_tail(cby_2__1__1_ccff_tail[0])); direct_interc direct_interc_0_ ( .in(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v index e0f7d9d..03671f6 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v @@ -1,292 +1,138 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -// -module grid_clb(prog_clk, - Test_en, - clk, - top_width_0_height_0__pin_32_, - top_width_0_height_0__pin_33_, - right_width_0_height_0__pin_0_, - right_width_0_height_0__pin_1_, - right_width_0_height_0__pin_2_, - right_width_0_height_0__pin_3_, - right_width_0_height_0__pin_4_, - right_width_0_height_0__pin_5_, - right_width_0_height_0__pin_6_, - right_width_0_height_0__pin_7_, - right_width_0_height_0__pin_8_, - right_width_0_height_0__pin_9_, - right_width_0_height_0__pin_10_, - right_width_0_height_0__pin_11_, - right_width_0_height_0__pin_12_, - right_width_0_height_0__pin_13_, - right_width_0_height_0__pin_14_, - right_width_0_height_0__pin_15_, - bottom_width_0_height_0__pin_16_, - bottom_width_0_height_0__pin_17_, - bottom_width_0_height_0__pin_18_, - bottom_width_0_height_0__pin_19_, - bottom_width_0_height_0__pin_20_, - bottom_width_0_height_0__pin_21_, - bottom_width_0_height_0__pin_22_, - bottom_width_0_height_0__pin_23_, - bottom_width_0_height_0__pin_24_, - bottom_width_0_height_0__pin_25_, - bottom_width_0_height_0__pin_26_, - bottom_width_0_height_0__pin_27_, - bottom_width_0_height_0__pin_28_, - bottom_width_0_height_0__pin_29_, - bottom_width_0_height_0__pin_30_, - bottom_width_0_height_0__pin_31_, - left_width_0_height_0__pin_52_, - ccff_head, - right_width_0_height_0__pin_34_upper, - right_width_0_height_0__pin_34_lower, - right_width_0_height_0__pin_35_upper, - right_width_0_height_0__pin_35_lower, - right_width_0_height_0__pin_36_upper, - right_width_0_height_0__pin_36_lower, - right_width_0_height_0__pin_37_upper, - right_width_0_height_0__pin_37_lower, - right_width_0_height_0__pin_38_upper, - right_width_0_height_0__pin_38_lower, - right_width_0_height_0__pin_39_upper, - right_width_0_height_0__pin_39_lower, - right_width_0_height_0__pin_40_upper, - right_width_0_height_0__pin_40_lower, - right_width_0_height_0__pin_41_upper, - right_width_0_height_0__pin_41_lower, - bottom_width_0_height_0__pin_42_upper, - bottom_width_0_height_0__pin_42_lower, - bottom_width_0_height_0__pin_43_upper, - bottom_width_0_height_0__pin_43_lower, - bottom_width_0_height_0__pin_44_upper, - bottom_width_0_height_0__pin_44_lower, - bottom_width_0_height_0__pin_45_upper, - bottom_width_0_height_0__pin_45_lower, - bottom_width_0_height_0__pin_46_upper, - bottom_width_0_height_0__pin_46_lower, - bottom_width_0_height_0__pin_47_upper, - bottom_width_0_height_0__pin_47_lower, - bottom_width_0_height_0__pin_48_upper, - bottom_width_0_height_0__pin_48_lower, - bottom_width_0_height_0__pin_49_upper, - bottom_width_0_height_0__pin_49_lower, - bottom_width_0_height_0__pin_50_, - bottom_width_0_height_0__pin_51_, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] Test_en; -// -input [0:0] clk; -// -input [0:0] top_width_0_height_0__pin_32_; -// -input [0:0] top_width_0_height_0__pin_33_; -// -input [0:0] right_width_0_height_0__pin_0_; -// -input [0:0] right_width_0_height_0__pin_1_; -// -input [0:0] right_width_0_height_0__pin_2_; -// -input [0:0] right_width_0_height_0__pin_3_; -// -input [0:0] right_width_0_height_0__pin_4_; -// -input [0:0] right_width_0_height_0__pin_5_; -// -input [0:0] right_width_0_height_0__pin_6_; -// -input [0:0] right_width_0_height_0__pin_7_; -// -input [0:0] right_width_0_height_0__pin_8_; -// -input [0:0] right_width_0_height_0__pin_9_; -// -input [0:0] right_width_0_height_0__pin_10_; -// -input [0:0] right_width_0_height_0__pin_11_; -// -input [0:0] right_width_0_height_0__pin_12_; -// -input [0:0] right_width_0_height_0__pin_13_; -// -input [0:0] right_width_0_height_0__pin_14_; -// -input [0:0] right_width_0_height_0__pin_15_; -// -input [0:0] bottom_width_0_height_0__pin_16_; -// -input [0:0] bottom_width_0_height_0__pin_17_; -// -input [0:0] bottom_width_0_height_0__pin_18_; -// -input [0:0] bottom_width_0_height_0__pin_19_; -// -input [0:0] bottom_width_0_height_0__pin_20_; -// -input [0:0] bottom_width_0_height_0__pin_21_; -// -input [0:0] bottom_width_0_height_0__pin_22_; -// -input [0:0] bottom_width_0_height_0__pin_23_; -// -input [0:0] bottom_width_0_height_0__pin_24_; -// -input [0:0] bottom_width_0_height_0__pin_25_; -// -input [0:0] bottom_width_0_height_0__pin_26_; -// -input [0:0] bottom_width_0_height_0__pin_27_; -// -input [0:0] bottom_width_0_height_0__pin_28_; -// -input [0:0] bottom_width_0_height_0__pin_29_; -// -input [0:0] bottom_width_0_height_0__pin_30_; -// -input [0:0] bottom_width_0_height_0__pin_31_; -// -input [0:0] left_width_0_height_0__pin_52_; -// -input [0:0] ccff_head; -// -output [0:0] right_width_0_height_0__pin_34_upper; -// -output [0:0] right_width_0_height_0__pin_34_lower; -// -output [0:0] right_width_0_height_0__pin_35_upper; -// -output [0:0] right_width_0_height_0__pin_35_lower; -// -output [0:0] right_width_0_height_0__pin_36_upper; -// -output [0:0] right_width_0_height_0__pin_36_lower; -// -output [0:0] right_width_0_height_0__pin_37_upper; -// -output [0:0] right_width_0_height_0__pin_37_lower; -// -output [0:0] right_width_0_height_0__pin_38_upper; -// -output [0:0] right_width_0_height_0__pin_38_lower; -// -output [0:0] right_width_0_height_0__pin_39_upper; -// -output [0:0] right_width_0_height_0__pin_39_lower; -// -output [0:0] right_width_0_height_0__pin_40_upper; -// -output [0:0] right_width_0_height_0__pin_40_lower; -// -output [0:0] right_width_0_height_0__pin_41_upper; -// -output [0:0] right_width_0_height_0__pin_41_lower; -// -output [0:0] bottom_width_0_height_0__pin_42_upper; -// -output [0:0] bottom_width_0_height_0__pin_42_lower; -// -output [0:0] bottom_width_0_height_0__pin_43_upper; -// -output [0:0] bottom_width_0_height_0__pin_43_lower; -// -output [0:0] bottom_width_0_height_0__pin_44_upper; -// -output [0:0] bottom_width_0_height_0__pin_44_lower; -// -output [0:0] bottom_width_0_height_0__pin_45_upper; -// -output [0:0] bottom_width_0_height_0__pin_45_lower; -// -output [0:0] bottom_width_0_height_0__pin_46_upper; -// -output [0:0] bottom_width_0_height_0__pin_46_lower; -// -output [0:0] bottom_width_0_height_0__pin_47_upper; -// -output [0:0] bottom_width_0_height_0__pin_47_lower; -// -output [0:0] bottom_width_0_height_0__pin_48_upper; -// -output [0:0] bottom_width_0_height_0__pin_48_lower; -// -output [0:0] bottom_width_0_height_0__pin_49_upper; -// -output [0:0] bottom_width_0_height_0__pin_49_lower; -// -output [0:0] bottom_width_0_height_0__pin_50_; -// -output [0:0] bottom_width_0_height_0__pin_51_; -// -output [0:0] ccff_tail; - -// -// -// -// +module grid_clb +( + input [0:0] prog_clk, + input [0:0] Test_en, + input [0:0] clk, + input [0:0] top_width_0_height_0__pin_0_, + input [0:0] top_width_0_height_0__pin_1_, + input [0:0] top_width_0_height_0__pin_2_, + input [0:0] top_width_0_height_0__pin_3_, + input [0:0] top_width_0_height_0__pin_4_, + input [0:0] top_width_0_height_0__pin_5_, + input [0:0] top_width_0_height_0__pin_6_, + input [0:0] top_width_0_height_0__pin_7_, + input [0:0] top_width_0_height_0__pin_8_, + input [0:0] top_width_0_height_0__pin_9_, + input [0:0] top_width_0_height_0__pin_10_, + input [0:0] top_width_0_height_0__pin_11_, + input [0:0] top_width_0_height_0__pin_12_, + input [0:0] top_width_0_height_0__pin_13_, + input [0:0] top_width_0_height_0__pin_14_, + input [0:0] top_width_0_height_0__pin_15_, + input [0:0] top_width_0_height_0__pin_32_, + input [0:0] top_width_0_height_0__pin_33_, + input [0:0] right_width_0_height_0__pin_16_, + input [0:0] right_width_0_height_0__pin_17_, + input [0:0] right_width_0_height_0__pin_18_, + input [0:0] right_width_0_height_0__pin_19_, + input [0:0] right_width_0_height_0__pin_20_, + input [0:0] right_width_0_height_0__pin_21_, + input [0:0] right_width_0_height_0__pin_22_, + input [0:0] right_width_0_height_0__pin_23_, + input [0:0] right_width_0_height_0__pin_24_, + input [0:0] right_width_0_height_0__pin_25_, + input [0:0] right_width_0_height_0__pin_26_, + input [0:0] right_width_0_height_0__pin_27_, + input [0:0] right_width_0_height_0__pin_28_, + input [0:0] right_width_0_height_0__pin_29_, + input [0:0] right_width_0_height_0__pin_30_, + input [0:0] right_width_0_height_0__pin_31_, + input [0:0] left_width_0_height_0__pin_52_, + input [0:0] ccff_head, + output [0:0] top_width_0_height_0__pin_34_upper, + output [0:0] top_width_0_height_0__pin_34_lower, + output [0:0] top_width_0_height_0__pin_35_upper, + output [0:0] top_width_0_height_0__pin_35_lower, + output [0:0] top_width_0_height_0__pin_36_upper, + output [0:0] top_width_0_height_0__pin_36_lower, + output [0:0] top_width_0_height_0__pin_37_upper, + output [0:0] top_width_0_height_0__pin_37_lower, + output [0:0] top_width_0_height_0__pin_38_upper, + output [0:0] top_width_0_height_0__pin_38_lower, + output [0:0] top_width_0_height_0__pin_39_upper, + output [0:0] top_width_0_height_0__pin_39_lower, + output [0:0] top_width_0_height_0__pin_40_upper, + output [0:0] top_width_0_height_0__pin_40_lower, + output [0:0] top_width_0_height_0__pin_41_upper, + output [0:0] top_width_0_height_0__pin_41_lower, + output [0:0] right_width_0_height_0__pin_42_upper, + output [0:0] right_width_0_height_0__pin_42_lower, + output [0:0] right_width_0_height_0__pin_43_upper, + output [0:0] right_width_0_height_0__pin_43_lower, + output [0:0] right_width_0_height_0__pin_44_upper, + output [0:0] right_width_0_height_0__pin_44_lower, + output [0:0] right_width_0_height_0__pin_45_upper, + output [0:0] right_width_0_height_0__pin_45_lower, + output [0:0] right_width_0_height_0__pin_46_upper, + output [0:0] right_width_0_height_0__pin_46_lower, + output [0:0] right_width_0_height_0__pin_47_upper, + output [0:0] right_width_0_height_0__pin_47_lower, + output [0:0] right_width_0_height_0__pin_48_upper, + output [0:0] right_width_0_height_0__pin_48_lower, + output [0:0] right_width_0_height_0__pin_49_upper, + output [0:0] right_width_0_height_0__pin_49_lower, + output [0:0] bottom_width_0_height_0__pin_50_, + output [0:0] bottom_width_0_height_0__pin_51_, + output [0:0] ccff_tail, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + assign top_width_0_height_0__pin_34_lower[0] = top_width_0_height_0__pin_34_upper[0]; + assign top_width_0_height_0__pin_35_lower[0] = top_width_0_height_0__pin_35_upper[0]; + assign top_width_0_height_0__pin_36_lower[0] = top_width_0_height_0__pin_36_upper[0]; + assign top_width_0_height_0__pin_37_lower[0] = top_width_0_height_0__pin_37_upper[0]; + assign top_width_0_height_0__pin_38_lower[0] = top_width_0_height_0__pin_38_upper[0]; + assign top_width_0_height_0__pin_39_lower[0] = top_width_0_height_0__pin_39_upper[0]; + assign top_width_0_height_0__pin_40_lower[0] = top_width_0_height_0__pin_40_upper[0]; + assign top_width_0_height_0__pin_41_lower[0] = top_width_0_height_0__pin_41_upper[0]; + assign right_width_0_height_0__pin_42_lower[0] = right_width_0_height_0__pin_42_upper[0]; + assign right_width_0_height_0__pin_43_lower[0] = right_width_0_height_0__pin_43_upper[0]; + assign right_width_0_height_0__pin_44_lower[0] = right_width_0_height_0__pin_44_upper[0]; + assign right_width_0_height_0__pin_45_lower[0] = right_width_0_height_0__pin_45_upper[0]; + assign right_width_0_height_0__pin_46_lower[0] = right_width_0_height_0__pin_46_upper[0]; + assign right_width_0_height_0__pin_47_lower[0] = right_width_0_height_0__pin_47_upper[0]; + assign right_width_0_height_0__pin_48_lower[0] = right_width_0_height_0__pin_48_upper[0]; + assign right_width_0_height_0__pin_49_lower[0] = right_width_0_height_0__pin_49_upper[0]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + logical_tile_clb_mode_clb_ + logical_tile_clb_mode_clb__0 + ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .clb_I0({ top_width_0_height_0__pin_0_[0], top_width_0_height_0__pin_1_[0], top_width_0_height_0__pin_2_[0] }), + .clb_I0i(top_width_0_height_0__pin_3_[0]), + .clb_I1({ top_width_0_height_0__pin_4_[0], top_width_0_height_0__pin_5_[0], top_width_0_height_0__pin_6_[0] }), + .clb_I1i(top_width_0_height_0__pin_7_[0]), + .clb_I2({ top_width_0_height_0__pin_8_[0], top_width_0_height_0__pin_9_[0], top_width_0_height_0__pin_10_[0] }), + .clb_I2i(top_width_0_height_0__pin_11_[0]), + .clb_I3({ top_width_0_height_0__pin_12_[0], top_width_0_height_0__pin_13_[0], top_width_0_height_0__pin_14_[0] }), + .clb_I3i(top_width_0_height_0__pin_15_[0]), + .clb_I4({ right_width_0_height_0__pin_16_[0], right_width_0_height_0__pin_17_[0], right_width_0_height_0__pin_18_[0] }), + .clb_I4i(right_width_0_height_0__pin_19_[0]), + .clb_I5({ right_width_0_height_0__pin_20_[0], right_width_0_height_0__pin_21_[0], right_width_0_height_0__pin_22_[0] }), + .clb_I5i(right_width_0_height_0__pin_23_[0]), + .clb_I6({ right_width_0_height_0__pin_24_[0], right_width_0_height_0__pin_25_[0], right_width_0_height_0__pin_26_[0] }), + .clb_I6i(right_width_0_height_0__pin_27_[0]), + .clb_I7({ right_width_0_height_0__pin_28_[0], right_width_0_height_0__pin_29_[0], right_width_0_height_0__pin_30_[0] }), + .clb_I7i(right_width_0_height_0__pin_31_[0]), + .clb_regin(top_width_0_height_0__pin_32_[0]), + .clb_sc_in(SC_IN_TOP), + .clb_clk(left_width_0_height_0__pin_52_[0]), + .ccff_head(ccff_head[0]), + .clb_O({ top_width_0_height_0__pin_34_upper[0], top_width_0_height_0__pin_35_upper[0], top_width_0_height_0__pin_36_upper[0], top_width_0_height_0__pin_37_upper[0], top_width_0_height_0__pin_38_upper[0], top_width_0_height_0__pin_39_upper[0], top_width_0_height_0__pin_40_upper[0], top_width_0_height_0__pin_41_upper[0], right_width_0_height_0__pin_42_upper[0], right_width_0_height_0__pin_43_upper[0], right_width_0_height_0__pin_44_upper[0], right_width_0_height_0__pin_45_upper[0], right_width_0_height_0__pin_46_upper[0], right_width_0_height_0__pin_47_upper[0], right_width_0_height_0__pin_48_upper[0], right_width_0_height_0__pin_49_upper[0] }), + .clb_regout(bottom_width_0_height_0__pin_50_[0]), + .clb_sc_out(SC_OUT_BOT), + .ccff_tail(ccff_tail[0]) + ); -// -// -// - assign right_width_0_height_0__pin_34_lower[0] = right_width_0_height_0__pin_34_upper[0]; - assign right_width_0_height_0__pin_35_lower[0] = right_width_0_height_0__pin_35_upper[0]; - assign right_width_0_height_0__pin_36_lower[0] = right_width_0_height_0__pin_36_upper[0]; - assign right_width_0_height_0__pin_37_lower[0] = right_width_0_height_0__pin_37_upper[0]; - assign right_width_0_height_0__pin_38_lower[0] = right_width_0_height_0__pin_38_upper[0]; - assign right_width_0_height_0__pin_39_lower[0] = right_width_0_height_0__pin_39_upper[0]; - assign right_width_0_height_0__pin_40_lower[0] = right_width_0_height_0__pin_40_upper[0]; - assign right_width_0_height_0__pin_41_lower[0] = right_width_0_height_0__pin_41_upper[0]; - assign bottom_width_0_height_0__pin_42_lower[0] = bottom_width_0_height_0__pin_42_upper[0]; - assign bottom_width_0_height_0__pin_43_lower[0] = bottom_width_0_height_0__pin_43_upper[0]; - assign bottom_width_0_height_0__pin_44_lower[0] = bottom_width_0_height_0__pin_44_upper[0]; - assign bottom_width_0_height_0__pin_45_lower[0] = bottom_width_0_height_0__pin_45_upper[0]; - assign bottom_width_0_height_0__pin_46_lower[0] = bottom_width_0_height_0__pin_46_upper[0]; - assign bottom_width_0_height_0__pin_47_lower[0] = bottom_width_0_height_0__pin_47_upper[0]; - assign bottom_width_0_height_0__pin_48_lower[0] = bottom_width_0_height_0__pin_48_upper[0]; - assign bottom_width_0_height_0__pin_49_lower[0] = bottom_width_0_height_0__pin_49_upper[0]; -// - - logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .clb_I0({right_width_0_height_0__pin_0_[0], right_width_0_height_0__pin_1_[0], right_width_0_height_0__pin_2_[0], right_width_0_height_0__pin_3_[0]}), - .clb_I1({right_width_0_height_0__pin_4_[0], right_width_0_height_0__pin_5_[0], right_width_0_height_0__pin_6_[0], right_width_0_height_0__pin_7_[0]}), - .clb_I2({right_width_0_height_0__pin_8_[0], right_width_0_height_0__pin_9_[0], right_width_0_height_0__pin_10_[0], right_width_0_height_0__pin_11_[0]}), - .clb_I3({right_width_0_height_0__pin_12_[0], right_width_0_height_0__pin_13_[0], right_width_0_height_0__pin_14_[0], right_width_0_height_0__pin_15_[0]}), - .clb_I4({bottom_width_0_height_0__pin_16_[0], bottom_width_0_height_0__pin_17_[0], bottom_width_0_height_0__pin_18_[0], bottom_width_0_height_0__pin_19_[0]}), - .clb_I5({bottom_width_0_height_0__pin_20_[0], bottom_width_0_height_0__pin_21_[0], bottom_width_0_height_0__pin_22_[0], bottom_width_0_height_0__pin_23_[0]}), - .clb_I6({bottom_width_0_height_0__pin_24_[0], bottom_width_0_height_0__pin_25_[0], bottom_width_0_height_0__pin_26_[0], bottom_width_0_height_0__pin_27_[0]}), - .clb_I7({bottom_width_0_height_0__pin_28_[0], bottom_width_0_height_0__pin_29_[0], bottom_width_0_height_0__pin_30_[0], bottom_width_0_height_0__pin_31_[0]}), - .clb_regin(top_width_0_height_0__pin_32_[0]), - .clb_scin(top_width_0_height_0__pin_33_[0]), - .clb_clk(left_width_0_height_0__pin_52_[0]), - .ccff_head(ccff_head[0]), - .clb_O({right_width_0_height_0__pin_34_upper[0], right_width_0_height_0__pin_35_upper[0], right_width_0_height_0__pin_36_upper[0], right_width_0_height_0__pin_37_upper[0], right_width_0_height_0__pin_38_upper[0], right_width_0_height_0__pin_39_upper[0], right_width_0_height_0__pin_40_upper[0], right_width_0_height_0__pin_41_upper[0], bottom_width_0_height_0__pin_42_upper[0], bottom_width_0_height_0__pin_43_upper[0], bottom_width_0_height_0__pin_44_upper[0], bottom_width_0_height_0__pin_45_upper[0], bottom_width_0_height_0__pin_46_upper[0], bottom_width_0_height_0__pin_47_upper[0], bottom_width_0_height_0__pin_48_upper[0], bottom_width_0_height_0__pin_49_upper[0]}), - .clb_regout(bottom_width_0_height_0__pin_50_[0]), - .clb_scout(bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(ccff_tail[0])); endmodule -// - - -// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v index 654b409..2c819d1 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v @@ -11,34 +11,76 @@ // // module grid_io_bottom(prog_clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, - top_width_0_height_0__pin_0_, - ccff_head, - top_width_0_height_0__pin_1_upper, - top_width_0_height_0__pin_1_lower, - ccff_tail); + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, + top_width_0_height_0__pin_0_, + top_width_0_height_0__pin_2_, + top_width_0_height_0__pin_4_, + top_width_0_height_0__pin_6_, + top_width_0_height_0__pin_8_, + top_width_0_height_0__pin_10_, + ccff_head, + top_width_0_height_0__pin_1_upper, + top_width_0_height_0__pin_1_lower, + top_width_0_height_0__pin_3_upper, + top_width_0_height_0__pin_3_lower, + top_width_0_height_0__pin_5_upper, + top_width_0_height_0__pin_5_lower, + top_width_0_height_0__pin_7_upper, + top_width_0_height_0__pin_7_lower, + top_width_0_height_0__pin_9_upper, + top_width_0_height_0__pin_9_lower, + top_width_0_height_0__pin_11_upper, + top_width_0_height_0__pin_11_lower, + ccff_tail); // input [0:0] prog_clk; // -output [0:0] gfpga_pad_GPIO_A; +input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:0] gfpga_pad_GPIO_IE; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:0] gfpga_pad_GPIO_OE; -// -inout [0:0] gfpga_pad_GPIO_Y; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] top_width_0_height_0__pin_0_; // +input [0:0] top_width_0_height_0__pin_2_; +// +input [0:0] top_width_0_height_0__pin_4_; +// +input [0:0] top_width_0_height_0__pin_6_; +// +input [0:0] top_width_0_height_0__pin_8_; +// +input [0:0] top_width_0_height_0__pin_10_; +// input [0:0] ccff_head; // output [0:0] top_width_0_height_0__pin_1_upper; // output [0:0] top_width_0_height_0__pin_1_lower; // +output [0:0] top_width_0_height_0__pin_3_upper; +// +output [0:0] top_width_0_height_0__pin_3_lower; +// +output [0:0] top_width_0_height_0__pin_5_upper; +// +output [0:0] top_width_0_height_0__pin_5_lower; +// +output [0:0] top_width_0_height_0__pin_7_upper; +// +output [0:0] top_width_0_height_0__pin_7_lower; +// +output [0:0] top_width_0_height_0__pin_9_upper; +// +output [0:0] top_width_0_height_0__pin_9_lower; +// +output [0:0] top_width_0_height_0__pin_11_upper; +// +output [0:0] top_width_0_height_0__pin_11_lower; +// output [0:0] ccff_tail; // @@ -49,22 +91,81 @@ output [0:0] ccff_tail; // +wire [0:0] logical_tile_io_mode_io__0_ccff_tail; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail; // // // assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0]; + assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0]; + assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0]; + assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0]; + assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0]; + assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0]; // logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), .io_outpad(top_width_0_height_0__pin_0_[0]), .ccff_head(ccff_head[0]), .io_inpad(top_width_0_height_0__pin_1_upper[0]), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0])); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), + .io_outpad(top_width_0_height_0__pin_2_[0]), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail[0]), + .io_inpad(top_width_0_height_0__pin_3_upper[0]), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0])); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), + .io_outpad(top_width_0_height_0__pin_4_[0]), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail[0]), + .io_inpad(top_width_0_height_0__pin_5_upper[0]), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0])); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), + .io_outpad(top_width_0_height_0__pin_6_[0]), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail[0]), + .io_inpad(top_width_0_height_0__pin_7_upper[0]), + .ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0])); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]), + .io_outpad(top_width_0_height_0__pin_8_[0]), + .ccff_head(logical_tile_io_mode_io__3_ccff_tail[0]), + .io_inpad(top_width_0_height_0__pin_9_upper[0]), + .ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0])); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[5]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]), + .io_outpad(top_width_0_height_0__pin_10_[0]), + .ccff_head(logical_tile_io_mode_io__4_ccff_tail[0]), + .io_inpad(top_width_0_height_0__pin_11_upper[0]), .ccff_tail(ccff_tail[0])); endmodule diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v index 2426295..53ad4f9 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v @@ -11,25 +11,22 @@ // // module grid_io_left(prog_clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, - right_width_0_height_0__pin_0_, - ccff_head, - right_width_0_height_0__pin_1_upper, - right_width_0_height_0__pin_1_lower, - ccff_tail); + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, + right_width_0_height_0__pin_0_, + ccff_head, + right_width_0_height_0__pin_1_upper, + right_width_0_height_0__pin_1_lower, + ccff_tail); // input [0:0] prog_clk; // -output [0:0] gfpga_pad_GPIO_A; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:0] gfpga_pad_GPIO_IE; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:0] gfpga_pad_GPIO_OE; -// -inout [0:0] gfpga_pad_GPIO_Y; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] right_width_0_height_0__pin_0_; // @@ -58,10 +55,9 @@ output [0:0] ccff_tail; logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), .io_outpad(right_width_0_height_0__pin_0_[0]), .ccff_head(ccff_head[0]), .io_inpad(right_width_0_height_0__pin_1_upper[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v index 2d402ca..5c65f69 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v @@ -11,25 +11,22 @@ // // module grid_io_right(prog_clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, - left_width_0_height_0__pin_0_, - ccff_head, - left_width_0_height_0__pin_1_upper, - left_width_0_height_0__pin_1_lower, - ccff_tail); + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, + left_width_0_height_0__pin_0_, + ccff_head, + left_width_0_height_0__pin_1_upper, + left_width_0_height_0__pin_1_lower, + ccff_tail); // input [0:0] prog_clk; // -output [0:0] gfpga_pad_GPIO_A; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:0] gfpga_pad_GPIO_IE; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:0] gfpga_pad_GPIO_OE; -// -inout [0:0] gfpga_pad_GPIO_Y; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] left_width_0_height_0__pin_0_; // @@ -58,10 +55,9 @@ output [0:0] ccff_tail; logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), .io_outpad(left_width_0_height_0__pin_0_[0]), .ccff_head(ccff_head[0]), .io_inpad(left_width_0_height_0__pin_1_upper[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v index c21d0d6..15931d1 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v @@ -11,25 +11,22 @@ // // module grid_io_top(prog_clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, - bottom_width_0_height_0__pin_0_, - ccff_head, - bottom_width_0_height_0__pin_1_upper, - bottom_width_0_height_0__pin_1_lower, - ccff_tail); + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, + bottom_width_0_height_0__pin_0_, + ccff_head, + bottom_width_0_height_0__pin_1_upper, + bottom_width_0_height_0__pin_1_lower, + ccff_tail); // input [0:0] prog_clk; // -output [0:0] gfpga_pad_GPIO_A; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:0] gfpga_pad_GPIO_IE; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:0] gfpga_pad_GPIO_OE; -// -inout [0:0] gfpga_pad_GPIO_Y; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] bottom_width_0_height_0__pin_0_; // @@ -58,10 +55,9 @@ output [0:0] ccff_tail; logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), .io_outpad(bottom_width_0_height_0__pin_0_[0]), .ccff_head(ccff_head[0]), .io_inpad(bottom_width_0_height_0__pin_1_upper[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v index 9b755b2..356dd66 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v @@ -14,20 +14,28 @@ module logical_tile_clb_mode_clb_(prog_clk, Test_en, clk, clb_I0, + clb_I0i, clb_I1, + clb_I1i, clb_I2, + clb_I2i, clb_I3, + clb_I3i, clb_I4, + clb_I4i, clb_I5, + clb_I5i, clb_I6, + clb_I6i, clb_I7, + clb_I7i, clb_regin, - clb_scin, + clb_sc_in, clb_clk, ccff_head, clb_O, clb_regout, - clb_scout, + clb_sc_out, ccff_tail); // input [0:0] prog_clk; @@ -36,25 +44,41 @@ input [0:0] Test_en; // input [0:0] clk; // -input [0:3] clb_I0; +input [0:2] clb_I0; // -input [0:3] clb_I1; +input [0:0] clb_I0i; // -input [0:3] clb_I2; +input [0:2] clb_I1; // -input [0:3] clb_I3; +input [0:0] clb_I1i; // -input [0:3] clb_I4; +input [0:2] clb_I2; // -input [0:3] clb_I5; +input [0:0] clb_I2i; // -input [0:3] clb_I6; +input [0:2] clb_I3; // -input [0:3] clb_I7; +input [0:0] clb_I3i; +// +input [0:2] clb_I4; +// +input [0:0] clb_I4i; +// +input [0:2] clb_I5; +// +input [0:0] clb_I5i; +// +input [0:2] clb_I6; +// +input [0:0] clb_I6i; +// +input [0:2] clb_I7; +// +input [0:0] clb_I7i; // input [0:0] clb_regin; // -input [0:0] clb_scin; +input [0:0] clb_sc_in; // input [0:0] clb_clk; // @@ -64,25 +88,33 @@ output [0:15] clb_O; // output [0:0] clb_regout; // -output [0:0] clb_scout; +output [0:0] clb_sc_out; // output [0:0] ccff_tail; // -wire [0:3] clb_I0; -wire [0:3] clb_I1; -wire [0:3] clb_I2; -wire [0:3] clb_I3; -wire [0:3] clb_I4; -wire [0:3] clb_I5; -wire [0:3] clb_I6; -wire [0:3] clb_I7; +wire [0:2] clb_I0; +wire [0:0] clb_I0i; +wire [0:2] clb_I1; +wire [0:0] clb_I1i; +wire [0:2] clb_I2; +wire [0:0] clb_I2i; +wire [0:2] clb_I3; +wire [0:0] clb_I3i; +wire [0:2] clb_I4; +wire [0:0] clb_I4i; +wire [0:2] clb_I5; +wire [0:0] clb_I5i; +wire [0:2] clb_I6; +wire [0:0] clb_I6i; +wire [0:2] clb_I7; +wire [0:0] clb_I7i; wire [0:0] clb_regin; -wire [0:0] clb_scin; +wire [0:0] clb_sc_in; wire [0:0] clb_clk; wire [0:15] clb_O; wire [0:0] clb_regout; -wire [0:0] clb_scout; +wire [0:0] clb_sc_out; // @@ -149,34 +181,34 @@ wire [0:0] direct_interc_73_out; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out; wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out; wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out; wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out; wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_4_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out; wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_5_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out; wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_6_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out; wire [0:1] logical_tile_clb_mode_default__fle_7_fle_out; wire [0:0] logical_tile_clb_mode_default__fle_7_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; // // @@ -189,12 +221,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_18_out[0], direct_interc_19_out[0], direct_interc_20_out[0], direct_interc_21_out[0]}), .fle_regin(direct_interc_22_out[0]), - .fle_scin(direct_interc_23_out[0]), + .fle_sc_in(direct_interc_23_out[0]), .fle_clk(direct_interc_24_out[0]), .ccff_head(ccff_head[0]), .fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_0_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_0_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 ( @@ -203,12 +235,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_25_out[0], direct_interc_26_out[0], direct_interc_27_out[0], direct_interc_28_out[0]}), .fle_regin(direct_interc_29_out[0]), - .fle_scin(direct_interc_30_out[0]), + .fle_sc_in(direct_interc_30_out[0]), .fle_clk(direct_interc_31_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_1_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_1_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 ( @@ -217,12 +249,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_32_out[0], direct_interc_33_out[0], direct_interc_34_out[0], direct_interc_35_out[0]}), .fle_regin(direct_interc_36_out[0]), - .fle_scin(direct_interc_37_out[0]), + .fle_sc_in(direct_interc_37_out[0]), .fle_clk(direct_interc_38_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_2_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_2_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 ( @@ -231,12 +263,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_39_out[0], direct_interc_40_out[0], direct_interc_41_out[0], direct_interc_42_out[0]}), .fle_regin(direct_interc_43_out[0]), - .fle_scin(direct_interc_44_out[0]), + .fle_sc_in(direct_interc_44_out[0]), .fle_clk(direct_interc_45_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_3_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_3_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 ( @@ -245,12 +277,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_46_out[0], direct_interc_47_out[0], direct_interc_48_out[0], direct_interc_49_out[0]}), .fle_regin(direct_interc_50_out[0]), - .fle_scin(direct_interc_51_out[0]), + .fle_sc_in(direct_interc_51_out[0]), .fle_clk(direct_interc_52_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_4_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_4_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_4_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 ( @@ -259,12 +291,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_53_out[0], direct_interc_54_out[0], direct_interc_55_out[0], direct_interc_56_out[0]}), .fle_regin(direct_interc_57_out[0]), - .fle_scin(direct_interc_58_out[0]), + .fle_sc_in(direct_interc_58_out[0]), .fle_clk(direct_interc_59_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_5_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_5_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_5_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 ( @@ -273,12 +305,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_60_out[0], direct_interc_61_out[0], direct_interc_62_out[0], direct_interc_63_out[0]}), .fle_regin(direct_interc_64_out[0]), - .fle_scin(direct_interc_65_out[0]), + .fle_sc_in(direct_interc_65_out[0]), .fle_clk(direct_interc_66_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_6_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_6_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_6_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]), .ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail[0])); logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( @@ -287,12 +319,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .clk(clk[0]), .fle_in({direct_interc_67_out[0], direct_interc_68_out[0], direct_interc_69_out[0], direct_interc_70_out[0]}), .fle_regin(direct_interc_71_out[0]), - .fle_scin(direct_interc_72_out[0]), + .fle_sc_in(direct_interc_72_out[0]), .fle_clk(direct_interc_73_out[0]), .ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail[0]), .fle_out(logical_tile_clb_mode_default__fle_7_fle_out[0:1]), .fle_regout(logical_tile_clb_mode_default__fle_7_fle_regout[0]), - .fle_scout(logical_tile_clb_mode_default__fle_7_fle_scout[0]), + .fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]), .ccff_tail(ccff_tail[0])); direct_interc direct_interc_0_ ( @@ -364,11 +396,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(clb_regout[0])); direct_interc direct_interc_17_ ( - .in(logical_tile_clb_mode_default__fle_7_fle_scout[0]), - .out(clb_scout[0])); + .in(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]), + .out(clb_sc_out[0])); direct_interc direct_interc_18_ ( - .in(clb_I0[0]), + .in(clb_I0[2]), .out(direct_interc_18_out[0])); direct_interc direct_interc_19_ ( @@ -376,11 +408,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_19_out[0])); direct_interc direct_interc_20_ ( - .in(clb_I0[2]), + .in(clb_I0[0]), .out(direct_interc_20_out[0])); direct_interc direct_interc_21_ ( - .in(clb_I0[3]), + .in(clb_I0i[0]), .out(direct_interc_21_out[0])); direct_interc direct_interc_22_ ( @@ -388,7 +420,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_22_out[0])); direct_interc direct_interc_23_ ( - .in(clb_scin[0]), + .in(clb_sc_in[0]), .out(direct_interc_23_out[0])); direct_interc direct_interc_24_ ( @@ -396,7 +428,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_24_out[0])); direct_interc direct_interc_25_ ( - .in(clb_I1[0]), + .in(clb_I1[2]), .out(direct_interc_25_out[0])); direct_interc direct_interc_26_ ( @@ -404,11 +436,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_26_out[0])); direct_interc direct_interc_27_ ( - .in(clb_I1[2]), + .in(clb_I1[0]), .out(direct_interc_27_out[0])); direct_interc direct_interc_28_ ( - .in(clb_I1[3]), + .in(clb_I1i[0]), .out(direct_interc_28_out[0])); direct_interc direct_interc_29_ ( @@ -416,7 +448,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_29_out[0])); direct_interc direct_interc_30_ ( - .in(logical_tile_clb_mode_default__fle_0_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]), .out(direct_interc_30_out[0])); direct_interc direct_interc_31_ ( @@ -424,7 +456,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_31_out[0])); direct_interc direct_interc_32_ ( - .in(clb_I2[0]), + .in(clb_I2[2]), .out(direct_interc_32_out[0])); direct_interc direct_interc_33_ ( @@ -432,11 +464,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_33_out[0])); direct_interc direct_interc_34_ ( - .in(clb_I2[2]), + .in(clb_I2[0]), .out(direct_interc_34_out[0])); direct_interc direct_interc_35_ ( - .in(clb_I2[3]), + .in(clb_I2i[0]), .out(direct_interc_35_out[0])); direct_interc direct_interc_36_ ( @@ -444,7 +476,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_36_out[0])); direct_interc direct_interc_37_ ( - .in(logical_tile_clb_mode_default__fle_1_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]), .out(direct_interc_37_out[0])); direct_interc direct_interc_38_ ( @@ -452,7 +484,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_38_out[0])); direct_interc direct_interc_39_ ( - .in(clb_I3[0]), + .in(clb_I3[2]), .out(direct_interc_39_out[0])); direct_interc direct_interc_40_ ( @@ -460,11 +492,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_40_out[0])); direct_interc direct_interc_41_ ( - .in(clb_I3[2]), + .in(clb_I3[0]), .out(direct_interc_41_out[0])); direct_interc direct_interc_42_ ( - .in(clb_I3[3]), + .in(clb_I3i[0]), .out(direct_interc_42_out[0])); direct_interc direct_interc_43_ ( @@ -472,7 +504,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_43_out[0])); direct_interc direct_interc_44_ ( - .in(logical_tile_clb_mode_default__fle_2_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]), .out(direct_interc_44_out[0])); direct_interc direct_interc_45_ ( @@ -480,7 +512,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_45_out[0])); direct_interc direct_interc_46_ ( - .in(clb_I4[0]), + .in(clb_I4[2]), .out(direct_interc_46_out[0])); direct_interc direct_interc_47_ ( @@ -488,11 +520,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_47_out[0])); direct_interc direct_interc_48_ ( - .in(clb_I4[2]), + .in(clb_I4[0]), .out(direct_interc_48_out[0])); direct_interc direct_interc_49_ ( - .in(clb_I4[3]), + .in(clb_I4i[0]), .out(direct_interc_49_out[0])); direct_interc direct_interc_50_ ( @@ -500,7 +532,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_50_out[0])); direct_interc direct_interc_51_ ( - .in(logical_tile_clb_mode_default__fle_3_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]), .out(direct_interc_51_out[0])); direct_interc direct_interc_52_ ( @@ -508,7 +540,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_52_out[0])); direct_interc direct_interc_53_ ( - .in(clb_I5[0]), + .in(clb_I5[2]), .out(direct_interc_53_out[0])); direct_interc direct_interc_54_ ( @@ -516,11 +548,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_54_out[0])); direct_interc direct_interc_55_ ( - .in(clb_I5[2]), + .in(clb_I5[0]), .out(direct_interc_55_out[0])); direct_interc direct_interc_56_ ( - .in(clb_I5[3]), + .in(clb_I5i[0]), .out(direct_interc_56_out[0])); direct_interc direct_interc_57_ ( @@ -528,7 +560,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_57_out[0])); direct_interc direct_interc_58_ ( - .in(logical_tile_clb_mode_default__fle_4_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]), .out(direct_interc_58_out[0])); direct_interc direct_interc_59_ ( @@ -536,7 +568,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_59_out[0])); direct_interc direct_interc_60_ ( - .in(clb_I6[0]), + .in(clb_I6[2]), .out(direct_interc_60_out[0])); direct_interc direct_interc_61_ ( @@ -544,11 +576,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_61_out[0])); direct_interc direct_interc_62_ ( - .in(clb_I6[2]), + .in(clb_I6[0]), .out(direct_interc_62_out[0])); direct_interc direct_interc_63_ ( - .in(clb_I6[3]), + .in(clb_I6i[0]), .out(direct_interc_63_out[0])); direct_interc direct_interc_64_ ( @@ -556,7 +588,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_64_out[0])); direct_interc direct_interc_65_ ( - .in(logical_tile_clb_mode_default__fle_5_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]), .out(direct_interc_65_out[0])); direct_interc direct_interc_66_ ( @@ -564,7 +596,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_66_out[0])); direct_interc direct_interc_67_ ( - .in(clb_I7[0]), + .in(clb_I7[2]), .out(direct_interc_67_out[0])); direct_interc direct_interc_68_ ( @@ -572,11 +604,11 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_68_out[0])); direct_interc direct_interc_69_ ( - .in(clb_I7[2]), + .in(clb_I7[0]), .out(direct_interc_69_out[0])); direct_interc direct_interc_70_ ( - .in(clb_I7[3]), + .in(clb_I7i[0]), .out(direct_interc_70_out[0])); direct_interc direct_interc_71_ ( @@ -584,7 +616,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; .out(direct_interc_71_out[0])); direct_interc direct_interc_72_ ( - .in(logical_tile_clb_mode_default__fle_6_fle_scout[0]), + .in(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]), .out(direct_interc_72_out[0])); direct_interc direct_interc_73_ ( diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v index b7b27e9..7eb2470 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v @@ -15,12 +15,12 @@ module logical_tile_clb_mode_default__fle(prog_clk, clk, fle_in, fle_regin, - fle_scin, + fle_sc_in, fle_clk, ccff_head, fle_out, fle_regout, - fle_scout, + fle_sc_out, ccff_tail); // input [0:0] prog_clk; @@ -33,7 +33,7 @@ input [0:3] fle_in; // input [0:0] fle_regin; // -input [0:0] fle_scin; +input [0:0] fle_sc_in; // input [0:0] fle_clk; // @@ -43,18 +43,18 @@ output [0:1] fle_out; // output [0:0] fle_regout; // -output [0:0] fle_scout; +output [0:0] fle_sc_out; // output [0:0] ccff_tail; // wire [0:3] fle_in; wire [0:0] fle_regin; -wire [0:0] fle_scin; +wire [0:0] fle_sc_in; wire [0:0] fle_clk; wire [0:1] fle_out; wire [0:0] fle_regout; -wire [0:0] fle_scout; +wire [0:0] fle_sc_out; // @@ -71,7 +71,7 @@ wire [0:0] direct_interc_8_out; wire [0:0] direct_interc_9_out; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_scout; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out; // // @@ -84,12 +84,12 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sco .clk(clk[0]), .fabric_in({direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0], direct_interc_7_out[0]}), .fabric_regin(direct_interc_8_out[0]), - .fabric_scin(direct_interc_9_out[0]), + .fabric_sc_in(direct_interc_9_out[0]), .fabric_clk(direct_interc_10_out[0]), .ccff_head(ccff_head[0]), .fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]), .fabric_regout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout[0]), - .fabric_scout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_scout[0]), + .fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]), .ccff_tail(ccff_tail[0])); direct_interc direct_interc_0_ ( @@ -105,8 +105,8 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sco .out(fle_regout[0])); direct_interc direct_interc_3_ ( - .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_scout[0]), - .out(fle_scout[0])); + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]), + .out(fle_sc_out[0])); direct_interc direct_interc_4_ ( .in(fle_in[0]), @@ -129,7 +129,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sco .out(direct_interc_8_out[0])); direct_interc direct_interc_9_ ( - .in(fle_scin[0]), + .in(fle_sc_in[0]), .out(direct_interc_9_out[0])); direct_interc direct_interc_10_ ( diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v index 0364910..047fb7b 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v @@ -15,12 +15,12 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric(prog_clk, clk, fabric_in, fabric_regin, - fabric_scin, + fabric_sc_in, fabric_clk, ccff_head, fabric_out, fabric_regout, - fabric_scout, + fabric_sc_out, ccff_tail); // input [0:0] prog_clk; @@ -33,7 +33,7 @@ input [0:3] fabric_in; // input [0:0] fabric_regin; // -input [0:0] fabric_scin; +input [0:0] fabric_sc_in; // input [0:0] fabric_clk; // @@ -43,18 +43,18 @@ output [0:1] fabric_out; // output [0:0] fabric_regout; // -output [0:0] fabric_scout; +output [0:0] fabric_sc_out; // output [0:0] ccff_tail; // wire [0:3] fabric_in; wire [0:0] fabric_regin; -wire [0:0] fabric_scin; +wire [0:0] fabric_sc_in; wire [0:0] fabric_clk; wire [0:1] fabric_out; wire [0:0] fabric_regout; -wire [0:0] fabric_scout; +wire [0:0] fabric_sc_out; // @@ -158,7 +158,7 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail; direct_interc direct_interc_1_ ( .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]), - .out(fabric_scout[0])); + .out(fabric_sc_out[0])); direct_interc direct_interc_2_ ( .in(fabric_in[0]), @@ -177,7 +177,7 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail; .out(direct_interc_5_out[0])); direct_interc direct_interc_6_ ( - .in(fabric_scin[0]), + .in(fabric_sc_in[0]), .out(direct_interc_6_out[0])); direct_interc direct_interc_7_ ( diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v index 824e4d4..e484d05 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v @@ -46,7 +46,7 @@ wire [0:0] ff_clk; // // - sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( + sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .SCE(Test_en[0]), .CLK(clk[0]), .D(ff_D[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v index 247d7f4..ae105cb 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v @@ -11,10 +11,9 @@ // // module logical_tile_io_mode_io_(prog_clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, io_outpad, ccff_head, io_inpad, @@ -22,13 +21,11 @@ module logical_tile_io_mode_io_(prog_clk, // input [0:0] prog_clk; // -output [0:0] gfpga_pad_GPIO_A; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:0] gfpga_pad_GPIO_IE; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:0] gfpga_pad_GPIO_OE; -// -inout [0:0] gfpga_pad_GPIO_Y; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] io_outpad; // @@ -58,10 +55,9 @@ wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad; logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk(prog_clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), .iopad_outpad(direct_interc_1_out[0]), .ccff_head(ccff_head[0]), .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v index a39f079..0d0c7f5 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v @@ -10,10 +10,9 @@ // module logical_tile_io_mode_physical__iopad(prog_clk, - gfpga_pad_GPIO_A, - gfpga_pad_GPIO_IE, - gfpga_pad_GPIO_OE, - gfpga_pad_GPIO_Y, + gfpga_pad_EMBEDDED_IO_SOC_IN, + gfpga_pad_EMBEDDED_IO_SOC_OUT, + gfpga_pad_EMBEDDED_IO_SOC_DIR, iopad_outpad, ccff_head, iopad_inpad, @@ -21,13 +20,11 @@ module logical_tile_io_mode_physical__iopad(prog_clk, // input [0:0] prog_clk; // -output [0:0] gfpga_pad_GPIO_A; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; // -output [0:0] gfpga_pad_GPIO_IE; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; // -output [0:0] gfpga_pad_GPIO_OE; -// -inout [0:0] gfpga_pad_GPIO_Y; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; // input [0:0] iopad_outpad; // @@ -47,29 +44,28 @@ wire [0:0] iopad_inpad; // -wire [0:0] GPIO_0_en; -wire [0:0] GPIO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb; +wire [0:0] EMBEDDED_IO_0_en; +wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb; // // // // - GPIO GPIO_0_ ( - .A(gfpga_pad_GPIO_A[0]), - .IE(gfpga_pad_GPIO_IE[0]), - .OE(gfpga_pad_GPIO_OE[0]), - .Y(gfpga_pad_GPIO_Y[0]), - .in(iopad_outpad[0]), - .mem_out(GPIO_0_en[0]), - .out(iopad_inpad[0])); + EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), + .FPGA_OUT(iopad_outpad[0]), + .FPGA_DIR(EMBEDDED_IO_0_en[0]), + .FPGA_IN(iopad_inpad[0])); - GPIO_sky130_fd_sc_hd__dfxbp_1_mem GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0]), - .mem_out(GPIO_0_en[0]), - .mem_outb(GPIO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb[0])); + .mem_out(EMBEDDED_IO_0_en[0]), + .mem_outb(EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb[0])); endmodule // diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v index 8be116b..7e6adb0 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v @@ -1,534 +1,328 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module cbx_1__0_(prog_clk, - chanx_left_in, - chanx_right_in, - ccff_head, - chanx_left_out, - chanx_right_out, - top_grid_pin_16_, - top_grid_pin_17_, - top_grid_pin_18_, - top_grid_pin_19_, - top_grid_pin_20_, - top_grid_pin_21_, - top_grid_pin_22_, - top_grid_pin_23_, - top_grid_pin_24_, - top_grid_pin_25_, - top_grid_pin_26_, - top_grid_pin_27_, - top_grid_pin_28_, - top_grid_pin_29_, - top_grid_pin_30_, - top_grid_pin_31_, - bottom_grid_pin_0_, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chanx_left_in; -// -input [0:19] chanx_right_in; -// -input [0:0] ccff_head; -// -output [0:19] chanx_left_out; -// -output [0:19] chanx_right_out; -// -output [0:0] top_grid_pin_16_; -// -output [0:0] top_grid_pin_17_; -// -output [0:0] top_grid_pin_18_; -// -output [0:0] top_grid_pin_19_; -// -output [0:0] top_grid_pin_20_; -// -output [0:0] top_grid_pin_21_; -// -output [0:0] top_grid_pin_22_; -// -output [0:0] top_grid_pin_23_; -// -output [0:0] top_grid_pin_24_; -// -output [0:0] top_grid_pin_25_; -// -output [0:0] top_grid_pin_26_; -// -output [0:0] top_grid_pin_27_; -// -output [0:0] top_grid_pin_28_; -// -output [0:0] top_grid_pin_29_; -// -output [0:0] top_grid_pin_30_; -// -output [0:0] top_grid_pin_31_; -// -output [0:0] bottom_grid_pin_0_; -// -output [0:0] ccff_tail; - -// -// -// -// +module cbx_1__0_ +( + input [0:0] prog_clk, + input [0:19] chanx_left_in, + input [0:19] chanx_right_in, + input [0:0] ccff_head, + output [0:19] chanx_left_out, + output [0:19] chanx_right_out, + output [0:0] bottom_grid_pin_0_, + output [0:0] bottom_grid_pin_2_, + output [0:0] bottom_grid_pin_4_, + output [0:0] bottom_grid_pin_6_, + output [0:0] bottom_grid_pin_8_, + output [0:0] bottom_grid_pin_10_, + output [0:0] ccff_tail, + input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN, + output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT, + output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR, + input [0:0] top_width_0_height_0__pin_0_, + input [0:0] top_width_0_height_0__pin_2_, + input [0:0] top_width_0_height_0__pin_4_, + input [0:0] top_width_0_height_0__pin_6_, + input [0:0] top_width_0_height_0__pin_8_, + input [0:0] top_width_0_height_0__pin_10_, + output [0:0] top_width_0_height_0__pin_1_upper, + output [0:0] top_width_0_height_0__pin_1_lower, + output [0:0] top_width_0_height_0__pin_3_upper, + output [0:0] top_width_0_height_0__pin_3_lower, + output [0:0] top_width_0_height_0__pin_5_upper, + output [0:0] top_width_0_height_0__pin_5_lower, + output [0:0] top_width_0_height_0__pin_7_upper, + output [0:0] top_width_0_height_0__pin_7_lower, + output [0:0] top_width_0_height_0__pin_9_upper, + output [0:0] top_width_0_height_0__pin_9_lower, + output [0:0] top_width_0_height_0__pin_11_upper, + output [0:0] top_width_0_height_0__pin_11_lower, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_2_sram; + wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_3_sram; + wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_4_sram; + wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_5_sram; + wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire ccff_tail_mid; + wire [0:0] logical_tile_io_mode_io__0_ccff_tail; + wire [0:0] logical_tile_io_mode_io__1_ccff_tail; + wire [0:0] logical_tile_io_mode_io__2_ccff_tail; + wire [0:0] logical_tile_io_mode_io__3_ccff_tail; + wire [0:0] logical_tile_io_mode_io__4_ccff_tail; + assign chanx_right_out[0] = chanx_left_in[0]; + assign chanx_right_out[1] = chanx_left_in[1]; + assign chanx_right_out[2] = chanx_left_in[2]; + assign chanx_right_out[3] = chanx_left_in[3]; + assign chanx_right_out[4] = chanx_left_in[4]; + assign chanx_right_out[5] = chanx_left_in[5]; + assign chanx_right_out[6] = chanx_left_in[6]; + assign chanx_right_out[7] = chanx_left_in[7]; + assign chanx_right_out[8] = chanx_left_in[8]; + assign chanx_right_out[9] = chanx_left_in[9]; + assign chanx_right_out[10] = chanx_left_in[10]; + assign chanx_right_out[11] = chanx_left_in[11]; + assign chanx_right_out[12] = chanx_left_in[12]; + assign chanx_right_out[13] = chanx_left_in[13]; + assign chanx_right_out[14] = chanx_left_in[14]; + assign chanx_right_out[15] = chanx_left_in[15]; + assign chanx_right_out[16] = chanx_left_in[16]; + assign chanx_right_out[17] = chanx_left_in[17]; + assign chanx_right_out[18] = chanx_left_in[18]; + assign chanx_right_out[19] = chanx_left_in[19]; + assign chanx_left_out[0] = chanx_right_in[0]; + assign chanx_left_out[1] = chanx_right_in[1]; + assign chanx_left_out[2] = chanx_right_in[2]; + assign chanx_left_out[3] = chanx_right_in[3]; + assign chanx_left_out[4] = chanx_right_in[4]; + assign chanx_left_out[5] = chanx_right_in[5]; + assign chanx_left_out[6] = chanx_right_in[6]; + assign chanx_left_out[7] = chanx_right_in[7]; + assign chanx_left_out[8] = chanx_right_in[8]; + assign chanx_left_out[9] = chanx_right_in[9]; + assign chanx_left_out[10] = chanx_right_in[10]; + assign chanx_left_out[11] = chanx_right_in[11]; + assign chanx_left_out[12] = chanx_right_in[12]; + assign chanx_left_out[13] = chanx_right_in[13]; + assign chanx_left_out[14] = chanx_right_in[14]; + assign chanx_left_out[15] = chanx_right_in[15]; + assign chanx_left_out[16] = chanx_right_in[16]; + assign chanx_left_out[17] = chanx_right_in[17]; + assign chanx_left_out[18] = chanx_right_in[18]; + assign chanx_left_out[19] = chanx_right_in[19]; + assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0]; + assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0]; + assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0]; + assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0]; + assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0]; + assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size10 + mux_top_ipin_0 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(bottom_grid_pin_0_[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_2_sram; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_3_sram; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_4_sram; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_5_sram; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_6_sram; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_7_sram; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_8_sram; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; -wire [0:3] mux_tree_tapbuf_size8_0_sram; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_1_sram; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_2_sram; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_3_sram; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_4_sram; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_5_sram; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_6_sram; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_7_sram; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; + mux_tree_tapbuf_size10 + mux_top_ipin_1 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(bottom_grid_pin_2_[0]) + ); -// -// -// -// - assign chanx_right_out[0] = chanx_left_in[0]; -// -// -// - assign chanx_right_out[1] = chanx_left_in[1]; -// -// -// - assign chanx_right_out[2] = chanx_left_in[2]; -// -// -// - assign chanx_right_out[3] = chanx_left_in[3]; -// -// -// - assign chanx_right_out[4] = chanx_left_in[4]; -// -// -// - assign chanx_right_out[5] = chanx_left_in[5]; -// -// -// - assign chanx_right_out[6] = chanx_left_in[6]; -// -// -// - assign chanx_right_out[7] = chanx_left_in[7]; -// -// -// - assign chanx_right_out[8] = chanx_left_in[8]; -// -// -// - assign chanx_right_out[9] = chanx_left_in[9]; -// -// -// - assign chanx_right_out[10] = chanx_left_in[10]; -// -// -// - assign chanx_right_out[11] = chanx_left_in[11]; -// -// -// - assign chanx_right_out[12] = chanx_left_in[12]; -// -// -// - assign chanx_right_out[13] = chanx_left_in[13]; -// -// -// - assign chanx_right_out[14] = chanx_left_in[14]; -// -// -// - assign chanx_right_out[15] = chanx_left_in[15]; -// -// -// - assign chanx_right_out[16] = chanx_left_in[16]; -// -// -// - assign chanx_right_out[17] = chanx_left_in[17]; -// -// -// - assign chanx_right_out[18] = chanx_left_in[18]; -// -// -// - assign chanx_right_out[19] = chanx_left_in[19]; -// -// -// - assign chanx_left_out[0] = chanx_right_in[0]; -// -// -// - assign chanx_left_out[1] = chanx_right_in[1]; -// -// -// - assign chanx_left_out[2] = chanx_right_in[2]; -// -// -// - assign chanx_left_out[3] = chanx_right_in[3]; -// -// -// - assign chanx_left_out[4] = chanx_right_in[4]; -// -// -// - assign chanx_left_out[5] = chanx_right_in[5]; -// -// -// - assign chanx_left_out[6] = chanx_right_in[6]; -// -// -// - assign chanx_left_out[7] = chanx_right_in[7]; -// -// -// - assign chanx_left_out[8] = chanx_right_in[8]; -// -// -// - assign chanx_left_out[9] = chanx_right_in[9]; -// -// -// - assign chanx_left_out[10] = chanx_right_in[10]; -// -// -// - assign chanx_left_out[11] = chanx_right_in[11]; -// -// -// - assign chanx_left_out[12] = chanx_right_in[12]; -// -// -// - assign chanx_left_out[13] = chanx_right_in[13]; -// -// -// - assign chanx_left_out[14] = chanx_right_in[14]; -// -// -// - assign chanx_left_out[15] = chanx_right_in[15]; -// -// -// - assign chanx_left_out[16] = chanx_right_in[16]; -// -// -// - assign chanx_left_out[17] = chanx_right_in[17]; -// -// -// - assign chanx_left_out[18] = chanx_right_in[18]; -// -// -// - assign chanx_left_out[19] = chanx_right_in[19]; -// -// -// - mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(top_grid_pin_16_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_2 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(bottom_grid_pin_4_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_1 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), - .out(top_grid_pin_17_[0])); - mux_tree_tapbuf_size10 mux_bottom_ipin_4 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), - .out(top_grid_pin_20_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_3 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(bottom_grid_pin_6_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_5 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), - .out(top_grid_pin_21_[0])); - mux_tree_tapbuf_size10 mux_bottom_ipin_8 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), - .out(top_grid_pin_24_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_4 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(bottom_grid_pin_8_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_9 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19]}), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), - .out(top_grid_pin_25_[0])); - mux_tree_tapbuf_size10 mux_bottom_ipin_12 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16]}), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), - .out(top_grid_pin_28_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_5 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(bottom_grid_pin_10_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_13 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17]}), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), - .out(top_grid_pin_29_[0])); - mux_tree_tapbuf_size10 mux_top_ipin_0 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), - .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), - .out(bottom_grid_pin_0_[0])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_top_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])); - mux_tree_tapbuf_size8 mux_bottom_ipin_2 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), - .out(top_grid_pin_18_[0])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_3 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), - .out(top_grid_pin_19_[0])); - mux_tree_tapbuf_size8 mux_bottom_ipin_6 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), - .out(top_grid_pin_22_[0])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__0 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), + .io_outpad(top_width_0_height_0__pin_0_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(top_width_0_height_0__pin_1_upper[0]), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}), - .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), - .out(top_grid_pin_23_[0])); - mux_tree_tapbuf_size8 mux_bottom_ipin_10 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), - .out(top_grid_pin_26_[0])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__1 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), + .io_outpad(top_width_0_height_0__pin_2_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(top_width_0_height_0__pin_3_upper[0]), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_11 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), - .out(top_grid_pin_27_[0])); - mux_tree_tapbuf_size8 mux_bottom_ipin_14 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), - .out(top_grid_pin_30_[0])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__2 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), + .io_outpad(top_width_0_height_0__pin_4_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(top_width_0_height_0__pin_5_upper[0]), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_15 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}), - .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), - .out(top_grid_pin_31_[0])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__3 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), + .io_outpad(top_width_0_height_0__pin_6_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(top_width_0_height_0__pin_7_upper[0]), + .ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__4 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]), + .io_outpad(top_width_0_height_0__pin_8_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(top_width_0_height_0__pin_9_upper[0]), + .ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__5 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[5]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]), + .io_outpad(top_width_0_height_0__pin_10_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(top_width_0_height_0__pin_11_upper[0]), + .ccff_tail(ccff_tail[0]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])); - - mux_tree_tapbuf_size8_mem mem_bottom_ipin_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])); - - mux_tree_tapbuf_size8_mem mem_bottom_ipin_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])); endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v index d3201ef..2c3eebd 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v @@ -1,515 +1,464 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module cbx_1__1_(prog_clk, - chanx_left_in, - chanx_right_in, - ccff_head, - chanx_left_out, - chanx_right_out, - top_grid_pin_16_, - top_grid_pin_17_, - top_grid_pin_18_, - top_grid_pin_19_, - top_grid_pin_20_, - top_grid_pin_21_, - top_grid_pin_22_, - top_grid_pin_23_, - top_grid_pin_24_, - top_grid_pin_25_, - top_grid_pin_26_, - top_grid_pin_27_, - top_grid_pin_28_, - top_grid_pin_29_, - top_grid_pin_30_, - top_grid_pin_31_, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chanx_left_in; -// -input [0:19] chanx_right_in; -// -input [0:0] ccff_head; -// -output [0:19] chanx_left_out; -// -output [0:19] chanx_right_out; -// -output [0:0] top_grid_pin_16_; -// -output [0:0] top_grid_pin_17_; -// -output [0:0] top_grid_pin_18_; -// -output [0:0] top_grid_pin_19_; -// -output [0:0] top_grid_pin_20_; -// -output [0:0] top_grid_pin_21_; -// -output [0:0] top_grid_pin_22_; -// -output [0:0] top_grid_pin_23_; -// -output [0:0] top_grid_pin_24_; -// -output [0:0] top_grid_pin_25_; -// -output [0:0] top_grid_pin_26_; -// -output [0:0] top_grid_pin_27_; -// -output [0:0] top_grid_pin_28_; -// -output [0:0] top_grid_pin_29_; -// -output [0:0] top_grid_pin_30_; -// -output [0:0] top_grid_pin_31_; -// -output [0:0] ccff_tail; - -// -// -// -// +module cbx_1__1_ +( + input [0:0] prog_clk, + input [0:19] chanx_left_in, + input [0:19] chanx_right_in, + input [0:0] ccff_head, + output [0:19] chanx_left_out, + output [0:19] chanx_right_out, + output [0:0] bottom_grid_pin_0_, + output [0:0] bottom_grid_pin_1_, + output [0:0] bottom_grid_pin_2_, + output [0:0] bottom_grid_pin_3_, + output [0:0] bottom_grid_pin_4_, + output [0:0] bottom_grid_pin_5_, + output [0:0] bottom_grid_pin_6_, + output [0:0] bottom_grid_pin_7_, + output [0:0] bottom_grid_pin_8_, + output [0:0] bottom_grid_pin_9_, + output [0:0] bottom_grid_pin_10_, + output [0:0] bottom_grid_pin_11_, + output [0:0] bottom_grid_pin_12_, + output [0:0] bottom_grid_pin_13_, + output [0:0] bottom_grid_pin_14_, + output [0:0] bottom_grid_pin_15_, + output [0:0] ccff_tail, + input CLB_SC_IN, + output CLB_SC_OUT, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_2_sram; + wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_3_sram; + wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_4_sram; + wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_5_sram; + wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_6_sram; + wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_7_sram; + wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_2_sram; + wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_3_sram; + wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_4_sram; + wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_5_sram; + wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_6_sram; + wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_7_sram; + wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; + assign chanx_right_out[0] = chanx_left_in[0]; + assign chanx_right_out[1] = chanx_left_in[1]; + assign chanx_right_out[2] = chanx_left_in[2]; + assign chanx_right_out[3] = chanx_left_in[3]; + assign chanx_right_out[4] = chanx_left_in[4]; + assign chanx_right_out[5] = chanx_left_in[5]; + assign chanx_right_out[6] = chanx_left_in[6]; + assign chanx_right_out[7] = chanx_left_in[7]; + assign chanx_right_out[8] = chanx_left_in[8]; + assign chanx_right_out[9] = chanx_left_in[9]; + assign chanx_right_out[10] = chanx_left_in[10]; + assign chanx_right_out[11] = chanx_left_in[11]; + assign chanx_right_out[12] = chanx_left_in[12]; + assign chanx_right_out[13] = chanx_left_in[13]; + assign chanx_right_out[14] = chanx_left_in[14]; + assign chanx_right_out[15] = chanx_left_in[15]; + assign chanx_right_out[16] = chanx_left_in[16]; + assign chanx_right_out[17] = chanx_left_in[17]; + assign chanx_right_out[18] = chanx_left_in[18]; + assign chanx_right_out[19] = chanx_left_in[19]; + assign chanx_left_out[0] = chanx_right_in[0]; + assign chanx_left_out[1] = chanx_right_in[1]; + assign chanx_left_out[2] = chanx_right_in[2]; + assign chanx_left_out[3] = chanx_right_in[3]; + assign chanx_left_out[4] = chanx_right_in[4]; + assign chanx_left_out[5] = chanx_right_in[5]; + assign chanx_left_out[6] = chanx_right_in[6]; + assign chanx_left_out[7] = chanx_right_in[7]; + assign chanx_left_out[8] = chanx_right_in[8]; + assign chanx_left_out[9] = chanx_right_in[9]; + assign chanx_left_out[10] = chanx_right_in[10]; + assign chanx_left_out[11] = chanx_right_in[11]; + assign chanx_left_out[12] = chanx_right_in[12]; + assign chanx_left_out[13] = chanx_right_in[13]; + assign chanx_left_out[14] = chanx_right_in[14]; + assign chanx_left_out[15] = chanx_right_in[15]; + assign chanx_left_out[16] = chanx_right_in[16]; + assign chanx_left_out[17] = chanx_right_in[17]; + assign chanx_left_out[18] = chanx_right_in[18]; + assign chanx_left_out[19] = chanx_right_in[19]; + assign CLB_SC_OUT = CLB_SC_IN; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size10 + mux_top_ipin_0 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(bottom_grid_pin_0_[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_2_sram; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_3_sram; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_4_sram; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_5_sram; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_6_sram; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_7_sram; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; -wire [0:3] mux_tree_tapbuf_size8_0_sram; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_1_sram; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_2_sram; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_3_sram; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_4_sram; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_5_sram; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_6_sram; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_7_sram; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + mux_tree_tapbuf_size10 + mux_top_ipin_3 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(bottom_grid_pin_3_[0]) + ); -// -// -// -// - assign chanx_right_out[0] = chanx_left_in[0]; -// -// -// - assign chanx_right_out[1] = chanx_left_in[1]; -// -// -// - assign chanx_right_out[2] = chanx_left_in[2]; -// -// -// - assign chanx_right_out[3] = chanx_left_in[3]; -// -// -// - assign chanx_right_out[4] = chanx_left_in[4]; -// -// -// - assign chanx_right_out[5] = chanx_left_in[5]; -// -// -// - assign chanx_right_out[6] = chanx_left_in[6]; -// -// -// - assign chanx_right_out[7] = chanx_left_in[7]; -// -// -// - assign chanx_right_out[8] = chanx_left_in[8]; -// -// -// - assign chanx_right_out[9] = chanx_left_in[9]; -// -// -// - assign chanx_right_out[10] = chanx_left_in[10]; -// -// -// - assign chanx_right_out[11] = chanx_left_in[11]; -// -// -// - assign chanx_right_out[12] = chanx_left_in[12]; -// -// -// - assign chanx_right_out[13] = chanx_left_in[13]; -// -// -// - assign chanx_right_out[14] = chanx_left_in[14]; -// -// -// - assign chanx_right_out[15] = chanx_left_in[15]; -// -// -// - assign chanx_right_out[16] = chanx_left_in[16]; -// -// -// - assign chanx_right_out[17] = chanx_left_in[17]; -// -// -// - assign chanx_right_out[18] = chanx_left_in[18]; -// -// -// - assign chanx_right_out[19] = chanx_left_in[19]; -// -// -// - assign chanx_left_out[0] = chanx_right_in[0]; -// -// -// - assign chanx_left_out[1] = chanx_right_in[1]; -// -// -// - assign chanx_left_out[2] = chanx_right_in[2]; -// -// -// - assign chanx_left_out[3] = chanx_right_in[3]; -// -// -// - assign chanx_left_out[4] = chanx_right_in[4]; -// -// -// - assign chanx_left_out[5] = chanx_right_in[5]; -// -// -// - assign chanx_left_out[6] = chanx_right_in[6]; -// -// -// - assign chanx_left_out[7] = chanx_right_in[7]; -// -// -// - assign chanx_left_out[8] = chanx_right_in[8]; -// -// -// - assign chanx_left_out[9] = chanx_right_in[9]; -// -// -// - assign chanx_left_out[10] = chanx_right_in[10]; -// -// -// - assign chanx_left_out[11] = chanx_right_in[11]; -// -// -// - assign chanx_left_out[12] = chanx_right_in[12]; -// -// -// - assign chanx_left_out[13] = chanx_right_in[13]; -// -// -// - assign chanx_left_out[14] = chanx_right_in[14]; -// -// -// - assign chanx_left_out[15] = chanx_right_in[15]; -// -// -// - assign chanx_left_out[16] = chanx_right_in[16]; -// -// -// - assign chanx_left_out[17] = chanx_right_in[17]; -// -// -// - assign chanx_left_out[18] = chanx_right_in[18]; -// -// -// - assign chanx_left_out[19] = chanx_right_in[19]; -// -// -// - mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(top_grid_pin_16_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_4 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(bottom_grid_pin_4_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_1 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), - .out(top_grid_pin_17_[0])); - mux_tree_tapbuf_size10 mux_bottom_ipin_4 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), - .out(top_grid_pin_20_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_7 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(bottom_grid_pin_7_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_5 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), - .out(top_grid_pin_21_[0])); - mux_tree_tapbuf_size10 mux_bottom_ipin_8 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), - .out(top_grid_pin_24_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_8 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(bottom_grid_pin_8_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_9 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19]}), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), - .out(top_grid_pin_25_[0])); - mux_tree_tapbuf_size10 mux_bottom_ipin_12 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16]}), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), - .out(top_grid_pin_28_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_11 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[15], chanx_right_in[15] }), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(bottom_grid_pin_11_[0]) + ); - mux_tree_tapbuf_size10 mux_bottom_ipin_13 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17]}), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), - .out(top_grid_pin_29_[0])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + mux_tree_tapbuf_size10 + mux_top_ipin_12 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(bottom_grid_pin_12_[0]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); + mux_tree_tapbuf_size10 + mux_top_ipin_15 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[19], chanx_right_in[19] }), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(bottom_grid_pin_15_[0]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); - mux_tree_tapbuf_size8 mux_bottom_ipin_2 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), - .out(top_grid_pin_18_[0])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_3 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), - .out(top_grid_pin_19_[0])); - mux_tree_tapbuf_size8 mux_bottom_ipin_6 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), - .out(top_grid_pin_22_[0])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}), - .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), - .out(top_grid_pin_23_[0])); - mux_tree_tapbuf_size8 mux_bottom_ipin_10 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), - .out(top_grid_pin_26_[0])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_11 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), - .out(top_grid_pin_27_[0])); - mux_tree_tapbuf_size8 mux_bottom_ipin_14 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), - .out(top_grid_pin_30_[0])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_bottom_ipin_15 ( - .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}), - .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), - .out(top_grid_pin_31_[0])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_top_ipin_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])); + mux_tree_tapbuf_size8 + mux_top_ipin_1 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(bottom_grid_pin_1_[0]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])); + mux_tree_tapbuf_size8 + mux_top_ipin_2 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(bottom_grid_pin_2_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_5 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(bottom_grid_pin_5_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_6 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size8_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .out(bottom_grid_pin_6_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_9 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }), + .sram(mux_tree_tapbuf_size8_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .out(bottom_grid_pin_9_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_10 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size8_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .out(bottom_grid_pin_10_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_13 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }), + .sram(mux_tree_tapbuf_size8_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .out(bottom_grid_pin_13_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_14 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size8_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .out(bottom_grid_pin_14_[0]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_ipin_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])); endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v index 23694e7..4b0b6f0 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v @@ -1,230 +1,508 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module cbx_1__2_(prog_clk, - chanx_left_in, - chanx_right_in, - ccff_head, - chanx_left_out, - chanx_right_out, - top_grid_pin_0_, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chanx_left_in; -// -input [0:19] chanx_right_in; -// -input [0:0] ccff_head; -// -output [0:19] chanx_left_out; -// -output [0:19] chanx_right_out; -// -output [0:0] top_grid_pin_0_; -// -output [0:0] ccff_tail; - -// -// -// -// +module cbx_1__2_ +( + input [0:0] prog_clk, + input [0:19] chanx_left_in, + input [0:19] chanx_right_in, + input [0:0] ccff_head, + output [0:19] chanx_left_out, + output [0:19] chanx_right_out, + output [0:0] top_grid_pin_0_, + output [0:0] bottom_grid_pin_0_, + output [0:0] bottom_grid_pin_1_, + output [0:0] bottom_grid_pin_2_, + output [0:0] bottom_grid_pin_3_, + output [0:0] bottom_grid_pin_4_, + output [0:0] bottom_grid_pin_5_, + output [0:0] bottom_grid_pin_6_, + output [0:0] bottom_grid_pin_7_, + output [0:0] bottom_grid_pin_8_, + output [0:0] bottom_grid_pin_9_, + output [0:0] bottom_grid_pin_10_, + output [0:0] bottom_grid_pin_11_, + output [0:0] bottom_grid_pin_12_, + output [0:0] bottom_grid_pin_13_, + output [0:0] bottom_grid_pin_14_, + output [0:0] bottom_grid_pin_15_, + output [0:0] ccff_tail, + input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN, + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT, + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR, + input [0:0] bottom_width_0_height_0__pin_0_, + output [0:0] bottom_width_0_height_0__pin_1_upper, + output [0:0] bottom_width_0_height_0__pin_1_lower, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_2_sram; + wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_3_sram; + wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_4_sram; + wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_5_sram; + wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_6_sram; + wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_7_sram; + wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_8_sram; + wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_2_sram; + wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_3_sram; + wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_4_sram; + wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_5_sram; + wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_6_sram; + wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_7_sram; + wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; + wire ccff_tail_mid; + assign chanx_right_out[0] = chanx_left_in[0]; + assign chanx_right_out[1] = chanx_left_in[1]; + assign chanx_right_out[2] = chanx_left_in[2]; + assign chanx_right_out[3] = chanx_left_in[3]; + assign chanx_right_out[4] = chanx_left_in[4]; + assign chanx_right_out[5] = chanx_left_in[5]; + assign chanx_right_out[6] = chanx_left_in[6]; + assign chanx_right_out[7] = chanx_left_in[7]; + assign chanx_right_out[8] = chanx_left_in[8]; + assign chanx_right_out[9] = chanx_left_in[9]; + assign chanx_right_out[10] = chanx_left_in[10]; + assign chanx_right_out[11] = chanx_left_in[11]; + assign chanx_right_out[12] = chanx_left_in[12]; + assign chanx_right_out[13] = chanx_left_in[13]; + assign chanx_right_out[14] = chanx_left_in[14]; + assign chanx_right_out[15] = chanx_left_in[15]; + assign chanx_right_out[16] = chanx_left_in[16]; + assign chanx_right_out[17] = chanx_left_in[17]; + assign chanx_right_out[18] = chanx_left_in[18]; + assign chanx_right_out[19] = chanx_left_in[19]; + assign chanx_left_out[0] = chanx_right_in[0]; + assign chanx_left_out[1] = chanx_right_in[1]; + assign chanx_left_out[2] = chanx_right_in[2]; + assign chanx_left_out[3] = chanx_right_in[3]; + assign chanx_left_out[4] = chanx_right_in[4]; + assign chanx_left_out[5] = chanx_right_in[5]; + assign chanx_left_out[6] = chanx_right_in[6]; + assign chanx_left_out[7] = chanx_right_in[7]; + assign chanx_left_out[8] = chanx_right_in[8]; + assign chanx_left_out[9] = chanx_right_in[9]; + assign chanx_left_out[10] = chanx_right_in[10]; + assign chanx_left_out[11] = chanx_right_in[11]; + assign chanx_left_out[12] = chanx_right_in[12]; + assign chanx_left_out[13] = chanx_right_in[13]; + assign chanx_left_out[14] = chanx_right_in[14]; + assign chanx_left_out[15] = chanx_right_in[15]; + assign chanx_left_out[16] = chanx_right_in[16]; + assign chanx_left_out[17] = chanx_right_in[17]; + assign chanx_left_out[18] = chanx_right_in[18]; + assign chanx_left_out[19] = chanx_right_in[19]; + assign bottom_width_0_height_0__pin_1_lower[0] = bottom_width_0_height_0__pin_1_upper[0]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size10 + mux_bottom_ipin_0 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(top_grid_pin_0_[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + mux_tree_tapbuf_size10 + mux_top_ipin_0 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(bottom_grid_pin_0_[0]) + ); -// -// -// -// - assign chanx_right_out[0] = chanx_left_in[0]; -// -// -// - assign chanx_right_out[1] = chanx_left_in[1]; -// -// -// - assign chanx_right_out[2] = chanx_left_in[2]; -// -// -// - assign chanx_right_out[3] = chanx_left_in[3]; -// -// -// - assign chanx_right_out[4] = chanx_left_in[4]; -// -// -// - assign chanx_right_out[5] = chanx_left_in[5]; -// -// -// - assign chanx_right_out[6] = chanx_left_in[6]; -// -// -// - assign chanx_right_out[7] = chanx_left_in[7]; -// -// -// - assign chanx_right_out[8] = chanx_left_in[8]; -// -// -// - assign chanx_right_out[9] = chanx_left_in[9]; -// -// -// - assign chanx_right_out[10] = chanx_left_in[10]; -// -// -// - assign chanx_right_out[11] = chanx_left_in[11]; -// -// -// - assign chanx_right_out[12] = chanx_left_in[12]; -// -// -// - assign chanx_right_out[13] = chanx_left_in[13]; -// -// -// - assign chanx_right_out[14] = chanx_left_in[14]; -// -// -// - assign chanx_right_out[15] = chanx_left_in[15]; -// -// -// - assign chanx_right_out[16] = chanx_left_in[16]; -// -// -// - assign chanx_right_out[17] = chanx_left_in[17]; -// -// -// - assign chanx_right_out[18] = chanx_left_in[18]; -// -// -// - assign chanx_right_out[19] = chanx_left_in[19]; -// -// -// - assign chanx_left_out[0] = chanx_right_in[0]; -// -// -// - assign chanx_left_out[1] = chanx_right_in[1]; -// -// -// - assign chanx_left_out[2] = chanx_right_in[2]; -// -// -// - assign chanx_left_out[3] = chanx_right_in[3]; -// -// -// - assign chanx_left_out[4] = chanx_right_in[4]; -// -// -// - assign chanx_left_out[5] = chanx_right_in[5]; -// -// -// - assign chanx_left_out[6] = chanx_right_in[6]; -// -// -// - assign chanx_left_out[7] = chanx_right_in[7]; -// -// -// - assign chanx_left_out[8] = chanx_right_in[8]; -// -// -// - assign chanx_left_out[9] = chanx_right_in[9]; -// -// -// - assign chanx_left_out[10] = chanx_right_in[10]; -// -// -// - assign chanx_left_out[11] = chanx_right_in[11]; -// -// -// - assign chanx_left_out[12] = chanx_right_in[12]; -// -// -// - assign chanx_left_out[13] = chanx_right_in[13]; -// -// -// - assign chanx_left_out[14] = chanx_right_in[14]; -// -// -// - assign chanx_left_out[15] = chanx_right_in[15]; -// -// -// - assign chanx_left_out[16] = chanx_right_in[16]; -// -// -// - assign chanx_left_out[17] = chanx_right_in[17]; -// -// -// - assign chanx_left_out[18] = chanx_right_in[18]; -// -// -// - assign chanx_left_out[19] = chanx_right_in[19]; -// -// -// - mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( - .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(top_grid_pin_0_[0])); + mux_tree_tapbuf_size10 + mux_top_ipin_3 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(bottom_grid_pin_3_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_top_ipin_4 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(bottom_grid_pin_4_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_top_ipin_7 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(bottom_grid_pin_7_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_top_ipin_8 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(bottom_grid_pin_8_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_top_ipin_11 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(bottom_grid_pin_11_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_top_ipin_12 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17] }), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(bottom_grid_pin_12_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_top_ipin_15 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), + .sram(mux_tree_tapbuf_size10_8_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), + .out(bottom_grid_pin_15_[0]) + ); + + + mux_tree_tapbuf_size10_mem + mem_bottom_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_ipin_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_1 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(bottom_grid_pin_1_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_2 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(bottom_grid_pin_2_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_5 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(bottom_grid_pin_5_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_6 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }), + .sram(mux_tree_tapbuf_size8_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .out(bottom_grid_pin_6_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_9 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size8_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .out(bottom_grid_pin_9_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_10 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }), + .sram(mux_tree_tapbuf_size8_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .out(bottom_grid_pin_10_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_13 + ( + .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size8_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .out(bottom_grid_pin_13_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_top_ipin_14 + ( + .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }), + .sram(mux_tree_tapbuf_size8_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .out(bottom_grid_pin_14_[0]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_ipin_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) + ); + + + logical_tile_io_mode_io_ + logical_tile_io_mode_io__0 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), + .io_outpad(bottom_width_0_height_0__pin_0_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(bottom_width_0_height_0__pin_1_upper[0]), + .ccff_tail(ccff_tail[0]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v index 169d56d..a7f5a19 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v @@ -1,249 +1,102 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module cby_0__1_(prog_clk, - chany_bottom_in, - chany_top_in, - ccff_head, - chany_bottom_out, - chany_top_out, - right_grid_pin_52_, - left_grid_pin_0_, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_bottom_in; -// -input [0:19] chany_top_in; -// -input [0:0] ccff_head; -// -output [0:19] chany_bottom_out; -// -output [0:19] chany_top_out; -// -output [0:0] right_grid_pin_52_; -// -output [0:0] left_grid_pin_0_; -// -output [0:0] ccff_tail; - -// -// -// -// +module cby_0__1_ +( + input [0:0] prog_clk, + input [0:19] chany_bottom_in, + input [0:19] chany_top_in, + input [0:0] ccff_head, + output [0:19] chany_bottom_out, + output [0:19] chany_top_out, + output [0:0] left_grid_pin_0_, + output [0:0] ccff_tail, + input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN, + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT, + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR, + input [0:0] right_width_0_height_0__pin_0_, + output [0:0] right_width_0_height_0__pin_1_upper, + output [0:0] right_width_0_height_0__pin_1_lower +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire ccff_tail_mid; + assign chany_top_out[0] = chany_bottom_in[0]; + assign chany_top_out[1] = chany_bottom_in[1]; + assign chany_top_out[2] = chany_bottom_in[2]; + assign chany_top_out[3] = chany_bottom_in[3]; + assign chany_top_out[4] = chany_bottom_in[4]; + assign chany_top_out[5] = chany_bottom_in[5]; + assign chany_top_out[6] = chany_bottom_in[6]; + assign chany_top_out[7] = chany_bottom_in[7]; + assign chany_top_out[8] = chany_bottom_in[8]; + assign chany_top_out[9] = chany_bottom_in[9]; + assign chany_top_out[10] = chany_bottom_in[10]; + assign chany_top_out[11] = chany_bottom_in[11]; + assign chany_top_out[12] = chany_bottom_in[12]; + assign chany_top_out[13] = chany_bottom_in[13]; + assign chany_top_out[14] = chany_bottom_in[14]; + assign chany_top_out[15] = chany_bottom_in[15]; + assign chany_top_out[16] = chany_bottom_in[16]; + assign chany_top_out[17] = chany_bottom_in[17]; + assign chany_top_out[18] = chany_bottom_in[18]; + assign chany_top_out[19] = chany_bottom_in[19]; + assign chany_bottom_out[0] = chany_top_in[0]; + assign chany_bottom_out[1] = chany_top_in[1]; + assign chany_bottom_out[2] = chany_top_in[2]; + assign chany_bottom_out[3] = chany_top_in[3]; + assign chany_bottom_out[4] = chany_top_in[4]; + assign chany_bottom_out[5] = chany_top_in[5]; + assign chany_bottom_out[6] = chany_top_in[6]; + assign chany_bottom_out[7] = chany_top_in[7]; + assign chany_bottom_out[8] = chany_top_in[8]; + assign chany_bottom_out[9] = chany_top_in[9]; + assign chany_bottom_out[10] = chany_top_in[10]; + assign chany_bottom_out[11] = chany_top_in[11]; + assign chany_bottom_out[12] = chany_top_in[12]; + assign chany_bottom_out[13] = chany_top_in[13]; + assign chany_bottom_out[14] = chany_top_in[14]; + assign chany_bottom_out[15] = chany_top_in[15]; + assign chany_bottom_out[16] = chany_top_in[16]; + assign chany_bottom_out[17] = chany_top_in[17]; + assign chany_bottom_out[18] = chany_top_in[18]; + assign chany_bottom_out[19] = chany_top_in[19]; + assign right_width_0_height_0__pin_1_lower[0] = right_width_0_height_0__pin_1_upper[0]; + + mux_tree_tapbuf_size10 + mux_right_ipin_0 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(left_grid_pin_0_[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + mux_tree_tapbuf_size10_mem + mem_right_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); -// -// -// -// - assign chany_top_out[0] = chany_bottom_in[0]; -// -// -// - assign chany_top_out[1] = chany_bottom_in[1]; -// -// -// - assign chany_top_out[2] = chany_bottom_in[2]; -// -// -// - assign chany_top_out[3] = chany_bottom_in[3]; -// -// -// - assign chany_top_out[4] = chany_bottom_in[4]; -// -// -// - assign chany_top_out[5] = chany_bottom_in[5]; -// -// -// - assign chany_top_out[6] = chany_bottom_in[6]; -// -// -// - assign chany_top_out[7] = chany_bottom_in[7]; -// -// -// - assign chany_top_out[8] = chany_bottom_in[8]; -// -// -// - assign chany_top_out[9] = chany_bottom_in[9]; -// -// -// - assign chany_top_out[10] = chany_bottom_in[10]; -// -// -// - assign chany_top_out[11] = chany_bottom_in[11]; -// -// -// - assign chany_top_out[12] = chany_bottom_in[12]; -// -// -// - assign chany_top_out[13] = chany_bottom_in[13]; -// -// -// - assign chany_top_out[14] = chany_bottom_in[14]; -// -// -// - assign chany_top_out[15] = chany_bottom_in[15]; -// -// -// - assign chany_top_out[16] = chany_bottom_in[16]; -// -// -// - assign chany_top_out[17] = chany_bottom_in[17]; -// -// -// - assign chany_top_out[18] = chany_bottom_in[18]; -// -// -// - assign chany_top_out[19] = chany_bottom_in[19]; -// -// -// - assign chany_bottom_out[0] = chany_top_in[0]; -// -// -// - assign chany_bottom_out[1] = chany_top_in[1]; -// -// -// - assign chany_bottom_out[2] = chany_top_in[2]; -// -// -// - assign chany_bottom_out[3] = chany_top_in[3]; -// -// -// - assign chany_bottom_out[4] = chany_top_in[4]; -// -// -// - assign chany_bottom_out[5] = chany_top_in[5]; -// -// -// - assign chany_bottom_out[6] = chany_top_in[6]; -// -// -// - assign chany_bottom_out[7] = chany_top_in[7]; -// -// -// - assign chany_bottom_out[8] = chany_top_in[8]; -// -// -// - assign chany_bottom_out[9] = chany_top_in[9]; -// -// -// - assign chany_bottom_out[10] = chany_top_in[10]; -// -// -// - assign chany_bottom_out[11] = chany_top_in[11]; -// -// -// - assign chany_bottom_out[12] = chany_top_in[12]; -// -// -// - assign chany_bottom_out[13] = chany_top_in[13]; -// -// -// - assign chany_bottom_out[14] = chany_top_in[14]; -// -// -// - assign chany_bottom_out[15] = chany_top_in[15]; -// -// -// - assign chany_bottom_out[16] = chany_top_in[16]; -// -// -// - assign chany_bottom_out[17] = chany_top_in[17]; -// -// -// - assign chany_bottom_out[18] = chany_top_in[18]; -// -// -// - assign chany_bottom_out[19] = chany_top_in[19]; -// -// -// - mux_tree_tapbuf_size10 mux_left_ipin_0 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(right_grid_pin_52_[0])); + logical_tile_io_mode_io_ + logical_tile_io_mode_io__0 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), + .io_outpad(right_width_0_height_0__pin_0_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(right_width_0_height_0__pin_1_upper[0]), + .ccff_tail(ccff_tail[0]) + ); - mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), - .out(left_grid_pin_0_[0])); - - mux_tree_tapbuf_size10_mem mem_left_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); - - mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v index 72ba185..0c41972 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v @@ -1,534 +1,455 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module cby_1__1_(prog_clk, - chany_bottom_in, - chany_top_in, - ccff_head, - chany_bottom_out, - chany_top_out, - right_grid_pin_52_, - left_grid_pin_0_, - left_grid_pin_1_, - left_grid_pin_2_, - left_grid_pin_3_, - left_grid_pin_4_, - left_grid_pin_5_, - left_grid_pin_6_, - left_grid_pin_7_, - left_grid_pin_8_, - left_grid_pin_9_, - left_grid_pin_10_, - left_grid_pin_11_, - left_grid_pin_12_, - left_grid_pin_13_, - left_grid_pin_14_, - left_grid_pin_15_, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_bottom_in; -// -input [0:19] chany_top_in; -// -input [0:0] ccff_head; -// -output [0:19] chany_bottom_out; -// -output [0:19] chany_top_out; -// -output [0:0] right_grid_pin_52_; -// -output [0:0] left_grid_pin_0_; -// -output [0:0] left_grid_pin_1_; -// -output [0:0] left_grid_pin_2_; -// -output [0:0] left_grid_pin_3_; -// -output [0:0] left_grid_pin_4_; -// -output [0:0] left_grid_pin_5_; -// -output [0:0] left_grid_pin_6_; -// -output [0:0] left_grid_pin_7_; -// -output [0:0] left_grid_pin_8_; -// -output [0:0] left_grid_pin_9_; -// -output [0:0] left_grid_pin_10_; -// -output [0:0] left_grid_pin_11_; -// -output [0:0] left_grid_pin_12_; -// -output [0:0] left_grid_pin_13_; -// -output [0:0] left_grid_pin_14_; -// -output [0:0] left_grid_pin_15_; -// -output [0:0] ccff_tail; - -// -// -// -// +module cby_1__1_ +( + input [0:0] prog_clk, + input [0:19] chany_bottom_in, + input [0:19] chany_top_in, + input [0:0] ccff_head, + output [0:19] chany_bottom_out, + output [0:19] chany_top_out, + output [0:0] left_grid_pin_16_, + output [0:0] left_grid_pin_17_, + output [0:0] left_grid_pin_18_, + output [0:0] left_grid_pin_19_, + output [0:0] left_grid_pin_20_, + output [0:0] left_grid_pin_21_, + output [0:0] left_grid_pin_22_, + output [0:0] left_grid_pin_23_, + output [0:0] left_grid_pin_24_, + output [0:0] left_grid_pin_25_, + output [0:0] left_grid_pin_26_, + output [0:0] left_grid_pin_27_, + output [0:0] left_grid_pin_28_, + output [0:0] left_grid_pin_29_, + output [0:0] left_grid_pin_30_, + output [0:0] left_grid_pin_31_, + output [0:0] ccff_tail +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_2_sram; + wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_3_sram; + wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_4_sram; + wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_5_sram; + wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_6_sram; + wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_7_sram; + wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_2_sram; + wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_3_sram; + wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_4_sram; + wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_5_sram; + wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_6_sram; + wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_7_sram; + wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; + assign chany_top_out[0] = chany_bottom_in[0]; + assign chany_top_out[1] = chany_bottom_in[1]; + assign chany_top_out[2] = chany_bottom_in[2]; + assign chany_top_out[3] = chany_bottom_in[3]; + assign chany_top_out[4] = chany_bottom_in[4]; + assign chany_top_out[5] = chany_bottom_in[5]; + assign chany_top_out[6] = chany_bottom_in[6]; + assign chany_top_out[7] = chany_bottom_in[7]; + assign chany_top_out[8] = chany_bottom_in[8]; + assign chany_top_out[9] = chany_bottom_in[9]; + assign chany_top_out[10] = chany_bottom_in[10]; + assign chany_top_out[11] = chany_bottom_in[11]; + assign chany_top_out[12] = chany_bottom_in[12]; + assign chany_top_out[13] = chany_bottom_in[13]; + assign chany_top_out[14] = chany_bottom_in[14]; + assign chany_top_out[15] = chany_bottom_in[15]; + assign chany_top_out[16] = chany_bottom_in[16]; + assign chany_top_out[17] = chany_bottom_in[17]; + assign chany_top_out[18] = chany_bottom_in[18]; + assign chany_top_out[19] = chany_bottom_in[19]; + assign chany_bottom_out[0] = chany_top_in[0]; + assign chany_bottom_out[1] = chany_top_in[1]; + assign chany_bottom_out[2] = chany_top_in[2]; + assign chany_bottom_out[3] = chany_top_in[3]; + assign chany_bottom_out[4] = chany_top_in[4]; + assign chany_bottom_out[5] = chany_top_in[5]; + assign chany_bottom_out[6] = chany_top_in[6]; + assign chany_bottom_out[7] = chany_top_in[7]; + assign chany_bottom_out[8] = chany_top_in[8]; + assign chany_bottom_out[9] = chany_top_in[9]; + assign chany_bottom_out[10] = chany_top_in[10]; + assign chany_bottom_out[11] = chany_top_in[11]; + assign chany_bottom_out[12] = chany_top_in[12]; + assign chany_bottom_out[13] = chany_top_in[13]; + assign chany_bottom_out[14] = chany_top_in[14]; + assign chany_bottom_out[15] = chany_top_in[15]; + assign chany_bottom_out[16] = chany_top_in[16]; + assign chany_bottom_out[17] = chany_top_in[17]; + assign chany_bottom_out[18] = chany_top_in[18]; + assign chany_bottom_out[19] = chany_top_in[19]; + + mux_tree_tapbuf_size10 + mux_right_ipin_0 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(left_grid_pin_16_[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_2_sram; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_3_sram; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_4_sram; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_5_sram; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_6_sram; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_7_sram; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_8_sram; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; -wire [0:3] mux_tree_tapbuf_size8_0_sram; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_1_sram; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_2_sram; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_3_sram; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_4_sram; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_5_sram; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_6_sram; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_7_sram; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + mux_tree_tapbuf_size10 + mux_right_ipin_3 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(left_grid_pin_19_[0]) + ); -// -// -// -// - assign chany_top_out[0] = chany_bottom_in[0]; -// -// -// - assign chany_top_out[1] = chany_bottom_in[1]; -// -// -// - assign chany_top_out[2] = chany_bottom_in[2]; -// -// -// - assign chany_top_out[3] = chany_bottom_in[3]; -// -// -// - assign chany_top_out[4] = chany_bottom_in[4]; -// -// -// - assign chany_top_out[5] = chany_bottom_in[5]; -// -// -// - assign chany_top_out[6] = chany_bottom_in[6]; -// -// -// - assign chany_top_out[7] = chany_bottom_in[7]; -// -// -// - assign chany_top_out[8] = chany_bottom_in[8]; -// -// -// - assign chany_top_out[9] = chany_bottom_in[9]; -// -// -// - assign chany_top_out[10] = chany_bottom_in[10]; -// -// -// - assign chany_top_out[11] = chany_bottom_in[11]; -// -// -// - assign chany_top_out[12] = chany_bottom_in[12]; -// -// -// - assign chany_top_out[13] = chany_bottom_in[13]; -// -// -// - assign chany_top_out[14] = chany_bottom_in[14]; -// -// -// - assign chany_top_out[15] = chany_bottom_in[15]; -// -// -// - assign chany_top_out[16] = chany_bottom_in[16]; -// -// -// - assign chany_top_out[17] = chany_bottom_in[17]; -// -// -// - assign chany_top_out[18] = chany_bottom_in[18]; -// -// -// - assign chany_top_out[19] = chany_bottom_in[19]; -// -// -// - assign chany_bottom_out[0] = chany_top_in[0]; -// -// -// - assign chany_bottom_out[1] = chany_top_in[1]; -// -// -// - assign chany_bottom_out[2] = chany_top_in[2]; -// -// -// - assign chany_bottom_out[3] = chany_top_in[3]; -// -// -// - assign chany_bottom_out[4] = chany_top_in[4]; -// -// -// - assign chany_bottom_out[5] = chany_top_in[5]; -// -// -// - assign chany_bottom_out[6] = chany_top_in[6]; -// -// -// - assign chany_bottom_out[7] = chany_top_in[7]; -// -// -// - assign chany_bottom_out[8] = chany_top_in[8]; -// -// -// - assign chany_bottom_out[9] = chany_top_in[9]; -// -// -// - assign chany_bottom_out[10] = chany_top_in[10]; -// -// -// - assign chany_bottom_out[11] = chany_top_in[11]; -// -// -// - assign chany_bottom_out[12] = chany_top_in[12]; -// -// -// - assign chany_bottom_out[13] = chany_top_in[13]; -// -// -// - assign chany_bottom_out[14] = chany_top_in[14]; -// -// -// - assign chany_bottom_out[15] = chany_top_in[15]; -// -// -// - assign chany_bottom_out[16] = chany_top_in[16]; -// -// -// - assign chany_bottom_out[17] = chany_top_in[17]; -// -// -// - assign chany_bottom_out[18] = chany_top_in[18]; -// -// -// - assign chany_bottom_out[19] = chany_top_in[19]; -// -// -// - mux_tree_tapbuf_size10 mux_left_ipin_0 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(right_grid_pin_52_[0])); + mux_tree_tapbuf_size10 + mux_right_ipin_4 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(left_grid_pin_20_[0]) + ); - mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), - .out(left_grid_pin_0_[0])); - mux_tree_tapbuf_size10 mux_right_ipin_1 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18]}), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), - .out(left_grid_pin_1_[0])); + mux_tree_tapbuf_size10 + mux_right_ipin_7 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(left_grid_pin_23_[0]) + ); - mux_tree_tapbuf_size10 mux_right_ipin_4 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15]}), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), - .out(left_grid_pin_4_[0])); - mux_tree_tapbuf_size10 mux_right_ipin_5 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16]}), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), - .out(left_grid_pin_5_[0])); + mux_tree_tapbuf_size10 + mux_right_ipin_8 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(left_grid_pin_24_[0]) + ); - mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19]}), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), - .out(left_grid_pin_8_[0])); - mux_tree_tapbuf_size10 mux_right_ipin_9 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[14], chany_top_in[14]}), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), - .out(left_grid_pin_9_[0])); + mux_tree_tapbuf_size10 + mux_right_ipin_11 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[15], chany_top_in[15] }), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(left_grid_pin_27_[0]) + ); - mux_tree_tapbuf_size10 mux_right_ipin_12 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17]}), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), - .out(left_grid_pin_12_[0])); - mux_tree_tapbuf_size10 mux_right_ipin_13 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[18], chany_top_in[18]}), - .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), - .out(left_grid_pin_13_[0])); + mux_tree_tapbuf_size10 + mux_right_ipin_12 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(left_grid_pin_28_[0]) + ); - mux_tree_tapbuf_size10_mem mem_left_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); + mux_tree_tapbuf_size10 + mux_right_ipin_15 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[19], chany_top_in[19] }), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(left_grid_pin_31_[0]) + ); - mux_tree_tapbuf_size10_mem mem_right_ipin_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_right_ipin_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_right_ipin_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_right_ipin_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_right_ipin_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_right_ipin_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])); - mux_tree_tapbuf_size8 mux_right_ipin_2 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15]}), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), - .out(left_grid_pin_2_[0])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_right_ipin_3 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[16], chany_top_in[16]}), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), - .out(left_grid_pin_3_[0])); - mux_tree_tapbuf_size8 mux_right_ipin_6 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19]}), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), - .out(left_grid_pin_6_[0])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_right_ipin_7 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[12], chany_top_in[12]}), - .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), - .out(left_grid_pin_7_[0])); - mux_tree_tapbuf_size8 mux_right_ipin_10 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15]}), - .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), - .out(left_grid_pin_10_[0])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_right_ipin_11 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[16], chany_top_in[16]}), - .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), - .out(left_grid_pin_11_[0])); - mux_tree_tapbuf_size8 mux_right_ipin_14 ( - .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19]}), - .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), - .out(left_grid_pin_14_[0])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8 mux_right_ipin_15 ( - .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[12], chany_top_in[12]}), - .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), - .out(left_grid_pin_15_[0])); - mux_tree_tapbuf_size8_mem mem_right_ipin_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_right_ipin_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8_mem mem_right_ipin_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_right_ipin_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); + mux_tree_tapbuf_size8 + mux_right_ipin_1 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(left_grid_pin_17_[0]) + ); - mux_tree_tapbuf_size8_mem mem_right_ipin_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_right_ipin_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])); + mux_tree_tapbuf_size8 + mux_right_ipin_2 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(left_grid_pin_18_[0]) + ); - mux_tree_tapbuf_size8_mem mem_right_ipin_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])); + mux_tree_tapbuf_size8 + mux_right_ipin_5 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(left_grid_pin_21_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_6 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), + .sram(mux_tree_tapbuf_size8_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .out(left_grid_pin_22_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_9 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }), + .sram(mux_tree_tapbuf_size8_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .out(left_grid_pin_25_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_10 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), + .sram(mux_tree_tapbuf_size8_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .out(left_grid_pin_26_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_13 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }), + .sram(mux_tree_tapbuf_size8_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .out(left_grid_pin_29_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_14 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), + .sram(mux_tree_tapbuf_size8_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .out(left_grid_pin_30_[0]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) + ); - mux_tree_tapbuf_size8_mem mem_right_ipin_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])); endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v new file mode 100644 index 0000000..b4f8f45 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v @@ -0,0 +1,502 @@ + + +module cby_2__1_ +( + input [0:0] prog_clk, + input [0:19] chany_bottom_in, + input [0:19] chany_top_in, + input [0:0] ccff_head, + output [0:19] chany_bottom_out, + output [0:19] chany_top_out, + output [0:0] right_grid_pin_0_, + output [0:0] left_grid_pin_16_, + output [0:0] left_grid_pin_17_, + output [0:0] left_grid_pin_18_, + output [0:0] left_grid_pin_19_, + output [0:0] left_grid_pin_20_, + output [0:0] left_grid_pin_21_, + output [0:0] left_grid_pin_22_, + output [0:0] left_grid_pin_23_, + output [0:0] left_grid_pin_24_, + output [0:0] left_grid_pin_25_, + output [0:0] left_grid_pin_26_, + output [0:0] left_grid_pin_27_, + output [0:0] left_grid_pin_28_, + output [0:0] left_grid_pin_29_, + output [0:0] left_grid_pin_30_, + output [0:0] left_grid_pin_31_, + output [0:0] ccff_tail, + input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN, + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT, + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR, + input [0:0] left_width_0_height_0__pin_0_, + output [0:0] left_width_0_height_0__pin_1_upper, + output [0:0] left_width_0_height_0__pin_1_lower +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_2_sram; + wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_3_sram; + wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_4_sram; + wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_5_sram; + wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_6_sram; + wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_7_sram; + wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_8_sram; + wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_2_sram; + wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_3_sram; + wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_4_sram; + wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_5_sram; + wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_6_sram; + wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_7_sram; + wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; + wire ccff_tail_mid; + assign chany_top_out[0] = chany_bottom_in[0]; + assign chany_top_out[1] = chany_bottom_in[1]; + assign chany_top_out[2] = chany_bottom_in[2]; + assign chany_top_out[3] = chany_bottom_in[3]; + assign chany_top_out[4] = chany_bottom_in[4]; + assign chany_top_out[5] = chany_bottom_in[5]; + assign chany_top_out[6] = chany_bottom_in[6]; + assign chany_top_out[7] = chany_bottom_in[7]; + assign chany_top_out[8] = chany_bottom_in[8]; + assign chany_top_out[9] = chany_bottom_in[9]; + assign chany_top_out[10] = chany_bottom_in[10]; + assign chany_top_out[11] = chany_bottom_in[11]; + assign chany_top_out[12] = chany_bottom_in[12]; + assign chany_top_out[13] = chany_bottom_in[13]; + assign chany_top_out[14] = chany_bottom_in[14]; + assign chany_top_out[15] = chany_bottom_in[15]; + assign chany_top_out[16] = chany_bottom_in[16]; + assign chany_top_out[17] = chany_bottom_in[17]; + assign chany_top_out[18] = chany_bottom_in[18]; + assign chany_top_out[19] = chany_bottom_in[19]; + assign chany_bottom_out[0] = chany_top_in[0]; + assign chany_bottom_out[1] = chany_top_in[1]; + assign chany_bottom_out[2] = chany_top_in[2]; + assign chany_bottom_out[3] = chany_top_in[3]; + assign chany_bottom_out[4] = chany_top_in[4]; + assign chany_bottom_out[5] = chany_top_in[5]; + assign chany_bottom_out[6] = chany_top_in[6]; + assign chany_bottom_out[7] = chany_top_in[7]; + assign chany_bottom_out[8] = chany_top_in[8]; + assign chany_bottom_out[9] = chany_top_in[9]; + assign chany_bottom_out[10] = chany_top_in[10]; + assign chany_bottom_out[11] = chany_top_in[11]; + assign chany_bottom_out[12] = chany_top_in[12]; + assign chany_bottom_out[13] = chany_top_in[13]; + assign chany_bottom_out[14] = chany_top_in[14]; + assign chany_bottom_out[15] = chany_top_in[15]; + assign chany_bottom_out[16] = chany_top_in[16]; + assign chany_bottom_out[17] = chany_top_in[17]; + assign chany_bottom_out[18] = chany_top_in[18]; + assign chany_bottom_out[19] = chany_top_in[19]; + assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0]; + + mux_tree_tapbuf_size10 + mux_left_ipin_0 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(right_grid_pin_0_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_0 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(left_grid_pin_16_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_3 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(left_grid_pin_19_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_4 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15] }), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(left_grid_pin_20_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_7 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(left_grid_pin_23_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_8 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(left_grid_pin_24_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_11 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(left_grid_pin_27_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_12 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17] }), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(left_grid_pin_28_[0]) + ); + + + mux_tree_tapbuf_size10 + mux_right_ipin_15 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), + .sram(mux_tree_tapbuf_size10_8_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), + .out(left_grid_pin_31_[0]) + ); + + + mux_tree_tapbuf_size10_mem + mem_left_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_ipin_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_1 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(left_grid_pin_17_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_2 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(left_grid_pin_18_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_5 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(left_grid_pin_21_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_6 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }), + .sram(mux_tree_tapbuf_size8_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .out(left_grid_pin_22_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_9 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), + .sram(mux_tree_tapbuf_size8_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .out(left_grid_pin_25_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_10 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }), + .sram(mux_tree_tapbuf_size8_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .out(left_grid_pin_26_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_13 + ( + .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), + .sram(mux_tree_tapbuf_size8_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .out(left_grid_pin_29_[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_ipin_14 + ( + .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }), + .sram(mux_tree_tapbuf_size8_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .out(left_grid_pin_30_[0]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_ipin_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail_mid), + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) + ); + + + logical_tile_io_mode_io_ + logical_tile_io_mode_io__0 + ( + .prog_clk(prog_clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), + .io_outpad(left_width_0_height_0__pin_0_[0]), + .ccff_head(ccff_tail_mid), + .io_inpad(left_width_0_height_0__pin_1_upper[0]), + .ccff_tail(ccff_tail[0]) + ); + + +endmodule + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v index 4dabe79..520177c 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v @@ -1,456 +1,522 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_0__0_(prog_clk, - chany_top_in, - top_left_grid_pin_1_, - chanx_right_in, - right_top_grid_pin_42_, - right_top_grid_pin_43_, - right_top_grid_pin_44_, - right_top_grid_pin_45_, - right_top_grid_pin_46_, - right_top_grid_pin_47_, - right_top_grid_pin_48_, - right_top_grid_pin_49_, - right_bottom_grid_pin_1_, - ccff_head, - chany_top_out, - chanx_right_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_top_in; -// -input [0:0] top_left_grid_pin_1_; -// -input [0:19] chanx_right_in; -// -input [0:0] right_top_grid_pin_42_; -// -input [0:0] right_top_grid_pin_43_; -// -input [0:0] right_top_grid_pin_44_; -// -input [0:0] right_top_grid_pin_45_; -// -input [0:0] right_top_grid_pin_46_; -// -input [0:0] right_top_grid_pin_47_; -// -input [0:0] right_top_grid_pin_48_; -// -input [0:0] right_top_grid_pin_49_; -// -input [0:0] right_bottom_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chany_top_out; -// -output [0:19] chanx_right_out; -// -output [0:0] ccff_tail; - -// -// -// -// +module sb_0__0_ +( + input [0:0] prog_clk, + input [0:19] chany_top_in, + input [0:0] top_left_grid_pin_1_, + input [0:19] chanx_right_in, + input [0:0] right_bottom_grid_pin_1_, + input [0:0] right_bottom_grid_pin_3_, + input [0:0] right_bottom_grid_pin_5_, + input [0:0] right_bottom_grid_pin_7_, + input [0:0] right_bottom_grid_pin_9_, + input [0:0] right_bottom_grid_pin_11_, + input [0:0] ccff_head, + output [0:19] chany_top_out, + output [0:19] chanx_right_out, + output [0:0] ccff_tail +); + + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_10_sram; + wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_11_sram; + wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_12_sram; + wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_13_sram; + wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_14_sram; + wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_15_sram; + wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_1_sram; + wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_2_sram; + wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_3_sram; + wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_4_sram; + wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_5_sram; + wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_6_sram; + wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_7_sram; + wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_8_sram; + wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_9_sram; + wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:2] mux_tree_tapbuf_size4_0_sram; + wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_1_sram; + wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_2_sram; + wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_3_sram; + wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; + assign chanx_right_out[10] = chany_top_in[9]; + assign chanx_right_out[11] = chany_top_in[10]; + assign chanx_right_out[18] = chany_top_in[17]; + assign chanx_right_out[19] = chany_top_in[18]; + assign chany_top_out[19] = chanx_right_in[0]; + assign chany_top_out[1] = chanx_right_in[2]; + assign chany_top_out[3] = chanx_right_in[4]; + assign chany_top_out[5] = chanx_right_in[6]; + assign chany_top_out[6] = chanx_right_in[7]; + assign chany_top_out[7] = chanx_right_in[8]; + assign chany_top_out[8] = chanx_right_in[9]; + assign chany_top_out[9] = chanx_right_in[10]; + assign chany_top_out[10] = chanx_right_in[11]; + assign chany_top_out[11] = chanx_right_in[12]; + assign chany_top_out[13] = chanx_right_in[14]; + assign chany_top_out[14] = chanx_right_in[15]; + assign chany_top_out[15] = chanx_right_in[16]; + assign chany_top_out[16] = chanx_right_in[17]; + assign chany_top_out[17] = chanx_right_in[18]; + assign chany_top_out[18] = chanx_right_in[19]; + + mux_tree_tapbuf_size2 + mux_top_track_0 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[1] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[0]) + ); -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_10_sram; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_11_sram; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_5_sram; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_6_sram; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_7_sram; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_8_sram; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_9_sram; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:2] mux_tree_tapbuf_size5_0_sram; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_1_sram; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + mux_tree_tapbuf_size2 + mux_top_track_4 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[3] }), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_top_out[2]) + ); -// -// -// -// - assign chanx_right_out[14] = chany_top_in[13]; -// -// -// - assign chanx_right_out[15] = chany_top_in[14]; -// -// -// - assign chanx_right_out[16] = chany_top_in[15]; -// -// -// - assign chanx_right_out[17] = chany_top_in[16]; -// -// -// - assign chanx_right_out[18] = chany_top_in[17]; -// -// -// - assign chanx_right_out[19] = chany_top_in[18]; -// -// -// - assign chany_top_out[19] = chanx_right_in[0]; -// -// -// - assign chany_top_out[1] = chanx_right_in[2]; -// -// -// - assign chany_top_out[3] = chanx_right_in[4]; -// -// -// - assign chany_top_out[5] = chanx_right_in[6]; -// -// -// - assign chany_top_out[6] = chanx_right_in[7]; -// -// -// - assign chany_top_out[7] = chanx_right_in[8]; -// -// -// - assign chany_top_out[8] = chanx_right_in[9]; -// -// -// - assign chany_top_out[9] = chanx_right_in[10]; -// -// -// - assign chany_top_out[10] = chanx_right_in[11]; -// -// -// - assign chany_top_out[11] = chanx_right_in[12]; -// -// -// - assign chany_top_out[13] = chanx_right_in[14]; -// -// -// - assign chany_top_out[14] = chanx_right_in[15]; -// -// -// - assign chany_top_out[15] = chanx_right_in[16]; -// -// -// - assign chany_top_out[16] = chanx_right_in[17]; -// -// -// - assign chany_top_out[17] = chanx_right_in[18]; -// -// -// - assign chany_top_out[18] = chanx_right_in[19]; -// -// -// - mux_tree_tapbuf_size2 mux_top_track_0 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[1]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chany_top_out[0])); + mux_tree_tapbuf_size2 + mux_top_track_8 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[5] }), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_top_out[4]) + ); - mux_tree_tapbuf_size2 mux_top_track_4 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[3]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), - .out(chany_top_out[2])); - mux_tree_tapbuf_size2 mux_top_track_8 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[5]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), - .out(chany_top_out[4])); + mux_tree_tapbuf_size2 + mux_top_track_24 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[13] }), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_top_out[12]) + ); - mux_tree_tapbuf_size2 mux_top_track_24 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[13]}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), - .out(chany_top_out[12])); - mux_tree_tapbuf_size2 mux_right_track_10 ( - .in({chany_top_in[4], right_top_grid_pin_43_[0]}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), - .out(chanx_right_out[5])); + mux_tree_tapbuf_size2 + mux_right_track_8 + ( + .in({ chany_top_in[3], right_bottom_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_right_out[4]) + ); - mux_tree_tapbuf_size2 mux_right_track_12 ( - .in({chany_top_in[5], right_top_grid_pin_44_[0]}), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), - .out(chanx_right_out[6])); - mux_tree_tapbuf_size2 mux_right_track_14 ( - .in({chany_top_in[6], right_top_grid_pin_45_[0]}), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), - .out(chanx_right_out[7])); + mux_tree_tapbuf_size2 + mux_right_track_10 + ( + .in({ chany_top_in[4], right_bottom_grid_pin_3_[0] }), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_right_out[5]) + ); - mux_tree_tapbuf_size2 mux_right_track_16 ( - .in({chany_top_in[7], right_top_grid_pin_46_[0]}), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), - .out(chanx_right_out[8])); - mux_tree_tapbuf_size2 mux_right_track_18 ( - .in({chany_top_in[8], right_top_grid_pin_47_[0]}), - .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), - .out(chanx_right_out[9])); + mux_tree_tapbuf_size2 + mux_right_track_12 + ( + .in({ chany_top_in[5], right_bottom_grid_pin_5_[0] }), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chanx_right_out[6]) + ); - mux_tree_tapbuf_size2 mux_right_track_20 ( - .in({chany_top_in[9], right_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), - .out(chanx_right_out[10])); - mux_tree_tapbuf_size2 mux_right_track_22 ( - .in({chany_top_in[10], right_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), - .out(chanx_right_out[11])); + mux_tree_tapbuf_size2 + mux_right_track_14 + ( + .in({ chany_top_in[6], right_bottom_grid_pin_7_[0] }), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .out(chanx_right_out[7]) + ); - mux_tree_tapbuf_size2 mux_right_track_26 ( - .in({chany_top_in[12], right_top_grid_pin_43_[0]}), - .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), - .out(chanx_right_out[13])); - mux_tree_tapbuf_size2_mem mem_top_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_right_track_16 + ( + .in({ chany_top_in[7], right_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .out(chanx_right_out[8]) + ); - mux_tree_tapbuf_size2_mem mem_top_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_top_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_right_track_18 + ( + .in({ chany_top_in[8], right_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .out(chanx_right_out[9]) + ); - mux_tree_tapbuf_size2_mem mem_top_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_right_track_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_right_track_24 + ( + .in({ chany_top_in[11], right_bottom_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .out(chanx_right_out[12]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_right_track_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_right_track_26 + ( + .in({ chany_top_in[12], right_bottom_grid_pin_3_[0] }), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .out(chanx_right_out[13]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_right_track_18 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_right_track_28 + ( + .in({ chany_top_in[13], right_bottom_grid_pin_5_[0] }), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .out(chanx_right_out[14]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_20 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_right_track_22 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_right_track_30 + ( + .in({ chany_top_in[14], right_bottom_grid_pin_7_[0] }), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .out(chanx_right_out[15]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_26 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])); - mux_tree_tapbuf_size6 mux_right_track_0 ( - .in({chany_top_in[19], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], right_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chanx_right_out[0])); + mux_tree_tapbuf_size2 + mux_right_track_32 + ( + .in({ chany_top_in[15], right_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .out(chanx_right_out[16]) + ); - mux_tree_tapbuf_size6 mux_right_track_4 ( - .in({chany_top_in[1], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], right_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chanx_right_out[2])); - mux_tree_tapbuf_size6_mem mem_right_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + mux_tree_tapbuf_size2 + mux_right_track_34 + ( + .in({ chany_top_in[16], right_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .out(chanx_right_out[17]) + ); - mux_tree_tapbuf_size6_mem mem_right_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); - mux_tree_tapbuf_size5 mux_right_track_2 ( - .in({chany_top_in[0], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), - .out(chanx_right_out[1])); + mux_tree_tapbuf_size2_mem + mem_top_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); - mux_tree_tapbuf_size5 mux_right_track_6 ( - .in({chany_top_in[2], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), - .out(chanx_right_out[3])); - mux_tree_tapbuf_size5_mem mem_right_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); + mux_tree_tapbuf_size2_mem + mem_top_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + ); - mux_tree_tapbuf_size5_mem mem_right_track_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); - mux_tree_tapbuf_size3 mux_right_track_8 ( - .in({chany_top_in[3], right_top_grid_pin_42_[0], right_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chanx_right_out[4])); + mux_tree_tapbuf_size2_mem + mem_top_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + ); - mux_tree_tapbuf_size3 mux_right_track_24 ( - .in({chany_top_in[11], right_top_grid_pin_42_[0], right_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chanx_right_out[12])); - mux_tree_tapbuf_size3_mem mem_right_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + mux_tree_tapbuf_size2_mem + mem_top_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_18 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_26 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_28 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_30 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_34 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size4 + mux_right_track_0 + ( + .in({ chany_top_in[19], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chanx_right_out[0]) + ); + + + mux_tree_tapbuf_size4 + mux_right_track_2 + ( + .in({ chany_top_in[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chanx_right_out[1]) + ); + + + mux_tree_tapbuf_size4 + mux_right_track_4 + ( + .in({ chany_top_in[1], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_right_out[2]) + ); + + + mux_tree_tapbuf_size4 + mux_right_track_6 + ( + .in({ chany_top_in[2], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_right_out[3]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3_mem mem_right_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v index ae0f810..dc3f1ab 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v @@ -1,658 +1,846 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_0__1_(prog_clk, - chany_top_in, - top_left_grid_pin_1_, - chanx_right_in, - right_top_grid_pin_42_, - right_top_grid_pin_43_, - right_top_grid_pin_44_, - right_top_grid_pin_45_, - right_top_grid_pin_46_, - right_top_grid_pin_47_, - right_top_grid_pin_48_, - right_top_grid_pin_49_, - chany_bottom_in, - bottom_left_grid_pin_1_, - ccff_head, - chany_top_out, - chanx_right_out, - chany_bottom_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_top_in; -// -input [0:0] top_left_grid_pin_1_; -// -input [0:19] chanx_right_in; -// -input [0:0] right_top_grid_pin_42_; -// -input [0:0] right_top_grid_pin_43_; -// -input [0:0] right_top_grid_pin_44_; -// -input [0:0] right_top_grid_pin_45_; -// -input [0:0] right_top_grid_pin_46_; -// -input [0:0] right_top_grid_pin_47_; -// -input [0:0] right_top_grid_pin_48_; -// -input [0:0] right_top_grid_pin_49_; -// -input [0:19] chany_bottom_in; -// -input [0:0] bottom_left_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chany_top_out; -// -output [0:19] chanx_right_out; -// -output [0:19] chany_bottom_out; -// -output [0:0] ccff_tail; - -// -// -// -// +module sb_0__1_ +( + input [0:0] prog_clk, + input [0:19] chany_top_in, + input [0:0] top_left_grid_pin_1_, + input [0:19] chanx_right_in, + input [0:0] right_bottom_grid_pin_34_, + input [0:0] right_bottom_grid_pin_35_, + input [0:0] right_bottom_grid_pin_36_, + input [0:0] right_bottom_grid_pin_37_, + input [0:0] right_bottom_grid_pin_38_, + input [0:0] right_bottom_grid_pin_39_, + input [0:0] right_bottom_grid_pin_40_, + input [0:0] right_bottom_grid_pin_41_, + input [0:19] chany_bottom_in, + input [0:0] bottom_left_grid_pin_1_, + input [0:0] ccff_head, + output [0:19] chany_top_out, + output [0:19] chanx_right_out, + output [0:19] chany_bottom_out, + output [0:0] ccff_tail +); + + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_1_sram; + wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_2_sram; + wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_3_sram; + wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_4_sram; + wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_5_sram; + wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_2_sram; + wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_3_sram; + wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_4_sram; + wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire [0:2] mux_tree_tapbuf_size4_0_sram; + wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_1_sram; + wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_2_sram; + wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_3_sram; + wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_4_sram; + wire [0:2] mux_tree_tapbuf_size4_4_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_5_sram; + wire [0:2] mux_tree_tapbuf_size4_5_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_6_sram; + wire [0:2] mux_tree_tapbuf_size4_6_sram_inv; + wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail; + wire [0:2] mux_tree_tapbuf_size5_0_sram; + wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_1_sram; + wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_2_sram; + wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_3_sram; + wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_4_sram; + wire [0:2] mux_tree_tapbuf_size5_4_sram_inv; + wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_1_sram; + wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_2_sram; + wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_3_sram; + wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_4_sram; + wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_5_sram; + wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_6_sram; + wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; + wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; + wire [0:2] mux_tree_tapbuf_size7_0_sram; + wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_1_sram; + wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_2_sram; + wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + assign chany_bottom_out[3] = chany_top_in[2]; + assign chany_bottom_out[5] = chany_top_in[4]; + assign chany_bottom_out[6] = chany_top_in[5]; + assign chany_bottom_out[7] = chany_top_in[6]; + assign chany_bottom_out[9] = chany_top_in[8]; + assign chany_bottom_out[10] = chany_top_in[9]; + assign chany_bottom_out[11] = chany_top_in[10]; + assign chany_bottom_out[13] = chany_top_in[12]; + assign chany_bottom_out[14] = chany_top_in[13]; + assign chany_bottom_out[15] = chany_top_in[14]; + assign chany_bottom_out[17] = chany_top_in[16]; + assign chany_bottom_out[18] = chany_top_in[17]; + assign chany_bottom_out[19] = chany_top_in[18]; + assign chanx_right_out[19] = right_bottom_grid_pin_41_[0]; + assign chany_top_out[3] = chany_bottom_in[2]; + assign chany_top_out[5] = chany_bottom_in[4]; + assign chany_top_out[6] = chany_bottom_in[5]; + assign chany_top_out[7] = chany_bottom_in[6]; + assign chany_top_out[9] = chany_bottom_in[8]; + assign chany_top_out[10] = chany_bottom_in[9]; + assign chany_top_out[11] = chany_bottom_in[10]; + assign chany_top_out[13] = chany_bottom_in[12]; + assign chany_top_out[14] = chany_bottom_in[13]; + assign chany_top_out[15] = chany_bottom_in[14]; + assign chany_top_out[17] = chany_bottom_in[16]; + assign chany_top_out[18] = chany_bottom_in[17]; + assign chany_top_out[19] = chany_bottom_in[18]; + + mux_tree_tapbuf_size6 + mux_top_track_0 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15], chany_bottom_in[2], chany_bottom_in[12] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chany_top_out[0]) + ); -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_4_sram; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:2] mux_tree_tapbuf_size4_0_sram; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_1_sram; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_2_sram; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_3_sram; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_4_sram; -wire [0:2] mux_tree_tapbuf_size4_4_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_5_sram; -wire [0:2] mux_tree_tapbuf_size4_5_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_6_sram; -wire [0:2] mux_tree_tapbuf_size4_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail; -wire [0:2] mux_tree_tapbuf_size5_0_sram; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_1_sram; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_2_sram; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_3_sram; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_4_sram; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_2_sram; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_3_sram; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_4_sram; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_5_sram; -wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_6_sram; -wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; -wire [0:2] mux_tree_tapbuf_size7_0_sram; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_1_sram; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_2_sram; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + mux_tree_tapbuf_size6 + mux_top_track_4 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], chany_bottom_in[5], chany_bottom_in[14] }), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chany_top_out[2]) + ); -// -// -// -// - assign chany_bottom_out[3] = chany_top_in[2]; -// -// -// - assign chany_bottom_out[5] = chany_top_in[4]; -// -// -// - assign chany_bottom_out[6] = chany_top_in[5]; -// -// -// - assign chany_bottom_out[7] = chany_top_in[6]; -// -// -// - assign chany_bottom_out[9] = chany_top_in[8]; -// -// -// - assign chany_bottom_out[10] = chany_top_in[9]; -// -// -// - assign chany_bottom_out[11] = chany_top_in[10]; -// -// -// - assign chany_bottom_out[13] = chany_top_in[12]; -// -// -// - assign chany_bottom_out[14] = chany_top_in[13]; -// -// -// - assign chany_bottom_out[15] = chany_top_in[14]; -// -// -// - assign chany_bottom_out[17] = chany_top_in[16]; -// -// -// - assign chany_bottom_out[18] = chany_top_in[17]; -// -// -// - assign chany_bottom_out[19] = chany_top_in[18]; -// -// -// - assign chanx_right_out[18] = chany_bottom_in[0]; -// -// -// - assign chanx_right_out[17] = chany_bottom_in[1]; -// -// -// - assign chany_top_out[3] = chany_bottom_in[2]; -// -// -// - assign chanx_right_out[16] = chany_bottom_in[3]; -// -// -// - assign chany_top_out[5] = chany_bottom_in[4]; -// -// -// - assign chany_top_out[6] = chany_bottom_in[5]; -// -// -// - assign chany_top_out[7] = chany_bottom_in[6]; -// -// -// - assign chanx_right_out[15] = chany_bottom_in[7]; -// -// -// - assign chany_top_out[9] = chany_bottom_in[8]; -// -// -// - assign chany_top_out[10] = chany_bottom_in[9]; -// -// -// - assign chany_top_out[11] = chany_bottom_in[10]; -// -// -// - assign chanx_right_out[14] = chany_bottom_in[11]; -// -// -// - assign chany_top_out[13] = chany_bottom_in[12]; -// -// -// - assign chany_top_out[14] = chany_bottom_in[13]; -// -// -// - assign chany_top_out[15] = chany_bottom_in[14]; -// -// -// - assign chany_top_out[17] = chany_bottom_in[16]; -// -// -// - assign chany_top_out[18] = chany_bottom_in[17]; -// -// -// - assign chany_top_out[19] = chany_bottom_in[18]; -// -// -// - mux_tree_tapbuf_size6 mux_top_track_0 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15], chany_bottom_in[2], chany_bottom_in[12]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chany_top_out[0])); + mux_tree_tapbuf_size6 + mux_top_track_8 + ( + .in({ top_left_grid_pin_1_[0], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18], chany_bottom_in[6], chany_bottom_in[16] }), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(chany_top_out[4]) + ); - mux_tree_tapbuf_size6 mux_top_track_4 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], chany_bottom_in[5], chany_bottom_in[14]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chany_top_out[2])); - mux_tree_tapbuf_size6 mux_top_track_8 ( - .in({top_left_grid_pin_1_[0], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18], chany_bottom_in[6], chany_bottom_in[16]}), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), - .out(chany_top_out[4])); + mux_tree_tapbuf_size6 + mux_right_track_0 + ( + .in({ chany_top_in[2], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2] }), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(chanx_right_out[0]) + ); - mux_tree_tapbuf_size6 mux_right_track_0 ( - .in({chany_top_in[2], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], chany_bottom_in[2]}), - .sram(mux_tree_tapbuf_size6_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), - .out(chanx_right_out[0])); - mux_tree_tapbuf_size6 mux_bottom_track_1 ( - .in({chany_top_in[2], chany_top_in[12], chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), - .out(chany_bottom_out[0])); + mux_tree_tapbuf_size6 + mux_bottom_track_1 + ( + .in({ chany_top_in[2], chany_top_in[12], chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .out(chany_bottom_out[0]) + ); - mux_tree_tapbuf_size6 mux_bottom_track_5 ( - .in({chany_top_in[5], chany_top_in[14], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), - .out(chany_bottom_out[2])); - mux_tree_tapbuf_size6 mux_bottom_track_9 ( - .in({chany_top_in[6], chany_top_in[16], chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), - .out(chany_bottom_out[4])); + mux_tree_tapbuf_size6 + mux_bottom_track_5 + ( + .in({ chany_top_in[5], chany_top_in[14], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), + .out(chany_bottom_out[2]) + ); - mux_tree_tapbuf_size6_mem mem_top_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); - mux_tree_tapbuf_size6_mem mem_top_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + mux_tree_tapbuf_size6 + mux_bottom_track_9 + ( + .in({ chany_top_in[6], chany_top_in[16], chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), + .out(chany_bottom_out[4]) + ); - mux_tree_tapbuf_size6_mem mem_top_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); - mux_tree_tapbuf_size6_mem mem_right_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + mux_tree_tapbuf_size6_mem + mem_top_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size6_mem mem_bottom_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); - mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2])); + mux_tree_tapbuf_size6_mem + mem_top_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2])); - mux_tree_tapbuf_size5 mux_top_track_2 ( - .in({chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], chany_bottom_in[4], chany_bottom_in[13]}), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), - .out(chany_top_out[1])); + mux_tree_tapbuf_size6_mem + mem_top_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5 mux_top_track_16 ( - .in({chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], chany_bottom_in[8], chany_bottom_in[17]}), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), - .out(chany_top_out[8])); - mux_tree_tapbuf_size5 mux_bottom_track_3 ( - .in({chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18]}), - .sram(mux_tree_tapbuf_size5_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), - .out(chany_bottom_out[1])); + mux_tree_tapbuf_size6_mem + mem_right_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5 mux_bottom_track_17 ( - .in({chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15]}), - .sram(mux_tree_tapbuf_size5_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), - .out(chany_bottom_out[8])); - mux_tree_tapbuf_size5 mux_bottom_track_25 ( - .in({chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[7], chanx_right_in[14]}), - .sram(mux_tree_tapbuf_size5_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_4_sram_inv[0:2]), - .out(chany_bottom_out[12])); + mux_tree_tapbuf_size6_mem + mem_bottom_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5_mem mem_top_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); - mux_tree_tapbuf_size5_mem mem_top_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); + mux_tree_tapbuf_size6_mem + mem_bottom_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5_mem mem_bottom_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2])); - mux_tree_tapbuf_size5_mem mem_bottom_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2])); + mux_tree_tapbuf_size6_mem + mem_bottom_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5_mem mem_bottom_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_4_sram_inv[0:2])); - mux_tree_tapbuf_size4 mux_top_track_24 ( - .in({chanx_right_in[6], chanx_right_in[13], chany_bottom_in[9], chany_bottom_in[18]}), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), - .out(chany_top_out[12])); + mux_tree_tapbuf_size5 + mux_top_track_2 + ( + .in({ chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], chany_bottom_in[4], chany_bottom_in[13] }), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chany_top_out[1]) + ); - mux_tree_tapbuf_size4 mux_top_track_32 ( - .in({chanx_right_in[0], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[10]}), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), - .out(chany_top_out[16])); - mux_tree_tapbuf_size4 mux_right_track_8 ( - .in({chany_top_in[7:8], right_top_grid_pin_42_[0], chany_bottom_in[8]}), - .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), - .out(chanx_right_out[4])); + mux_tree_tapbuf_size5 + mux_top_track_16 + ( + .in({ chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], chany_bottom_in[8], chany_bottom_in[17] }), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chany_top_out[8]) + ); - mux_tree_tapbuf_size4 mux_right_track_10 ( - .in({chany_top_in[9], chany_top_in[11], right_top_grid_pin_43_[0], chany_bottom_in[9]}), - .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), - .out(chanx_right_out[5])); - mux_tree_tapbuf_size4 mux_right_track_12 ( - .in({chany_top_in[10], chany_top_in[15], right_top_grid_pin_44_[0], chany_bottom_in[10]}), - .sram(mux_tree_tapbuf_size4_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]), - .out(chanx_right_out[6])); + mux_tree_tapbuf_size5 + mux_bottom_track_3 + ( + .in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18] }), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), + .out(chany_bottom_out[1]) + ); - mux_tree_tapbuf_size4 mux_right_track_14 ( - .in({chany_top_in[12], chany_top_in[19], right_top_grid_pin_45_[0], chany_bottom_in[12]}), - .sram(mux_tree_tapbuf_size4_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]), - .out(chanx_right_out[7])); - mux_tree_tapbuf_size4 mux_right_track_24 ( - .in({chany_top_in[18], right_top_grid_pin_42_[0], chany_bottom_in[18:19]}), - .sram(mux_tree_tapbuf_size4_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]), - .out(chanx_right_out[12])); + mux_tree_tapbuf_size5 + mux_bottom_track_17 + ( + .in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15] }), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), + .out(chany_bottom_out[8]) + ); - mux_tree_tapbuf_size4_mem mem_top_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); - mux_tree_tapbuf_size4_mem mem_top_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + mux_tree_tapbuf_size5 + mux_bottom_track_25 + ( + .in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[7], chanx_right_in[14] }), + .sram(mux_tree_tapbuf_size5_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_4_sram_inv[0:2]), + .out(chany_bottom_out[12]) + ); - mux_tree_tapbuf_size4_mem mem_right_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); - mux_tree_tapbuf_size4_mem mem_right_track_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + mux_tree_tapbuf_size5_mem + mem_top_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size4_mem mem_right_track_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2])); - mux_tree_tapbuf_size4_mem mem_right_track_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2])); + mux_tree_tapbuf_size5_mem + mem_top_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size4_mem mem_right_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2])); - mux_tree_tapbuf_size7 mux_right_track_2 ( - .in({chany_top_in[0], chany_top_in[4], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0], chany_bottom_in[4]}), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), - .out(chanx_right_out[1])); + mux_tree_tapbuf_size5_mem + mem_bottom_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2]) + ); - mux_tree_tapbuf_size7 mux_right_track_4 ( - .in({chany_top_in[1], chany_top_in[5], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], chany_bottom_in[5]}), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), - .out(chanx_right_out[2])); - mux_tree_tapbuf_size7 mux_right_track_6 ( - .in({chany_top_in[3], chany_top_in[6], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0], chany_bottom_in[6]}), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), - .out(chanx_right_out[3])); + mux_tree_tapbuf_size5_mem + mem_bottom_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size7_mem mem_right_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); - mux_tree_tapbuf_size7_mem mem_right_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); + mux_tree_tapbuf_size5_mem + mem_bottom_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_4_sram_inv[0:2]) + ); - mux_tree_tapbuf_size7_mem mem_right_track_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); - mux_tree_tapbuf_size3 mux_right_track_16 ( - .in({chany_top_in[13], right_top_grid_pin_46_[0], chany_bottom_in[13]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chanx_right_out[8])); + mux_tree_tapbuf_size4 + mux_top_track_24 + ( + .in({ chanx_right_in[6], chanx_right_in[13], chany_bottom_in[9], chany_bottom_in[18] }), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_top_out[12]) + ); - mux_tree_tapbuf_size3 mux_right_track_18 ( - .in({chany_top_in[14], right_top_grid_pin_47_[0], chany_bottom_in[14]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chanx_right_out[9])); - mux_tree_tapbuf_size3 mux_right_track_20 ( - .in({chany_top_in[16], right_top_grid_pin_48_[0], chany_bottom_in[16]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), - .out(chanx_right_out[10])); + mux_tree_tapbuf_size4 + mux_top_track_32 + ( + .in({ chanx_right_in[0], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[10] }), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_top_out[16]) + ); - mux_tree_tapbuf_size3 mux_right_track_22 ( - .in({chany_top_in[17], right_top_grid_pin_49_[0], chany_bottom_in[17]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), - .out(chanx_right_out[11])); - mux_tree_tapbuf_size3 mux_bottom_track_33 ( - .in({chany_top_in[10], chanx_right_in[6], chanx_right_in[13]}), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), - .out(chany_bottom_out[16])); + mux_tree_tapbuf_size4 + mux_right_track_8 + ( + .in({ chany_top_in[7:8], right_bottom_grid_pin_34_[0], chany_bottom_in[8] }), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_right_out[4]) + ); - mux_tree_tapbuf_size3_mem mem_right_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); - mux_tree_tapbuf_size3_mem mem_right_track_18 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + mux_tree_tapbuf_size4 + mux_right_track_10 + ( + .in({ chany_top_in[9], chany_top_in[11], right_bottom_grid_pin_35_[0], chany_bottom_in[9] }), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_right_out[5]) + ); - mux_tree_tapbuf_size3_mem mem_right_track_20 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); - mux_tree_tapbuf_size3_mem mem_right_track_22 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + mux_tree_tapbuf_size4 + mux_right_track_12 + ( + .in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_36_[0], chany_bottom_in[10] }), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]), + .out(chanx_right_out[6]) + ); - mux_tree_tapbuf_size3_mem mem_bottom_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); - mux_tree_tapbuf_size2 mux_right_track_26 ( - .in({right_top_grid_pin_43_[0], chany_bottom_in[15]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chanx_right_out[13])); + mux_tree_tapbuf_size4 + mux_right_track_14 + ( + .in({ chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_37_[0], chany_bottom_in[12] }), + .sram(mux_tree_tapbuf_size4_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]), + .out(chanx_right_out[7]) + ); + + + mux_tree_tapbuf_size4 + mux_right_track_24 + ( + .in({ chany_top_in[18], right_bottom_grid_pin_34_[0], chany_bottom_in[18:19] }), + .sram(mux_tree_tapbuf_size4_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]), + .out(chanx_right_out[12]) + ); + + + mux_tree_tapbuf_size4_mem + mem_top_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_top_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_right_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_2 + ( + .in({ chany_top_in[0], chany_top_in[4], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4] }), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chanx_right_out[1]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_4 + ( + .in({ chany_top_in[1], chany_top_in[5], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[5] }), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chanx_right_out[2]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_6 + ( + .in({ chany_top_in[3], chany_top_in[6], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chanx_right_out[3]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size3 + mux_right_track_16 + ( + .in({ chany_top_in[13], right_bottom_grid_pin_38_[0], chany_bottom_in[13] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chanx_right_out[8]) + ); + + + mux_tree_tapbuf_size3 + mux_right_track_18 + ( + .in({ chany_top_in[14], right_bottom_grid_pin_39_[0], chany_bottom_in[14] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_right_out[9]) + ); + + + mux_tree_tapbuf_size3 + mux_right_track_20 + ( + .in({ chany_top_in[16], right_bottom_grid_pin_40_[0], chany_bottom_in[16] }), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chanx_right_out[10]) + ); + + + mux_tree_tapbuf_size3 + mux_right_track_22 + ( + .in({ chany_top_in[17], right_bottom_grid_pin_41_[0], chany_bottom_in[17] }), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chanx_right_out[11]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_33 + ( + .in({ chany_top_in[10], chanx_right_in[6], chanx_right_in[13] }), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_bottom_out[16]) + ); + + + mux_tree_tapbuf_size3_mem + mem_right_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_right_track_18 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_right_track_20 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_right_track_22 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_26 + ( + .in({ right_bottom_grid_pin_35_[0], chany_bottom_in[15] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chanx_right_out[13]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_28 + ( + .in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chanx_right_out[14]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_30 + ( + .in({ right_bottom_grid_pin_37_[0], chany_bottom_in[7] }), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chanx_right_out[15]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_32 + ( + .in({ right_bottom_grid_pin_38_[0], chany_bottom_in[3] }), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chanx_right_out[16]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_34 + ( + .in({ right_bottom_grid_pin_39_[0], chany_bottom_in[1] }), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_right_out[17]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_36 + ( + .in({ right_bottom_grid_pin_40_[0], chany_bottom_in[0] }), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_right_out[18]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_26 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_28 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_30 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_34 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_36 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_26 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v index 62bac18..6d4a63a 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v @@ -1,312 +1,623 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_0__2_(prog_clk, - chanx_right_in, - right_top_grid_pin_1_, - chany_bottom_in, - bottom_left_grid_pin_1_, - ccff_head, - chanx_right_out, - chany_bottom_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chanx_right_in; -// -input [0:0] right_top_grid_pin_1_; -// -input [0:19] chany_bottom_in; -// -input [0:0] bottom_left_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chanx_right_out; -// -output [0:19] chany_bottom_out; -// -output [0:0] ccff_tail; - -// -// -// -// +module sb_0__2_ +( + input [0:0] prog_clk, + input [0:19] chanx_right_in, + input [0:0] right_top_grid_pin_1_, + input [0:0] right_bottom_grid_pin_34_, + input [0:0] right_bottom_grid_pin_35_, + input [0:0] right_bottom_grid_pin_36_, + input [0:0] right_bottom_grid_pin_37_, + input [0:0] right_bottom_grid_pin_38_, + input [0:0] right_bottom_grid_pin_39_, + input [0:0] right_bottom_grid_pin_40_, + input [0:0] right_bottom_grid_pin_41_, + input [0:19] chany_bottom_in, + input [0:0] bottom_left_grid_pin_1_, + input [0:0] ccff_head, + output [0:19] chanx_right_out, + output [0:19] chany_bottom_out, + output [0:0] ccff_tail, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_10_sram; + wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_11_sram; + wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_12_sram; + wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_13_sram; + wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_14_sram; + wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_15_sram; + wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_16_sram; + wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_17_sram; + wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_1_sram; + wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_2_sram; + wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_3_sram; + wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_4_sram; + wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_5_sram; + wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_6_sram; + wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_7_sram; + wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_8_sram; + wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_9_sram; + wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:2] mux_tree_tapbuf_size5_0_sram; + wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_1_sram; + wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_1_sram; + wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + assign chany_bottom_out[18] = chanx_right_in[0]; + assign chany_bottom_out[17] = chanx_right_in[1]; + assign chany_bottom_out[16] = chanx_right_in[2]; + assign chany_bottom_out[15] = chanx_right_in[3]; + assign chany_bottom_out[14] = chanx_right_in[4]; + assign chany_bottom_out[13] = chanx_right_in[5]; + assign chany_bottom_out[11] = chanx_right_in[7]; + assign chany_bottom_out[10] = chanx_right_in[8]; + assign chany_bottom_out[9] = chanx_right_in[9]; + assign chany_bottom_out[8] = chanx_right_in[10]; + assign chany_bottom_out[7] = chanx_right_in[11]; + assign chany_bottom_out[6] = chanx_right_in[12]; + assign chany_bottom_out[5] = chanx_right_in[13]; + assign chany_bottom_out[3] = chanx_right_in[15]; + assign chany_bottom_out[1] = chanx_right_in[17]; + assign chany_bottom_out[19] = chanx_right_in[19]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size6 + mux_right_track_0 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[18] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chanx_right_out[0]) + ); -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_5_sram; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_6_sram; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_7_sram; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; + mux_tree_tapbuf_size6 + mux_right_track_4 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[16] }), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chanx_right_out[2]) + ); -// -// -// -// - assign chany_bottom_out[18] = chanx_right_in[0]; -// -// -// - assign chany_bottom_out[17] = chanx_right_in[1]; -// -// -// - assign chany_bottom_out[16] = chanx_right_in[2]; -// -// -// - assign chany_bottom_out[15] = chanx_right_in[3]; -// -// -// - assign chany_bottom_out[14] = chanx_right_in[4]; -// -// -// - assign chany_bottom_out[13] = chanx_right_in[5]; -// -// -// - assign chany_bottom_out[11] = chanx_right_in[7]; -// -// -// - assign chany_bottom_out[10] = chanx_right_in[8]; -// -// -// - assign chany_bottom_out[9] = chanx_right_in[9]; -// -// -// - assign chany_bottom_out[8] = chanx_right_in[10]; -// -// -// - assign chany_bottom_out[7] = chanx_right_in[11]; -// -// -// - assign chany_bottom_out[6] = chanx_right_in[12]; -// -// -// - assign chany_bottom_out[5] = chanx_right_in[13]; -// -// -// - assign chany_bottom_out[3] = chanx_right_in[15]; -// -// -// - assign chany_bottom_out[1] = chanx_right_in[17]; -// -// -// - assign chany_bottom_out[19] = chanx_right_in[19]; -// -// -// - assign chanx_right_out[18] = chany_bottom_in[0]; -// -// -// - assign chanx_right_out[17] = chany_bottom_in[1]; -// -// -// - assign chanx_right_out[16] = chany_bottom_in[2]; -// -// -// - assign chanx_right_out[15] = chany_bottom_in[3]; -// -// -// - assign chanx_right_out[14] = chany_bottom_in[4]; -// -// -// - assign chanx_right_out[13] = chany_bottom_in[5]; -// -// -// - assign chanx_right_out[11] = chany_bottom_in[7]; -// -// -// - assign chanx_right_out[10] = chany_bottom_in[8]; -// -// -// - assign chanx_right_out[9] = chany_bottom_in[9]; -// -// -// - assign chanx_right_out[8] = chany_bottom_in[10]; -// -// -// - assign chanx_right_out[7] = chany_bottom_in[11]; -// -// -// - assign chanx_right_out[6] = chany_bottom_in[12]; -// -// -// - assign chanx_right_out[5] = chany_bottom_in[13]; -// -// -// - assign chanx_right_out[3] = chany_bottom_in[15]; -// -// -// - assign chanx_right_out[1] = chany_bottom_in[17]; -// -// -// - assign chanx_right_out[19] = chany_bottom_in[19]; -// -// -// - mux_tree_tapbuf_size2 mux_right_track_0 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[18]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chanx_right_out[0])); + mux_tree_tapbuf_size6_mem + mem_right_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2 mux_right_track_4 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[16]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), - .out(chanx_right_out[2])); - mux_tree_tapbuf_size2 mux_right_track_8 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[14]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), - .out(chanx_right_out[4])); + mux_tree_tapbuf_size6_mem + mem_right_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2 mux_right_track_24 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[6]}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), - .out(chanx_right_out[12])); - mux_tree_tapbuf_size2 mux_bottom_track_1 ( - .in({chanx_right_in[18], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), - .out(chany_bottom_out[0])); + mux_tree_tapbuf_size5 + mux_right_track_2 + ( + .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[17] }), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chanx_right_out[1]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_5 ( - .in({chanx_right_in[16], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), - .out(chany_bottom_out[2])); - mux_tree_tapbuf_size2 mux_bottom_track_9 ( - .in({chanx_right_in[14], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), - .out(chany_bottom_out[4])); + mux_tree_tapbuf_size5 + mux_right_track_6 + ( + .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[15] }), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chanx_right_out[3]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_25 ( - .in({chanx_right_in[6], bottom_left_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), - .out(chany_bottom_out[12])); - mux_tree_tapbuf_size2_mem mem_right_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + mux_tree_tapbuf_size5_mem + mem_right_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_right_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + mux_tree_tapbuf_size5_mem + mem_right_track_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2_mem mem_right_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + mux_tree_tapbuf_size3 + mux_right_track_8 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[14] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chanx_right_out[4]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + mux_tree_tapbuf_size3 + mux_right_track_24 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_right_out[12]) + ); + + + mux_tree_tapbuf_size3_mem + mem_right_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_right_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_10 + ( + .in({ right_bottom_grid_pin_34_[0], chany_bottom_in[13] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chanx_right_out[5]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_12 + ( + .in({ right_bottom_grid_pin_35_[0], chany_bottom_in[12] }), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chanx_right_out[6]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_14 + ( + .in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chanx_right_out[7]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_16 + ( + .in({ right_bottom_grid_pin_37_[0], chany_bottom_in[10] }), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chanx_right_out[8]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_18 + ( + .in({ right_bottom_grid_pin_38_[0], chany_bottom_in[9] }), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_right_out[9]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_20 + ( + .in({ right_bottom_grid_pin_39_[0], chany_bottom_in[8] }), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_right_out[10]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_22 + ( + .in({ right_bottom_grid_pin_40_[0], chany_bottom_in[7] }), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chanx_right_out[11]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_26 + ( + .in({ right_bottom_grid_pin_34_[0], chany_bottom_in[5] }), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .out(chanx_right_out[13]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_28 + ( + .in({ right_bottom_grid_pin_35_[0], chany_bottom_in[4] }), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .out(chanx_right_out[14]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_30 + ( + .in({ right_bottom_grid_pin_36_[0], chany_bottom_in[3] }), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .out(chanx_right_out[15]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_32 + ( + .in({ right_bottom_grid_pin_37_[0], chany_bottom_in[2] }), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .out(chanx_right_out[16]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_34 + ( + .in({ right_bottom_grid_pin_38_[0], chany_bottom_in[1] }), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .out(chanx_right_out[17]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_36 + ( + .in({ right_bottom_grid_pin_39_[0], chany_bottom_in[0] }), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .out(chanx_right_out[18]) + ); + + + mux_tree_tapbuf_size2 + mux_right_track_38 + ( + .in({ right_bottom_grid_pin_40_[0], chany_bottom_in[19] }), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .out(chanx_right_out[19]) + ); + + + mux_tree_tapbuf_size2 + mux_bottom_track_1 + ( + .in({ chanx_right_in[18], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .out(chany_bottom_out[0]) + ); + + + mux_tree_tapbuf_size2 + mux_bottom_track_5 + ( + .in({ chanx_right_in[16], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .out(chany_bottom_out[2]) + ); + + + mux_tree_tapbuf_size2 + mux_bottom_track_9 + ( + .in({ chanx_right_in[14], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_16_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), + .out(chany_bottom_out[4]) + ); + + + mux_tree_tapbuf_size2 + mux_bottom_track_25 + ( + .in({ chanx_right_in[6], bottom_left_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_17_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), + .out(chany_bottom_out[12]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_18 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_20 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_22 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_26 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_28 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_30 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_34 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_36 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_right_track_38 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])); endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v index 2ed68b1..2b08218 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v @@ -1,770 +1,747 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_1__0_(prog_clk, - chany_top_in, - top_left_grid_pin_34_, - top_left_grid_pin_35_, - top_left_grid_pin_36_, - top_left_grid_pin_37_, - top_left_grid_pin_38_, - top_left_grid_pin_39_, - top_left_grid_pin_40_, - top_left_grid_pin_41_, - chanx_right_in, - right_top_grid_pin_42_, - right_top_grid_pin_43_, - right_top_grid_pin_44_, - right_top_grid_pin_45_, - right_top_grid_pin_46_, - right_top_grid_pin_47_, - right_top_grid_pin_48_, - right_top_grid_pin_49_, - right_bottom_grid_pin_1_, - chanx_left_in, - left_top_grid_pin_42_, - left_top_grid_pin_43_, - left_top_grid_pin_44_, - left_top_grid_pin_45_, - left_top_grid_pin_46_, - left_top_grid_pin_47_, - left_top_grid_pin_48_, - left_top_grid_pin_49_, - left_bottom_grid_pin_1_, - ccff_head, - chany_top_out, - chanx_right_out, - chanx_left_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_top_in; -// -input [0:0] top_left_grid_pin_34_; -// -input [0:0] top_left_grid_pin_35_; -// -input [0:0] top_left_grid_pin_36_; -// -input [0:0] top_left_grid_pin_37_; -// -input [0:0] top_left_grid_pin_38_; -// -input [0:0] top_left_grid_pin_39_; -// -input [0:0] top_left_grid_pin_40_; -// -input [0:0] top_left_grid_pin_41_; -// -input [0:19] chanx_right_in; -// -input [0:0] right_top_grid_pin_42_; -// -input [0:0] right_top_grid_pin_43_; -// -input [0:0] right_top_grid_pin_44_; -// -input [0:0] right_top_grid_pin_45_; -// -input [0:0] right_top_grid_pin_46_; -// -input [0:0] right_top_grid_pin_47_; -// -input [0:0] right_top_grid_pin_48_; -// -input [0:0] right_top_grid_pin_49_; -// -input [0:0] right_bottom_grid_pin_1_; -// -input [0:19] chanx_left_in; -// -input [0:0] left_top_grid_pin_42_; -// -input [0:0] left_top_grid_pin_43_; -// -input [0:0] left_top_grid_pin_44_; -// -input [0:0] left_top_grid_pin_45_; -// -input [0:0] left_top_grid_pin_46_; -// -input [0:0] left_top_grid_pin_47_; -// -input [0:0] left_top_grid_pin_48_; -// -input [0:0] left_top_grid_pin_49_; -// -input [0:0] left_bottom_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chany_top_out; -// -output [0:19] chanx_right_out; -// -output [0:19] chanx_left_out; -// -output [0:0] ccff_tail; - -// -// - - -// -// - - -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:3] mux_tree_tapbuf_size14_0_sram; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size14_1_sram; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_4_sram; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_5_sram; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_6_sram; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_7_sram; -wire [0:1] mux_tree_tapbuf_size3_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; -wire [0:2] mux_tree_tapbuf_size4_0_sram; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_1_sram; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:2] mux_tree_tapbuf_size7_0_sram; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_1_sram; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_2_sram; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_3_sram; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_4_sram; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_5_sram; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_6_sram; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; -wire [0:3] mux_tree_tapbuf_size8_0_sram; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_1_sram; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_2_sram; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_3_sram; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; -wire [0:3] mux_tree_tapbuf_size9_0_sram; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size9_1_sram; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail; - -// -// -// -// - assign chany_top_out[13] = top_left_grid_pin_35_[0]; -// -// -// - assign chanx_left_out[3] = chanx_right_in[2]; -// -// -// - assign chanx_left_out[5] = chanx_right_in[4]; -// -// -// - assign chanx_left_out[6] = chanx_right_in[5]; -// -// -// - assign chanx_left_out[7] = chanx_right_in[6]; -// -// -// - assign chanx_left_out[9] = chanx_right_in[8]; -// -// -// - assign chanx_left_out[10] = chanx_right_in[9]; -// -// -// - assign chanx_left_out[11] = chanx_right_in[10]; -// -// -// - assign chanx_left_out[13] = chanx_right_in[12]; -// -// -// - assign chanx_left_out[14] = chanx_right_in[13]; -// -// -// - assign chanx_left_out[15] = chanx_right_in[14]; -// -// -// - assign chanx_left_out[17] = chanx_right_in[16]; -// -// -// - assign chanx_left_out[18] = chanx_right_in[17]; -// -// -// - assign chanx_left_out[19] = chanx_right_in[18]; -// -// -// - assign chanx_right_out[3] = chanx_left_in[2]; -// -// -// - assign chanx_right_out[5] = chanx_left_in[4]; -// -// -// - assign chanx_right_out[6] = chanx_left_in[5]; -// -// -// - assign chanx_right_out[7] = chanx_left_in[6]; -// -// -// - assign chanx_right_out[9] = chanx_left_in[8]; -// -// -// - assign chanx_right_out[10] = chanx_left_in[9]; -// -// -// - assign chanx_right_out[11] = chanx_left_in[10]; -// -// -// - assign chanx_right_out[13] = chanx_left_in[12]; -// -// -// - assign chanx_right_out[14] = chanx_left_in[13]; -// -// -// - assign chanx_right_out[15] = chanx_left_in[14]; -// -// -// - assign chanx_right_out[17] = chanx_left_in[16]; -// -// -// - assign chanx_right_out[18] = chanx_left_in[17]; -// -// -// - assign chanx_right_out[19] = chanx_left_in[18]; -// -// -// - - mux_tree_tapbuf_size8 mux_top_track_0 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], chanx_right_in[1:2], chanx_left_in[0], chanx_left_in[2]}), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), - .out(chany_top_out[0])); - - mux_tree_tapbuf_size8 mux_right_track_8 ( - .in({chany_top_in[2], chany_top_in[9], chany_top_in[16], right_top_grid_pin_42_[0], right_top_grid_pin_46_[0], right_bottom_grid_pin_1_[0], chanx_left_in[6], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), - .out(chanx_right_out[4])); - - mux_tree_tapbuf_size8 mux_left_track_3 ( - .in({chany_top_in[6], chany_top_in[13], chanx_right_in[4], chanx_right_in[13], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), - .out(chanx_left_out[1])); - - mux_tree_tapbuf_size8 mux_left_track_9 ( - .in({chany_top_in[4], chany_top_in[11], chany_top_in[18], chanx_right_in[6], chanx_right_in[16], left_top_grid_pin_42_[0], left_top_grid_pin_46_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), - .out(chanx_left_out[4])); - - mux_tree_tapbuf_size8_mem mem_top_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); - - mux_tree_tapbuf_size8_mem mem_right_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); - - mux_tree_tapbuf_size8_mem mem_left_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); - - mux_tree_tapbuf_size8_mem mem_left_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])); - - mux_tree_tapbuf_size7 mux_top_track_2 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_right_in[3:4], chanx_left_in[4]}), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), - .out(chany_top_out[1])); - - mux_tree_tapbuf_size7 mux_top_track_4 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], chanx_right_in[5], chanx_right_in[7], chanx_left_in[5]}), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), - .out(chany_top_out[2])); - - mux_tree_tapbuf_size7 mux_top_track_6 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_right_in[6], chanx_right_in[11], chanx_left_in[6]}), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), - .out(chany_top_out[3])); - - mux_tree_tapbuf_size7 mux_right_track_16 ( - .in({chany_top_in[3], chany_top_in[10], chany_top_in[17], right_top_grid_pin_43_[0], right_top_grid_pin_47_[0], chanx_left_in[8], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), - .out(chanx_right_out[8])); - - mux_tree_tapbuf_size7 mux_right_track_24 ( - .in({chany_top_in[4], chany_top_in[11], chany_top_in[18], right_top_grid_pin_44_[0], right_top_grid_pin_48_[0], chanx_left_in[9], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size7_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), - .out(chanx_right_out[12])); - - mux_tree_tapbuf_size7 mux_left_track_17 ( - .in({chany_top_in[3], chany_top_in[10], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], left_top_grid_pin_43_[0], left_top_grid_pin_47_[0]}), - .sram(mux_tree_tapbuf_size7_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), - .out(chanx_left_out[8])); - - mux_tree_tapbuf_size7 mux_left_track_25 ( - .in({chany_top_in[2], chany_top_in[9], chany_top_in[16], chanx_right_in[9], chanx_right_in[18], left_top_grid_pin_44_[0], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size7_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), - .out(chanx_left_out[12])); - - mux_tree_tapbuf_size7_mem mem_top_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_top_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_top_track_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_right_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_right_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_left_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_left_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2])); - - mux_tree_tapbuf_size4 mux_top_track_8 ( - .in({top_left_grid_pin_34_[0], chanx_right_in[8], chanx_right_in[15], chanx_left_in[8]}), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), - .out(chany_top_out[4])); - - mux_tree_tapbuf_size4 mux_top_track_10 ( - .in({top_left_grid_pin_35_[0], chanx_right_in[9], chanx_right_in[19], chanx_left_in[9]}), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), - .out(chany_top_out[5])); - - mux_tree_tapbuf_size4_mem mem_top_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); - - mux_tree_tapbuf_size4_mem mem_top_track_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); - - mux_tree_tapbuf_size3 mux_top_track_12 ( - .in({top_left_grid_pin_36_[0], chanx_right_in[10], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chany_top_out[6])); - - mux_tree_tapbuf_size3 mux_top_track_14 ( - .in({top_left_grid_pin_37_[0], chanx_right_in[12], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chany_top_out[7])); - - mux_tree_tapbuf_size3 mux_top_track_16 ( - .in({top_left_grid_pin_38_[0], chanx_right_in[13], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), - .out(chany_top_out[8])); - - mux_tree_tapbuf_size3 mux_top_track_18 ( - .in({top_left_grid_pin_39_[0], chanx_right_in[14], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), - .out(chany_top_out[9])); - - mux_tree_tapbuf_size3 mux_top_track_20 ( - .in({top_left_grid_pin_40_[0], chanx_right_in[16], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), - .out(chany_top_out[10])); - - mux_tree_tapbuf_size3 mux_top_track_22 ( - .in({top_left_grid_pin_41_[0], chanx_right_in[17], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size3_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), - .out(chany_top_out[11])); - - mux_tree_tapbuf_size3 mux_top_track_24 ( - .in({top_left_grid_pin_34_[0], chanx_right_in[18], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size3_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), - .out(chany_top_out[12])); - - mux_tree_tapbuf_size3 mux_top_track_38 ( - .in({top_left_grid_pin_41_[0], chanx_right_in[0], chanx_left_in[1]}), - .sram(mux_tree_tapbuf_size3_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]), - .out(chany_top_out[19])); - - mux_tree_tapbuf_size3_mem mem_top_track_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_18 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_20 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_22 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_38 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1])); - - mux_tree_tapbuf_size2 mux_top_track_28 ( - .in({top_left_grid_pin_36_[0], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chany_top_out[14])); - - mux_tree_tapbuf_size2 mux_top_track_30 ( - .in({top_left_grid_pin_37_[0], chanx_left_in[15]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), - .out(chany_top_out[15])); - - mux_tree_tapbuf_size2 mux_top_track_32 ( - .in({top_left_grid_pin_38_[0], chanx_left_in[11]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), - .out(chany_top_out[16])); - - mux_tree_tapbuf_size2 mux_top_track_34 ( - .in({top_left_grid_pin_39_[0], chanx_left_in[7]}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), - .out(chany_top_out[17])); - - mux_tree_tapbuf_size2 mux_top_track_36 ( - .in({top_left_grid_pin_40_[0], chanx_left_in[3]}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), - .out(chany_top_out[18])); - - mux_tree_tapbuf_size2_mem mem_top_track_28 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_30 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_34 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_36 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); - - mux_tree_tapbuf_size9 mux_right_track_0 ( - .in({chany_top_in[6], chany_top_in[13], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], right_bottom_grid_pin_1_[0], chanx_left_in[2], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size9_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]), - .out(chanx_right_out[0])); - - mux_tree_tapbuf_size9 mux_right_track_2 ( - .in({chany_top_in[0], chany_top_in[7], chany_top_in[14], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0], chanx_left_in[4], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size9_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size9_1_sram_inv[0:3]), - .out(chanx_right_out[1])); - - mux_tree_tapbuf_size9_mem mem_right_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3])); - - mux_tree_tapbuf_size9_mem mem_right_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size9_1_sram_inv[0:3])); - - mux_tree_tapbuf_size14 mux_right_track_4 ( - .in({chany_top_in[1], chany_top_in[8], chany_top_in[15], right_top_grid_pin_42_[0], right_top_grid_pin_43_[0], right_top_grid_pin_44_[0], right_top_grid_pin_45_[0], right_top_grid_pin_46_[0], right_top_grid_pin_47_[0], right_top_grid_pin_48_[0], right_top_grid_pin_49_[0], right_bottom_grid_pin_1_[0], chanx_left_in[5], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size14_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]), - .out(chanx_right_out[2])); - - mux_tree_tapbuf_size14 mux_left_track_5 ( - .in({chany_top_in[5], chany_top_in[12], chany_top_in[19], chanx_right_in[5], chanx_right_in[14], left_top_grid_pin_42_[0], left_top_grid_pin_43_[0], left_top_grid_pin_44_[0], left_top_grid_pin_45_[0], left_top_grid_pin_46_[0], left_top_grid_pin_47_[0], left_top_grid_pin_48_[0], left_top_grid_pin_49_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size14_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]), - .out(chanx_left_out[2])); - - mux_tree_tapbuf_size14_mem mem_right_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3])); - - mux_tree_tapbuf_size14_mem mem_left_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3])); - - mux_tree_tapbuf_size6 mux_right_track_32 ( - .in({chany_top_in[5], chany_top_in[12], chany_top_in[19], right_top_grid_pin_45_[0], right_top_grid_pin_49_[0], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chanx_right_out[16])); - - mux_tree_tapbuf_size6 mux_left_track_33 ( - .in({chany_top_in[1], chany_top_in[8], chany_top_in[15], chanx_right_in[10], left_top_grid_pin_45_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chanx_left_out[16])); - - mux_tree_tapbuf_size6_mem mem_right_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_left_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); - - mux_tree_tapbuf_size10 mux_left_track_1 ( - .in({chany_top_in[0], chany_top_in[7], chany_top_in[14], chanx_right_in[2], chanx_right_in[12], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(chanx_left_out[0])); - - mux_tree_tapbuf_size10_mem mem_left_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + + +module sb_1__0_ +( + input [0:0] prog_clk, + input [0:19] chany_top_in, + input [0:0] top_left_grid_pin_42_, + input [0:0] top_left_grid_pin_43_, + input [0:0] top_left_grid_pin_44_, + input [0:0] top_left_grid_pin_45_, + input [0:0] top_left_grid_pin_46_, + input [0:0] top_left_grid_pin_47_, + input [0:0] top_left_grid_pin_48_, + input [0:0] top_left_grid_pin_49_, + input [0:19] chanx_right_in, + input [0:0] right_bottom_grid_pin_1_, + input [0:0] right_bottom_grid_pin_3_, + input [0:0] right_bottom_grid_pin_5_, + input [0:0] right_bottom_grid_pin_7_, + input [0:0] right_bottom_grid_pin_9_, + input [0:0] right_bottom_grid_pin_11_, + input [0:19] chanx_left_in, + input [0:0] left_bottom_grid_pin_1_, + input [0:0] left_bottom_grid_pin_3_, + input [0:0] left_bottom_grid_pin_5_, + input [0:0] left_bottom_grid_pin_7_, + input [0:0] left_bottom_grid_pin_9_, + input [0:0] left_bottom_grid_pin_11_, + input [0:0] ccff_head, + output [0:19] chany_top_out, + output [0:19] chanx_right_out, + output [0:19] chanx_left_out, + output [0:0] ccff_tail, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:3] mux_tree_tapbuf_size11_0_sram; + wire [0:3] mux_tree_tapbuf_size11_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size11_1_sram; + wire [0:3] mux_tree_tapbuf_size11_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail; + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_2_sram; + wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_3_sram; + wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_4_sram; + wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_5_sram; + wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_6_sram; + wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; + wire [0:2] mux_tree_tapbuf_size4_0_sram; + wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_1_sram; + wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire [0:2] mux_tree_tapbuf_size5_0_sram; + wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_1_sram; + wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_1_sram; + wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire [0:2] mux_tree_tapbuf_size7_0_sram; + wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_1_sram; + wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_2_sram; + wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_3_sram; + wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_4_sram; + wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_5_sram; + wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_6_sram; + wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_7_sram; + wire [0:2] mux_tree_tapbuf_size7_7_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_8_sram; + wire [0:2] mux_tree_tapbuf_size7_8_sram_inv; + wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_2_sram; + wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; + assign chany_top_out[13] = top_left_grid_pin_43_[0]; + assign chanx_left_out[3] = chanx_right_in[2]; + assign chanx_left_out[5] = chanx_right_in[4]; + assign chanx_left_out[6] = chanx_right_in[5]; + assign chanx_left_out[7] = chanx_right_in[6]; + assign chanx_left_out[9] = chanx_right_in[8]; + assign chanx_left_out[10] = chanx_right_in[9]; + assign chanx_left_out[11] = chanx_right_in[10]; + assign chanx_left_out[13] = chanx_right_in[12]; + assign chanx_left_out[14] = chanx_right_in[13]; + assign chanx_left_out[15] = chanx_right_in[14]; + assign chanx_left_out[17] = chanx_right_in[16]; + assign chanx_left_out[18] = chanx_right_in[17]; + assign chanx_left_out[19] = chanx_right_in[18]; + assign chanx_right_out[3] = chanx_left_in[2]; + assign chany_top_out[18] = chanx_left_in[3]; + assign chanx_right_out[5] = chanx_left_in[4]; + assign chanx_right_out[6] = chanx_left_in[5]; + assign chanx_right_out[7] = chanx_left_in[6]; + assign chany_top_out[17] = chanx_left_in[7]; + assign chanx_right_out[9] = chanx_left_in[8]; + assign chanx_right_out[10] = chanx_left_in[9]; + assign chanx_right_out[11] = chanx_left_in[10]; + assign chany_top_out[16] = chanx_left_in[11]; + assign chanx_right_out[13] = chanx_left_in[12]; + assign chanx_right_out[14] = chanx_left_in[13]; + assign chanx_right_out[15] = chanx_left_in[14]; + assign chany_top_out[15] = chanx_left_in[15]; + assign chanx_right_out[17] = chanx_left_in[16]; + assign chanx_right_out[18] = chanx_left_in[17]; + assign chanx_right_out[19] = chanx_left_in[18]; + assign chany_top_out[14] = chanx_left_in[19]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size8 + mux_top_track_0 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_left_in[0], chanx_left_in[2] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(chany_top_out[0]) + ); + + + mux_tree_tapbuf_size8 + mux_right_track_2 + ( + .in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0], chanx_left_in[4], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(chanx_right_out[1]) + ); + + + mux_tree_tapbuf_size8 + mux_left_track_1 + ( + .in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], chanx_right_in[2], chanx_right_in[12], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(chanx_left_out[0]) + ); + + + mux_tree_tapbuf_size8_mem + mem_top_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_left_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size7 + mux_top_track_2 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_left_in[4] }), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chany_top_out[1]) + ); + + + mux_tree_tapbuf_size7 + mux_top_track_4 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[5], chanx_right_in[7], chanx_left_in[5] }), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chany_top_out[2]) + ); + + + mux_tree_tapbuf_size7 + mux_top_track_6 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[6], chanx_right_in[11], chanx_left_in[6] }), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chany_top_out[3]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_0 + ( + .in({ chany_top_in[6], chany_top_in[13], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0], chanx_left_in[2], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .out(chanx_right_out[0]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_8 + ( + .in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_9_[0], chanx_left_in[6], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size7_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), + .out(chanx_right_out[4]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_16 + ( + .in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_11_[0], chanx_left_in[8], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size7_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), + .out(chanx_right_out[8]) + ); + + + mux_tree_tapbuf_size7 + mux_left_track_3 + ( + .in({ chany_top_in[6], chany_top_in[13], chanx_right_in[4], chanx_right_in[13], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size7_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), + .out(chanx_left_out[1]) + ); + + + mux_tree_tapbuf_size7 + mux_left_track_9 + ( + .in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], chanx_right_in[6], chanx_right_in[16], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size7_7_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_7_sram_inv[0:2]), + .out(chanx_left_out[4]) + ); + + + mux_tree_tapbuf_size7 + mux_left_track_17 + ( + .in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size7_8_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_8_sram_inv[0:2]), + .out(chanx_left_out[8]) + ); + + + mux_tree_tapbuf_size7_mem + mem_top_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_top_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_top_track_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_left_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_left_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_7_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_7_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_left_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_8_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_8_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4 + mux_top_track_8 + ( + .in({ top_left_grid_pin_42_[0], chanx_right_in[8], chanx_right_in[15], chanx_left_in[8] }), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_top_out[4]) + ); + + + mux_tree_tapbuf_size4 + mux_top_track_10 + ( + .in({ top_left_grid_pin_43_[0], chanx_right_in[9], chanx_right_in[19], chanx_left_in[9] }), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_top_out[5]) + ); + + + mux_tree_tapbuf_size4_mem + mem_top_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_top_track_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_12 + ( + .in({ top_left_grid_pin_44_[0], chanx_right_in[10], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_top_out[6]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_14 + ( + .in({ top_left_grid_pin_45_[0], chanx_right_in[12], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_top_out[7]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_16 + ( + .in({ top_left_grid_pin_46_[0], chanx_right_in[13], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chany_top_out[8]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_18 + ( + .in({ top_left_grid_pin_47_[0], chanx_right_in[14], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chany_top_out[9]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_20 + ( + .in({ top_left_grid_pin_48_[0], chanx_right_in[16], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_top_out[10]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_22 + ( + .in({ top_left_grid_pin_49_[0], chanx_right_in[17], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chany_top_out[11]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_24 + ( + .in({ top_left_grid_pin_42_[0], chanx_right_in[18], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .out(chany_top_out[12]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_18 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_20 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_22 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_38 + ( + .in({ chanx_right_in[0], chanx_left_in[1] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[19]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_38 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size11 + mux_right_track_4 + ( + .in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_11_[0], chanx_left_in[5], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size11_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size11_0_sram_inv[0:3]), + .out(chanx_right_out[2]) + ); + + + mux_tree_tapbuf_size11 + mux_left_track_5 + ( + .in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], chanx_right_in[5], chanx_right_in[14], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size11_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size11_1_sram_inv[0:3]), + .out(chanx_left_out[2]) + ); + + + mux_tree_tapbuf_size11_mem + mem_right_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size11_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size11_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size11_mem + mem_left_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size11_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size11_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size6 + mux_right_track_24 + ( + .in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_5_[0], chanx_left_in[9], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chanx_right_out[12]) + ); + + + mux_tree_tapbuf_size6 + mux_left_track_25 + ( + .in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], chanx_right_in[9], chanx_right_in[18], left_bottom_grid_pin_5_[0] }), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chanx_left_out[12]) + ); + + + mux_tree_tapbuf_size6_mem + mem_right_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size6_mem + mem_left_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size5 + mux_right_track_32 + ( + .in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_7_[0], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chanx_right_out[16]) + ); + + + mux_tree_tapbuf_size5 + mux_left_track_33 + ( + .in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], chanx_right_in[10], left_bottom_grid_pin_7_[0] }), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chanx_left_out[16]) + ); + + + mux_tree_tapbuf_size5_mem + mem_right_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size5_mem + mem_left_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + ); + endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v index 3e6c226..0296f7a 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v @@ -1,814 +1,775 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_1__1_(prog_clk, - chany_top_in, - top_left_grid_pin_34_, - top_left_grid_pin_35_, - top_left_grid_pin_36_, - top_left_grid_pin_37_, - top_left_grid_pin_38_, - top_left_grid_pin_39_, - top_left_grid_pin_40_, - top_left_grid_pin_41_, - chanx_right_in, - right_top_grid_pin_42_, - right_top_grid_pin_43_, - right_top_grid_pin_44_, - right_top_grid_pin_45_, - right_top_grid_pin_46_, - right_top_grid_pin_47_, - right_top_grid_pin_48_, - right_top_grid_pin_49_, - chany_bottom_in, - bottom_left_grid_pin_34_, - bottom_left_grid_pin_35_, - bottom_left_grid_pin_36_, - bottom_left_grid_pin_37_, - bottom_left_grid_pin_38_, - bottom_left_grid_pin_39_, - bottom_left_grid_pin_40_, - bottom_left_grid_pin_41_, - chanx_left_in, - left_top_grid_pin_42_, - left_top_grid_pin_43_, - left_top_grid_pin_44_, - left_top_grid_pin_45_, - left_top_grid_pin_46_, - left_top_grid_pin_47_, - left_top_grid_pin_48_, - left_top_grid_pin_49_, - ccff_head, - chany_top_out, - chanx_right_out, - chany_bottom_out, - chanx_left_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_top_in; -// -input [0:0] top_left_grid_pin_34_; -// -input [0:0] top_left_grid_pin_35_; -// -input [0:0] top_left_grid_pin_36_; -// -input [0:0] top_left_grid_pin_37_; -// -input [0:0] top_left_grid_pin_38_; -// -input [0:0] top_left_grid_pin_39_; -// -input [0:0] top_left_grid_pin_40_; -// -input [0:0] top_left_grid_pin_41_; -// -input [0:19] chanx_right_in; -// -input [0:0] right_top_grid_pin_42_; -// -input [0:0] right_top_grid_pin_43_; -// -input [0:0] right_top_grid_pin_44_; -// -input [0:0] right_top_grid_pin_45_; -// -input [0:0] right_top_grid_pin_46_; -// -input [0:0] right_top_grid_pin_47_; -// -input [0:0] right_top_grid_pin_48_; -// -input [0:0] right_top_grid_pin_49_; -// -input [0:19] chany_bottom_in; -// -input [0:0] bottom_left_grid_pin_34_; -// -input [0:0] bottom_left_grid_pin_35_; -// -input [0:0] bottom_left_grid_pin_36_; -// -input [0:0] bottom_left_grid_pin_37_; -// -input [0:0] bottom_left_grid_pin_38_; -// -input [0:0] bottom_left_grid_pin_39_; -// -input [0:0] bottom_left_grid_pin_40_; -// -input [0:0] bottom_left_grid_pin_41_; -// -input [0:19] chanx_left_in; -// -input [0:0] left_top_grid_pin_42_; -// -input [0:0] left_top_grid_pin_43_; -// -input [0:0] left_top_grid_pin_44_; -// -input [0:0] left_top_grid_pin_45_; -// -input [0:0] left_top_grid_pin_46_; -// -input [0:0] left_top_grid_pin_47_; -// -input [0:0] left_top_grid_pin_48_; -// -input [0:0] left_top_grid_pin_49_; -// -input [0:0] ccff_head; -// -output [0:19] chany_top_out; -// -output [0:19] chanx_right_out; -// -output [0:19] chany_bottom_out; -// -output [0:19] chanx_left_out; -// -output [0:0] ccff_tail; - -// -// -// -// +module sb_1__1_ +( + input [0:0] prog_clk, + input [0:19] chany_top_in, + input [0:0] top_left_grid_pin_42_, + input [0:0] top_left_grid_pin_43_, + input [0:0] top_left_grid_pin_44_, + input [0:0] top_left_grid_pin_45_, + input [0:0] top_left_grid_pin_46_, + input [0:0] top_left_grid_pin_47_, + input [0:0] top_left_grid_pin_48_, + input [0:0] top_left_grid_pin_49_, + input [0:19] chanx_right_in, + input [0:0] right_bottom_grid_pin_34_, + input [0:0] right_bottom_grid_pin_35_, + input [0:0] right_bottom_grid_pin_36_, + input [0:0] right_bottom_grid_pin_37_, + input [0:0] right_bottom_grid_pin_38_, + input [0:0] right_bottom_grid_pin_39_, + input [0:0] right_bottom_grid_pin_40_, + input [0:0] right_bottom_grid_pin_41_, + input [0:19] chany_bottom_in, + input [0:0] bottom_left_grid_pin_42_, + input [0:0] bottom_left_grid_pin_43_, + input [0:0] bottom_left_grid_pin_44_, + input [0:0] bottom_left_grid_pin_45_, + input [0:0] bottom_left_grid_pin_46_, + input [0:0] bottom_left_grid_pin_47_, + input [0:0] bottom_left_grid_pin_48_, + input [0:0] bottom_left_grid_pin_49_, + input [0:19] chanx_left_in, + input [0:0] left_bottom_grid_pin_34_, + input [0:0] left_bottom_grid_pin_35_, + input [0:0] left_bottom_grid_pin_36_, + input [0:0] left_bottom_grid_pin_37_, + input [0:0] left_bottom_grid_pin_38_, + input [0:0] left_bottom_grid_pin_39_, + input [0:0] left_bottom_grid_pin_40_, + input [0:0] left_bottom_grid_pin_41_, + input [0:0] ccff_head, + output [0:19] chany_top_out, + output [0:19] chanx_right_out, + output [0:19] chany_bottom_out, + output [0:19] chanx_left_out, + output [0:0] ccff_tail +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_10_sram; + wire [0:3] mux_tree_tapbuf_size10_10_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_11_sram; + wire [0:3] mux_tree_tapbuf_size10_11_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_2_sram; + wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_3_sram; + wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_4_sram; + wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_5_sram; + wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_6_sram; + wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_7_sram; + wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_8_sram; + wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_9_sram; + wire [0:3] mux_tree_tapbuf_size10_9_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail; + wire [0:3] mux_tree_tapbuf_size12_0_sram; + wire [0:3] mux_tree_tapbuf_size12_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_1_sram; + wire [0:3] mux_tree_tapbuf_size12_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_2_sram; + wire [0:3] mux_tree_tapbuf_size12_2_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_3_sram; + wire [0:3] mux_tree_tapbuf_size12_3_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_4_sram; + wire [0:3] mux_tree_tapbuf_size12_4_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_5_sram; + wire [0:3] mux_tree_tapbuf_size12_5_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_6_sram; + wire [0:3] mux_tree_tapbuf_size12_6_sram_inv; + wire [0:3] mux_tree_tapbuf_size12_7_sram; + wire [0:3] mux_tree_tapbuf_size12_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail; + wire [0:4] mux_tree_tapbuf_size16_0_sram; + wire [0:4] mux_tree_tapbuf_size16_0_sram_inv; + wire [0:4] mux_tree_tapbuf_size16_1_sram; + wire [0:4] mux_tree_tapbuf_size16_1_sram_inv; + wire [0:4] mux_tree_tapbuf_size16_2_sram; + wire [0:4] mux_tree_tapbuf_size16_2_sram_inv; + wire [0:4] mux_tree_tapbuf_size16_3_sram; + wire [0:4] mux_tree_tapbuf_size16_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail; + wire [0:2] mux_tree_tapbuf_size7_0_sram; + wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_1_sram; + wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_2_sram; + wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_3_sram; + wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + assign chany_bottom_out[3] = chany_top_in[2]; + assign chany_bottom_out[5] = chany_top_in[4]; + assign chany_bottom_out[6] = chany_top_in[5]; + assign chany_bottom_out[7] = chany_top_in[6]; + assign chany_bottom_out[9] = chany_top_in[8]; + assign chany_bottom_out[10] = chany_top_in[9]; + assign chany_bottom_out[11] = chany_top_in[10]; + assign chany_bottom_out[13] = chany_top_in[12]; + assign chany_bottom_out[14] = chany_top_in[13]; + assign chany_bottom_out[15] = chany_top_in[14]; + assign chany_bottom_out[17] = chany_top_in[16]; + assign chany_bottom_out[18] = chany_top_in[17]; + assign chany_bottom_out[19] = chany_top_in[18]; + assign chanx_left_out[3] = chanx_right_in[2]; + assign chanx_left_out[5] = chanx_right_in[4]; + assign chanx_left_out[6] = chanx_right_in[5]; + assign chanx_left_out[7] = chanx_right_in[6]; + assign chanx_left_out[9] = chanx_right_in[8]; + assign chanx_left_out[10] = chanx_right_in[9]; + assign chanx_left_out[11] = chanx_right_in[10]; + assign chanx_left_out[13] = chanx_right_in[12]; + assign chanx_left_out[14] = chanx_right_in[13]; + assign chanx_left_out[15] = chanx_right_in[14]; + assign chanx_left_out[17] = chanx_right_in[16]; + assign chanx_left_out[18] = chanx_right_in[17]; + assign chanx_left_out[19] = chanx_right_in[18]; + assign chany_top_out[3] = chany_bottom_in[2]; + assign chany_top_out[5] = chany_bottom_in[4]; + assign chany_top_out[6] = chany_bottom_in[5]; + assign chany_top_out[7] = chany_bottom_in[6]; + assign chany_top_out[9] = chany_bottom_in[8]; + assign chany_top_out[10] = chany_bottom_in[9]; + assign chany_top_out[11] = chany_bottom_in[10]; + assign chany_top_out[13] = chany_bottom_in[12]; + assign chany_top_out[14] = chany_bottom_in[13]; + assign chany_top_out[15] = chany_bottom_in[14]; + assign chany_top_out[17] = chany_bottom_in[16]; + assign chany_top_out[18] = chany_bottom_in[17]; + assign chany_top_out[19] = chany_bottom_in[18]; + assign chanx_right_out[3] = chanx_left_in[2]; + assign chanx_right_out[5] = chanx_left_in[4]; + assign chanx_right_out[6] = chanx_left_in[5]; + assign chanx_right_out[7] = chanx_left_in[6]; + assign chanx_right_out[9] = chanx_left_in[8]; + assign chanx_right_out[10] = chanx_left_in[9]; + assign chanx_right_out[11] = chanx_left_in[10]; + assign chanx_right_out[13] = chanx_left_in[12]; + assign chanx_right_out[14] = chanx_left_in[13]; + assign chanx_right_out[15] = chanx_left_in[14]; + assign chanx_right_out[17] = chanx_left_in[16]; + assign chanx_right_out[18] = chanx_left_in[17]; + assign chanx_right_out[19] = chanx_left_in[18]; + + mux_tree_tapbuf_size12 + mux_top_track_0 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[2], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size12_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_0_sram_inv[0:3]), + .out(chany_top_out[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_10_sram; -wire [0:3] mux_tree_tapbuf_size10_10_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_11_sram; -wire [0:3] mux_tree_tapbuf_size10_11_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_2_sram; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_3_sram; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_4_sram; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_5_sram; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_6_sram; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_7_sram; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_8_sram; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_9_sram; -wire [0:3] mux_tree_tapbuf_size10_9_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail; -wire [0:3] mux_tree_tapbuf_size12_0_sram; -wire [0:3] mux_tree_tapbuf_size12_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_1_sram; -wire [0:3] mux_tree_tapbuf_size12_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_2_sram; -wire [0:3] mux_tree_tapbuf_size12_2_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_3_sram; -wire [0:3] mux_tree_tapbuf_size12_3_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_4_sram; -wire [0:3] mux_tree_tapbuf_size12_4_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_5_sram; -wire [0:3] mux_tree_tapbuf_size12_5_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_6_sram; -wire [0:3] mux_tree_tapbuf_size12_6_sram_inv; -wire [0:3] mux_tree_tapbuf_size12_7_sram; -wire [0:3] mux_tree_tapbuf_size12_7_sram_inv; -wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail; -wire [0:4] mux_tree_tapbuf_size16_0_sram; -wire [0:4] mux_tree_tapbuf_size16_0_sram_inv; -wire [0:4] mux_tree_tapbuf_size16_1_sram; -wire [0:4] mux_tree_tapbuf_size16_1_sram_inv; -wire [0:4] mux_tree_tapbuf_size16_2_sram; -wire [0:4] mux_tree_tapbuf_size16_2_sram_inv; -wire [0:4] mux_tree_tapbuf_size16_3_sram; -wire [0:4] mux_tree_tapbuf_size16_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail; -wire [0:2] mux_tree_tapbuf_size7_0_sram; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_1_sram; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_2_sram; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_3_sram; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + mux_tree_tapbuf_size12 + mux_top_track_2 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_right_in[13], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13], chanx_left_in[19] }), + .sram(mux_tree_tapbuf_size12_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_1_sram_inv[0:3]), + .out(chany_top_out[1]) + ); -// -// -// -// - assign chany_bottom_out[3] = chany_top_in[2]; -// -// -// - assign chany_bottom_out[5] = chany_top_in[4]; -// -// -// - assign chany_bottom_out[6] = chany_top_in[5]; -// -// -// - assign chany_bottom_out[7] = chany_top_in[6]; -// -// -// - assign chany_bottom_out[9] = chany_top_in[8]; -// -// -// - assign chany_bottom_out[10] = chany_top_in[9]; -// -// -// - assign chany_bottom_out[11] = chany_top_in[10]; -// -// -// - assign chany_bottom_out[13] = chany_top_in[12]; -// -// -// - assign chany_bottom_out[14] = chany_top_in[13]; -// -// -// - assign chany_bottom_out[15] = chany_top_in[14]; -// -// -// - assign chany_bottom_out[17] = chany_top_in[16]; -// -// -// - assign chany_bottom_out[18] = chany_top_in[17]; -// -// -// - assign chany_bottom_out[19] = chany_top_in[18]; -// -// -// - assign chanx_left_out[3] = chanx_right_in[2]; -// -// -// - assign chanx_left_out[5] = chanx_right_in[4]; -// -// -// - assign chanx_left_out[6] = chanx_right_in[5]; -// -// -// - assign chanx_left_out[7] = chanx_right_in[6]; -// -// -// - assign chanx_left_out[9] = chanx_right_in[8]; -// -// -// - assign chanx_left_out[10] = chanx_right_in[9]; -// -// -// - assign chanx_left_out[11] = chanx_right_in[10]; -// -// -// - assign chanx_left_out[13] = chanx_right_in[12]; -// -// -// - assign chanx_left_out[14] = chanx_right_in[13]; -// -// -// - assign chanx_left_out[15] = chanx_right_in[14]; -// -// -// - assign chanx_left_out[17] = chanx_right_in[16]; -// -// -// - assign chanx_left_out[18] = chanx_right_in[17]; -// -// -// - assign chanx_left_out[19] = chanx_right_in[18]; -// -// -// - assign chany_top_out[3] = chany_bottom_in[2]; -// -// -// - assign chany_top_out[5] = chany_bottom_in[4]; -// -// -// - assign chany_top_out[6] = chany_bottom_in[5]; -// -// -// - assign chany_top_out[7] = chany_bottom_in[6]; -// -// -// - assign chany_top_out[9] = chany_bottom_in[8]; -// -// -// - assign chany_top_out[10] = chany_bottom_in[9]; -// -// -// - assign chany_top_out[11] = chany_bottom_in[10]; -// -// -// - assign chany_top_out[13] = chany_bottom_in[12]; -// -// -// - assign chany_top_out[14] = chany_bottom_in[13]; -// -// -// - assign chany_top_out[15] = chany_bottom_in[14]; -// -// -// - assign chany_top_out[17] = chany_bottom_in[16]; -// -// -// - assign chany_top_out[18] = chany_bottom_in[17]; -// -// -// - assign chany_top_out[19] = chany_bottom_in[18]; -// -// -// - assign chanx_right_out[3] = chanx_left_in[2]; -// -// -// - assign chanx_right_out[5] = chanx_left_in[4]; -// -// -// - assign chanx_right_out[6] = chanx_left_in[5]; -// -// -// - assign chanx_right_out[7] = chanx_left_in[6]; -// -// -// - assign chanx_right_out[9] = chanx_left_in[8]; -// -// -// - assign chanx_right_out[10] = chanx_left_in[9]; -// -// -// - assign chanx_right_out[11] = chanx_left_in[10]; -// -// -// - assign chanx_right_out[13] = chanx_left_in[12]; -// -// -// - assign chanx_right_out[14] = chanx_left_in[13]; -// -// -// - assign chanx_right_out[15] = chanx_left_in[14]; -// -// -// - assign chanx_right_out[17] = chanx_left_in[16]; -// -// -// - assign chanx_right_out[18] = chanx_left_in[17]; -// -// -// - assign chanx_right_out[19] = chanx_left_in[18]; -// -// -// - mux_tree_tapbuf_size12 mux_top_track_0 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], chanx_right_in[1:2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[2], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size12_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_0_sram_inv[0:3]), - .out(chany_top_out[0])); + mux_tree_tapbuf_size12 + mux_right_track_0 + ( + .in({ chany_top_in[2], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[15], chanx_left_in[2], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size12_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_2_sram_inv[0:3]), + .out(chanx_right_out[0]) + ); - mux_tree_tapbuf_size12 mux_top_track_2 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_right_in[3:4], chanx_right_in[13], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size12_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_1_sram_inv[0:3]), - .out(chany_top_out[1])); - mux_tree_tapbuf_size12 mux_right_track_0 ( - .in({chany_top_in[2], chany_top_in[12], chany_top_in[19], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[15], chanx_left_in[2], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size12_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_2_sram_inv[0:3]), - .out(chanx_right_out[0])); + mux_tree_tapbuf_size12 + mux_right_track_2 + ( + .in({ chany_top_in[0], chany_top_in[4], chany_top_in[13], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size12_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_3_sram_inv[0:3]), + .out(chanx_right_out[1]) + ); - mux_tree_tapbuf_size12 mux_right_track_2 ( - .in({chany_top_in[0], chany_top_in[4], chany_top_in[13], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size12_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_3_sram_inv[0:3]), - .out(chanx_right_out[1])); - mux_tree_tapbuf_size12 mux_bottom_track_1 ( - .in({chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chanx_right_in[15], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[1:2], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size12_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_4_sram_inv[0:3]), - .out(chany_bottom_out[0])); + mux_tree_tapbuf_size12 + mux_bottom_track_1 + ( + .in({ chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chanx_right_in[15], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size12_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_4_sram_inv[0:3]), + .out(chany_bottom_out[0]) + ); - mux_tree_tapbuf_size12 mux_bottom_track_3 ( - .in({chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[13], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[3:4], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size12_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_5_sram_inv[0:3]), - .out(chany_bottom_out[1])); - mux_tree_tapbuf_size12 mux_left_track_1 ( - .in({chany_top_in[0], chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[19], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size12_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_6_sram_inv[0:3]), - .out(chanx_left_out[0])); + mux_tree_tapbuf_size12 + mux_bottom_track_3 + ( + .in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[13], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size12_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_5_sram_inv[0:3]), + .out(chany_bottom_out[1]) + ); - mux_tree_tapbuf_size12 mux_left_track_3 ( - .in({chany_top_in[4], chany_top_in[13], chany_top_in[19], chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[13], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size12_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_7_sram_inv[0:3]), - .out(chanx_left_out[1])); - mux_tree_tapbuf_size12_mem mem_top_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_0_sram_inv[0:3])); + mux_tree_tapbuf_size12 + mux_left_track_1 + ( + .in({ chany_top_in[0], chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size12_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_6_sram_inv[0:3]), + .out(chanx_left_out[0]) + ); - mux_tree_tapbuf_size12_mem mem_top_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_1_sram_inv[0:3])); - mux_tree_tapbuf_size12_mem mem_right_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_2_sram_inv[0:3])); + mux_tree_tapbuf_size12 + mux_left_track_3 + ( + .in({ chany_top_in[4], chany_top_in[13], chany_top_in[19], chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[13], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size12_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_7_sram_inv[0:3]), + .out(chanx_left_out[1]) + ); - mux_tree_tapbuf_size12_mem mem_right_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_3_sram_inv[0:3])); - mux_tree_tapbuf_size12_mem mem_bottom_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_4_sram_inv[0:3])); + mux_tree_tapbuf_size12_mem + mem_top_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size12_mem mem_bottom_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_5_sram_inv[0:3])); - mux_tree_tapbuf_size12_mem mem_left_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_6_sram_inv[0:3])); + mux_tree_tapbuf_size12_mem + mem_top_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size12_mem mem_left_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_7_sram_inv[0:3])); - mux_tree_tapbuf_size16 mux_top_track_4 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_35_[0], top_left_grid_pin_36_[0], top_left_grid_pin_37_[0], top_left_grid_pin_38_[0], top_left_grid_pin_39_[0], top_left_grid_pin_40_[0], top_left_grid_pin_41_[0], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14:15]}), - .sram(mux_tree_tapbuf_size16_0_sram[0:4]), - .sram_inv(mux_tree_tapbuf_size16_0_sram_inv[0:4]), - .out(chany_top_out[2])); + mux_tree_tapbuf_size12_mem + mem_right_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_2_sram_inv[0:3]) + ); - mux_tree_tapbuf_size16 mux_right_track_4 ( - .in({chany_top_in[1], chany_top_in[5], chany_top_in[14], right_top_grid_pin_42_[0], right_top_grid_pin_43_[0], right_top_grid_pin_44_[0], right_top_grid_pin_45_[0], right_top_grid_pin_46_[0], right_top_grid_pin_47_[0], right_top_grid_pin_48_[0], right_top_grid_pin_49_[0], chany_bottom_in[5], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size16_1_sram[0:4]), - .sram_inv(mux_tree_tapbuf_size16_1_sram_inv[0:4]), - .out(chanx_right_out[2])); - mux_tree_tapbuf_size16 mux_bottom_track_5 ( - .in({chany_top_in[5], chany_top_in[14], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_40_[0], bottom_left_grid_pin_41_[0], chanx_left_in[5], chanx_left_in[7], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size16_2_sram[0:4]), - .sram_inv(mux_tree_tapbuf_size16_2_sram_inv[0:4]), - .out(chany_bottom_out[2])); + mux_tree_tapbuf_size12_mem + mem_right_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_3_sram_inv[0:3]) + ); - mux_tree_tapbuf_size16 mux_left_track_5 ( - .in({chany_top_in[5], chany_top_in[14:15], chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[5], chany_bottom_in[14], left_top_grid_pin_42_[0], left_top_grid_pin_43_[0], left_top_grid_pin_44_[0], left_top_grid_pin_45_[0], left_top_grid_pin_46_[0], left_top_grid_pin_47_[0], left_top_grid_pin_48_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size16_3_sram[0:4]), - .sram_inv(mux_tree_tapbuf_size16_3_sram_inv[0:4]), - .out(chanx_left_out[2])); - mux_tree_tapbuf_size16_mem mem_top_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_0_sram[0:4]), - .mem_outb(mux_tree_tapbuf_size16_0_sram_inv[0:4])); + mux_tree_tapbuf_size12_mem + mem_bottom_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_4_sram_inv[0:3]) + ); - mux_tree_tapbuf_size16_mem mem_right_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_1_sram[0:4]), - .mem_outb(mux_tree_tapbuf_size16_1_sram_inv[0:4])); - mux_tree_tapbuf_size16_mem mem_bottom_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_2_sram[0:4]), - .mem_outb(mux_tree_tapbuf_size16_2_sram_inv[0:4])); + mux_tree_tapbuf_size12_mem + mem_bottom_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_5_sram_inv[0:3]) + ); - mux_tree_tapbuf_size16_mem mem_left_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_3_sram[0:4]), - .mem_outb(mux_tree_tapbuf_size16_3_sram_inv[0:4])); - mux_tree_tapbuf_size10 mux_top_track_8 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_38_[0], chanx_right_in[6], chanx_right_in[11], chanx_right_in[16], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(chany_top_out[4])); + mux_tree_tapbuf_size12_mem + mem_left_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_6_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10 mux_top_track_16 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_39_[0], chanx_right_in[8], chanx_right_in[15], chanx_right_in[17], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[7:8], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), - .out(chany_top_out[8])); - mux_tree_tapbuf_size10 mux_top_track_24 ( - .in({top_left_grid_pin_36_[0], top_left_grid_pin_40_[0], chanx_right_in[9], chanx_right_in[18:19], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[3], chanx_left_in[9], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), - .out(chany_top_out[12])); + mux_tree_tapbuf_size12_mem + mem_left_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_7_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10 mux_right_track_8 ( - .in({chany_top_in[3], chany_top_in[6], chany_top_in[16], right_top_grid_pin_42_[0], right_top_grid_pin_46_[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), - .out(chanx_right_out[4])); - mux_tree_tapbuf_size10 mux_right_track_16 ( - .in({chany_top_in[7:8], chany_top_in[17], right_top_grid_pin_43_[0], right_top_grid_pin_47_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[8], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), - .out(chanx_right_out[8])); + mux_tree_tapbuf_size16 + mux_top_track_4 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14:15] }), + .sram(mux_tree_tapbuf_size16_0_sram[0:4]), + .sram_inv(mux_tree_tapbuf_size16_0_sram_inv[0:4]), + .out(chany_top_out[2]) + ); - mux_tree_tapbuf_size10 mux_right_track_24 ( - .in({chany_top_in[9], chany_top_in[11], chany_top_in[18], right_top_grid_pin_44_[0], right_top_grid_pin_48_[0], chany_bottom_in[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[9], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), - .out(chanx_right_out[12])); - mux_tree_tapbuf_size10 mux_bottom_track_9 ( - .in({chany_top_in[6], chany_top_in[16], chanx_right_in[3], chanx_right_in[6], chanx_right_in[16], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_38_[0], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), - .out(chany_bottom_out[4])); + mux_tree_tapbuf_size16 + mux_right_track_4 + ( + .in({ chany_top_in[1], chany_top_in[5], chany_top_in[14], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size16_1_sram[0:4]), + .sram_inv(mux_tree_tapbuf_size16_1_sram_inv[0:4]), + .out(chanx_right_out[2]) + ); - mux_tree_tapbuf_size10 mux_bottom_track_17 ( - .in({chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[17], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_39_[0], chanx_left_in[8], chanx_left_in[15], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), - .out(chany_bottom_out[8])); - mux_tree_tapbuf_size10 mux_bottom_track_25 ( - .in({chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[9], chanx_right_in[18], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_40_[0], chanx_left_in[9], chanx_left_in[18:19]}), - .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), - .out(chany_bottom_out[12])); + mux_tree_tapbuf_size16 + mux_bottom_track_5 + ( + .in({ chany_top_in[5], chany_top_in[14], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[5], chanx_left_in[7], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size16_2_sram[0:4]), + .sram_inv(mux_tree_tapbuf_size16_2_sram_inv[0:4]), + .out(chany_bottom_out[2]) + ); - mux_tree_tapbuf_size10 mux_left_track_9 ( - .in({chany_top_in[6], chany_top_in[11], chany_top_in[16], chanx_right_in[6], chanx_right_in[16], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], left_top_grid_pin_42_[0], left_top_grid_pin_46_[0]}), - .sram(mux_tree_tapbuf_size10_9_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_9_sram_inv[0:3]), - .out(chanx_left_out[4])); - mux_tree_tapbuf_size10 mux_left_track_17 ( - .in({chany_top_in[7:8], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], chany_bottom_in[7:8], chany_bottom_in[17], left_top_grid_pin_43_[0], left_top_grid_pin_47_[0]}), - .sram(mux_tree_tapbuf_size10_10_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_10_sram_inv[0:3]), - .out(chanx_left_out[8])); + mux_tree_tapbuf_size16 + mux_left_track_5 + ( + .in({ chany_top_in[5], chany_top_in[14:15], chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[5], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size16_3_sram[0:4]), + .sram_inv(mux_tree_tapbuf_size16_3_sram_inv[0:4]), + .out(chanx_left_out[2]) + ); - mux_tree_tapbuf_size10 mux_left_track_25 ( - .in({chany_top_in[3], chany_top_in[9], chany_top_in[18], chanx_right_in[9], chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[11], chany_bottom_in[18], left_top_grid_pin_44_[0], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size10_11_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_11_sram_inv[0:3]), - .out(chanx_left_out[12])); - mux_tree_tapbuf_size10_mem mem_top_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + mux_tree_tapbuf_size16_mem + mem_top_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size16_0_sram[0:4]), + .mem_outb(mux_tree_tapbuf_size16_0_sram_inv[0:4]) + ); - mux_tree_tapbuf_size10_mem mem_top_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_top_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); + mux_tree_tapbuf_size16_mem + mem_right_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size16_1_sram[0:4]), + .mem_outb(mux_tree_tapbuf_size16_1_sram_inv[0:4]) + ); - mux_tree_tapbuf_size10_mem mem_right_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_right_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); + mux_tree_tapbuf_size16_mem + mem_bottom_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size16_2_sram[0:4]), + .mem_outb(mux_tree_tapbuf_size16_2_sram_inv[0:4]) + ); - mux_tree_tapbuf_size10_mem mem_right_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); + mux_tree_tapbuf_size16_mem + mem_left_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size16_3_sram[0:4]), + .mem_outb(mux_tree_tapbuf_size16_3_sram_inv[0:4]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_bottom_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])); + mux_tree_tapbuf_size10 + mux_top_track_8 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], chanx_right_in[6], chanx_right_in[11], chanx_right_in[16], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(chany_top_out[4]) + ); - mux_tree_tapbuf_size10_mem mem_left_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_9_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_9_sram_inv[0:3])); - mux_tree_tapbuf_size10_mem mem_left_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_10_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_10_sram_inv[0:3])); + mux_tree_tapbuf_size10 + mux_top_track_16 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chanx_right_in[8], chanx_right_in[15], chanx_right_in[17], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[7:8], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(chany_top_out[8]) + ); - mux_tree_tapbuf_size10_mem mem_left_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_11_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_11_sram_inv[0:3])); - mux_tree_tapbuf_size7 mux_top_track_32 ( - .in({top_left_grid_pin_37_[0], top_left_grid_pin_41_[0], chanx_right_in[0], chanx_right_in[10], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), - .out(chany_top_out[16])); + mux_tree_tapbuf_size10 + mux_top_track_24 + ( + .in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chanx_right_in[9], chanx_right_in[18:19], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[3], chanx_left_in[9], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(chany_top_out[12]) + ); - mux_tree_tapbuf_size7 mux_right_track_32 ( - .in({chany_top_in[10], chany_top_in[15], right_top_grid_pin_45_[0], right_top_grid_pin_49_[0], chany_bottom_in[10], chany_bottom_in[19], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), - .out(chanx_right_out[16])); - mux_tree_tapbuf_size7 mux_bottom_track_33 ( - .in({chany_top_in[10], chanx_right_in[10], chanx_right_in[19], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_41_[0], chanx_left_in[0], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), - .out(chany_bottom_out[16])); + mux_tree_tapbuf_size10 + mux_right_track_8 + ( + .in({ chany_top_in[3], chany_top_in[6], chany_top_in[16], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(chanx_right_out[4]) + ); - mux_tree_tapbuf_size7 mux_left_track_33 ( - .in({chany_top_in[1], chany_top_in[10], chanx_right_in[10], chany_bottom_in[10], chany_bottom_in[15], left_top_grid_pin_45_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), - .out(chanx_left_out[16])); - mux_tree_tapbuf_size7_mem mem_top_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); + mux_tree_tapbuf_size10 + mux_right_track_16 + ( + .in({ chany_top_in[7:8], chany_top_in[17], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[8], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(chanx_right_out[8]) + ); - mux_tree_tapbuf_size7_mem mem_right_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); - mux_tree_tapbuf_size7_mem mem_bottom_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); + mux_tree_tapbuf_size10 + mux_right_track_24 + ( + .in({ chany_top_in[9], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[9], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(chanx_right_out[12]) + ); + + + mux_tree_tapbuf_size10 + mux_bottom_track_9 + ( + .in({ chany_top_in[6], chany_top_in[16], chanx_right_in[3], chanx_right_in[6], chanx_right_in[16], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(chany_bottom_out[4]) + ); + + + mux_tree_tapbuf_size10 + mux_bottom_track_17 + ( + .in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[17], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[8], chanx_left_in[15], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(chany_bottom_out[8]) + ); + + + mux_tree_tapbuf_size10 + mux_bottom_track_25 + ( + .in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[9], chanx_right_in[18], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[9], chanx_left_in[18:19] }), + .sram(mux_tree_tapbuf_size10_8_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), + .out(chany_bottom_out[12]) + ); + + + mux_tree_tapbuf_size10 + mux_left_track_9 + ( + .in({ chany_top_in[6], chany_top_in[11], chany_top_in[16], chanx_right_in[6], chanx_right_in[16], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }), + .sram(mux_tree_tapbuf_size10_9_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_9_sram_inv[0:3]), + .out(chanx_left_out[4]) + ); + + + mux_tree_tapbuf_size10 + mux_left_track_17 + ( + .in({ chany_top_in[7:8], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], chany_bottom_in[7:8], chany_bottom_in[17], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }), + .sram(mux_tree_tapbuf_size10_10_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_10_sram_inv[0:3]), + .out(chanx_left_out[8]) + ); + + + mux_tree_tapbuf_size10 + mux_left_track_25 + ( + .in({ chany_top_in[3], chany_top_in[9], chany_top_in[18], chanx_right_in[9], chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size10_11_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_11_sram_inv[0:3]), + .out(chanx_left_out[12]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_top_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_bottom_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_bottom_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_bottom_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_left_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_9_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_9_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_left_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_10_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_10_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size10_mem + mem_left_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_11_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_11_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size7 + mux_top_track_32 + ( + .in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chanx_right_in[0], chanx_right_in[10], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chany_top_out[16]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_32 + ( + .in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[10], chany_bottom_in[19], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chanx_right_out[16]) + ); + + + mux_tree_tapbuf_size7 + mux_bottom_track_33 + ( + .in({ chany_top_in[10], chanx_right_in[10], chanx_right_in[19], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[0], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chany_bottom_out[16]) + ); + + + mux_tree_tapbuf_size7 + mux_left_track_33 + ( + .in({ chany_top_in[1], chany_top_in[10], chanx_right_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .out(chanx_left_out[16]) + ); + + + mux_tree_tapbuf_size7_mem + mem_top_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_bottom_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_left_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size7_mem mem_left_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])); endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v index 0897208..5253fe0 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v @@ -1,734 +1,753 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_1__2_(prog_clk, - chanx_right_in, - right_top_grid_pin_1_, - chany_bottom_in, - bottom_left_grid_pin_34_, - bottom_left_grid_pin_35_, - bottom_left_grid_pin_36_, - bottom_left_grid_pin_37_, - bottom_left_grid_pin_38_, - bottom_left_grid_pin_39_, - bottom_left_grid_pin_40_, - bottom_left_grid_pin_41_, - chanx_left_in, - left_top_grid_pin_1_, - ccff_head, - chanx_right_out, - chany_bottom_out, - chanx_left_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chanx_right_in; -// -input [0:0] right_top_grid_pin_1_; -// -input [0:19] chany_bottom_in; -// -input [0:0] bottom_left_grid_pin_34_; -// -input [0:0] bottom_left_grid_pin_35_; -// -input [0:0] bottom_left_grid_pin_36_; -// -input [0:0] bottom_left_grid_pin_37_; -// -input [0:0] bottom_left_grid_pin_38_; -// -input [0:0] bottom_left_grid_pin_39_; -// -input [0:0] bottom_left_grid_pin_40_; -// -input [0:0] bottom_left_grid_pin_41_; -// -input [0:19] chanx_left_in; -// -input [0:0] left_top_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chanx_right_out; -// -output [0:19] chany_bottom_out; -// -output [0:19] chanx_left_out; -// -output [0:0] ccff_tail; - -// -// - - -// -// - - -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_5_sram; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_6_sram; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_4_sram; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_5_sram; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_6_sram; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; -wire [0:2] mux_tree_tapbuf_size4_0_sram; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_1_sram; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_2_sram; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_3_sram; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; -wire [0:2] mux_tree_tapbuf_size5_0_sram; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_1_sram; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_2_sram; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_3_sram; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_4_sram; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_5_sram; -wire [0:2] mux_tree_tapbuf_size5_5_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_6_sram; -wire [0:2] mux_tree_tapbuf_size5_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_2_sram; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_3_sram; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_4_sram; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; -wire [0:2] mux_tree_tapbuf_size7_0_sram; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_1_sram; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_2_sram; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_3_sram; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; - -// -// -// -// - assign chanx_left_out[3] = chanx_right_in[2]; -// -// -// - assign chanx_left_out[5] = chanx_right_in[4]; -// -// -// - assign chanx_left_out[6] = chanx_right_in[5]; -// -// -// - assign chanx_left_out[7] = chanx_right_in[6]; -// -// -// - assign chanx_left_out[9] = chanx_right_in[8]; -// -// -// - assign chanx_left_out[10] = chanx_right_in[9]; -// -// -// - assign chanx_left_out[11] = chanx_right_in[10]; -// -// -// - assign chanx_left_out[13] = chanx_right_in[12]; -// -// -// - assign chanx_left_out[14] = chanx_right_in[13]; -// -// -// - assign chanx_left_out[15] = chanx_right_in[14]; -// -// -// - assign chanx_left_out[17] = chanx_right_in[16]; -// -// -// - assign chanx_left_out[18] = chanx_right_in[17]; -// -// -// - assign chanx_left_out[19] = chanx_right_in[18]; -// -// -// - assign chanx_right_out[3] = chanx_left_in[2]; -// -// -// - assign chanx_right_out[5] = chanx_left_in[4]; -// -// -// - assign chanx_right_out[6] = chanx_left_in[5]; -// -// -// - assign chanx_right_out[7] = chanx_left_in[6]; -// -// -// - assign chanx_right_out[9] = chanx_left_in[8]; -// -// -// - assign chanx_right_out[10] = chanx_left_in[9]; -// -// -// - assign chanx_right_out[11] = chanx_left_in[10]; -// -// -// - assign chanx_right_out[13] = chanx_left_in[12]; -// -// -// - assign chanx_right_out[14] = chanx_left_in[13]; -// -// -// - assign chanx_right_out[15] = chanx_left_in[14]; -// -// -// - assign chanx_right_out[17] = chanx_left_in[16]; -// -// -// - assign chanx_right_out[18] = chanx_left_in[17]; -// -// -// - assign chanx_right_out[19] = chanx_left_in[18]; -// -// -// - - mux_tree_tapbuf_size6 mux_right_track_0 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], chanx_left_in[2], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chanx_right_out[0])); - - mux_tree_tapbuf_size6 mux_right_track_4 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], chanx_left_in[5], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chanx_right_out[2])); - - mux_tree_tapbuf_size6 mux_right_track_8 ( - .in({right_top_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), - .out(chanx_right_out[4])); - - mux_tree_tapbuf_size6 mux_left_track_5 ( - .in({chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), - .out(chanx_left_out[2])); - - mux_tree_tapbuf_size6 mux_left_track_9 ( - .in({chanx_right_in[6], chanx_right_in[16], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), - .out(chanx_left_out[4])); - - mux_tree_tapbuf_size6_mem mem_right_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_right_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_right_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_left_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_left_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); - - mux_tree_tapbuf_size5 mux_right_track_2 ( - .in({chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], chanx_left_in[4], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), - .out(chanx_right_out[1])); - - mux_tree_tapbuf_size5 mux_right_track_16 ( - .in({chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], chanx_left_in[8], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), - .out(chanx_right_out[8])); - - mux_tree_tapbuf_size5 mux_right_track_24 ( - .in({chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[9], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size5_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), - .out(chanx_right_out[12])); - - mux_tree_tapbuf_size5 mux_left_track_1 ( - .in({chanx_right_in[2], chanx_right_in[12], chany_bottom_in[6], chany_bottom_in[13], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size5_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), - .out(chanx_left_out[0])); - - mux_tree_tapbuf_size5 mux_left_track_3 ( - .in({chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14]}), - .sram(mux_tree_tapbuf_size5_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_4_sram_inv[0:2]), - .out(chanx_left_out[1])); - - mux_tree_tapbuf_size5 mux_left_track_17 ( - .in({chanx_right_in[8], chanx_right_in[17], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17]}), - .sram(mux_tree_tapbuf_size5_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_5_sram_inv[0:2]), - .out(chanx_left_out[8])); - - mux_tree_tapbuf_size5 mux_left_track_25 ( - .in({chanx_right_in[9], chanx_right_in[18], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18]}), - .sram(mux_tree_tapbuf_size5_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_6_sram_inv[0:2]), - .out(chanx_left_out[12])); - - mux_tree_tapbuf_size5_mem mem_right_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_right_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_right_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_left_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_left_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_4_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_left_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_5_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_left_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_6_sram_inv[0:2])); - - mux_tree_tapbuf_size3 mux_right_track_32 ( - .in({chany_bottom_in[6], chany_bottom_in[13], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chanx_right_out[16])); - - mux_tree_tapbuf_size3 mux_bottom_track_13 ( - .in({chanx_right_in[10], bottom_left_grid_pin_36_[0], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chany_bottom_out[6])); - - mux_tree_tapbuf_size3 mux_bottom_track_15 ( - .in({chanx_right_in[12], bottom_left_grid_pin_37_[0], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), - .out(chany_bottom_out[7])); - - mux_tree_tapbuf_size3 mux_bottom_track_17 ( - .in({chanx_right_in[13], bottom_left_grid_pin_38_[0], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), - .out(chany_bottom_out[8])); - - mux_tree_tapbuf_size3 mux_bottom_track_19 ( - .in({chanx_right_in[14], bottom_left_grid_pin_39_[0], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), - .out(chany_bottom_out[9])); - - mux_tree_tapbuf_size3 mux_bottom_track_21 ( - .in({chanx_right_in[16], bottom_left_grid_pin_40_[0], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size3_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), - .out(chany_bottom_out[10])); - - mux_tree_tapbuf_size3 mux_bottom_track_23 ( - .in({chanx_right_in[17], bottom_left_grid_pin_41_[0], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size3_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), - .out(chany_bottom_out[11])); - - mux_tree_tapbuf_size3_mem mem_right_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_19 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_21 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); - - mux_tree_tapbuf_size7 mux_bottom_track_1 ( - .in({chanx_right_in[2], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[1:2]}), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), - .out(chany_bottom_out[0])); - - mux_tree_tapbuf_size7 mux_bottom_track_3 ( - .in({chanx_right_in[4], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[3:4]}), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), - .out(chany_bottom_out[1])); - - mux_tree_tapbuf_size7 mux_bottom_track_5 ( - .in({chanx_right_in[5], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[5], chanx_left_in[7]}), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), - .out(chany_bottom_out[2])); - - mux_tree_tapbuf_size7 mux_bottom_track_7 ( - .in({chanx_right_in[6], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[6], chanx_left_in[11]}), - .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), - .out(chany_bottom_out[3])); - - mux_tree_tapbuf_size7_mem mem_bottom_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_bottom_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_bottom_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); - - mux_tree_tapbuf_size7_mem mem_bottom_track_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])); - - mux_tree_tapbuf_size4 mux_bottom_track_9 ( - .in({chanx_right_in[8], bottom_left_grid_pin_34_[0], chanx_left_in[8], chanx_left_in[15]}), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), - .out(chany_bottom_out[4])); - - mux_tree_tapbuf_size4 mux_bottom_track_11 ( - .in({chanx_right_in[9], bottom_left_grid_pin_35_[0], chanx_left_in[9], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), - .out(chany_bottom_out[5])); - - mux_tree_tapbuf_size4 mux_bottom_track_25 ( - .in({chanx_right_in[18:19], bottom_left_grid_pin_34_[0], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), - .out(chany_bottom_out[12])); - - mux_tree_tapbuf_size4 mux_left_track_33 ( - .in({chanx_right_in[10], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19]}), - .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), - .out(chanx_left_out[16])); - - mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); - - mux_tree_tapbuf_size4_mem mem_bottom_track_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); - - mux_tree_tapbuf_size4_mem mem_bottom_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); - - mux_tree_tapbuf_size4_mem mem_left_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); - - mux_tree_tapbuf_size2 mux_bottom_track_27 ( - .in({chanx_right_in[15], bottom_left_grid_pin_35_[0]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chany_bottom_out[13])); - - mux_tree_tapbuf_size2 mux_bottom_track_29 ( - .in({chanx_right_in[11], bottom_left_grid_pin_36_[0]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), - .out(chany_bottom_out[14])); - - mux_tree_tapbuf_size2 mux_bottom_track_31 ( - .in({chanx_right_in[7], bottom_left_grid_pin_37_[0]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), - .out(chany_bottom_out[15])); - - mux_tree_tapbuf_size2 mux_bottom_track_33 ( - .in({chanx_right_in[3], bottom_left_grid_pin_38_[0]}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), - .out(chany_bottom_out[16])); - - mux_tree_tapbuf_size2 mux_bottom_track_35 ( - .in({chanx_right_in[1], bottom_left_grid_pin_39_[0]}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), - .out(chany_bottom_out[17])); - - mux_tree_tapbuf_size2 mux_bottom_track_37 ( - .in({chanx_right_in[0], bottom_left_grid_pin_40_[0]}), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), - .out(chany_bottom_out[18])); - - mux_tree_tapbuf_size2 mux_bottom_track_39 ( - .in({bottom_left_grid_pin_41_[0], chanx_left_in[0]}), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), - .out(chany_bottom_out[19])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_29 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_31 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_35 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_37 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + + +module sb_1__2_ +( + input [0:0] prog_clk, + input [0:19] chanx_right_in, + input [0:0] right_top_grid_pin_1_, + input [0:0] right_bottom_grid_pin_34_, + input [0:0] right_bottom_grid_pin_35_, + input [0:0] right_bottom_grid_pin_36_, + input [0:0] right_bottom_grid_pin_37_, + input [0:0] right_bottom_grid_pin_38_, + input [0:0] right_bottom_grid_pin_39_, + input [0:0] right_bottom_grid_pin_40_, + input [0:0] right_bottom_grid_pin_41_, + input [0:19] chany_bottom_in, + input [0:0] bottom_left_grid_pin_42_, + input [0:0] bottom_left_grid_pin_43_, + input [0:0] bottom_left_grid_pin_44_, + input [0:0] bottom_left_grid_pin_45_, + input [0:0] bottom_left_grid_pin_46_, + input [0:0] bottom_left_grid_pin_47_, + input [0:0] bottom_left_grid_pin_48_, + input [0:0] bottom_left_grid_pin_49_, + input [0:19] chanx_left_in, + input [0:0] left_top_grid_pin_1_, + input [0:0] left_bottom_grid_pin_34_, + input [0:0] left_bottom_grid_pin_35_, + input [0:0] left_bottom_grid_pin_36_, + input [0:0] left_bottom_grid_pin_37_, + input [0:0] left_bottom_grid_pin_38_, + input [0:0] left_bottom_grid_pin_39_, + input [0:0] left_bottom_grid_pin_40_, + input [0:0] left_bottom_grid_pin_41_, + input [0:0] ccff_head, + output [0:19] chanx_right_out, + output [0:19] chany_bottom_out, + output [0:19] chanx_left_out, + output [0:0] ccff_tail, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:3] mux_tree_tapbuf_size14_0_sram; + wire [0:3] mux_tree_tapbuf_size14_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size14_1_sram; + wire [0:3] mux_tree_tapbuf_size14_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_2_sram; + wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_3_sram; + wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_4_sram; + wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_5_sram; + wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; + wire [0:2] mux_tree_tapbuf_size4_0_sram; + wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_1_sram; + wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_2_sram; + wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire [0:2] mux_tree_tapbuf_size5_0_sram; + wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; + wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_0_sram; + wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_1_sram; + wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_2_sram; + wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_3_sram; + wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_4_sram; + wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_5_sram; + wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_6_sram; + wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_7_sram; + wire [0:2] mux_tree_tapbuf_size7_7_sram_inv; + wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:3] mux_tree_tapbuf_size9_0_sram; + wire [0:3] mux_tree_tapbuf_size9_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size9_1_sram; + wire [0:3] mux_tree_tapbuf_size9_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size9_2_sram; + wire [0:3] mux_tree_tapbuf_size9_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail; + assign chany_bottom_out[18] = chanx_right_in[0]; + assign chany_bottom_out[17] = chanx_right_in[1]; + assign chanx_left_out[3] = chanx_right_in[2]; + assign chany_bottom_out[16] = chanx_right_in[3]; + assign chanx_left_out[5] = chanx_right_in[4]; + assign chanx_left_out[6] = chanx_right_in[5]; + assign chanx_left_out[7] = chanx_right_in[6]; + assign chany_bottom_out[15] = chanx_right_in[7]; + assign chanx_left_out[9] = chanx_right_in[8]; + assign chanx_left_out[10] = chanx_right_in[9]; + assign chanx_left_out[11] = chanx_right_in[10]; + assign chany_bottom_out[14] = chanx_right_in[11]; + assign chanx_left_out[13] = chanx_right_in[12]; + assign chanx_left_out[14] = chanx_right_in[13]; + assign chanx_left_out[15] = chanx_right_in[14]; + assign chanx_left_out[17] = chanx_right_in[16]; + assign chanx_left_out[18] = chanx_right_in[17]; + assign chanx_left_out[19] = chanx_right_in[18]; + assign chany_bottom_out[19] = chanx_left_in[0]; + assign chanx_right_out[3] = chanx_left_in[2]; + assign chanx_right_out[5] = chanx_left_in[4]; + assign chanx_right_out[6] = chanx_left_in[5]; + assign chanx_right_out[7] = chanx_left_in[6]; + assign chanx_right_out[9] = chanx_left_in[8]; + assign chanx_right_out[10] = chanx_left_in[9]; + assign chanx_right_out[11] = chanx_left_in[10]; + assign chanx_right_out[13] = chanx_left_in[12]; + assign chanx_right_out[14] = chanx_left_in[13]; + assign chanx_right_out[15] = chanx_left_in[14]; + assign chanx_right_out[17] = chanx_left_in[16]; + assign chanx_right_out[18] = chanx_left_in[17]; + assign chanx_right_out[19] = chanx_left_in[18]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size10 + mux_right_track_0 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], chanx_left_in[2], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(chanx_right_out[0]) + ); + + + mux_tree_tapbuf_size10_mem + mem_right_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size9 + mux_right_track_2 + ( + .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], chanx_left_in[4], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size9_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]), + .out(chanx_right_out[1]) + ); + + + mux_tree_tapbuf_size9 + mux_left_track_1 + ( + .in({ chanx_right_in[2], chanx_right_in[12], chany_bottom_in[6], chany_bottom_in[13], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size9_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size9_1_sram_inv[0:3]), + .out(chanx_left_out[0]) + ); + + + mux_tree_tapbuf_size9 + mux_left_track_3 + ( + .in({ chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size9_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size9_2_sram_inv[0:3]), + .out(chanx_left_out[1]) + ); + + + mux_tree_tapbuf_size9_mem + mem_right_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size9_mem + mem_left_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size9_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size9_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size9_mem + mem_left_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size9_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size9_2_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size14 + mux_right_track_4 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], chanx_left_in[5], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size14_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]), + .out(chanx_right_out[2]) + ); + + + mux_tree_tapbuf_size14 + mux_left_track_5 + ( + .in({ chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], left_top_grid_pin_1_[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size14_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]), + .out(chanx_left_out[2]) + ); + + + mux_tree_tapbuf_size14_mem + mem_right_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size14_mem + mem_left_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8 + mux_right_track_8 + ( + .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(chanx_right_out[4]) + ); + + + mux_tree_tapbuf_size8 + mux_left_track_9 + ( + .in({ chanx_right_in[6], chanx_right_in[16], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], left_top_grid_pin_1_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(chanx_left_out[4]) + ); + + + mux_tree_tapbuf_size8_mem + mem_right_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size8_mem + mem_left_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_16 + ( + .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], chanx_left_in[8], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chanx_right_out[8]) + ); + + + mux_tree_tapbuf_size7 + mux_right_track_24 + ( + .in({ right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[9], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chanx_right_out[12]) + ); + + + mux_tree_tapbuf_size7 + mux_bottom_track_1 + ( + .in({ chanx_right_in[2], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2] }), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chany_bottom_out[0]) + ); + + + mux_tree_tapbuf_size7 + mux_bottom_track_3 + ( + .in({ chanx_right_in[4], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4] }), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .out(chany_bottom_out[1]) + ); + + + mux_tree_tapbuf_size7 + mux_bottom_track_5 + ( + .in({ chanx_right_in[5], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[5], chanx_left_in[7] }), + .sram(mux_tree_tapbuf_size7_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), + .out(chany_bottom_out[2]) + ); + + + mux_tree_tapbuf_size7 + mux_bottom_track_7 + ( + .in({ chanx_right_in[6], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[6], chanx_left_in[11] }), + .sram(mux_tree_tapbuf_size7_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), + .out(chany_bottom_out[3]) + ); + + + mux_tree_tapbuf_size7 + mux_left_track_17 + ( + .in({ chanx_right_in[8], chanx_right_in[17], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }), + .sram(mux_tree_tapbuf_size7_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), + .out(chanx_left_out[8]) + ); + + + mux_tree_tapbuf_size7 + mux_left_track_25 + ( + .in({ chanx_right_in[9], chanx_right_in[18], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }), + .sram(mux_tree_tapbuf_size7_7_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_7_sram_inv[0:2]), + .out(chanx_left_out[12]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_right_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_bottom_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_bottom_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_bottom_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_bottom_track_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_left_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size7_mem + mem_left_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_7_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_7_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size5 + mux_right_track_32 + ( + .in({ right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[6], chany_bottom_in[13], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chanx_right_out[16]) + ); + + + mux_tree_tapbuf_size5_mem + mem_right_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4 + mux_bottom_track_9 + ( + .in({ chanx_right_in[8], bottom_left_grid_pin_42_[0], chanx_left_in[8], chanx_left_in[15] }), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_bottom_out[4]) + ); + + + mux_tree_tapbuf_size4 + mux_bottom_track_11 + ( + .in({ chanx_right_in[9], bottom_left_grid_pin_43_[0], chanx_left_in[9], chanx_left_in[19] }), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_bottom_out[5]) + ); + + + mux_tree_tapbuf_size4 + mux_bottom_track_25 + ( + .in({ chanx_right_in[18:19], bottom_left_grid_pin_42_[0], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chany_bottom_out[12]) + ); + + + mux_tree_tapbuf_size4_mem + mem_bottom_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_bottom_track_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_bottom_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_13 + ( + .in({ chanx_right_in[10], bottom_left_grid_pin_44_[0], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_bottom_out[6]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_15 + ( + .in({ chanx_right_in[12], bottom_left_grid_pin_45_[0], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_bottom_out[7]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_17 + ( + .in({ chanx_right_in[13], bottom_left_grid_pin_46_[0], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chany_bottom_out[8]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_19 + ( + .in({ chanx_right_in[14], bottom_left_grid_pin_47_[0], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chany_bottom_out[9]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_21 + ( + .in({ chanx_right_in[16], bottom_left_grid_pin_48_[0], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_bottom_out[10]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_23 + ( + .in({ chanx_right_in[17], bottom_left_grid_pin_49_[0], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chany_bottom_out[11]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_19 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_21 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_23 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2 + mux_bottom_track_27 + ( + .in({ chanx_right_in[15], bottom_left_grid_pin_43_[0] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_bottom_out[13]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_27 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size6 + mux_left_track_33 + ( + .in({ chanx_right_in[10], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chanx_left_out[16]) + ); + + + mux_tree_tapbuf_size6_mem + mem_left_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); + endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v index 07d171b..e2a146e 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v @@ -1,672 +1,760 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_2__0_(prog_clk, - chany_top_in, - top_left_grid_pin_34_, - top_left_grid_pin_35_, - top_left_grid_pin_36_, - top_left_grid_pin_37_, - top_left_grid_pin_38_, - top_left_grid_pin_39_, - top_left_grid_pin_40_, - top_left_grid_pin_41_, - top_right_grid_pin_1_, - chanx_left_in, - left_top_grid_pin_42_, - left_top_grid_pin_43_, - left_top_grid_pin_44_, - left_top_grid_pin_45_, - left_top_grid_pin_46_, - left_top_grid_pin_47_, - left_top_grid_pin_48_, - left_top_grid_pin_49_, - left_bottom_grid_pin_1_, - ccff_head, - chany_top_out, - chanx_left_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_top_in; -// -input [0:0] top_left_grid_pin_34_; -// -input [0:0] top_left_grid_pin_35_; -// -input [0:0] top_left_grid_pin_36_; -// -input [0:0] top_left_grid_pin_37_; -// -input [0:0] top_left_grid_pin_38_; -// -input [0:0] top_left_grid_pin_39_; -// -input [0:0] top_left_grid_pin_40_; -// -input [0:0] top_left_grid_pin_41_; -// -input [0:0] top_right_grid_pin_1_; -// -input [0:19] chanx_left_in; -// -input [0:0] left_top_grid_pin_42_; -// -input [0:0] left_top_grid_pin_43_; -// -input [0:0] left_top_grid_pin_44_; -// -input [0:0] left_top_grid_pin_45_; -// -input [0:0] left_top_grid_pin_46_; -// -input [0:0] left_top_grid_pin_47_; -// -input [0:0] left_top_grid_pin_48_; -// -input [0:0] left_top_grid_pin_49_; -// -input [0:0] left_bottom_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chany_top_out; -// -output [0:19] chanx_left_out; -// -output [0:0] ccff_tail; - -// -// - - -// -// - - -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_10_sram; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_11_sram; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_12_sram; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_13_sram; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_14_sram; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_15_sram; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_16_sram; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_17_sram; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_18_sram; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_19_sram; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_20_sram; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_21_sram; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_5_sram; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_6_sram; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_7_sram; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_8_sram; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_9_sram; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:2] mux_tree_tapbuf_size5_0_sram; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_1_sram; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_2_sram; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_3_sram; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_2_sram; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_3_sram; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; - -// -// -// -// - assign chanx_left_out[19] = chany_top_in[1]; -// -// -// - assign chanx_left_out[18] = chany_top_in[2]; -// -// -// - assign chanx_left_out[17] = chany_top_in[3]; -// -// -// - assign chanx_left_out[16] = chany_top_in[4]; -// -// -// - assign chanx_left_out[15] = chany_top_in[5]; -// -// -// - assign chanx_left_out[14] = chany_top_in[6]; -// -// -// - - mux_tree_tapbuf_size6 mux_top_track_0 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], top_right_grid_pin_1_[0], chanx_left_in[0]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chany_top_out[0])); - - mux_tree_tapbuf_size6 mux_top_track_4 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], top_right_grid_pin_1_[0], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chany_top_out[2])); - - mux_tree_tapbuf_size6 mux_left_track_1 ( - .in({chany_top_in[0], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), - .out(chanx_left_out[0])); - - mux_tree_tapbuf_size6 mux_left_track_5 ( - .in({chany_top_in[18], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size6_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), - .out(chanx_left_out[2])); - - mux_tree_tapbuf_size6_mem mem_top_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_top_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_left_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); - - mux_tree_tapbuf_size6_mem mem_left_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); - - mux_tree_tapbuf_size5 mux_top_track_2 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), - .out(chany_top_out[1])); - - mux_tree_tapbuf_size5 mux_top_track_6 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), - .out(chany_top_out[3])); - - mux_tree_tapbuf_size5 mux_left_track_3 ( - .in({chany_top_in[19], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size5_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), - .out(chanx_left_out[1])); - - mux_tree_tapbuf_size5 mux_left_track_7 ( - .in({chany_top_in[17], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size5_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), - .out(chanx_left_out[3])); - - mux_tree_tapbuf_size5_mem mem_top_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_top_track_6 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_left_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2])); - - mux_tree_tapbuf_size5_mem mem_left_track_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2])); - - mux_tree_tapbuf_size3 mux_top_track_8 ( - .in({top_left_grid_pin_34_[0], top_right_grid_pin_1_[0], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chany_top_out[4])); - - mux_tree_tapbuf_size3 mux_top_track_24 ( - .in({top_left_grid_pin_34_[0], top_right_grid_pin_1_[0], chanx_left_in[8]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chany_top_out[12])); - - mux_tree_tapbuf_size3 mux_left_track_9 ( - .in({chany_top_in[16], left_top_grid_pin_42_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), - .out(chanx_left_out[4])); - - mux_tree_tapbuf_size3 mux_left_track_25 ( - .in({chany_top_in[8], left_top_grid_pin_42_[0], left_bottom_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), - .out(chanx_left_out[12])); - - mux_tree_tapbuf_size3_mem mem_top_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_top_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_left_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); - - mux_tree_tapbuf_size3_mem mem_left_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); - - mux_tree_tapbuf_size2 mux_top_track_10 ( - .in({top_left_grid_pin_35_[0], chanx_left_in[15]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chany_top_out[5])); - - mux_tree_tapbuf_size2 mux_top_track_12 ( - .in({top_left_grid_pin_36_[0], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), - .out(chany_top_out[6])); - - mux_tree_tapbuf_size2 mux_top_track_14 ( - .in({top_left_grid_pin_37_[0], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), - .out(chany_top_out[7])); - - mux_tree_tapbuf_size2 mux_top_track_16 ( - .in({top_left_grid_pin_38_[0], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), - .out(chany_top_out[8])); - - mux_tree_tapbuf_size2 mux_top_track_18 ( - .in({top_left_grid_pin_39_[0], chanx_left_in[11]}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), - .out(chany_top_out[9])); - - mux_tree_tapbuf_size2 mux_top_track_20 ( - .in({top_left_grid_pin_40_[0], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), - .out(chany_top_out[10])); - - mux_tree_tapbuf_size2 mux_top_track_22 ( - .in({top_left_grid_pin_41_[0], chanx_left_in[9]}), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), - .out(chany_top_out[11])); - - mux_tree_tapbuf_size2 mux_top_track_26 ( - .in({top_left_grid_pin_35_[0], chanx_left_in[7]}), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), - .out(chany_top_out[13])); - - mux_tree_tapbuf_size2 mux_top_track_28 ( - .in({top_left_grid_pin_36_[0], chanx_left_in[6]}), - .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), - .out(chany_top_out[14])); - - mux_tree_tapbuf_size2 mux_top_track_30 ( - .in({top_left_grid_pin_37_[0], chanx_left_in[5]}), - .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), - .out(chany_top_out[15])); - - mux_tree_tapbuf_size2 mux_top_track_32 ( - .in({top_left_grid_pin_38_[0], chanx_left_in[4]}), - .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), - .out(chany_top_out[16])); - - mux_tree_tapbuf_size2 mux_top_track_34 ( - .in({top_left_grid_pin_39_[0], chanx_left_in[3]}), - .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), - .out(chany_top_out[17])); - - mux_tree_tapbuf_size2 mux_top_track_36 ( - .in({top_left_grid_pin_40_[0], chanx_left_in[2]}), - .sram(mux_tree_tapbuf_size2_12_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), - .out(chany_top_out[18])); - - mux_tree_tapbuf_size2 mux_top_track_38 ( - .in({top_left_grid_pin_41_[0], chanx_left_in[1]}), - .sram(mux_tree_tapbuf_size2_13_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), - .out(chany_top_out[19])); - - mux_tree_tapbuf_size2 mux_left_track_11 ( - .in({chany_top_in[15], left_top_grid_pin_43_[0]}), - .sram(mux_tree_tapbuf_size2_14_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), - .out(chanx_left_out[5])); - - mux_tree_tapbuf_size2 mux_left_track_13 ( - .in({chany_top_in[14], left_top_grid_pin_44_[0]}), - .sram(mux_tree_tapbuf_size2_15_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), - .out(chanx_left_out[6])); - - mux_tree_tapbuf_size2 mux_left_track_15 ( - .in({chany_top_in[13], left_top_grid_pin_45_[0]}), - .sram(mux_tree_tapbuf_size2_16_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), - .out(chanx_left_out[7])); - - mux_tree_tapbuf_size2 mux_left_track_17 ( - .in({chany_top_in[12], left_top_grid_pin_46_[0]}), - .sram(mux_tree_tapbuf_size2_17_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), - .out(chanx_left_out[8])); - - mux_tree_tapbuf_size2 mux_left_track_19 ( - .in({chany_top_in[11], left_top_grid_pin_47_[0]}), - .sram(mux_tree_tapbuf_size2_18_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_18_sram_inv[0:1]), - .out(chanx_left_out[9])); - - mux_tree_tapbuf_size2 mux_left_track_21 ( - .in({chany_top_in[10], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size2_19_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_19_sram_inv[0:1]), - .out(chanx_left_out[10])); - - mux_tree_tapbuf_size2 mux_left_track_23 ( - .in({chany_top_in[9], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size2_20_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_20_sram_inv[0:1]), - .out(chanx_left_out[11])); - - mux_tree_tapbuf_size2 mux_left_track_27 ( - .in({chany_top_in[7], left_top_grid_pin_43_[0]}), - .sram(mux_tree_tapbuf_size2_21_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_21_sram_inv[0:1]), - .out(chanx_left_out[13])); - - mux_tree_tapbuf_size2_mem mem_top_track_10 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_12 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_14 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_18 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_20 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_22 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_26 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_28 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_30 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_34 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_36 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_top_track_38 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_19 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_18_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_21 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_19_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_23 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_20_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_20_sram_inv[0:1])); - - mux_tree_tapbuf_size2_mem mem_left_track_27 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_21_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_21_sram_inv[0:1])); + + +module sb_2__0_ +( + input [0:0] prog_clk, + input [0:19] chany_top_in, + input [0:0] top_left_grid_pin_42_, + input [0:0] top_left_grid_pin_43_, + input [0:0] top_left_grid_pin_44_, + input [0:0] top_left_grid_pin_45_, + input [0:0] top_left_grid_pin_46_, + input [0:0] top_left_grid_pin_47_, + input [0:0] top_left_grid_pin_48_, + input [0:0] top_left_grid_pin_49_, + input [0:0] top_right_grid_pin_1_, + input [0:19] chanx_left_in, + input [0:0] left_bottom_grid_pin_1_, + input [0:0] left_bottom_grid_pin_3_, + input [0:0] left_bottom_grid_pin_5_, + input [0:0] left_bottom_grid_pin_7_, + input [0:0] left_bottom_grid_pin_9_, + input [0:0] left_bottom_grid_pin_11_, + input [0:0] ccff_head, + output [0:19] chany_top_out, + output [0:19] chanx_left_out, + output [0:0] ccff_tail +); + + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_10_sram; + wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_11_sram; + wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_12_sram; + wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_13_sram; + wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_14_sram; + wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_15_sram; + wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_16_sram; + wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_17_sram; + wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_18_sram; + wire [0:1] mux_tree_tapbuf_size2_18_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_19_sram; + wire [0:1] mux_tree_tapbuf_size2_19_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_1_sram; + wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_2_sram; + wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_3_sram; + wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_4_sram; + wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_5_sram; + wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_6_sram; + wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_7_sram; + wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_8_sram; + wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_9_sram; + wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:2] mux_tree_tapbuf_size4_0_sram; + wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_1_sram; + wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_2_sram; + wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_3_sram; + wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire [0:2] mux_tree_tapbuf_size5_0_sram; + wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_1_sram; + wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_1_sram; + wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + assign chanx_left_out[19] = chany_top_in[1]; + assign chanx_left_out[18] = chany_top_in[2]; + assign chanx_left_out[11] = chany_top_in[9]; + assign chanx_left_out[10] = chany_top_in[10]; + assign chany_top_out[19] = chanx_left_in[1]; + assign chany_top_out[18] = chanx_left_in[2]; + assign chany_top_out[17] = chanx_left_in[3]; + assign chany_top_out[16] = chanx_left_in[4]; + assign chany_top_out[15] = chanx_left_in[5]; + assign chany_top_out[14] = chanx_left_in[6]; + + mux_tree_tapbuf_size6 + mux_top_track_0 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[0] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chany_top_out[0]) + ); + + + mux_tree_tapbuf_size6 + mux_top_track_4 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chany_top_out[2]) + ); + + + mux_tree_tapbuf_size6_mem + mem_top_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size6_mem + mem_top_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size5 + mux_top_track_2 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[19] }), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chany_top_out[1]) + ); + + + mux_tree_tapbuf_size5 + mux_top_track_6 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chany_top_out[3]) + ); + + + mux_tree_tapbuf_size5_mem + mem_top_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size5_mem + mem_top_track_6 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_8 + ( + .in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_top_out[4]) + ); + + + mux_tree_tapbuf_size3 + mux_top_track_24 + ( + .in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[8] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_top_out[12]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_top_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_10 + ( + .in({ top_left_grid_pin_43_[0], chanx_left_in[15] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[5]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_12 + ( + .in({ top_left_grid_pin_44_[0], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_top_out[6]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_14 + ( + .in({ top_left_grid_pin_45_[0], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_top_out[7]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_16 + ( + .in({ top_left_grid_pin_46_[0], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_top_out[8]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_18 + ( + .in({ top_left_grid_pin_47_[0], chanx_left_in[11] }), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chany_top_out[9]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_20 + ( + .in({ top_left_grid_pin_48_[0], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chany_top_out[10]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_22 + ( + .in({ top_left_grid_pin_49_[0], chanx_left_in[9] }), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chany_top_out[11]) + ); + + + mux_tree_tapbuf_size2 + mux_top_track_26 + ( + .in({ top_left_grid_pin_43_[0], chanx_left_in[7] }), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .out(chany_top_out[13]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_9 + ( + .in({ chany_top_in[16], left_bottom_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .out(chanx_left_out[4]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_11 + ( + .in({ chany_top_in[15], left_bottom_grid_pin_3_[0] }), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .out(chanx_left_out[5]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_13 + ( + .in({ chany_top_in[14], left_bottom_grid_pin_5_[0] }), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .out(chanx_left_out[6]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_15 + ( + .in({ chany_top_in[13], left_bottom_grid_pin_7_[0] }), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .out(chanx_left_out[7]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_17 + ( + .in({ chany_top_in[12], left_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .out(chanx_left_out[8]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_19 + ( + .in({ chany_top_in[11], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .out(chanx_left_out[9]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_25 + ( + .in({ chany_top_in[8], left_bottom_grid_pin_1_[0] }), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .out(chanx_left_out[12]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_27 + ( + .in({ chany_top_in[7], left_bottom_grid_pin_3_[0] }), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .out(chanx_left_out[13]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_29 + ( + .in({ chany_top_in[6], left_bottom_grid_pin_5_[0] }), + .sram(mux_tree_tapbuf_size2_16_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), + .out(chanx_left_out[14]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_31 + ( + .in({ chany_top_in[5], left_bottom_grid_pin_7_[0] }), + .sram(mux_tree_tapbuf_size2_17_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), + .out(chanx_left_out[15]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_33 + ( + .in({ chany_top_in[4], left_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size2_18_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_18_sram_inv[0:1]), + .out(chanx_left_out[16]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_35 + ( + .in({ chany_top_in[3], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size2_19_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_19_sram_inv[0:1]), + .out(chanx_left_out[17]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_10 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_12 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_14 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_18 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_20 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_22 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_top_track_26 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_19 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_27 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_29 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_31 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_18_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_35 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_19_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_1 + ( + .in({ chany_top_in[0], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chanx_left_out[0]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_3 + ( + .in({ chany_top_in[19], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chanx_left_out[1]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_5 + ( + .in({ chany_top_in[18], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_left_out[2]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_7 + ( + .in({ chany_top_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_left_out[3]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]) + ); + endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v index bc9f272..8aa2dd2 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v @@ -1,698 +1,862 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_2__1_(prog_clk, - chany_top_in, - top_left_grid_pin_34_, - top_left_grid_pin_35_, - top_left_grid_pin_36_, - top_left_grid_pin_37_, - top_left_grid_pin_38_, - top_left_grid_pin_39_, - top_left_grid_pin_40_, - top_left_grid_pin_41_, - top_right_grid_pin_1_, - chany_bottom_in, - bottom_right_grid_pin_1_, - bottom_left_grid_pin_34_, - bottom_left_grid_pin_35_, - bottom_left_grid_pin_36_, - bottom_left_grid_pin_37_, - bottom_left_grid_pin_38_, - bottom_left_grid_pin_39_, - bottom_left_grid_pin_40_, - bottom_left_grid_pin_41_, - chanx_left_in, - left_top_grid_pin_42_, - left_top_grid_pin_43_, - left_top_grid_pin_44_, - left_top_grid_pin_45_, - left_top_grid_pin_46_, - left_top_grid_pin_47_, - left_top_grid_pin_48_, - left_top_grid_pin_49_, - ccff_head, - chany_top_out, - chany_bottom_out, - chanx_left_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_top_in; -// -input [0:0] top_left_grid_pin_34_; -// -input [0:0] top_left_grid_pin_35_; -// -input [0:0] top_left_grid_pin_36_; -// -input [0:0] top_left_grid_pin_37_; -// -input [0:0] top_left_grid_pin_38_; -// -input [0:0] top_left_grid_pin_39_; -// -input [0:0] top_left_grid_pin_40_; -// -input [0:0] top_left_grid_pin_41_; -// -input [0:0] top_right_grid_pin_1_; -// -input [0:19] chany_bottom_in; -// -input [0:0] bottom_right_grid_pin_1_; -// -input [0:0] bottom_left_grid_pin_34_; -// -input [0:0] bottom_left_grid_pin_35_; -// -input [0:0] bottom_left_grid_pin_36_; -// -input [0:0] bottom_left_grid_pin_37_; -// -input [0:0] bottom_left_grid_pin_38_; -// -input [0:0] bottom_left_grid_pin_39_; -// -input [0:0] bottom_left_grid_pin_40_; -// -input [0:0] bottom_left_grid_pin_41_; -// -input [0:19] chanx_left_in; -// -input [0:0] left_top_grid_pin_42_; -// -input [0:0] left_top_grid_pin_43_; -// -input [0:0] left_top_grid_pin_44_; -// -input [0:0] left_top_grid_pin_45_; -// -input [0:0] left_top_grid_pin_46_; -// -input [0:0] left_top_grid_pin_47_; -// -input [0:0] left_top_grid_pin_48_; -// -input [0:0] left_top_grid_pin_49_; -// -input [0:0] ccff_head; -// -output [0:19] chany_top_out; -// -output [0:19] chany_bottom_out; -// -output [0:19] chanx_left_out; -// -output [0:0] ccff_tail; - -// -// -// -// +module sb_2__1_ +( + input [0:0] prog_clk, + input [0:19] chany_top_in, + input [0:0] top_left_grid_pin_42_, + input [0:0] top_left_grid_pin_43_, + input [0:0] top_left_grid_pin_44_, + input [0:0] top_left_grid_pin_45_, + input [0:0] top_left_grid_pin_46_, + input [0:0] top_left_grid_pin_47_, + input [0:0] top_left_grid_pin_48_, + input [0:0] top_left_grid_pin_49_, + input [0:0] top_right_grid_pin_1_, + input [0:19] chany_bottom_in, + input [0:0] bottom_right_grid_pin_1_, + input [0:0] bottom_left_grid_pin_42_, + input [0:0] bottom_left_grid_pin_43_, + input [0:0] bottom_left_grid_pin_44_, + input [0:0] bottom_left_grid_pin_45_, + input [0:0] bottom_left_grid_pin_46_, + input [0:0] bottom_left_grid_pin_47_, + input [0:0] bottom_left_grid_pin_48_, + input [0:0] bottom_left_grid_pin_49_, + input [0:19] chanx_left_in, + input [0:0] left_bottom_grid_pin_34_, + input [0:0] left_bottom_grid_pin_35_, + input [0:0] left_bottom_grid_pin_36_, + input [0:0] left_bottom_grid_pin_37_, + input [0:0] left_bottom_grid_pin_38_, + input [0:0] left_bottom_grid_pin_39_, + input [0:0] left_bottom_grid_pin_40_, + input [0:0] left_bottom_grid_pin_41_, + input [0:0] ccff_head, + output [0:19] chany_top_out, + output [0:19] chany_bottom_out, + output [0:19] chanx_left_out, + output [0:0] ccff_tail +); + + wire [0:3] mux_tree_tapbuf_size10_0_sram; + wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size10_1_sram; + wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; + wire [0:3] mux_tree_tapbuf_size14_0_sram; + wire [0:3] mux_tree_tapbuf_size14_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size14_1_sram; + wire [0:3] mux_tree_tapbuf_size14_1_sram_inv; + wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_1_sram; + wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_2_sram; + wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_3_sram; + wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_4_sram; + wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_5_sram; + wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_2_sram; + wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_3_sram; + wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_4_sram; + wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; + wire [0:2] mux_tree_tapbuf_size4_0_sram; + wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_1_sram; + wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_2_sram; + wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size4_3_sram; + wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_1_sram; + wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_2_sram; + wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire [0:2] mux_tree_tapbuf_size7_0_sram; + wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_1_sram; + wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_2_sram; + wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_3_sram; + wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_4_sram; + wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_5_sram; + wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; + wire [0:2] mux_tree_tapbuf_size7_6_sram; + wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; + wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; + wire [0:3] mux_tree_tapbuf_size8_0_sram; + wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_1_sram; + wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; + wire [0:3] mux_tree_tapbuf_size8_2_sram; + wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; + wire [0:3] mux_tree_tapbuf_size9_0_sram; + wire [0:3] mux_tree_tapbuf_size9_0_sram_inv; + wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; + assign chany_bottom_out[3] = chany_top_in[2]; + assign chany_bottom_out[5] = chany_top_in[4]; + assign chany_bottom_out[6] = chany_top_in[5]; + assign chany_bottom_out[7] = chany_top_in[6]; + assign chany_bottom_out[9] = chany_top_in[8]; + assign chany_bottom_out[10] = chany_top_in[9]; + assign chany_bottom_out[11] = chany_top_in[10]; + assign chany_bottom_out[13] = chany_top_in[12]; + assign chany_bottom_out[14] = chany_top_in[13]; + assign chany_bottom_out[15] = chany_top_in[14]; + assign chany_bottom_out[17] = chany_top_in[16]; + assign chany_bottom_out[18] = chany_top_in[17]; + assign chany_bottom_out[19] = chany_top_in[18]; + assign chany_top_out[3] = chany_bottom_in[2]; + assign chany_top_out[5] = chany_bottom_in[4]; + assign chany_top_out[6] = chany_bottom_in[5]; + assign chany_top_out[7] = chany_bottom_in[6]; + assign chany_top_out[9] = chany_bottom_in[8]; + assign chany_top_out[10] = chany_bottom_in[9]; + assign chany_top_out[11] = chany_bottom_in[10]; + assign chany_top_out[13] = chany_bottom_in[12]; + assign chany_top_out[14] = chany_bottom_in[13]; + assign chany_top_out[15] = chany_bottom_in[14]; + assign chany_top_out[17] = chany_bottom_in[16]; + assign chany_top_out[18] = chany_bottom_in[17]; + assign chany_top_out[19] = chany_bottom_in[18]; + assign chanx_left_out[13] = left_bottom_grid_pin_35_[0]; + + mux_tree_tapbuf_size10 + mux_top_track_0 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(chany_top_out[0]) + ); -wire [0:3] mux_tree_tapbuf_size10_0_sram; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size10_1_sram; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; -wire [0:3] mux_tree_tapbuf_size14_0_sram; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size14_1_sram; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_2_sram; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_3_sram; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_4_sram; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; -wire [0:2] mux_tree_tapbuf_size4_0_sram; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_1_sram; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_2_sram; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size4_3_sram; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_2_sram; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; -wire [0:2] mux_tree_tapbuf_size7_0_sram; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_1_sram; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_2_sram; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_3_sram; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_4_sram; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_5_sram; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; -wire [0:2] mux_tree_tapbuf_size7_6_sram; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; -wire [0:3] mux_tree_tapbuf_size8_0_sram; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_1_sram; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; -wire [0:3] mux_tree_tapbuf_size8_2_sram; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; -wire [0:3] mux_tree_tapbuf_size9_0_sram; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; + mux_tree_tapbuf_size10 + mux_bottom_track_1 + ( + .in({ chany_top_in[2], chany_top_in[12], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(chany_bottom_out[0]) + ); -// -// -// -// - assign chanx_left_out[19] = chany_top_in[1]; -// -// -// - assign chany_bottom_out[3] = chany_top_in[2]; -// -// -// - assign chanx_left_out[18] = chany_top_in[3]; -// -// -// - assign chany_bottom_out[5] = chany_top_in[4]; -// -// -// - assign chany_bottom_out[6] = chany_top_in[5]; -// -// -// - assign chany_bottom_out[7] = chany_top_in[6]; -// -// -// - assign chanx_left_out[17] = chany_top_in[7]; -// -// -// - assign chany_bottom_out[9] = chany_top_in[8]; -// -// -// - assign chany_bottom_out[10] = chany_top_in[9]; -// -// -// - assign chany_bottom_out[11] = chany_top_in[10]; -// -// -// - assign chanx_left_out[16] = chany_top_in[11]; -// -// -// - assign chany_bottom_out[13] = chany_top_in[12]; -// -// -// - assign chany_bottom_out[14] = chany_top_in[13]; -// -// -// - assign chany_bottom_out[15] = chany_top_in[14]; -// -// -// - assign chanx_left_out[15] = chany_top_in[15]; -// -// -// - assign chany_bottom_out[17] = chany_top_in[16]; -// -// -// - assign chany_bottom_out[18] = chany_top_in[17]; -// -// -// - assign chany_bottom_out[19] = chany_top_in[18]; -// -// -// - assign chanx_left_out[14] = chany_top_in[19]; -// -// -// - assign chany_top_out[3] = chany_bottom_in[2]; -// -// -// - assign chany_top_out[5] = chany_bottom_in[4]; -// -// -// - assign chany_top_out[6] = chany_bottom_in[5]; -// -// -// - assign chany_top_out[7] = chany_bottom_in[6]; -// -// -// - assign chany_top_out[9] = chany_bottom_in[8]; -// -// -// - assign chany_top_out[10] = chany_bottom_in[9]; -// -// -// - assign chany_top_out[11] = chany_bottom_in[10]; -// -// -// - assign chany_top_out[13] = chany_bottom_in[12]; -// -// -// - assign chany_top_out[14] = chany_bottom_in[13]; -// -// -// - assign chany_top_out[15] = chany_bottom_in[14]; -// -// -// - assign chany_top_out[17] = chany_bottom_in[16]; -// -// -// - assign chany_top_out[18] = chany_bottom_in[17]; -// -// -// - assign chany_top_out[19] = chany_bottom_in[18]; -// -// -// - assign chanx_left_out[13] = left_top_grid_pin_43_[0]; -// -// -// - mux_tree_tapbuf_size10 mux_top_track_0 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], top_right_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), - .out(chany_top_out[0])); + mux_tree_tapbuf_size10_mem + mem_top_track_0 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10 mux_bottom_track_1 ( - .in({chany_top_in[2], chany_top_in[12], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15]}), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), - .out(chany_bottom_out[0])); - mux_tree_tapbuf_size10_mem mem_top_track_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + mux_tree_tapbuf_size10_mem + mem_bottom_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size10_mem mem_bottom_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); - mux_tree_tapbuf_size8 mux_top_track_2 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[6], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), - .out(chany_top_out[1])); + mux_tree_tapbuf_size8 + mux_top_track_2 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[6], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(chany_top_out[1]) + ); - mux_tree_tapbuf_size8 mux_top_track_8 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_38_[0], top_right_grid_pin_1_[0], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), - .out(chany_top_out[4])); - mux_tree_tapbuf_size8 mux_bottom_track_9 ( - .in({chany_top_in[6], chany_top_in[16], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_41_[0], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), - .out(chany_bottom_out[4])); + mux_tree_tapbuf_size8 + mux_top_track_8 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], top_right_grid_pin_1_[0], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(chany_top_out[4]) + ); - mux_tree_tapbuf_size8_mem mem_top_track_2 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); - mux_tree_tapbuf_size8_mem mem_top_track_8 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); + mux_tree_tapbuf_size8 + mux_bottom_track_9 + ( + .in({ chany_top_in[6], chany_top_in[16], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(chany_bottom_out[4]) + ); - mux_tree_tapbuf_size8_mem mem_bottom_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); - mux_tree_tapbuf_size14 mux_top_track_4 ( - .in({top_left_grid_pin_34_[0], top_left_grid_pin_35_[0], top_left_grid_pin_36_[0], top_left_grid_pin_37_[0], top_left_grid_pin_38_[0], top_left_grid_pin_39_[0], top_left_grid_pin_40_[0], top_left_grid_pin_41_[0], top_right_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size14_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]), - .out(chany_top_out[2])); + mux_tree_tapbuf_size8_mem + mem_top_track_2 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size14 mux_bottom_track_5 ( - .in({chany_top_in[5], chany_top_in[14], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_40_[0], bottom_left_grid_pin_41_[0], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size14_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]), - .out(chany_bottom_out[2])); - mux_tree_tapbuf_size14_mem mem_top_track_4 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3])); + mux_tree_tapbuf_size8_mem + mem_top_track_8 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size14_mem mem_bottom_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3])); - mux_tree_tapbuf_size7 mux_top_track_16 ( - .in({top_left_grid_pin_35_[0], top_left_grid_pin_39_[0], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), - .out(chany_top_out[8])); + mux_tree_tapbuf_size8_mem + mem_bottom_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + ); - mux_tree_tapbuf_size7 mux_top_track_24 ( - .in({top_left_grid_pin_36_[0], top_left_grid_pin_40_[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), - .out(chany_top_out[12])); - mux_tree_tapbuf_size7 mux_bottom_track_17 ( - .in({chany_top_in[8], chany_top_in[17], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_38_[0], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), - .out(chany_bottom_out[8])); + mux_tree_tapbuf_size14 + mux_top_track_4 + ( + .in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], top_right_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }), + .sram(mux_tree_tapbuf_size14_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]), + .out(chany_top_out[2]) + ); - mux_tree_tapbuf_size7 mux_left_track_1 ( - .in({chany_top_in[0], chany_top_in[2], chany_bottom_in[2], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), - .out(chanx_left_out[0])); - mux_tree_tapbuf_size7 mux_left_track_3 ( - .in({chany_top_in[4], chany_bottom_in[0], chany_bottom_in[4], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size7_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), - .out(chanx_left_out[1])); + mux_tree_tapbuf_size14 + mux_bottom_track_5 + ( + .in({ chany_top_in[5], chany_top_in[14], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size14_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]), + .out(chany_bottom_out[2]) + ); - mux_tree_tapbuf_size7 mux_left_track_5 ( - .in({chany_top_in[5], chany_bottom_in[1], chany_bottom_in[5], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size7_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), - .out(chanx_left_out[2])); - mux_tree_tapbuf_size7 mux_left_track_7 ( - .in({chany_top_in[6], chany_bottom_in[3], chany_bottom_in[6], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size7_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), - .out(chanx_left_out[3])); + mux_tree_tapbuf_size14_mem + mem_top_track_4 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3]) + ); - mux_tree_tapbuf_size7_mem mem_top_track_16 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); - mux_tree_tapbuf_size7_mem mem_top_track_24 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); + mux_tree_tapbuf_size14_mem + mem_bottom_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3]) + ); - mux_tree_tapbuf_size7_mem mem_bottom_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); - mux_tree_tapbuf_size7_mem mem_left_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])); + mux_tree_tapbuf_size7 + mux_top_track_16 + ( + .in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chany_top_out[8]) + ); - mux_tree_tapbuf_size7_mem mem_left_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2])); - mux_tree_tapbuf_size7_mem mem_left_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2])); + mux_tree_tapbuf_size7 + mux_top_track_24 + ( + .in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chany_top_out[12]) + ); - mux_tree_tapbuf_size7_mem mem_left_track_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2])); - mux_tree_tapbuf_size6 mux_top_track_32 ( - .in({top_left_grid_pin_37_[0], top_left_grid_pin_41_[0], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chany_top_out[16])); + mux_tree_tapbuf_size7 + mux_bottom_track_17 + ( + .in({ chany_top_in[8], chany_top_in[17], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chany_bottom_out[8]) + ); - mux_tree_tapbuf_size6 mux_bottom_track_25 ( - .in({chany_top_in[9], chany_top_in[18], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_39_[0], chanx_left_in[6], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chany_bottom_out[12])); - mux_tree_tapbuf_size6 mux_bottom_track_33 ( - .in({chany_top_in[10], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_40_[0], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), - .out(chany_bottom_out[16])); + mux_tree_tapbuf_size7 + mux_left_track_1 + ( + .in({ chany_top_in[0], chany_top_in[2], chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .out(chanx_left_out[0]) + ); - mux_tree_tapbuf_size6_mem mem_top_track_32 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); - mux_tree_tapbuf_size6_mem mem_bottom_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + mux_tree_tapbuf_size7 + mux_left_track_3 + ( + .in({ chany_top_in[4], chany_bottom_in[0], chany_bottom_in[4], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size7_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), + .out(chanx_left_out[1]) + ); - mux_tree_tapbuf_size6_mem mem_bottom_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); - mux_tree_tapbuf_size9 mux_bottom_track_3 ( - .in({chany_top_in[4], chany_top_in[13], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size9_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]), - .out(chany_bottom_out[1])); + mux_tree_tapbuf_size7 + mux_left_track_5 + ( + .in({ chany_top_in[5], chany_bottom_in[1], chany_bottom_in[5], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size7_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), + .out(chanx_left_out[2]) + ); - mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3])); - mux_tree_tapbuf_size4 mux_left_track_9 ( - .in({chany_top_in[8], chany_bottom_in[7:8], left_top_grid_pin_42_[0]}), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), - .out(chanx_left_out[4])); + mux_tree_tapbuf_size7 + mux_left_track_7 + ( + .in({ chany_top_in[6], chany_bottom_in[3], chany_bottom_in[6], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size7_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), + .out(chanx_left_out[3]) + ); - mux_tree_tapbuf_size4 mux_left_track_11 ( - .in({chany_top_in[9], chany_bottom_in[9], chany_bottom_in[11], left_top_grid_pin_43_[0]}), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), - .out(chanx_left_out[5])); - mux_tree_tapbuf_size4 mux_left_track_13 ( - .in({chany_top_in[10], chany_bottom_in[10], chany_bottom_in[15], left_top_grid_pin_44_[0]}), - .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), - .out(chanx_left_out[6])); + mux_tree_tapbuf_size7_mem + mem_top_track_16 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size4 mux_left_track_15 ( - .in({chany_top_in[12], chany_bottom_in[12], chany_bottom_in[19], left_top_grid_pin_45_[0]}), - .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), - .out(chanx_left_out[7])); - mux_tree_tapbuf_size4_mem mem_left_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + mux_tree_tapbuf_size7_mem + mem_top_track_24 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size4_mem mem_left_track_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); - mux_tree_tapbuf_size4_mem mem_left_track_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + mux_tree_tapbuf_size7_mem + mem_bottom_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + ); - mux_tree_tapbuf_size4_mem mem_left_track_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); - mux_tree_tapbuf_size3 mux_left_track_17 ( - .in({chany_top_in[13], chany_bottom_in[13], left_top_grid_pin_46_[0]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chanx_left_out[8])); + mux_tree_tapbuf_size7_mem + mem_left_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3 mux_left_track_19 ( - .in({chany_top_in[14], chany_bottom_in[14], left_top_grid_pin_47_[0]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chanx_left_out[9])); - mux_tree_tapbuf_size3 mux_left_track_21 ( - .in({chany_top_in[16], chany_bottom_in[16], left_top_grid_pin_48_[0]}), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), - .out(chanx_left_out[10])); + mux_tree_tapbuf_size7_mem + mem_left_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3 mux_left_track_23 ( - .in({chany_top_in[17], chany_bottom_in[17], left_top_grid_pin_49_[0]}), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), - .out(chanx_left_out[11])); - mux_tree_tapbuf_size3 mux_left_track_25 ( - .in({chany_top_in[18], chany_bottom_in[18], left_top_grid_pin_42_[0]}), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), - .out(chanx_left_out[12])); + mux_tree_tapbuf_size7_mem + mem_left_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3_mem mem_left_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); - mux_tree_tapbuf_size3_mem mem_left_track_19 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + mux_tree_tapbuf_size7_mem + mem_left_track_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3_mem mem_left_track_21 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); - mux_tree_tapbuf_size3_mem mem_left_track_23 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + mux_tree_tapbuf_size6 + mux_top_track_32 + ( + .in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chany_top_out[16]) + ); + + + mux_tree_tapbuf_size6 + mux_bottom_track_25 + ( + .in({ chany_top_in[9], chany_top_in[18], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[6], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chany_bottom_out[12]) + ); + + + mux_tree_tapbuf_size6 + mux_bottom_track_33 + ( + .in({ chany_top_in[10], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(chany_bottom_out[16]) + ); + + + mux_tree_tapbuf_size6_mem + mem_top_track_32 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size6_mem + mem_bottom_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size6_mem + mem_bottom_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size9 + mux_bottom_track_3 + ( + .in({ chany_top_in[4], chany_top_in[13], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }), + .sram(mux_tree_tapbuf_size9_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]), + .out(chany_bottom_out[1]) + ); + + + mux_tree_tapbuf_size9_mem + mem_bottom_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_9 + ( + .in({ chany_top_in[8], chany_bottom_in[7:8], left_bottom_grid_pin_34_[0] }), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chanx_left_out[4]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_11 + ( + .in({ chany_top_in[9], chany_bottom_in[9], chany_bottom_in[11], left_bottom_grid_pin_35_[0] }), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chanx_left_out[5]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_13 + ( + .in({ chany_top_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_36_[0] }), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_left_out[6]) + ); + + + mux_tree_tapbuf_size4 + mux_left_track_15 + ( + .in({ chany_top_in[12], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_37_[0] }), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_left_out[7]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size4_mem + mem_left_track_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_17 + ( + .in({ chany_top_in[13], chany_bottom_in[13], left_bottom_grid_pin_38_[0] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chanx_left_out[8]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_19 + ( + .in({ chany_top_in[14], chany_bottom_in[14], left_bottom_grid_pin_39_[0] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_left_out[9]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_21 + ( + .in({ chany_top_in[16], chany_bottom_in[16], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chanx_left_out[10]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_23 + ( + .in({ chany_top_in[17], chany_bottom_in[17], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chanx_left_out[11]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_25 + ( + .in({ chany_top_in[18], chany_bottom_in[18], left_bottom_grid_pin_34_[0] }), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chanx_left_out[12]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_19 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_21 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_23 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_29 + ( + .in({ chany_top_in[19], left_bottom_grid_pin_36_[0] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chanx_left_out[14]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_31 + ( + .in({ chany_top_in[15], left_bottom_grid_pin_37_[0] }), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chanx_left_out[15]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_33 + ( + .in({ chany_top_in[11], left_bottom_grid_pin_38_[0] }), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chanx_left_out[16]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_35 + ( + .in({ chany_top_in[7], left_bottom_grid_pin_39_[0] }), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chanx_left_out[17]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_37 + ( + .in({ chany_top_in[3], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_left_out[18]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_39 + ( + .in({ chany_top_in[1], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_left_out[19]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_29 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_31 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_35 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_37 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_39 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + ); - mux_tree_tapbuf_size3_mem mem_left_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v index da1d675..cf2fdd6 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v @@ -1,528 +1,884 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module sb_2__2_(prog_clk, - chany_bottom_in, - bottom_right_grid_pin_1_, - bottom_left_grid_pin_34_, - bottom_left_grid_pin_35_, - bottom_left_grid_pin_36_, - bottom_left_grid_pin_37_, - bottom_left_grid_pin_38_, - bottom_left_grid_pin_39_, - bottom_left_grid_pin_40_, - bottom_left_grid_pin_41_, - chanx_left_in, - left_top_grid_pin_1_, - ccff_head, - chany_bottom_out, - chanx_left_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:19] chany_bottom_in; -// -input [0:0] bottom_right_grid_pin_1_; -// -input [0:0] bottom_left_grid_pin_34_; -// -input [0:0] bottom_left_grid_pin_35_; -// -input [0:0] bottom_left_grid_pin_36_; -// -input [0:0] bottom_left_grid_pin_37_; -// -input [0:0] bottom_left_grid_pin_38_; -// -input [0:0] bottom_left_grid_pin_39_; -// -input [0:0] bottom_left_grid_pin_40_; -// -input [0:0] bottom_left_grid_pin_41_; -// -input [0:19] chanx_left_in; -// -input [0:0] left_top_grid_pin_1_; -// -input [0:0] ccff_head; -// -output [0:19] chany_bottom_out; -// -output [0:19] chanx_left_out; -// -output [0:0] ccff_tail; - -// -// -// -// +module sb_2__2_ +( + input [0:0] prog_clk, + input [0:19] chany_bottom_in, + input [0:0] bottom_right_grid_pin_1_, + input [0:0] bottom_left_grid_pin_42_, + input [0:0] bottom_left_grid_pin_43_, + input [0:0] bottom_left_grid_pin_44_, + input [0:0] bottom_left_grid_pin_45_, + input [0:0] bottom_left_grid_pin_46_, + input [0:0] bottom_left_grid_pin_47_, + input [0:0] bottom_left_grid_pin_48_, + input [0:0] bottom_left_grid_pin_49_, + input [0:19] chanx_left_in, + input [0:0] left_top_grid_pin_1_, + input [0:0] left_bottom_grid_pin_34_, + input [0:0] left_bottom_grid_pin_35_, + input [0:0] left_bottom_grid_pin_36_, + input [0:0] left_bottom_grid_pin_37_, + input [0:0] left_bottom_grid_pin_38_, + input [0:0] left_bottom_grid_pin_39_, + input [0:0] left_bottom_grid_pin_40_, + input [0:0] left_bottom_grid_pin_41_, + input [0:0] ccff_head, + output [0:19] chany_bottom_out, + output [0:19] chanx_left_out, + output [0:0] ccff_tail, + input SC_IN_TOP, + input SC_IN_BOT, + output SC_OUT_TOP, + output SC_OUT_BOT +); + + wire [0:1] mux_tree_tapbuf_size2_0_sram; + wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_10_sram; + wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_11_sram; + wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_12_sram; + wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_13_sram; + wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_14_sram; + wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_15_sram; + wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_16_sram; + wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_17_sram; + wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_18_sram; + wire [0:1] mux_tree_tapbuf_size2_18_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_19_sram; + wire [0:1] mux_tree_tapbuf_size2_19_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_1_sram; + wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_20_sram; + wire [0:1] mux_tree_tapbuf_size2_20_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_21_sram; + wire [0:1] mux_tree_tapbuf_size2_21_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_22_sram; + wire [0:1] mux_tree_tapbuf_size2_22_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_23_sram; + wire [0:1] mux_tree_tapbuf_size2_23_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_2_sram; + wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_3_sram; + wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_4_sram; + wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_5_sram; + wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_6_sram; + wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_7_sram; + wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_8_sram; + wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; + wire [0:1] mux_tree_tapbuf_size2_9_sram; + wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; + wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; + wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; + wire [0:1] mux_tree_tapbuf_size3_0_sram; + wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_1_sram; + wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; + wire [0:1] mux_tree_tapbuf_size3_2_sram; + wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; + wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; + wire [0:2] mux_tree_tapbuf_size5_0_sram; + wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_1_sram; + wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_2_sram; + wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size5_3_sram; + wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; + wire [0:2] mux_tree_tapbuf_size6_0_sram; + wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_1_sram; + wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_2_sram; + wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; + wire [0:2] mux_tree_tapbuf_size6_3_sram; + wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; + wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; + wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; + assign chany_bottom_out[19] = chanx_left_in[0]; + assign chany_bottom_out[15] = chanx_left_in[16]; + assign chany_bottom_out[16] = chanx_left_in[17]; + assign chany_bottom_out[17] = chanx_left_in[18]; + assign chany_bottom_out[18] = chanx_left_in[19]; + assign SC_IN_TOP = SC_IN_BOT; + assign SC_OUT_TOP = SC_OUT_BOT; + + mux_tree_tapbuf_size6 + mux_bottom_track_1 + ( + .in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1] }), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chany_bottom_out[0]) + ); -wire [0:1] mux_tree_tapbuf_size2_0_sram; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_10_sram; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_11_sram; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_12_sram; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_13_sram; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_14_sram; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_15_sram; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_16_sram; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_17_sram; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_1_sram; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_2_sram; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_3_sram; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_4_sram; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_5_sram; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_6_sram; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_7_sram; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_8_sram; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; -wire [0:1] mux_tree_tapbuf_size2_9_sram; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; -wire [0:1] mux_tree_tapbuf_size3_0_sram; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; -wire [0:1] mux_tree_tapbuf_size3_1_sram; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; -wire [0:2] mux_tree_tapbuf_size5_0_sram; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size5_1_sram; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; -wire [0:2] mux_tree_tapbuf_size6_0_sram; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; -wire [0:2] mux_tree_tapbuf_size6_1_sram; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + mux_tree_tapbuf_size6 + mux_bottom_track_5 + ( + .in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3] }), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chany_bottom_out[2]) + ); -// -// -// -// - assign chanx_left_out[1] = chany_bottom_in[0]; -// -// -// - assign chanx_left_out[3] = chany_bottom_in[2]; -// -// -// - assign chanx_left_out[5] = chany_bottom_in[4]; -// -// -// - assign chanx_left_out[6] = chany_bottom_in[5]; -// -// -// - assign chanx_left_out[7] = chany_bottom_in[6]; -// -// -// - assign chanx_left_out[8] = chany_bottom_in[7]; -// -// -// - assign chanx_left_out[9] = chany_bottom_in[8]; -// -// -// - assign chanx_left_out[10] = chany_bottom_in[9]; -// -// -// - assign chanx_left_out[11] = chany_bottom_in[10]; -// -// -// - assign chanx_left_out[13] = chany_bottom_in[12]; -// -// -// - assign chanx_left_out[14] = chany_bottom_in[13]; -// -// -// - assign chanx_left_out[15] = chany_bottom_in[14]; -// -// -// - assign chanx_left_out[16] = chany_bottom_in[15]; -// -// -// - assign chanx_left_out[17] = chany_bottom_in[16]; -// -// -// - assign chanx_left_out[18] = chany_bottom_in[17]; -// -// -// - assign chanx_left_out[19] = chany_bottom_in[18]; -// -// -// - mux_tree_tapbuf_size6 mux_bottom_track_1 ( - .in({bottom_right_grid_pin_1_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[1]}), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), - .out(chany_bottom_out[0])); + mux_tree_tapbuf_size6 + mux_left_track_1 + ( + .in({ chany_bottom_in[19], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(chanx_left_out[0]) + ); - mux_tree_tapbuf_size6 mux_bottom_track_5 ( - .in({bottom_right_grid_pin_1_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[3]}), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), - .out(chany_bottom_out[2])); - mux_tree_tapbuf_size6_mem mem_bottom_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + mux_tree_tapbuf_size6 + mux_left_track_5 + ( + .in({ chany_bottom_in[1], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(chanx_left_out[2]) + ); - mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); - mux_tree_tapbuf_size5 mux_bottom_track_3 ( - .in({bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[2]}), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), - .out(chany_bottom_out[1])); + mux_tree_tapbuf_size6_mem + mem_bottom_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5 mux_bottom_track_7 ( - .in({bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[4]}), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), - .out(chany_bottom_out[3])); - mux_tree_tapbuf_size5_mem mem_bottom_track_3 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); + mux_tree_tapbuf_size6_mem + mem_bottom_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size5_mem mem_bottom_track_7 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); - mux_tree_tapbuf_size3 mux_bottom_track_9 ( - .in({bottom_right_grid_pin_1_[0], bottom_left_grid_pin_41_[0], chanx_left_in[5]}), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), - .out(chany_bottom_out[4])); + mux_tree_tapbuf_size6_mem + mem_left_track_1 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3 mux_bottom_track_25 ( - .in({bottom_right_grid_pin_1_[0], bottom_left_grid_pin_41_[0], chanx_left_in[13]}), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), - .out(chany_bottom_out[12])); - mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + mux_tree_tapbuf_size6_mem + mem_left_track_5 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size3_mem mem_bottom_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); - mux_tree_tapbuf_size2 mux_bottom_track_11 ( - .in({bottom_left_grid_pin_34_[0], chanx_left_in[6]}), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), - .out(chany_bottom_out[5])); + mux_tree_tapbuf_size5 + mux_bottom_track_3 + ( + .in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2] }), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chany_bottom_out[1]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_13 ( - .in({bottom_left_grid_pin_35_[0], chanx_left_in[7]}), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), - .out(chany_bottom_out[6])); - mux_tree_tapbuf_size2 mux_bottom_track_15 ( - .in({bottom_left_grid_pin_36_[0], chanx_left_in[8]}), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), - .out(chany_bottom_out[7])); + mux_tree_tapbuf_size5 + mux_bottom_track_7 + ( + .in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[4] }), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chany_bottom_out[3]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_17 ( - .in({bottom_left_grid_pin_37_[0], chanx_left_in[9]}), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), - .out(chany_bottom_out[8])); - mux_tree_tapbuf_size2 mux_bottom_track_19 ( - .in({bottom_left_grid_pin_38_[0], chanx_left_in[10]}), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), - .out(chany_bottom_out[9])); + mux_tree_tapbuf_size5 + mux_left_track_3 + ( + .in({ chany_bottom_in[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), + .out(chanx_left_out[1]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_21 ( - .in({bottom_left_grid_pin_39_[0], chanx_left_in[11]}), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), - .out(chany_bottom_out[10])); - mux_tree_tapbuf_size2 mux_bottom_track_23 ( - .in({bottom_left_grid_pin_40_[0], chanx_left_in[12]}), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), - .out(chany_bottom_out[11])); + mux_tree_tapbuf_size5 + mux_left_track_7 + ( + .in({ chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), + .out(chanx_left_out[3]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_27 ( - .in({bottom_left_grid_pin_34_[0], chanx_left_in[14]}), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), - .out(chany_bottom_out[13])); - mux_tree_tapbuf_size2 mux_bottom_track_29 ( - .in({bottom_left_grid_pin_35_[0], chanx_left_in[15]}), - .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), - .out(chany_bottom_out[14])); + mux_tree_tapbuf_size5_mem + mem_bottom_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_31 ( - .in({bottom_left_grid_pin_36_[0], chanx_left_in[16]}), - .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), - .out(chany_bottom_out[15])); - mux_tree_tapbuf_size2 mux_bottom_track_33 ( - .in({bottom_left_grid_pin_37_[0], chanx_left_in[17]}), - .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), - .out(chany_bottom_out[16])); + mux_tree_tapbuf_size5_mem + mem_bottom_track_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_35 ( - .in({bottom_left_grid_pin_38_[0], chanx_left_in[18]}), - .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), - .out(chany_bottom_out[17])); - mux_tree_tapbuf_size2 mux_bottom_track_37 ( - .in({bottom_left_grid_pin_39_[0], chanx_left_in[19]}), - .sram(mux_tree_tapbuf_size2_12_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), - .out(chany_bottom_out[18])); + mux_tree_tapbuf_size5_mem + mem_left_track_3 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2 mux_bottom_track_39 ( - .in({bottom_left_grid_pin_40_[0], chanx_left_in[0]}), - .sram(mux_tree_tapbuf_size2_13_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), - .out(chany_bottom_out[19])); - mux_tree_tapbuf_size2 mux_left_track_1 ( - .in({chany_bottom_in[19], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_14_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), - .out(chanx_left_out[0])); + mux_tree_tapbuf_size5_mem + mem_left_track_7 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2]) + ); - mux_tree_tapbuf_size2 mux_left_track_5 ( - .in({chany_bottom_in[1], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_15_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), - .out(chanx_left_out[2])); - mux_tree_tapbuf_size2 mux_left_track_9 ( - .in({chany_bottom_in[3], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_16_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), - .out(chanx_left_out[4])); + mux_tree_tapbuf_size2 + mux_bottom_track_9 + ( + .in({ bottom_right_grid_pin_1_[0], chanx_left_in[5] }), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_bottom_out[4]) + ); - mux_tree_tapbuf_size2 mux_left_track_25 ( - .in({chany_bottom_in[11], left_top_grid_pin_1_[0]}), - .sram(mux_tree_tapbuf_size2_17_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), - .out(chanx_left_out[12])); - mux_tree_tapbuf_size2_mem mem_bottom_track_11 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_11 + ( + .in({ bottom_left_grid_pin_42_[0], chanx_left_in[6] }), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_bottom_out[5]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_13 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_15 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_13 + ( + .in({ bottom_left_grid_pin_43_[0], chanx_left_in[7] }), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_bottom_out[6]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_17 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_19 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_15 + ( + .in({ bottom_left_grid_pin_44_[0], chanx_left_in[8] }), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_bottom_out[7]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_21 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_23 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_17 + ( + .in({ bottom_left_grid_pin_45_[0], chanx_left_in[9] }), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chany_bottom_out[8]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_29 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_19 + ( + .in({ bottom_left_grid_pin_46_[0], chanx_left_in[10] }), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chany_bottom_out[9]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_31 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_33 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_21 + ( + .in({ bottom_left_grid_pin_47_[0], chanx_left_in[11] }), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chany_bottom_out[10]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_35 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_bottom_track_37 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_23 + ( + .in({ bottom_left_grid_pin_48_[0], chanx_left_in[12] }), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .out(chany_bottom_out[11]) + ); - mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_left_track_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_27 + ( + .in({ bottom_left_grid_pin_42_[0], chanx_left_in[14] }), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .out(chany_bottom_out[13]) + ); - mux_tree_tapbuf_size2_mem mem_left_track_5 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1])); - mux_tree_tapbuf_size2_mem mem_left_track_9 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1])); + mux_tree_tapbuf_size2 + mux_bottom_track_29 + ( + .in({ bottom_left_grid_pin_43_[0], chanx_left_in[15] }), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .out(chany_bottom_out[14]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_11 + ( + .in({ chany_bottom_in[4], left_bottom_grid_pin_34_[0] }), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .out(chanx_left_out[5]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_13 + ( + .in({ chany_bottom_in[5], left_bottom_grid_pin_35_[0] }), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .out(chanx_left_out[6]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_15 + ( + .in({ chany_bottom_in[6], left_bottom_grid_pin_36_[0] }), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .out(chanx_left_out[7]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_17 + ( + .in({ chany_bottom_in[7], left_bottom_grid_pin_37_[0] }), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .out(chanx_left_out[8]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_19 + ( + .in({ chany_bottom_in[8], left_bottom_grid_pin_38_[0] }), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .out(chanx_left_out[9]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_21 + ( + .in({ chany_bottom_in[9], left_bottom_grid_pin_39_[0] }), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .out(chanx_left_out[10]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_23 + ( + .in({ chany_bottom_in[10], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size2_16_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), + .out(chanx_left_out[11]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_27 + ( + .in({ chany_bottom_in[12], left_bottom_grid_pin_34_[0] }), + .sram(mux_tree_tapbuf_size2_17_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), + .out(chanx_left_out[13]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_29 + ( + .in({ chany_bottom_in[13], left_bottom_grid_pin_35_[0] }), + .sram(mux_tree_tapbuf_size2_18_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_18_sram_inv[0:1]), + .out(chanx_left_out[14]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_31 + ( + .in({ chany_bottom_in[14], left_bottom_grid_pin_36_[0] }), + .sram(mux_tree_tapbuf_size2_19_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_19_sram_inv[0:1]), + .out(chanx_left_out[15]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_33 + ( + .in({ chany_bottom_in[15], left_bottom_grid_pin_37_[0] }), + .sram(mux_tree_tapbuf_size2_20_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_20_sram_inv[0:1]), + .out(chanx_left_out[16]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_35 + ( + .in({ chany_bottom_in[16], left_bottom_grid_pin_38_[0] }), + .sram(mux_tree_tapbuf_size2_21_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_21_sram_inv[0:1]), + .out(chanx_left_out[17]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_37 + ( + .in({ chany_bottom_in[17], left_bottom_grid_pin_39_[0] }), + .sram(mux_tree_tapbuf_size2_22_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_22_sram_inv[0:1]), + .out(chanx_left_out[18]) + ); + + + mux_tree_tapbuf_size2 + mux_left_track_39 + ( + .in({ chany_bottom_in[18], left_bottom_grid_pin_40_[0] }), + .sram(mux_tree_tapbuf_size2_23_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_23_sram_inv[0:1]), + .out(chanx_left_out[19]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_19 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_21 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_23 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_27 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_bottom_track_29 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_11 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_13 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_15 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_17 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_19 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_21 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_23 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_27 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_29 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_18_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_31 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_19_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_33 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_20_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_20_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_35 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_21_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_21_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_37 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_22_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_22_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size2_mem + mem_left_track_39 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_23_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_23_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3 + mux_bottom_track_25 + ( + .in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_49_[0], chanx_left_in[13] }), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_bottom_out[12]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_9 + ( + .in({ chany_bottom_in[3], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_left_out[4]) + ); + + + mux_tree_tapbuf_size3 + mux_left_track_25 + ( + .in({ chany_bottom_in[11], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chanx_left_out[12]) + ); + + + mux_tree_tapbuf_size3_mem + mem_bottom_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_9 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + ); + + + mux_tree_tapbuf_size3_mem + mem_left_track_25 + ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + ); - mux_tree_tapbuf_size2_mem mem_left_track_25 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1])); endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/digital_io_hd.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/digital_io_hd.v new file mode 100644 index 0000000..0dcc04f --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/digital_io_hd.v @@ -0,0 +1,63 @@ +`timescale 1ns/1ps + +module GPIO (A, IE, OE, Y, in, out, mem_out); + output A; + output IE; + output OE; + output Y; + input in; + output out; + input mem_out; + + assign A = in; + assign out = Y; + assign IE = mem_out; + sky130_fd_sc_hd__inv_1 ie_oe_inv ( + .A (mem_out), + .Y (OE) ); +endmodule + + +// +// +// +// +module EMBEDDED_IO ( + input SOC_IN, // + output SOC_OUT, // + output SOC_DIR, // + output FPGA_IN, // + input FPGA_OUT, // + input FPGA_DIR // +); + + assign FPGA_IN = SOC_IN; + assign SOC_OUT = FPGA_OUT; + assign SOC_DIR = FPGA_DIR; +endmodule + +// +// +// +module GPIN ( + inout A, // + output Y // +); + // + sky130_fd_sc_hd__buf_4 in_buf ( + .A (A), + .X (Y) ); +endmodule + +// +// +// +module GPOUT ( + inout Y, // + input A // +); + // + sky130_fd_sc_hd__buf_4 in_buf ( + .A (A), + .X (Y) ); +endmodule diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v index bbe4829..ad8b2cc 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v @@ -130,6 +130,226 @@ endmodule +// +module mux_tree_tapbuf_size4_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:2] mem_out; +// +output [0:2] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[2]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size7_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:2] mem_out; +// +output [0:2] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[2]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size11_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:3] mem_out; +// +output [0:3] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[3]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size2_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:1] mem_out; +// +output [0:1] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[1]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + +endmodule +// + + + // module mux_tree_tapbuf_size6_mem(prog_clk, ccff_head, @@ -240,281 +460,6 @@ endmodule -// -module mux_tree_tapbuf_size14_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out, - mem_outb); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:3] mem_out; -// -output [0:3] mem_outb; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[3]; -// - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( - .CLK(prog_clk[0]), - .D(mem_out[2]), - .Q(mem_out[3]), - .Q_N(mem_outb[3])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size3_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out, - mem_outb); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:1] mem_out; -// -output [0:1] mem_outb; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[1]; -// - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size2_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out, - mem_outb); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:1] mem_out; -// -output [0:1] mem_outb; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[1]; -// - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size7_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out, - mem_outb); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:2] mem_out; -// -output [0:2] mem_outb; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[2]; -// - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size9_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out, - mem_outb); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:3] mem_out; -// -output [0:3] mem_outb; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[3]; -// - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); - - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( - .CLK(prog_clk[0]), - .D(mem_out[2]), - .Q(mem_out[3]), - .Q_N(mem_outb[3])); - -endmodule -// - - - // module mux_tree_tapbuf_size12_mem(prog_clk, ccff_head, @@ -644,7 +589,7 @@ endmodule // -module mux_tree_tapbuf_size4_mem(prog_clk, +module mux_tree_tapbuf_size3_mem(prog_clk, ccff_head, ccff_tail, mem_out, @@ -656,9 +601,9 @@ input [0:0] ccff_head; // output [0:0] ccff_tail; // -output [0:2] mem_out; +output [0:1] mem_out; // -output [0:2] mem_outb; +output [0:1] mem_outb; // // @@ -672,7 +617,56 @@ output [0:2] mem_outb; // // // - assign ccff_tail[0] = mem_out[2]; + assign ccff_tail[0] = mem_out[1]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size9_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:3] mem_out; +// +output [0:3] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[3]; // sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( @@ -693,6 +687,73 @@ output [0:2] mem_outb; .Q(mem_out[2]), .Q_N(mem_outb[2])); + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size14_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:3] mem_out; +// +output [0:3] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[3]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + endmodule // @@ -887,11 +948,11 @@ endmodule // -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out, - mem_outb); +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); // input [0:0] prog_clk; // diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v index 7ddd317..9d0204a 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v @@ -216,6 +216,338 @@ endmodule +// +module mux_tree_tapbuf_size4(in, + sram, + sram_inv, + out); +// +input [0:3] in; +// +input [0:2] sram; +// +input [0:2] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_3_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(in[2]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(in[3]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_1_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_2_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size7(in, + sram, + sram_inv, + out); +// +input [0:6] in; +// +input [0:2] sram; +// +input [0:2] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_6_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(const1_0_const1[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size11(in, + sram, + sram_inv, + out); +// +input [0:10] in; +// +input [0:3] sram; +// +input [0:3] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_10_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(in[8]), + .A0(in[9]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(in[10]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_8_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_7_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_9_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_8_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_9_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_10_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size2(in, + sram, + sram_inv, + out); +// +input [0:1] in; +// +input [0:1] sram; +// +input [0:1] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_1_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + +endmodule +// + + + // module mux_tree_tapbuf_size6(in, sram, @@ -375,456 +707,6 @@ endmodule -// -module mux_tree_tapbuf_size14(in, - sram, - sram_inv, - out); -// -input [0:13] in; -// -input [0:3] sram; -// -input [0:3] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_13_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( - .A1(in[6]), - .A0(in[7]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( - .A1(in[8]), - .A0(in[9]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( - .A1(in[10]), - .A0(in[11]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( - .A1(in[12]), - .A0(in[13]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_7_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_8_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_9_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_10_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_7_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_8_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_11_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_9_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_10_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_12_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_11_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_12_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_13_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size3(in, - sram, - sram_inv, - out); -// -input [0:2] in; -// -input [0:1] sram; -// -input [0:1] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_2_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(const1_0_const1[0]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size2(in, - sram, - sram_inv, - out); -// -input [0:1] in; -// -input [0:1] sram; -// -input [0:1] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_1_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size7(in, - sram, - sram_inv, - out); -// -input [0:6] in; -// -input [0:2] sram; -// -input [0:2] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_6_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( - .A1(in[6]), - .A0(const1_0_const1[0]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size9(in, - sram, - sram_inv, - out); -// -input [0:8] in; -// -input [0:3] sram; -// -input [0:3] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_8_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A1(in[6]), - .A0(in[7]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A1(in[8]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_7_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_7_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_8_X[0])); - -endmodule -// - - - // module mux_tree_tapbuf_size12(in, sram, @@ -1104,16 +986,78 @@ endmodule // -module mux_tree_tapbuf_size4(in, +module mux_tree_tapbuf_size3(in, sram, sram_inv, out); // -input [0:3] in; +input [0:2] in; // -input [0:2] sram; +input [0:1] sram; // -input [0:2] sram_inv; +input [0:1] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_2_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(const1_0_const1[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size9(in, + sram, + sram_inv, + out); +// +input [0:8] in; +// +input [0:3] sram; +// +input [0:3] sram_inv; // output [0:0] out; @@ -1130,6 +1074,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; // // @@ -1140,7 +1089,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; .const1(const1_0_const1[0])); sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_3_X[0]), + .A(sky130_fd_sc_hd__mux2_1_8_X[0]), .X(out[0])); sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( @@ -1149,24 +1098,193 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; .S(sram[0]), .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(in[2]), - .S(sram[1]), + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(in[3]), - .A0(const1_0_const1[0]), + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), .S(sram[1]), .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_1_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_2_X[0]), - .S(sram[2]), + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[1]), .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(in[6]), + .A0(in[7]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(in[8]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_7_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_8_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size14(in, + sram, + sram_inv, + out); +// +input [0:13] in; +// +input [0:3] sram; +// +input [0:3] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_13_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( + .A1(in[8]), + .A0(in[9]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( + .A1(in[10]), + .A0(in[11]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( + .A1(in[12]), + .A0(in[13]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_9_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_10_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_7_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_8_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_11_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_9_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_10_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_12_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_11_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_12_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_13_X[0])); + endmodule // diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v index d288329..b710461 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v @@ -15,12 +15,11 @@ wire [0:0] Test_en; wire [0:0] clk; // -wire [0:7] gfpga_pad_GPIO_Y; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN; -wire [0:7] gfpga_pad_GPIO_A; -wire [0:7] gfpga_pad_GPIO_IE; -wire [0:7] gfpga_pad_GPIO_OE; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR; reg [0:0] config_done; wire [0:0] prog_clock; @@ -85,7 +84,7 @@ initial end always wait(~greset) begin - #0.4159859717 op_clock_reg[0] = ~op_clock_reg[0]; + #0.5203860402 op_clock_reg[0] = ~op_clock_reg[0]; end // @@ -116,8 +115,8 @@ initial begin greset[0] = 1'b1; wait(config_done) - #0.8319719434 greset[0] = 1'b1; - #1.663943887 greset[0] = 1'b0; + #1.04077208 greset[0] = 1'b1; + #2.081544161 greset[0] = 1'b0; end // @@ -139,27 +138,57 @@ initial .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0:7]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0:7]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0:7]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0:7]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:17]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:17]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:17]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0])); // // - assign gfpga_pad_GPIO_Y[4] = a[0]; -// - assign gfpga_pad_GPIO_Y[6] = b[0]; -// - assign out:c_fpga[0] = gfpga_pad_GPIO_Y[5]; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[16] = a[0]; // - assign gfpga_pad_GPIO_Y[0] = 1'b0; - assign gfpga_pad_GPIO_Y[1] = 1'b0; - assign gfpga_pad_GPIO_Y[2] = 1'b0; - assign gfpga_pad_GPIO_Y[3] = 1'b0; - assign gfpga_pad_GPIO_Y[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[6] = b[0]; + +// + assign out:c_fpga[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[9]; + +// + assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[9] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[17] = 1'b0; + + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[6] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[16] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[17] = 1'b0; `ifdef AUTOCHECKED_SIMULATION // @@ -206,17 +235,10 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b0); - prog_cycle_task(1'b1); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -231,9 +253,8 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -245,6 +266,7 @@ initial prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); + prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b0); @@ -319,80 +341,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b1); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b1); - prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b1); prog_cycle_task(1'b0); @@ -419,30 +367,15 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -808,22 +741,18 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -884,10 +813,10 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1086,6 +1015,47 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1188,6 +1158,7 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -1240,32 +1211,8 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -2016,10 +1963,6 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -2045,6 +1988,38 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -2138,6 +2113,67 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); @@ -2195,6 +2231,96 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); @(negedge prog_clock[0]); config_done[0] <= 1'b1; end @@ -2260,7 +2386,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // - #20121 + #21092 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v index 0a9714c..745bf34 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v @@ -53,7 +53,7 @@ module top_top_formal_verification_random_tb; initial begin clk[0] <= 1'b0; while(1) begin - #0.4159859701 + #0.5203860242 clk[0] <= !clk[0]; end end @@ -112,7 +112,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // - #332 + #416 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v index a68418f..e4ba114 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v @@ -17,10 +17,9 @@ output [0:0] out:c_fm); wire [0:0] prog_clk; wire [0:0] Test_en; wire [0:0] clk; -wire [0:7] gfpga_pad_GPIO_Y; -wire [0:7] gfpga_pad_GPIO_A; -wire [0:7] gfpga_pad_GPIO_IE; -wire [0:7] gfpga_pad_GPIO_OE; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR; wire [0:0] ccff_head; wire [0:0] ccff_tail; @@ -29,10 +28,9 @@ wire [0:0] ccff_tail; .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), - .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0:7]), - .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0:7]), - .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0:7]), - .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0:7]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:17]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:17]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:17]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0])); @@ -43,18 +41,49 @@ wire [0:0] ccff_tail; // // - assign gfpga_pad_GPIO_Y[4] = a_fm[0]; -// - assign gfpga_pad_GPIO_Y[6] = b_fm[0]; -// - assign out:c_fm[0] = gfpga_pad_GPIO_Y[5]; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[16] = a_fm[0]; // - assign gfpga_pad_GPIO_Y[0] = 1'b0; - assign gfpga_pad_GPIO_Y[1] = 1'b0; - assign gfpga_pad_GPIO_Y[2] = 1'b0; - assign gfpga_pad_GPIO_Y[3] = 1'b0; - assign gfpga_pad_GPIO_Y[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[6] = b_fm[0]; + +// + assign out:c_fm[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[9]; + +// + assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[9] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[17] = 1'b0; + + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[6] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[16] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[17] = 1'b0; // `ifdef ICARUS_SIMULATOR @@ -94,7 +123,7 @@ wire [0:0] ccff_tail; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = 17'b00000000110000001; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = 17'b00000000100010001; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = 2'b01; @@ -219,32 +248,44 @@ wire [0:0] ccff_tail; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b0; - assign U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b0; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; assign U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b1}}; assign U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2] = 3'b010; - assign U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2] = {3{1'b1}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2] = 3'b110; + assign U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2] = 3'b001; + assign U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1] = {2{1'b1}}; assign U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_right_track_26.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_28.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_30.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_32.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_34.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_top_track_4.mem_out[0:2] = {3{1'b0}}; @@ -253,7 +294,7 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_0__1_.mem_top_track_24.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_top_track_32.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2] = 3'b100; assign U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:2] = {3{1'b0}}; @@ -266,22 +307,43 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_0__1_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_right_track_24.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_right_track_26.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2] = 3'b010; + assign U0_formal_verification.sb_0__1_.mem_right_track_28.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_30.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_32.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_34.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_36.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2] = 3'b110; assign U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_6.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_0__2_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_10.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_12.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__2_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_26.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_28.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_30.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_32.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_34.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_36.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_38.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3] = 4'b0010; assign U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:2] = {3{1'b0}}; @@ -291,26 +353,21 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b1}}; assign U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_28.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_30.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_32.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_34.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_36.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_top_track_38.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:3] = 4'b0010; + assign U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_right_track_2.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_right_track_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_right_track_16.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_right_track_24.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_right_track_32.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__0_.mem_left_track_33.mem_out[0:2] = {3{1'b0}}; @@ -328,7 +385,7 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_1__1_.mem_right_track_16.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__1_.mem_right_track_24.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__1_.mem_right_track_32.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3] = 4'b0110; assign U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:4] = {5{1'b0}}; assign U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:3] = {4{1'b0}}; @@ -341,14 +398,14 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2] = 3'b001; + assign U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_right_track_24.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_out[0:2] = {3{1'b0}}; @@ -363,16 +420,10 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_29.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_31.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_33.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_35.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_37.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_39.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_left_track_17.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_left_track_25.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_1__2_.mem_left_track_33.mem_out[0:2] = {3{1'b0}}; @@ -390,12 +441,6 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_2__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_top_track_26.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_28.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_30.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_32.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_34.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_36.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_38.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_5.mem_out[0:2] = {3{1'b0}}; @@ -406,10 +451,12 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_2__0_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__0_.mem_left_track_27.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_29.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_31.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_33.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_35.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_2__1_.mem_top_track_2.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.sb_2__1_.mem_top_track_4.mem_out[0:3] = {4{1'b0}}; @@ -437,6 +484,12 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_2__1_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__1_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__1_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_29.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_31.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_33.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_35.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_37.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_39.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_out[0:2] = {3{1'b0}}; @@ -452,88 +505,106 @@ wire [0:0] ccff_tail; assign U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_31.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_33.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_35.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_37.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_39.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_7.mem_out[0:2] = {3{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_13.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_2__2_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_12.mem_out[0:3] = {4{1'b1}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_13.mem_out[0:3] = {4{1'b1}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_27.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_29.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_31.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_33.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_35.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_37.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_39.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:3] = 4'b1101; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_15.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3] = {4{1'b1}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_0__2_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; @@ -546,11 +617,10 @@ wire [0:0] ccff_tail; assign U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3] = {4{1'b1}}; assign U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3] = 4'b0111; assign U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; @@ -637,7 +707,7 @@ initial begin force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = 17'b11111111001111110; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = 17'b11111111011101110; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = 2'b10; @@ -762,32 +832,44 @@ initial begin force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b1; - force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2] = 3'b101; - force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2] = {3{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:2] = 3'b001; + force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2] = 3'b110; + force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_26.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_28.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_30.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_32.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_34.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_top_track_4.mem_outb[0:2] = {3{1'b1}}; @@ -796,7 +878,7 @@ initial begin force U0_formal_verification.sb_0__1_.mem_top_track_24.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_top_track_32.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:2] = 3'b011; force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_outb[0:2] = {3{1'b1}}; @@ -809,22 +891,43 @@ initial begin force U0_formal_verification.sb_0__1_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_24.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_26.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2] = 3'b101; + force U0_formal_verification.sb_0__1_.mem_right_track_28.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_30.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_32.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_34.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_36.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:2] = 3'b001; force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_6.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__2_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__2_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_26.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_28.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_30.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_32.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_34.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_36.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_38.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:3] = 4'b1101; force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:2] = {3{1'b1}}; @@ -834,26 +937,21 @@ initial begin force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_28.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_30.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_32.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_34.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_36.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_38.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_right_track_0.mem_outb[0:3] = 4'b1101; + force U0_formal_verification.sb_1__0_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_right_track_2.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__0_.mem_right_track_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_right_track_8.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_right_track_16.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_right_track_24.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_right_track_32.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_left_track_25.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_left_track_33.mem_outb[0:2] = {3{1'b1}}; @@ -871,7 +969,7 @@ initial begin force U0_formal_verification.sb_1__1_.mem_right_track_16.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__1_.mem_right_track_24.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__1_.mem_right_track_32.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:3] = 4'b1001; force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_outb[0:4] = {5{1'b1}}; force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}}; @@ -884,14 +982,14 @@ initial begin force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_33.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_33.mem_outb[0:2] = 3'b110; + force U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_right_track_24.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_32.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_32.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_outb[0:2] = {3{1'b1}}; @@ -906,16 +1004,10 @@ initial begin force U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_29.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_31.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_33.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_35.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_37.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_39.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_5.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_9.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__2_.mem_left_track_17.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_left_track_25.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__2_.mem_left_track_33.mem_outb[0:2] = {3{1'b1}}; @@ -933,12 +1025,6 @@ initial begin force U0_formal_verification.sb_2__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_top_track_26.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_28.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_30.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_32.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_34.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_36.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_38.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_5.mem_outb[0:2] = {3{1'b1}}; @@ -949,10 +1035,12 @@ initial begin force U0_formal_verification.sb_2__0_.mem_left_track_15.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_left_track_27.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_29.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_31.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_33.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_35.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__1_.mem_top_track_2.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__1_.mem_top_track_4.mem_outb[0:3] = {4{1'b1}}; @@ -980,6 +1068,12 @@ initial begin force U0_formal_verification.sb_2__1_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__1_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__1_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_29.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_31.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_33.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_35.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_37.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_39.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_outb[0:2] = {3{1'b1}}; @@ -995,88 +1089,106 @@ initial begin force U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_31.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_33.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_35.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_37.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_39.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_7.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_13.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_15.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__2_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_12.mem_outb[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_13.mem_outb[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_27.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_29.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_31.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_33.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_35.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_37.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_39.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_outb[0:3] = 4'b0010; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_15.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b0}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_0__2_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_outb[0:3] = {4{1'b1}}; @@ -1089,11 +1201,10 @@ initial begin force U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_outb[0:3] = {4{1'b0}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_outb[0:3] = 4'b1000; force U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_outb[0:3] = {4{1'b1}}; @@ -1219,8 +1330,8 @@ initial begin $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], 17'b00000000110000001); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], 17'b11111111001111110); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], 17'b00000000100010001); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], 17'b11111111011101110); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); @@ -1469,42 +1580,62 @@ initial begin $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); - $deposit(U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); - $deposit(U0_formal_verification.grid_io_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); - $deposit(U0_formal_verification.grid_io_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); - $deposit(U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); - $deposit(U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b0); - $deposit(U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b1); - $deposit(U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); - $deposit(U0_formal_verification.grid_io_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_24.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2], 3'b010); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2], 3'b101); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2], 3'b110); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:2], 3'b001); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2], 3'b001); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2], 3'b110); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_6.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_8.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_12.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:1], {2{1'b0}}); @@ -1513,14 +1644,18 @@ initial begin $deposit(U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_26.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_28.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_28.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_30.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_30.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_32.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_34.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_34.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); @@ -1537,8 +1672,8 @@ initial begin $deposit(U0_formal_verification.sb_0__1_.mem_top_track_32.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2], 3'b100); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:2], 3'b011); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); @@ -1563,28 +1698,70 @@ initial begin $deposit(U0_formal_verification.sb_0__1_.mem_right_track_24.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_26.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2], 3'b010); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2], 3'b101); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_28.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_28.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_30.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_30.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_32.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_34.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_34.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_36.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_36.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2], 3'b110); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:2], 3'b001); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_2.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_6.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_8.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_8.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_10.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_10.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_12.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_12.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_14.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_14.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_16.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_16.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_18.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_18.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_20.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_20.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_22.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_22.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_24.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_24.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_26.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_28.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_28.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_30.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_30.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_32.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_34.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_34.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_36.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_36.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_38.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_38.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_out[0:1], {2{1'b0}}); @@ -1593,8 +1770,8 @@ initial begin $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3], 4'b0010); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:3], 4'b1101); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:2], {3{1'b0}}); @@ -1613,32 +1790,22 @@ initial begin $deposit(U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_24.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_28.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_28.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_30.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_30.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_32.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_32.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_34.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_34.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_36.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_36.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_38.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_38.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:3], 4'b0010); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_outb[0:3], 4'b1101); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_2.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_4.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_4.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_16.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_16.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); @@ -1647,12 +1814,12 @@ initial begin $deposit(U0_formal_verification.sb_1__0_.mem_right_track_32.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_1.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_5.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_17.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:2], {3{1'b0}}); @@ -1687,8 +1854,8 @@ initial begin $deposit(U0_formal_verification.sb_1__1_.mem_right_track_24.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_right_track_32.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__1_.mem_right_track_32.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3], 4'b0110); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:3], 4'b1001); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:4], {5{1'b0}}); @@ -1713,22 +1880,22 @@ initial begin $deposit(U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2], 3'b001); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_outb[0:2], 3'b110); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_24.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); @@ -1757,26 +1924,14 @@ initial begin $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_29.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_29.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_31.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_31.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_33.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_33.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_35.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_35.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_37.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_37.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_39.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_39.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_outb[0:2], {3{1'b1}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_17.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_17.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_25.mem_out[0:2], {3{1'b0}}); @@ -1811,18 +1966,6 @@ initial begin $deposit(U0_formal_verification.sb_2__0_.mem_top_track_24.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_26.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_26.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_28.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_28.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_30.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_30.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_32.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_32.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_34.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_34.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_36.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_36.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_38.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_38.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); @@ -1843,14 +1986,18 @@ initial begin $deposit(U0_formal_verification.sb_2__0_.mem_left_track_17.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_19.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_19.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_21.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_21.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_23.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_23.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_25.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_27.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_27.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_29.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_29.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_31.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_31.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_33.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_33.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_35.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_35.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_2.mem_out[0:3], {4{1'b0}}); @@ -1905,6 +2052,18 @@ initial begin $deposit(U0_formal_verification.sb_2__1_.mem_left_track_23.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_25.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_29.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_29.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_31.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_31.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_33.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_33.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_35.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_35.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_37.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_37.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_39.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_39.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); @@ -1935,170 +2094,206 @@ initial begin $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_31.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_31.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_33.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_33.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_35.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_35.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_37.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_37.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_39.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_39.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_7.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_7.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_11.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_11.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_13.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_13.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_15.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_15.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_17.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_17.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_19.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_19.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_21.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_21.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_23.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_23.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_25.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_3.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_4.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_5.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_6.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_7.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_8.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_9.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_10.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_11.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_12.mem_out[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_12.mem_outb[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_13.mem_out[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_13.mem_outb[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_14.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_27.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_27.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_29.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_29.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_31.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_31.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_33.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_33.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_35.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_35.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_37.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_37.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_39.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_39.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_8.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_9.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_10.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_11.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_12.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_13.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_14.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:3], 4'b1101); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_outb[0:3], 4'b0010); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_5.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_6.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_7.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_8.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_9.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_10.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_11.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_12.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_13.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_14.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_15.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_1.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_6.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_7.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_8.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_9.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_10.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_11.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_12.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_13.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_14.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_0__2_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_0__2_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); @@ -2123,16 +2318,14 @@ initial begin $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_outb[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3], 4'b0111); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_outb[0:3], 4'b1000); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_outb[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_1__2_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit index 546bf36..3763705 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit @@ -1 +1 @@ -00000000000000000000000011111010000000001000000000000111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000001111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 +000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010001000001000000000000000000000000000000000000000000000000001111000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100100000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000000000110111111000001100001000000000001100000000000000000000 diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml index 5a19e13..220b379 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml @@ -2,4026 +2,4220 @@ - Fabric bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Tue Oct 27 00:35:00 2020 + - Date: Fri Nov 6 14:45:09 2020 --> - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - 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-11088,13 +11951,13 @@ - + - - - - - + + + + + @@ -11112,8 +11975,6 @@ - - @@ -11132,23 +11993,23 @@ - - + + - + - + - + - - - + + + @@ -11166,6 +12027,8 @@ + + @@ -11179,34 +12042,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -11250,8 +12085,6 @@ - - @@ -11304,6 +12137,8 @@ + + @@ -11358,8 +12193,6 @@ - - @@ -11410,8 +12243,10 @@ - + + + @@ -11466,8 +12301,6 @@ - - @@ -11518,8 +12351,10 @@ - + + + @@ -11574,8 +12409,6 @@ - - @@ -11628,6 +12461,8 @@ + + @@ -11712,8 +12547,6 @@ - - @@ -11766,6 +12599,8 @@ + + @@ -11820,8 +12655,6 @@ - - @@ -11874,6 +12707,8 @@ + + @@ -11928,8 +12763,6 @@ - - @@ -11982,6 +12815,8 @@ + + @@ -12036,8 +12871,6 @@ - - @@ -12090,6 +12923,8 @@ + + @@ -12174,8 +13009,6 @@ - - @@ -12228,6 +13061,8 @@ + + @@ -12282,8 +13117,6 @@ - - @@ -12336,6 +13169,8 @@ + + @@ -12390,8 +13225,6 @@ - - @@ -12444,6 +13277,8 @@ + + @@ -12498,8 +13333,6 @@ - - @@ -12552,6 +13385,8 @@ + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log index 365b894..8da0c6f 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log @@ -41,9 +41,9 @@ THE SOFTWARE. Command line to execute: vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off VPR FPGA Placement and Routing. -Version: 0.0.0+48b2bff0 -Revision: 48b2bff0 -Compiled: 2020-09-27T20:43:27 +Version: 0.0.0+55f7a2c1 +Revision: 55f7a2c1 +Compiled: 2020-11-05T12:41:40 Compiler: GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64 Build Info: release VTR_ASSERT_LEVEL=2 @@ -65,35 +65,27 @@ Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) -# Loading Architecture Description took 0.00 seconds (max_rss 8.8 MiB, delta_rss +0.4 MiB) +# Loading Architecture Description took 0.00 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB) # Building complex block graph -Warning 6: [LINE 546] false logically-equivalent pin clb[0].I0[1]. -Warning 7: [LINE 546] false logically-equivalent pin clb[0].I0[2]. -Warning 8: [LINE 546] false logically-equivalent pin clb[0].I0[3]. -Warning 9: [LINE 548] false logically-equivalent pin clb[0].I1[1]. -Warning 10: [LINE 548] false logically-equivalent pin clb[0].I1[2]. -Warning 11: [LINE 548] false logically-equivalent pin clb[0].I1[3]. -Warning 12: [LINE 550] false logically-equivalent pin clb[0].I2[1]. -Warning 13: [LINE 550] false logically-equivalent pin clb[0].I2[2]. -Warning 14: [LINE 550] false logically-equivalent pin clb[0].I2[3]. -Warning 15: [LINE 552] false logically-equivalent pin clb[0].I3[1]. -Warning 16: [LINE 552] false logically-equivalent pin clb[0].I3[2]. -Warning 17: [LINE 552] false logically-equivalent pin clb[0].I3[3]. -Warning 18: [LINE 554] false logically-equivalent pin clb[0].I4[1]. -Warning 19: [LINE 554] false logically-equivalent pin clb[0].I4[2]. -Warning 20: [LINE 554] false logically-equivalent pin clb[0].I4[3]. -Warning 21: [LINE 556] false logically-equivalent pin clb[0].I5[1]. -Warning 22: [LINE 556] false logically-equivalent pin clb[0].I5[2]. -Warning 23: [LINE 556] false logically-equivalent pin clb[0].I5[3]. -Warning 24: [LINE 558] false logically-equivalent pin clb[0].I6[1]. -Warning 25: [LINE 558] false logically-equivalent pin clb[0].I6[2]. -Warning 26: [LINE 558] false logically-equivalent pin clb[0].I6[3]. -Warning 27: [LINE 560] false logically-equivalent pin clb[0].I7[1]. -Warning 28: [LINE 560] false logically-equivalent pin clb[0].I7[2]. -Warning 29: [LINE 560] false logically-equivalent pin clb[0].I7[3]. -# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.8 MiB) +Warning 6: [LINE 582] false logically-equivalent pin clb[0].I0[1]. +Warning 7: [LINE 582] false logically-equivalent pin clb[0].I0[2]. +Warning 8: [LINE 588] false logically-equivalent pin clb[0].I1[1]. +Warning 9: [LINE 588] false logically-equivalent pin clb[0].I1[2]. +Warning 10: [LINE 594] false logically-equivalent pin clb[0].I2[1]. +Warning 11: [LINE 594] false logically-equivalent pin clb[0].I2[2]. +Warning 12: [LINE 600] false logically-equivalent pin clb[0].I3[1]. +Warning 13: [LINE 600] false logically-equivalent pin clb[0].I3[2]. +Warning 14: [LINE 606] false logically-equivalent pin clb[0].I4[1]. +Warning 15: [LINE 606] false logically-equivalent pin clb[0].I4[2]. +Warning 16: [LINE 612] false logically-equivalent pin clb[0].I5[1]. +Warning 17: [LINE 612] false logically-equivalent pin clb[0].I5[2]. +Warning 18: [LINE 618] false logically-equivalent pin clb[0].I6[1]. +Warning 19: [LINE 618] false logically-equivalent pin clb[0].I6[2]. +Warning 20: [LINE 624] false logically-equivalent pin clb[0].I7[1]. +Warning 21: [LINE 624] false logically-equivalent pin clb[0].I7[2]. +# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB) # Load circuit -# Load circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.3 MiB) +# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB) # Clean circuit Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs Inferred 0 additional primitive pins as constant generators due to constant inputs @@ -102,11 +94,11 @@ Swept output(s) : 0 (0 dangling, 0 constant) Swept net(s) : 0 Swept block(s) : 0 Constant Pins Marked: 0 -# Clean circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +# Clean circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) # Compress circuit -# Compress circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +# Compress circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) # Verify circuit -# Verify circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +# Verify circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) Circuit Statistics: Blocks: 4 .input : 2 @@ -121,7 +113,7 @@ Circuit Statistics: Timing Graph Nodes: 6 Timing Graph Edges: 5 Timing Graph Levels: 4 -# Build Timing Graph took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +# Build Timing Graph took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) Netlist contains 0 clocks # Load Timing Constraints @@ -132,7 +124,7 @@ Setting default timing constraints: Timing constraints created 1 clocks Constrained Clock 'virtual_io_clock' (Virtual Clock) -# Load Timing Constraints took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +# Load Timing Constraints took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) Timing analysis: ON Circuit netlist file: top.net Circuit placement file: top.place @@ -201,6 +193,10 @@ RoutingArch.switch_block_type: WILTON RoutingArch.Fs: 3 # Packing +Warning 22: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 23: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 24: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 25: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. Begin packing 'top.blif'. After removing unused inputs... @@ -208,8 +204,12 @@ After removing unused inputs... Begin prepacking. Finish prepacking. Using inter-cluster delay: 1.33777e-09 -Packing with pin utilization targets: io:1,1 clb:0.8,1 -Packing with high fanout thresholds: io:128 clb:32 +Packing with pin utilization targets: io_top:1,1 io_right:1,1 io_bottom:1,1 io_left:1,1 clb:0.8,1 +Packing with high fanout thresholds: io_top:128 io_right:128 io_bottom:128 io_left:128 clb:32 +Warning 26: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 27: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 28: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 29: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. Not enough resources expand FPGA size to (4 x 4) Complex block 0: 'c' (clb) . Complex block 1: 'out:c' (io) . @@ -238,23 +238,27 @@ Logic Element (fle) detailed count: io: # blocks: 3, average # input + clock pins used: 0.333333, average # output pins used: 0.666667 clb: # blocks: 1, average # input + clock pins used: 2, average # output pins used: 1 Absorbed logical nets 0 out of 3 nets, 3 nets not absorbed. +Warning 30: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 31: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 32: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 33: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. FPGA sized to 4 x 4 (2x2) Device Utilization: 0.25 (target 1.00) - Block Utilization: 0.38 Type: io + Block Utilization: 0.17 Type: io Block Utilization: 0.25 Type: clb Netlist conversion complete. -# Packing took 0.01 seconds (max_rss 10.5 MiB, delta_rss +0.7 MiB) +# Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB) # Load Packing Begin loading packed FPGA netlist file. Netlist generated from file 'top.net'. Detected 0 constant generators (to see names run with higher pack verbosity) -Finished loading packed FPGA netlist file (took 0.02 seconds). -Warning 30: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). +Finished loading packed FPGA netlist file (took 0.01 seconds). +Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). # Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB) -Warning 31: Netlist contains 0 global net to non-global architecture pin connections +Warning 35: Netlist contains 0 global net to non-global architecture pin connections Netlist num_nets: 3 Netlist num_blocks: 4 @@ -266,237 +270,219 @@ Netlist output pins: 1 # Create Device ## Build Device Grid +Warning 36: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 37: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 38: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 39: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. FPGA sized to 4 x 4: 16 grid tiles (2x2) Resource usage... Netlist 3 blocks of type: io Architecture - 8 blocks of type: io + 2 blocks of type: io_top + 2 blocks of type: io_right + 12 blocks of type: io_bottom + 2 blocks of type: io_left Netlist 1 blocks of type: clb Architecture 4 blocks of type: clb Device Utilization: 0.25 (target 1.00) - Physical Tile io: - Block Utilization: 0.38 Logical Block: io + Physical Tile io_top: + Block Utilization: 1.50 Logical Block: io + Physical Tile io_right: + Block Utilization: 1.50 Logical Block: io + Physical Tile io_bottom: + Block Utilization: 0.25 Logical Block: io + Physical Tile io_left: + Block Utilization: 1.50 Logical Block: io Physical Tile clb: Block Utilization: 0.25 Logical Block: clb -## Build Device Grid took 0.00 seconds (max_rss 10.6 MiB, delta_rss +0.0 MiB) +## Build Device Grid took 0.00 seconds (max_rss 10.7 MiB, delta_rss +0.0 MiB) ## Build tileable routing resource graph X-direction routing channel width is 40 Y-direction routing channel width is 40 -Warning 32: in check_rr_node: RR node: 57 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 33: in check_rr_node: RR node: 58 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. -Warning 34: in check_rr_node: RR node: 139 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 35: in check_rr_node: RR node: 140 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. -Warning 36: in check_rr_graph: fringe node 452 CHANX at (1,1) has no fanin. - This is possible on a fringe node based on low Fc_out, N, and certain lengths. -## Build tileable routing resource graph took 0.00 seconds (max_rss 11.1 MiB, delta_rss +0.5 MiB) - RR Graph Nodes: 684 - RR Graph Edges: 2780 -# Create Device took 0.01 seconds (max_rss 11.1 MiB, delta_rss +0.5 MiB) +Warning 40: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 41: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 42: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 43: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +## Build tileable routing resource graph took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB) + RR Graph Nodes: 756 + RR Graph Edges: 2930 +# Create Device took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB) # Placement ## Computing placement delta delay look-up ### Build routing resource graph -Warning 37: in check_rr_node: RR node: 109 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 38: in check_rr_node: RR node: 110 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. -Warning 39: in check_rr_node: RR node: 293 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 40: in check_rr_node: RR node: 294 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. -Warning 41: in check_rr_graph: fringe node 2 IPIN at (0,1) has no fanin. - This is possible on a fringe node based on low Fc_out, N, and certain lengths. -### Build routing resource graph took 0.00 seconds (max_rss 11.1 MiB, delta_rss +0.0 MiB) - RR Graph Nodes: 732 - RR Graph Edges: 2188 +Warning 44: in check_rr_node: RR node: 119 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 45: in check_rr_node: RR node: 120 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 46: in check_rr_node: RR node: 327 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 47: in check_rr_node: RR node: 328 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +### Build routing resource graph took 0.00 seconds (max_rss 11.2 MiB, delta_rss +0.0 MiB) + RR Graph Nodes: 756 + RR Graph Edges: 2428 ### Computing delta delays -### Computing delta delays took 0.00 seconds (max_rss 11.4 MiB, delta_rss +0.3 MiB) -## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.4 MiB, delta_rss +0.3 MiB) +### Computing delta delays took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.0 MiB) +## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.3 MiB) There are 3 point to point connections in this circuit. -BB estimate of min-dist (placement) wire length: 11 +BB estimate of min-dist (placement) wire length: 10 Completed placement consistency check successfully. -Initial placement cost: 1 bb_cost: 0.275 td_cost: 5.6541e-10 -Initial placement estimated Critical Path Delay (CPD): 0.69331 ns -Initial placement estimated setup Total Negative Slack (sTNS): -0.69331 ns -Initial placement estimated setup Worst Negative Slack (sWNS): -0.69331 ns +Initial placement cost: 1 bb_cost: 0.25 td_cost: 6.04709e-10 +Initial placement estimated Critical Path Delay (CPD): 0.80931 ns +Initial placement estimated setup Total Negative Slack (sTNS): -0.80931 ns +Initial placement estimated setup Worst Negative Slack (sWNS): -0.80931 ns Initial placement estimated setup slack histogram: -[ -6.9e-10: -6.9e-10) 1 (100.0%) |************************************************** -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 1 (100.0%) |************************************************** +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | +[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | Placement contains 0 placement macros involving 0 blocks (average macro size -nan) ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ T Av Cost Av BB Cost Av TD Cost CPD sTNS sWNS Ac Rate Std Dev R lim Crit Exp Tot Moves Alpha ------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ -5.6e-01 0.892 0.21 5.1708e-10 0.693 -0.693 -0.693 1.000 0.0754 3.0 1.00 6 0.500 -2.8e-01 1.001 0.25 5.8474e-10 0.693 -0.693 -0.693 1.000 0.1044 3.0 1.00 12 0.500 -1.4e-01 0.828 0.19 5.1901e-10 0.751 -0.751 -0.751 0.833 0.0971 3.0 1.00 18 0.900 -1.3e-01 1.119 0.21 5.3388e-10 0.693 -0.693 -0.693 0.500 0.0412 3.0 1.00 24 0.950 -1.2e-01 1.017 0.24 5.3998e-10 0.693 -0.693 -0.693 0.833 0.0366 3.0 1.00 30 0.900 -1.1e-01 0.960 0.24 5.3641e-10 0.693 -0.693 -0.693 1.000 0.0433 3.0 1.00 36 0.500 -5.4e-02 0.970 0.21 4.9164e-10 0.693 -0.693 -0.693 0.667 0.0405 3.0 1.00 42 0.950 -5.1e-02 0.974 0.19 4.4803e-10 0.635 -0.635 -0.635 0.667 0.0470 3.0 1.00 48 0.950 -4.9e-02 0.999 0.18 4.3485e-10 0.635 -0.635 -0.635 0.333 0.0019 3.0 1.00 54 0.950 -4.6e-02 1.063 0.19 4.5701e-10 0.635 -0.635 -0.635 0.500 0.0549 2.7 2.12 60 0.950 -4.4e-02 1.019 0.21 4.9794e-10 0.693 -0.693 -0.693 0.667 0.0458 2.8 1.56 66 0.950 -4.2e-02 1.043 0.21 5.1943e-10 0.693 -0.693 -0.693 0.667 0.0215 3.0 1.00 72 0.950 -4.0e-02 0.903 0.18 4.7533e-10 0.751 -0.751 -0.751 0.500 0.0052 3.0 1.00 78 0.950 -3.8e-02 1.042 0.20 4.4941e-10 0.693 -0.693 -0.693 0.333 0.0000 3.0 1.00 84 0.950 -3.6e-02 1.000 0.20 4.2544e-10 0.635 -0.635 -0.635 0.167 0.0000 2.7 2.12 90 0.950 -3.4e-02 1.069 0.22 4.4576e-10 0.635 -0.635 -0.635 0.667 0.0458 1.9 4.68 96 0.950 -3.2e-02 0.969 0.21 4.6916e-10 0.693 -0.693 -0.693 0.667 0.0361 2.4 3.14 102 0.950 -3.1e-02 0.968 0.19 4.7066e-10 0.693 -0.693 -0.693 0.500 0.0537 2.9 1.24 108 0.950 -2.9e-02 0.997 0.18 4.322e-10 0.635 -0.635 -0.635 0.500 0.0000 3.0 1.00 114 0.950 -2.8e-02 0.999 0.18 4.3485e-10 0.635 -0.635 -0.635 0.333 0.0019 3.0 1.00 120 0.950 -2.6e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 2.7 2.12 126 0.950 -2.5e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 2.8 1.56 132 0.950 -2.4e-02 0.994 0.18 4.0763e-10 0.635 -0.635 -0.635 0.167 0.0000 2.5 2.62 138 0.950 -2.3e-02 0.996 0.18 3.9202e-10 0.635 -0.635 -0.635 0.500 0.0064 1.8 5.05 144 0.950 -2.1e-02 1.000 0.18 4.0247e-10 0.635 -0.635 -0.635 0.333 0.0000 2.0 4.66 150 0.950 -2.0e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.7 5.39 156 0.950 -1.9e-02 1.071 0.20 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.3 7.06 162 0.950 -1.8e-02 0.967 0.18 5.0741e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 6.79 168 0.950 -1.7e-02 0.985 0.18 4.7841e-10 0.693 -0.693 -0.693 0.333 0.0205 1.0 8.00 174 0.950 -1.7e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.0 8.00 180 0.950 -1.6e-02 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 186 0.950 -1.5e-02 0.989 0.18 3.5797e-10 0.635 -0.635 -0.635 0.667 0.0076 1.1 7.79 192 0.950 -1.4e-02 1.000 0.18 3.8602e-10 0.635 -0.635 -0.635 0.667 0.0000 1.3 6.95 198 0.950 -1.3e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.6 5.92 204 0.950 -1.3e-02 0.991 0.18 3.7094e-10 0.635 -0.635 -0.635 0.500 0.0078 1.4 6.51 210 0.950 -1.2e-02 0.995 0.18 3.809e-10 0.635 -0.635 -0.635 0.333 0.0113 1.5 6.21 216 0.950 -1.2e-02 1.000 0.18 4.1466e-10 0.693 -0.693 -0.693 0.167 0.0000 1.3 6.78 222 0.950 -1.1e-02 0.971 0.18 3.491e-10 0.693 -0.693 -0.693 0.500 0.0000 1.0 8.00 228 0.950 -1.0e-02 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.79 234 0.950 -9.9e-03 1.015 0.18 4.086e-10 0.635 -0.635 -0.635 0.333 0.0205 1.0 8.00 240 0.950 -9.4e-03 0.985 0.18 4.7841e-10 0.693 -0.693 -0.693 0.333 0.0205 1.0 8.00 246 0.950 -9.0e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.667 0.0000 1.0 8.00 252 0.950 -8.5e-03 1.000 0.18 3.8439e-10 0.635 -0.635 -0.635 0.333 0.0000 1.2 7.21 258 0.950 -8.1e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.66 264 0.950 -7.7e-03 1.000 0.18 3.8297e-10 0.635 -0.635 -0.635 0.167 0.0000 1.2 7.43 270 0.950 -7.3e-03 0.992 0.18 3.6408e-10 0.635 -0.635 -0.635 0.667 0.0090 1.0 8.00 276 0.950 -6.9e-03 1.000 0.18 3.8439e-10 0.635 -0.635 -0.635 0.500 0.0000 1.2 7.21 282 0.950 -6.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.3 6.95 288 0.950 -6.3e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.4 6.68 294 0.950 -5.9e-03 1.000 0.18 3.8973e-10 0.635 -0.635 -0.635 0.500 0.0000 1.5 6.39 300 0.950 -5.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.5 6.08 306 0.950 -5.4e-03 0.995 0.18 3.788e-10 0.635 -0.635 -0.635 0.500 0.0079 1.4 6.66 312 0.950 -5.1e-03 1.000 0.18 3.8986e-10 0.635 -0.635 -0.635 0.167 0.0000 1.5 6.37 318 0.950 -4.8e-03 1.000 0.18 3.8095e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.77 324 0.950 -4.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.55 330 0.950 -4.4e-03 0.995 0.18 3.7402e-10 0.635 -0.635 -0.635 0.500 0.0084 1.2 7.31 336 0.950 -4.1e-03 0.986 0.18 3.5684e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 7.06 342 0.950 -3.9e-03 0.984 0.18 3.4857e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 348 0.950 -3.7e-03 0.985 0.18 3.5034e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.79 354 0.950 -3.6e-03 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 360 0.950 -3.4e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 366 0.950 -3.2e-03 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.79 372 0.950 -3.0e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.57 378 0.950 -2.9e-03 0.995 0.18 3.7386e-10 0.635 -0.635 -0.635 0.500 0.0084 1.2 7.33 384 0.950 -2.8e-03 0.990 0.18 3.6614e-10 0.635 -0.635 -0.635 0.500 0.0082 1.3 7.08 390 0.950 -2.6e-03 1.000 0.18 3.8688e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 6.82 396 0.950 -2.5e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 402 0.950 -2.4e-03 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.000 0.0000 1.1 7.79 408 0.950 -2.2e-03 0.984 0.18 3.4857e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 414 0.950 -2.1e-03 0.995 0.18 3.7067e-10 0.635 -0.635 -0.635 0.500 0.0088 1.1 7.79 420 0.950 -2.0e-03 0.985 0.18 3.5227e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.57 426 0.950 -1.9e-03 0.992 0.18 3.6418e-10 0.635 -0.635 -0.635 0.333 0.0110 1.0 7.99 432 0.950 -1.8e-03 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 438 0.950 -1.7e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 444 0.950 -1.7e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.0 8.00 450 0.000 +9.2e-01 0.857 0.21 4.9164e-10 0.693 -0.693 -0.693 0.667 0.0425 3.0 1.00 6 0.950 +8.8e-01 1.031 0.22 5.2788e-10 0.693 -0.693 -0.693 1.000 0.1248 3.0 1.00 12 0.500 +4.4e-01 0.977 0.20 4.5978e-10 0.693 -0.693 -0.693 1.000 0.0478 3.0 1.00 18 0.500 +2.2e-01 1.296 0.24 6.1181e-10 0.577 -0.577 -0.577 0.833 0.1114 3.0 1.00 24 0.900 +2.0e-01 0.807 0.21 5.1793e-10 0.809 -0.809 -0.809 0.833 0.1585 3.0 1.00 30 0.900 +1.8e-01 1.284 0.23 4.5908e-10 0.577 -0.577 -0.577 1.000 0.1344 3.0 1.00 36 0.500 +8.9e-02 0.981 0.23 4.8318e-10 0.635 -0.635 -0.635 1.000 0.0703 3.0 1.00 42 0.500 +4.4e-02 0.906 0.23 4.617e-10 0.693 -0.693 -0.693 0.833 0.0159 3.0 1.00 48 0.900 +4.0e-02 0.915 0.20 4.3008e-10 0.693 -0.693 -0.693 1.000 0.0692 3.0 1.00 54 0.500 +2.0e-02 1.000 0.18 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 3.0 1.00 60 0.950 +1.9e-02 1.000 0.18 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 2.7 2.12 66 0.950 +1.8e-02 0.982 0.17 3.9141e-10 0.577 -0.577 -0.577 0.667 0.0357 1.9 4.68 72 0.950 +1.7e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 2.4 3.14 78 0.950 +1.6e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.7 5.42 84 0.950 +1.5e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.3 7.08 90 0.950 +1.5e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.3 6.82 96 0.950 +1.4e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.4 6.54 102 0.950 +1.3e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.3 7.07 108 0.950 +1.3e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.54 114 0.950 +1.2e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.2 7.30 120 0.950 +1.1e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 126 0.800 +9.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 132 0.950 +8.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.79 138 0.950 +8.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.57 144 0.950 +7.8e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 7.99 150 0.950 +7.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 156 0.950 +7.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.667 0.0000 1.1 7.79 162 0.950 +6.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.833 0.0000 1.3 6.95 168 0.900 +6.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.8 5.16 174 0.950 +5.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 7.95 180 0.950 +5.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.0 8.00 186 0.950 +5.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 192 0.950 +4.9e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.1 7.79 198 0.950 +4.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 204 0.950 +4.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 210 0.950 +4.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.79 216 0.950 +4.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.57 222 0.950 +3.8e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.0 7.99 228 0.950 +3.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 234 0.950 +3.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 240 0.950 +3.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 246 0.950 +3.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.79 252 0.950 +2.9e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 258 0.800 +2.3e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 264 0.950 +2.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 270 0.950 +2.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 276 0.800 +1.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 282 0.950 +1.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 288 0.000 -BB estimate of min-dist (placement) wire length: 7 +BB estimate of min-dist (placement) wire length: 6 Completed placement consistency check successfully. -Swaps called: 454 +Swaps called: 292 -Placement estimated critical path delay: 0.63531 ns -Placement estimated setup Total Negative Slack (sTNS): -0.63531 ns -Placement estimated setup Worst Negative Slack (sWNS): -0.63531 ns +Placement estimated critical path delay: 0.57731 ns +Placement estimated setup Total Negative Slack (sTNS): -0.57731 ns +Placement estimated setup Worst Negative Slack (sWNS): -0.57731 ns Placement estimated setup slack histogram: -[ -6.4e-10: -6.4e-10) 1 (100.0%) |************************************************** -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | -[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 1 (100.0%) |************************************************** +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | +[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | -Placement cost: 1, bb_cost: 0.175, td_cost: 4.4941e-10, +Placement cost: 1, bb_cost: 0.15, td_cost: 3.9141e-10, Placement resource usage: - io implemented as io : 3 - clb implemented as clb: 1 + io implemented as io_bottom: 2 + io implemented as io_left : 1 + clb implemented as clb : 1 -Placement number of temperatures: 75 -Placement total # of swap attempts: 454 - Swaps accepted: 208 (45.8 %) - Swaps rejected: 246 (54.2 %) +Placement number of temperatures: 48 +Placement total # of swap attempts: 292 + Swaps accepted: 125 (42.8 %) + Swaps rejected: 167 (57.2 %) Swaps aborted : 0 ( 0.0 %) Aborted Move Reasons: -# Placement took 0.01 seconds (max_rss 11.6 MiB, delta_rss +0.5 MiB) +# Placement took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.5 MiB) # Routing ## Build tileable routing resource graph X-direction routing channel width is 40 Y-direction routing channel width is 40 -Warning 42: in check_rr_node: RR node: 57 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 43: in check_rr_node: RR node: 58 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. -Warning 44: in check_rr_node: RR node: 139 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 45: in check_rr_node: RR node: 140 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. -Warning 46: in check_rr_graph: fringe node 452 CHANX at (1,1) has no fanin. - This is possible on a fringe node based on low Fc_out, N, and certain lengths. -## Build tileable routing resource graph took 0.00 seconds (max_rss 11.6 MiB, delta_rss +0.0 MiB) - RR Graph Nodes: 684 - RR Graph Edges: 2780 +Warning 48: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 49: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 50: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 51: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +## Build tileable routing resource graph took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.0 MiB) + RR Graph Nodes: 756 + RR Graph Edges: 2930 Confirming router algorithm: TIMING_DRIVEN. ---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wirelength CPD sTNS sWNS hTNS hWNS Est Succ (sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter ---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- - 1 0.0 0.0 0 80 3 3 0 ( 0.000%) 6 ( 1.2%) 0.693 -0.6933 -0.693 0.000 0.000 N/A + 1 0.0 0.0 0 203 3 3 1 ( 0.132%) 12 ( 2.5%) 0.867 -0.8673 -0.867 0.000 0.000 N/A + 2 0.0 0.5 0 86 1 1 0 ( 0.000%) 12 ( 2.5%) 0.867 -0.8673 -0.867 0.000 0.000 N/A Restoring best routing -Critical path: 0.69331 ns -Successfully routed after 1 routing iterations. -Router Stats: total_nets_routed: 3 total_connections_routed: 3 total_heap_pushes: 80 total_heap_pops: 45 -# Routing took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.1 MiB) +Critical path: 0.86731 ns +Successfully routed after 2 routing iterations. +Router Stats: total_nets_routed: 4 total_connections_routed: 4 total_heap_pushes: 289 total_heap_pops: 187 +# Routing took 0.01 seconds (max_rss 11.9 MiB, delta_rss +0.2 MiB) Checking to ensure routing is legal... Completed routing consistency check successfully. -Serial number (magic cookie) for the routing is: -11536 +Serial number (magic cookie) for the routing is: -18854 Circuit successfully routed with a channel width factor of 40. -Average number of bends per net: 0.333333 Maximum # of bends: 1 +Average number of bends per net: 2.00000 Maximum # of bends: 3 Number of global nets: 0 Number of routed nets (nonglobal): 3 Wire length results (in units of 1 clb segments)... - Total wirelength: 6, average net length: 2.00000 - Maximum net length: 3 + Total wirelength: 12, average net length: 4.00000 + Maximum net length: 6 Wire length results in terms of physical segments... - Total wiring segments used: 5, average wire segments per net: 1.66667 - Maximum segments used by a net: 2 + Total wiring segments used: 9, average wire segments per net: 3.00000 + Maximum segments used by a net: 4 Total local nets with reserved CLB opins: 0 Routing channel utilization histogram: @@ -510,17 +496,17 @@ Routing channel utilization histogram: [ 0.2: 0.3) 0 ( 0.0%) | [ 0.1: 0.2) 0 ( 0.0%) | [ 0: 0.1) 18 (100.0%) |************************************************ -Maximum routing channel utilization: 0.075 at (1,0) +Maximum routing channel utilization: 0.05 at (1,0) X - Directed channels: j max occ ave occ capacity ---- ------- ------- -------- - 0 3 1.250 40 - 1 0 0.000 40 + 0 2 0.750 40 + 1 2 0.500 40 2 0 0.000 40 Y - Directed channels: i max occ ave occ capacity ---- ------- ------- -------- - 0 1 0.250 40 - 1 0 0.000 40 + 0 2 0.750 40 + 1 3 1.000 40 2 0 0.000 40 Total tracks in x-direction: 120, in y-direction: 120 @@ -530,55 +516,55 @@ Logic area (in minimum width transistor areas, excludes I/Os and empty grid tile Total used logic block area: 53894 Routing area (in minimum width transistor areas)... - Total routing area: 22261.4, per logic tile: 1391.34 + Total routing area: 23072.6, per logic tile: 1442.04 Segment usage by type (index): type utilization ---- ----------- 0 0.0833 - 1 0.0278 - 2 0 + 1 0 + 2 0.0208 Segment usage by length: length utilization ------ ----------- 1 0.0833 - 2 0.0278 - 4 0 + 2 0 + 4 0.0208 Hold Worst Negative Slack (hWNS): 0 ns Hold Total Negative Slack (hTNS): 0 ns Hold slack histogram: -[ 5.5e-10: 5.5e-10) 1 (100.0%) |************************************************** -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | -[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 1 (100.0%) |************************************************** +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | +[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | -Final critical path: 0.69331 ns, Fmax: 1442.36 MHz -Setup Worst Negative Slack (sWNS): -0.69331 ns -Setup Total Negative Slack (sTNS): -0.69331 ns +Final critical path: 0.86731 ns, Fmax: 1152.99 MHz +Setup Worst Negative Slack (sWNS): -0.86731 ns +Setup Total Negative Slack (sTNS): -0.86731 ns Setup slack histogram: -[ -6.9e-10: -6.9e-10) 1 (100.0%) |************************************************** -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 1 (100.0%) |************************************************** +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | +[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | -Timing analysis took 0.000488774 seconds (0.000430824 STA, 5.795e-05 slack) (80 full updates: 78 setup, 0 hold, 2 combined). +Timing analysis took 0.000428495 seconds (0.000379131 STA, 4.9364e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined). VPR suceeded -The entire flow of VPR took 0.08 seconds (max_rss 11.9 MiB) +The entire flow of VPR took 0.09 seconds (max_rss 11.9 MiB) Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml @@ -586,17 +572,16 @@ Confirm selected options when call command 'read_openfpga_arch': --file, -f: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml'... Read OpenFPGA architecture -Warning 47: Automatically set circuit model 'frac_lut4' to be default in its type. -Warning 48: Automatically set circuit model 'sky130_fd_sc_hd__sdfxbp_1' to be default in its type. -Warning 49: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be default in its type. -Warning 50: Automatically set circuit model 'GPIO' to be default in its type. +Warning 52: Automatically set circuit model 'frac_lut4' to be default in its type. +Warning 53: Automatically set circuit model 'sky130_fd_sc_hd__sdfxtp_1' to be default in its type. +Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be default in its type. Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree' port 'sram') Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree_tapbuf' port 'sram') Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'frac_lut4' port 'sram') -Read OpenFPGA architecture took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.3 MiB) +Read OpenFPGA architecture took 0.00 seconds (max_rss 12.0 MiB, delta_rss +0.1 MiB) Check circuit library Checking circuit library passed. -Check circuit library took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) +Check circuit library took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) Found 0 errors when checking configurable memory circuit models! Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml @@ -605,7 +590,7 @@ Confirm selected options when call command 'read_openfpga_simulation_setting': --file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'... Read OpenFPGA simulation settings -Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) +Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges @@ -634,9 +619,9 @@ Check pb_graph annotation for physical nodes and pins passed. Binded 4 routing resource graph switches to circuit models Binded 3 routing segments to circuit models Binded 2 direct connections to circuit models -Annotating rr_node with routed nets...Done with 11 nodes mapping -Annotating previous nodes for rr_node...Warning 51: Override the previous node '89' by previous node '90' for node '37' with in routing context annotation! -Done with 14 nodes mapping +Annotating rr_node with routed nets...Done with 15 nodes mapping +Annotating previous nodes for rr_node...Warning 55: Override the previous node '139' by previous node '137' for node '84' with in routing context annotation! +Done with 18 nodes mapping # Build General Switch Block(GSB) annotation on top of routing resource graph [11%] Backannotated GSB[0][0] [22%] Backannotated GSB[0][1] @@ -648,7 +633,7 @@ Done with 14 nodes mapping [88%] Backannotated GSB[2][1] [100%] Backannotated GSB[2][2] Backannotated 9 General Switch Blocks (GSBs). -# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) +# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) # Sort incoming edges for each routing track output node of General Switch Block(GSB) [11%] Sorted edges for GSB[0][0] [22%] Sorted edges for GSB[0][1] @@ -660,9 +645,9 @@ Backannotated 9 General Switch Blocks (GSBs). [88%] Sorted edges for GSB[2][1] [100%] Sorted edges for GSB[2][2] Sorted edges for 9 General Switch Blocks (GSBs). -# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) +# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) # Build a library of physical multiplexers -Built a multiplexer library of 14 physical multiplexers. +Built a multiplexer library of 15 physical multiplexers. Maximum multiplexer size is 17. # Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB) # Build the annotation about direct connection between tiles @@ -670,8 +655,8 @@ Built 6 tile-to-tile direct connections # Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB) Building annotation for mapped blocks on grid locations...Done User specified the operating clock frequency to use VPR results -Use VPR critical path delay 8.31972e-19 [ns] with a 20 [%] slack in OpenFPGA. -Will apply operating clock frequency 1201.96 [MHz] to simulations +Use VPR critical path delay 1.04077e-18 [ns] with a 20 [%] slack in OpenFPGA. +Will apply operating clock frequency 960.825 [MHz] to simulations User specified the number of operating clock cycles to be inferred from signal activities Average net density: 0.42 Median net density: 0.00 @@ -694,63 +679,65 @@ Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00 Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) Read Fabric Key -Read Fabric Key took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +Read Fabric Key took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) Build fabric module graph # Build constant generator modules -# Build constant generator modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +# Build constant generator modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Build user-defined modules -# Build user-defined modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +# Build user-defined modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Build essential (inverter/buffer/logic gate) modules -# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Build local encoder (for multiplexers) modules -# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Building multiplexer modules -# Building multiplexer modules took 0.00 seconds (max_rss 12.8 MiB, delta_rss +0.3 MiB) +# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.3 MiB) # Build Look-Up Table (LUT) modules -# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 12.8 MiB, delta_rss +0.0 MiB) +# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.3 MiB) # Build wire modules -# Build wire modules took 0.00 seconds (max_rss 12.8 MiB, delta_rss +0.0 MiB) +# Build wire modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.0 MiB) # Build memory modules -# Build memory modules took 0.00 seconds (max_rss 13.1 MiB, delta_rss +0.3 MiB) +# Build memory modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.0 MiB) # Build grid modules Building logical tiles...Done Building physical tiles...Done -# Build grid modules took 0.00 seconds (max_rss 13.6 MiB, delta_rss +0.5 MiB) +# Build grid modules took 0.00 seconds (max_rss 13.7 MiB, delta_rss +0.5 MiB) # Build unique routing modules... -# Build unique routing modules... took 0.01 seconds (max_rss 15.9 MiB, delta_rss +2.3 MiB) +# Build unique routing modules... took 0.02 seconds (max_rss 16.5 MiB, delta_rss +2.8 MiB) # Build FPGA fabric module ## Add grid instances to top module -## Add grid instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) +## Add grid instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) ## Add switch block instances to top module -## Add switch block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) +## Add switch block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) ## Add connection block instances to top module -## Add connection block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) +## Add connection block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) ## Add connection block instances to top module -## Add connection block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) +## Add connection block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) ## Add module nets between grids and GSBs -## Add module nets between grids and GSBs took 0.00 seconds (max_rss 16.7 MiB, delta_rss +0.5 MiB) +## Add module nets between grids and GSBs took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.5 MiB) ## Add module nets for inter-tile connections -## Add module nets for inter-tile connections took 0.00 seconds (max_rss 16.7 MiB, delta_rss +0.0 MiB) +## Add module nets for inter-tile connections took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB) ## Add module nets for configuration buses -## Add module nets for configuration buses took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.1 MiB) -# Build FPGA fabric module took 0.01 seconds (max_rss 16.8 MiB, delta_rss +0.9 MiB) -Build fabric module graph took 0.02 seconds (max_rss 16.8 MiB, delta_rss +4.2 MiB) +## Add module nets for configuration buses took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) +# Build FPGA fabric module took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.8 MiB) +Build fabric module graph took 0.03 seconds (max_rss 17.3 MiB, delta_rss +4.6 MiB) +Create I/O location mapping for top module +Create I/O location mapping for top module took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) Command line to execute: repack Confirm selected options when call command 'repack': --verbose: off Build routing resource graph for the physical implementation of logical tile -Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.3 MiB) +Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.3 MiB) Repack clustered blocks to physical implementation of logical tile Repack clustered block 'c'...Done Repack clustered block 'out:c'...Done Repack clustered block 'a'...Done Repack clustered block 'b'...Done -Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.0 MiB) +Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) Build truth tables for physical LUTs -Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.0 MiB) +Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.8 MiB, delta_rss +0.3 MiB) Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml @@ -766,10 +753,10 @@ Generating bitstream for X-direction Connection blocks ...Done Generating bitstream for Y-direction Connection blocks ...Done Build fabric-independent bitstream for implementation 'top' - took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.3 MiB) -Warning 52: Directory path is empty and nothing will be created. -Write 2009 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' -Write 2009 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.02 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) + took 0.01 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB) +Warning 56: Directory path is empty and nothing will be created. +Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' +Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.03 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB) Command line to execute: build_fabric_bitstream @@ -780,7 +767,7 @@ Build fabric dependent bitstream Build fabric dependent bitstream - took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) + took 0.00 seconds (max_rss 18.1 MiB, delta_rss +0.3 MiB) Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit @@ -788,9 +775,9 @@ Confirm selected options when call command 'write_fabric_bitstream': --file, -f: fabric_bitstream.bit --format: plain_text --verbose: off -Warning 53: Directory path is empty and nothing will be created. -Write 2009 fabric bitstream into plain text file 'fabric_bitstream.bit' -Write 2009 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) +Warning 57: Directory path is empty and nothing will be created. +Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' +Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB) Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml @@ -798,9 +785,9 @@ Confirm selected options when call command 'write_fabric_bitstream': --file, -f: fabric_bitstream.xml --format: xml --verbose: off -Warning 54: Directory path is empty and nothing will be created. -Write 2009 fabric bitstream into xml file 'fabric_bitstream.xml' -Write 2009 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) +Warning 58: Directory path is empty and nothing will be created. +Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' +Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB) Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose @@ -852,22 +839,23 @@ Done Writing logical tiles...Done Building physical tiles... -Writing Verilog Netlist './SRC/lb/grid_io_top.v' for physical tile 'io' at top side ...Done -Writing Verilog Netlist './SRC/lb/grid_io_right.v' for physical tile 'io' at right side ...Done -Writing Verilog Netlist './SRC/lb/grid_io_bottom.v' for physical tile 'io' at bottom side ...Done -Writing Verilog Netlist './SRC/lb/grid_io_left.v' for physical tile 'io' at left side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_top_top.v' for physical tile 'io_top' at top side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_right_right.v' for physical tile 'io_right' at right side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_bottom_bottom.v' for physical tile 'io_bottom' at bottom side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_left_left.v' for physical tile 'io_left' at left side ...Done Writing Verilog Netlist './SRC/lb/grid_clb.v' for physical_tile 'clb'...Done Building physical tiles...Done Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done -Written 70 Verilog modules in total +Written 73 Verilog modules in total Write Verilog netlists for FPGA fabric - took 0.15 seconds (max_rss 17.6 MiB, delta_rss +0.3 MiB) + took 0.16 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB) Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping Confirm selected options when call command 'write_verilog_testbench': --file, -f: ./SRC +--fabric_netlist_file_path: off --reference_benchmark_file_path: top_output_verilog.v --print_top_testbench: on --fast_configuration: off @@ -876,22 +864,22 @@ Confirm selected options when call command 'write_verilog_testbench': --print_simulation_ini: ./SimulationDeck/simulation_deck.ini --explicit_port_mapping: on --verbose: off -Warning 55: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled +Warning 59: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled Write Verilog testbenches for FPGA fabric -Warning 56: Directory './SRC' already exists. Will overwrite contents +Warning 60: Directory './SRC' already exists. Will overwrite contents # Write pre-configured FPGA top-level Verilog netlist for design 'top' -# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) # Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' -# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) # Write autocheck testbench for FPGA top-level Verilog netlist for 'top' -Will use 2010 configuration clock cycles to top testbench -# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +Will use 2107 configuration clock cycles to top testbench +# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) Succeed to create directory './SimulationDeck' # Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' -# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) Write Verilog testbenches for FPGA fabric - took 0.03 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) + took 0.04 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) Command line to execute: exit @@ -899,6 +887,6 @@ Confirm selected options when call command 'exit': Finish execution with 0 errors -The entire OpenFPGA flow took 0.22 seconds +The entire OpenFPGA flow took 0.25 seconds Thank you for using OpenFPGA! diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml index 1f3d05a..47f4507 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml @@ -1,36 +1,38 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml index 2f3088b..5b8d71e 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml @@ -148,7 +148,7 @@ - + @@ -174,27 +174,25 @@ - + - - + - - - - - - - + + + + + + @@ -220,20 +218,16 @@ - + - - - - - + @@ -252,4 +246,4 @@ - + \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml index 536b9fc..843bc0f 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml @@ -33,7 +33,7 @@ - + @@ -60,7 +60,8 @@ If you need to register the I/O, define clocks in the circuit models These clocks can be handled in back-end --> - + + @@ -68,72 +69,117 @@ - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad + io_top.outpad io_top.inpad + + + + + + + + + + io_right.outpad io_right.inpad + + + + + + + + + + + + io_bottom.outpad io_bottom.inpad + + + + + + + + + + + + io_left.outpad io_left.inpad + + + - - - - - - - - + + + + + + + + + + + + + + + + - + - + - - + + + clb.clk - clb.regin clb.scin - clb.O[7:0] clb.I0 clb.I1 clb.I2 clb.I3 - clb.regout clb.scout clb.O[15:8] clb.I4 clb.I5 clb.I6 clb.I7 + clb.regin clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i + clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i + clb.regout clb.sc_out - + - + + + + - + + + + - + - - - - - - - - + + + + @@ -210,12 +256,10 @@ - + - - - + @@ -266,39 +310,37 @@ - - - - + - - - - - - - - + + + + + + + + + + + + + + + + - + - + - + - + @@ -350,9 +392,9 @@ - + - + @@ -375,10 +417,10 @@ - + - + @@ -534,30 +576,56 @@ - - + + + - + + - + + - + + - + + - + + - + + - + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -581,13 +649,13 @@ - + - + - + - + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/digital_io_hd.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/digital_io_hd.v new file mode 100644 index 0000000..0dcc04f --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/digital_io_hd.v @@ -0,0 +1,63 @@ +`timescale 1ns/1ps + +module GPIO (A, IE, OE, Y, in, out, mem_out); + output A; + output IE; + output OE; + output Y; + input in; + output out; + input mem_out; + + assign A = in; + assign out = Y; + assign IE = mem_out; + sky130_fd_sc_hd__inv_1 ie_oe_inv ( + .A (mem_out), + .Y (OE) ); +endmodule + + +// +// +// +// +module EMBEDDED_IO ( + input SOC_IN, // + output SOC_OUT, // + output SOC_DIR, // + output FPGA_IN, // + input FPGA_OUT, // + input FPGA_DIR // +); + + assign FPGA_IN = SOC_IN; + assign SOC_OUT = FPGA_OUT; + assign SOC_DIR = FPGA_DIR; +endmodule + +// +// +// +module GPIN ( + inout A, // + output Y // +); + // + sky130_fd_sc_hd__buf_4 in_buf ( + .A (A), + .X (Y) ); +endmodule + +// +// +// +module GPOUT ( + inout Y, // + input A // +); + // + sky130_fd_sc_hd__buf_4 in_buf ( + .A (A), + .X (Y) ); +endmodule diff --git a/FPGA22_HIER_SKY_PNR/README.md b/FPGA22_HIER_SKY_PNR/README.md index bc7be12..0c9ee97 100644 --- a/FPGA22_HIER_SKY_PNR/README.md +++ b/FPGA22_HIER_SKY_PNR/README.md @@ -2,7 +2,14 @@ FPGA22_HIER_SKY_PNR ==================== 2x2 FPGA designed using hierarchical flow and `SKY130_FD_SC_HD`. -Utilization set to 60% + +Updates +------------------- +- **Merged `grid_io` modules with connection blocks** +- **Pre-routed scan chain signals** +- **Created `carry_chain` feedthrough between `grid_clb` modules** +- Prerouting global signals (`Test_en`) +- Prerouting clock signals Directory Structure ------------------- @@ -21,4 +28,4 @@ Pending --------- - DRC SignOff - LVS SignOff -- PostPnR function simulation +- PostPnR functional simulation diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png index fbe96c5..9e0d25c 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/clockTree.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/clockTree.png index 71f04e2..92d81dc 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/clockTree.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/clockTree.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met1_utilization.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met1_utilization.png index bfc1897..a2248ab 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met1_utilization.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met1_utilization.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met2_utilization.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met2_utilization.png index edfa209..b4107db 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met2_utilization.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met2_utilization.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met3_utilization.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met3_utilization.png index e283d35..71773b9 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met3_utilization.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met3_utilization.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met4_utilization.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met4_utilization.png index 2eae45b..efdc230 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met4_utilization.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met4_utilization.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png index f12a880..fdadcfe 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png index 08a24be..7236298 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v index ffd8b79..0e90ffa 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v @@ -8,23 +8,19 @@ module direct_interc_5 ( in , out ) ; input [0:0] in ; output [0:0] out ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( in[0] ) , .X ( out[0] ) ) ; +assign out[0] = in[0] ; endmodule module direct_interc_4 ( in , out ) ; input [0:0] in ; output [0:0] out ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( in[0] ) , .X ( out[0] ) ) ; endmodule module direct_interc_3 ( in , out ) ; input [0:0] in ; output [0:0] out ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( in[0] ) , .X ( out[0] ) ) ; endmodule @@ -36,7 +32,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( in[0] ) , .X ( out[0] ) ) ; endmodule -module direct_interc_1 ( in , out ) ; +module direct_interc_1_1 ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -44,7 +40,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( in[0] ) , .X ( out[0] ) ) ; endmodule -module direct_interc_0 ( in , out ) ; +module direct_interc_0_1 ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -52,6 +48,1778 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) ) ; endmodule +module direct_interc_4 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +assign ccff_tail[0] = mem_out[0] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +endmodule + + +module EMBEDDED_IO_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; + +assign FPGA_IN = SOC_IN ; +assign SOC_OUT = FPGA_OUT ; +assign SOC_DIR = FPGA_DIR ; +endmodule + + +module logical_tile_io_mode_physical__iopad_7 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_0_en ; +wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ; + +EMBEDDED_IO_7 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_7 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ) ) ; +endmodule + + +module logical_tile_io_mode_io__7 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +direct_interc_4 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_4 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module const1_45 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_3_3 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_45 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_15_11 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_2_3 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_15_11 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_14_13 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_1_5 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_14_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_13_13 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_10 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_13_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_12_13 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_6_3 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_12_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_11_13 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_5_3 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_11_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_10_13 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_4_3 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_10_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_9_13 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_0_6 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_9_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module const1_8_13 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_4_5 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_8_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_7_13 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_3_5 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_7_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_6_13 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_2_5 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_5_13 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_18 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_4_14 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_7_2 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_3_14 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_6_4 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_3_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_2_14 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_5_4 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_2_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_1_14 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_1_5 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_0_14 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_0_6 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; + +assign chany_bottom_out[0] = chany_top_in[0] ; +assign chany_bottom_out[1] = chany_top_in[1] ; +assign chany_bottom_out[2] = chany_top_in[2] ; +assign chany_bottom_out[3] = chany_top_in[3] ; +assign chany_bottom_out[4] = chany_top_in[4] ; +assign chany_bottom_out[5] = chany_top_in[5] ; +assign chany_bottom_out[6] = chany_top_in[6] ; +assign chany_bottom_out[7] = chany_top_in[7] ; +assign chany_bottom_out[8] = chany_top_in[8] ; +assign chany_bottom_out[9] = chany_top_in[9] ; +assign chany_bottom_out[10] = chany_top_in[10] ; +assign chany_bottom_out[11] = chany_top_in[11] ; +assign chany_bottom_out[12] = chany_top_in[12] ; +assign chany_bottom_out[13] = chany_top_in[13] ; +assign chany_bottom_out[14] = chany_top_in[14] ; +assign chany_bottom_out[15] = chany_top_in[15] ; +assign chany_bottom_out[16] = chany_top_in[16] ; +assign chany_bottom_out[17] = chany_top_in[17] ; +assign chany_bottom_out[18] = chany_top_in[18] ; +assign chany_bottom_out[19] = chany_top_in[19] ; +assign chany_top_out[0] = chany_bottom_in[0] ; +assign chany_top_out[1] = chany_bottom_in[1] ; +assign chany_top_out[2] = chany_bottom_in[2] ; +assign chany_top_out[3] = chany_bottom_in[3] ; +assign chany_top_out[4] = chany_bottom_in[4] ; +assign chany_top_out[5] = chany_bottom_in[5] ; +assign chany_top_out[6] = chany_bottom_in[6] ; +assign chany_top_out[7] = chany_bottom_in[7] ; +assign chany_top_out[8] = chany_bottom_in[8] ; +assign chany_top_out[9] = chany_bottom_in[9] ; +assign chany_top_out[10] = chany_bottom_in[10] ; +assign chany_top_out[11] = chany_bottom_in[11] ; +assign chany_top_out[12] = chany_bottom_in[12] ; +assign chany_top_out[13] = chany_bottom_in[13] ; +assign chany_top_out[14] = chany_bottom_in[14] ; +assign chany_top_out[15] = chany_bottom_in[15] ; +assign chany_top_out[16] = chany_bottom_in[16] ; +assign chany_top_out[17] = chany_bottom_in[17] ; +assign chany_top_out[18] = chany_bottom_in[18] ; +assign chany_top_out[19] = chany_bottom_in[19] ; + +mux_tree_tapbuf_size10_0_6 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( right_grid_pin_0_ ) ) ; +mux_tree_tapbuf_size10_1_5 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_16_ ) ) ; +mux_tree_tapbuf_size10_5_4 mux_right_ipin_3 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_19_ ) ) ; +mux_tree_tapbuf_size10_6_4 mux_right_ipin_4 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_20_ ) ) ; +mux_tree_tapbuf_size10_7_2 mux_right_ipin_7 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_23_ ) ) ; +mux_tree_tapbuf_size10_18 mux_right_ipin_8 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_24_ ) ) ; +mux_tree_tapbuf_size10_2_5 mux_right_ipin_11 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_27_ ) ) ; +mux_tree_tapbuf_size10_3_5 mux_right_ipin_12 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_28_ ) ) ; +mux_tree_tapbuf_size10_4_5 mux_right_ipin_15 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( left_grid_pin_31_ ) ) ; +mux_tree_tapbuf_size10_mem_0_6 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1_5 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6_4 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7_2 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_18 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2_5 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3_5 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4_5 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_0_6 mux_right_ipin_1 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_17_ ) ) ; +mux_tree_tapbuf_size8_4_3 mux_right_ipin_2 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_18_ ) ) ; +mux_tree_tapbuf_size8_5_3 mux_right_ipin_5 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_21_ ) ) ; +mux_tree_tapbuf_size8_6_3 mux_right_ipin_6 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_22_ ) ) ; +mux_tree_tapbuf_size8_10 mux_right_ipin_9 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_25_ ) ) ; +mux_tree_tapbuf_size8_1_5 mux_right_ipin_10 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_26_ ) ) ; +mux_tree_tapbuf_size8_2_3 mux_right_ipin_13 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_29_ ) ) ; +mux_tree_tapbuf_size8_3_3 mux_right_ipin_14 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_30_ ) ) ; +mux_tree_tapbuf_size8_mem_0_6 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_4_3 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5_3 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6_3 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_10 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1_5 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2_3 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +logical_tile_io_mode_io__7 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_41 } ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_42 } ) ) ; +sky130_fd_sc_hd__buf_4 FTB_41__40 ( + .A ( left_width_0_height_0__pin_1_upper[0] ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_731 ( .A ( ropt_net_41 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_732 ( .A ( ropt_net_42 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size8_mem_3_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -68,14 +1836,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__56 ( .A ( mem_out[3] ) , - .X ( net_aps_56 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( net_aps_56 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_3 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_2_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -91,7 +1857,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -112,28 +1878,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -154,7 +1899,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -175,7 +1920,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -196,7 +1941,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -217,7 +1962,28 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -241,10 +2007,2176 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; const1_44 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_14_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_14_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_13_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_13_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_12_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_12_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_11_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_11_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_10_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_10_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_9_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_9_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_8_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_8_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( net_net_70 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_90 ( .A ( net_net_70 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_7_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_7_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_6_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_5_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_4_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_3_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_3_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_2_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_2_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_0_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; + +mux_tree_tapbuf_size10_0_5 mux_right_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_4_4 mux_right_ipin_3 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size10_6_3 mux_right_ipin_7 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_98 ) ) ; +mux_tree_tapbuf_size10_17 mux_right_ipin_8 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_1_4 mux_right_ipin_11 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_2_4 mux_right_ipin_12 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_3_4 mux_right_ipin_15 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_mem_0_5 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5_3 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6_3 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_17 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1_4 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2_4 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size8_0_5 mux_right_ipin_1 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[13] , chany_top_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size8_4_2 mux_right_ipin_2 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size8_5_2 mux_right_ipin_5 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[17] , chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_98 ) ) ; +mux_tree_tapbuf_size8_6_2 mux_right_ipin_6 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_9 mux_right_ipin_9 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[13] , chany_top_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size8_1_4 mux_right_ipin_10 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size8_2_2 mux_right_ipin_13 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[17] , chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_3_2 mux_right_ipin_14 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size8_mem_0_5 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_4_2 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5_2 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6_2 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_9 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1_4 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3_2 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_111 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( + .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_113 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_114 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_115 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , + .X ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_117 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( aps_rename_1_ ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_59 ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +endmodule + + +module direct_interc_3 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module EMBEDDED_IO_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +wire aps_rename_2_ ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , + .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_6 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_6 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__6 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_3 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_3 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_43 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , + right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; + +wire ropt_net_162 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; + +mux_tree_tapbuf_size10_16 mux_right_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size10_mem_16 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +logical_tile_io_mode_io__6 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_163 } ) , + .p_abuf0 ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) , + .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +endmodule + + +module direct_interc_2 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( net_aps_61 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module EMBEDDED_IO_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( p_abuf0 ) , .X ( FPGA_IN ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_5 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_5 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__5 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) ) ; +direct_interc_2 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf0 } ) ) ; +direct_interc_2 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_42 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -278,7 +4210,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_2_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -292,12 +4224,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; const1_15_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -317,10 +4246,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -329,7 +4257,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_1_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_1_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -380,54 +4308,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_13_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_12_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_9 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -443,7 +4324,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_12_11 const1_0_ ( +const1_13_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -473,12 +4354,59 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module const1_12_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_12_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + module const1_11_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_6_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_5_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -529,7 +4457,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_5_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -580,7 +4508,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_4_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_0_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -594,12 +4522,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; const1_9_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -619,10 +4544,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -642,7 +4566,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -663,91 +4587,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_7_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -768,7 +4608,91 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -789,12 +4713,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_5 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_0_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -810,7 +4734,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -933,12 +4857,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6_12 ( const1 ) ; +module const1_6_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_16 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -956,7 +4880,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6_12 const1_0_ ( +const1_6_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -992,12 +4916,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5_12 ( const1 ) ; +module const1_5_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_7_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_15 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1015,7 +4939,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5_12 const1_0_ ( +const1_5_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1056,7 +4980,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1115,7 +5039,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_6_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1174,7 +5098,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_2_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_5_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1287,568 +5211,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_0_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_0_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_0_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , - left_grid_pin_1_ , left_grid_pin_2_ , left_grid_pin_3_ , - left_grid_pin_4_ , left_grid_pin_5_ , left_grid_pin_6_ , - left_grid_pin_7_ , left_grid_pin_8_ , left_grid_pin_9_ , - left_grid_pin_10_ , left_grid_pin_11_ , left_grid_pin_12_ , - left_grid_pin_13_ , left_grid_pin_14_ , left_grid_pin_15_ , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] right_grid_pin_52_ ; -output [0:0] left_grid_pin_0_ ; -output [0:0] left_grid_pin_1_ ; -output [0:0] left_grid_pin_2_ ; -output [0:0] left_grid_pin_3_ ; -output [0:0] left_grid_pin_4_ ; -output [0:0] left_grid_pin_5_ ; -output [0:0] left_grid_pin_6_ ; -output [0:0] left_grid_pin_7_ ; -output [0:0] left_grid_pin_8_ ; -output [0:0] left_grid_pin_9_ ; -output [0:0] left_grid_pin_10_ ; -output [0:0] left_grid_pin_11_ ; -output [0:0] left_grid_pin_12_ ; -output [0:0] left_grid_pin_13_ ; -output [0:0] left_grid_pin_14_ ; -output [0:0] left_grid_pin_15_ ; -output [0:0] ccff_tail ; - -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; - -mux_tree_tapbuf_size10_0_5 mux_left_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_52_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size10_1_3 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_2_3 mux_right_ipin_1 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_1_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_4_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_6_3 mux_right_ipin_5 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_5_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_7_2 mux_right_ipin_8 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_8_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_16 mux_right_ipin_9 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_9_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_3_3 mux_right_ipin_12 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_12_ ) , .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size10_4_3 mux_right_ipin_13 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[14] , chany_top_in[14] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_13_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_mem_0_5 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_3 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_3 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_3 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_3 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7_2 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_16 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_3 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_4_2 mux_right_ipin_2 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_2_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size8_5_2 mux_right_ipin_3 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[16] , chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_3_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_6_2 mux_right_ipin_6 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_6_ ) , .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size8_9 mux_right_ipin_7 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[12] , chany_top_in[12] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_7_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_0_4 mux_right_ipin_10 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_10_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size8_1_4 mux_right_ipin_11 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[16] , chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_11_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size8_2_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_14_ ) , .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size8_3_2 mux_right_ipin_15 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[12] , chany_top_in[12] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_15_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_mem_4_2 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5_2 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6_2 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_9 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0_4 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_4 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3_2 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_113 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( aps_rename_4_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( aps_rename_5_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_29__28 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_bottom_in[19] ) , - .X ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_top_in[16] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_1_ ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( aps_rename_2_ ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( aps_rename_4_ ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_5_ ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_98 ( .A ( BUF_net_68 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_71 ) , - .X ( chany_bottom_out[16] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( net_net_76 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( net_net_76 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_43 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_43 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - module const1_0_12 ( const1 ) ; output [0:0] const1 ; endmodule @@ -1908,329 +5270,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , - ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] right_grid_pin_52_ ; -output [0:0] left_grid_pin_0_ ; -output [0:0] ccff_tail ; - -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; - -mux_tree_tapbuf_size10_0_4 mux_left_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_52_ ) , .p0 ( optlc_net_144 ) ) ; -mux_tree_tapbuf_size10_15 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_145 ) ) ; -mux_tree_tapbuf_size10_mem_0_4 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_15 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_177 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_153 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_154 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_155 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_156 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_157 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_158 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_159 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_164 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_166 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_167 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_168 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_169 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_172 ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_175 ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_176 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_180 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_45 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_182 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_183 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_184 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_185 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_186 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_188 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_189 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_190 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_191 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_192 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_193 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_194 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_65 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chany_top_in[9] ) , - .X ( BUF_net_66 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_196 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_197 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_198 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_111 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_115 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_117 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_131 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_66 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_160 ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( net_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_115 ( .A ( net_net_74 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_42 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_42 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_0_ , ccff_tail ) ; + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , + bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -2238,220 +5289,408 @@ input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +wire p_abuf0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -mux_tree_tapbuf_size10_14 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0_4 mux_bottom_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_143 ) ) ; -mux_tree_tapbuf_size10_mem_14 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_1_3 mux_top_ipin_0 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_5_2 mux_top_ipin_3 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_6_2 mux_top_ipin_4 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_7_1 mux_top_ipin_7 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_15 mux_top_ipin_8 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_2_3 mux_top_ipin_11 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_3_3 mux_top_ipin_12 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_4_3 mux_top_ipin_15 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_mem_0_4 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { ropt_net_181 } ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_144 ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_148 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_149 ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_152 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_155 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_167 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_172 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_44 ( .A ( chanx_left_in[8] ) , - .X ( BUF_net_44 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , +mux_tree_tapbuf_size10_mem_1_3 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5_2 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6_2 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7_1 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_15 mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2_3 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_0_4 mux_top_ipin_1 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_4_1 mux_top_ipin_2 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_5_1 mux_top_ipin_5 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_6_1 mux_top_ipin_6 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size8_8 mux_top_ipin_9 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_1_3 mux_top_ipin_10 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_2_1 mux_top_ipin_13 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_3_1 mux_top_ipin_14 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size8_mem_0_4 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_4_1 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5_1 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6_1 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_8 mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1_3 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2_1 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3_1 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +logical_tile_io_mode_io__5 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_197 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_198 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_199 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_200 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_203 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_204 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_207 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_209 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_211 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_216 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_103 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_104 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_116 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_44 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_132 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_119 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( p_abuf0 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_2_ ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_3_ ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -2467,14 +5706,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( net_net_72 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -2490,12 +5727,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_3 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_1_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -2511,7 +5748,91 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2532,91 +5853,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_5_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2626,7 +5863,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_3_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2677,7 +5914,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_2_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2728,7 +5965,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_1_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_1_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2779,7 +6016,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_7 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2830,54 +6067,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_11_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_10_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_6_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2893,7 +6083,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_10_10 const1_0_ ( +const1_11_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -2923,12 +6113,59 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module const1_10_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_10_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + module const1_9_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_5_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2979,7 +6216,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_4_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_0_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3041,7 +6278,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3062,91 +6299,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3167,7 +6320,91 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3188,7 +6425,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3252,7 +6489,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6_11 ( const1 ) ; +module const1_6_10 ( const1 ) ; output [0:0] const1 ; endmodule @@ -3275,7 +6512,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6_11 const1_0_ ( +const1_6_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -3311,12 +6548,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5_11 ( const1 ) ; +module const1_5_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_13 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_1_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3334,7 +6571,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5_11 const1_0_ ( +const1_5_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -3375,7 +6612,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_14 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3434,7 +6671,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3493,7 +6730,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_5_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3552,7 +6789,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3666,35 +6903,43 @@ endmodule module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , - top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , - top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , - top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , - top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , - top_grid_pin_30_ , top_grid_pin_31_ , ccff_tail ) ; + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , CLB_SC_IN , CLB_SC_OUT , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_16_ ; -output [0:0] top_grid_pin_17_ ; -output [0:0] top_grid_pin_18_ ; -output [0:0] top_grid_pin_19_ ; -output [0:0] top_grid_pin_20_ ; -output [0:0] top_grid_pin_21_ ; -output [0:0] top_grid_pin_22_ ; -output [0:0] top_grid_pin_23_ ; -output [0:0] top_grid_pin_24_ ; -output [0:0] top_grid_pin_25_ ; -output [0:0] top_grid_pin_26_ ; -output [0:0] top_grid_pin_27_ ; -output [0:0] top_grid_pin_28_ ; -output [0:0] top_grid_pin_29_ ; -output [0:0] top_grid_pin_30_ ; -output [0:0] top_grid_pin_31_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; +input CLB_SC_IN ; +output CLB_SC_OUT ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -3719,7 +6964,6 @@ wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; @@ -3743,887 +6987,919 @@ wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -mux_tree_tapbuf_size10_0_3 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0_3 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_16_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_1_2 mux_bottom_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_4_2 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_4_2 mux_bottom_ipin_4 ( + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_5_1 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_5_2 mux_bottom_ipin_5 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_6_1 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( top_grid_pin_21_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_6_2 mux_bottom_ipin_8 ( + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_14 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_13 mux_bottom_ipin_9 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_1_2 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , + chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_2_2 mux_bottom_ipin_12 ( + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_2_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_3_2 mux_bottom_ipin_13 ( + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_3_2 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , + chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_mem_0_3 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_mem_0_3 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_2 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4_2 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_2 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_5_1 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_2 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , +mux_tree_tapbuf_size10_mem_6_1 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_2 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_14 mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_13 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , +mux_tree_tapbuf_size10_mem_2_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_2 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +mux_tree_tapbuf_size10_mem_3_2 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size8_4_1 mux_bottom_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , +mux_tree_tapbuf_size8_0_3 mux_top_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_5_1 mux_bottom_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_6_1 mux_bottom_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( top_grid_pin_22_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_8 mux_bottom_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_0_3 mux_bottom_ipin_10 ( + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_1_3 mux_bottom_ipin_11 ( + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_2_2 mux_bottom_ipin_14 ( + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_7 mux_top_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_1_2 mux_top_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_3_1 mux_bottom_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_mem_4_1 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_mem_0_3 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5_1 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6_1 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , +mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_8 mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0_3 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , +mux_tree_tapbuf_size8_mem_7 mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_3 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_1_2 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , +mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3_1 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_97 } ) , +mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_105 ) , - .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( ropt_net_105 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( aps_rename_6_ ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_673 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_106 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_107 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_675 ( .A ( ropt_net_97 ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_108 ) , - .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_98 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( ropt_net_106 ) , + .X ( chanx_left_out[16] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_107 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_102 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_682 ( .A ( ropt_net_103 ) , - .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_108 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_109 ) , + .X ( chanx_right_out[15] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_104 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_59 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chanx_left_in[9] ) , - .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( BUF_net_61 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( aps_rename_3_ ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_82 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chanx_right_in[6] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( aps_rename_4_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[19] ) , + .X ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_2_ ) , - .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chanx_right_in[12] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chanx_right_in[16] ) , + .X ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( aps_rename_6_ ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( BUF_net_65 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( BUF_net_69 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_71 ) , + .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( CLB_SC_IN ) , + .X ( CLB_SC_OUT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( aps_rename_4_ ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__56 ( .A ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb15_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__70 ( .A ( mem_out[0] ) , + .X ( net_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_114 ( .A ( net_net_114 ) , + .X ( net_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_152 ( .A ( net_net_113 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb14_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( net_aps_67 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb11_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( net_aps_64 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__63 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb8_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_14__60 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_155 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; input [0:0] ccff_head ; +output [0:0] iopad_inpad ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output p_abuf0 ; +output p_abuf1 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; input [0:0] ccff_head ; +output [0:0] io_inpad ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output p_abuf0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; +logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_40 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; +module direct_interc_1 ( in , out ) ; +input [0:0] in ; output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_40 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule -module const1_15_9 ( const1 ) ; -output [0:0] const1 ; +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb5_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( net_aps_58 ) ) ; endmodule -module mux_tree_tapbuf_size8_2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; +module EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module direct_interc_1 ( in , out ) ; +input [0:0] in ; output [0:0] out ; -input p0 ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_15_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +assign out[0] = in[0] ; endmodule -module const1_14_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_1_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; +module direct_interc_0 ( in , out ) ; +input [0:0] in ; output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_14_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule -module const1_13_9 ( const1 ) ; -output [0:0] const1 ; +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb2_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( net_aps_55 ) ) ; endmodule -module mux_tree_tapbuf_size8_0_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; +module EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +assign SOC_OUT = FPGA_OUT ; -const1_13_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module const1_12_9 ( const1 ) ; -output [0:0] const1 ; +module logical_tile_io_mode_physical__iopad_0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; endmodule -module mux_tree_tapbuf_size8_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; +module logical_tile_io_mode_io__0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_12_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) ) ; +direct_interc_0 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( io_outpad ) ) ; endmodule -module const1_11_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_11_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_10_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_10_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_9_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_9_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_12 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_13 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -4639,114 +7915,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( net_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( net_net_69 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_7_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -4767,7 +7936,49 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -4788,7 +7999,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -4809,17 +8020,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_8_9 ( const1 ) ; +module const1_40 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_12 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_13 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4837,184 +8048,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_8_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module const1_7_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_7_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module const1_6_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_6_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module const1_5_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_5_10 const1_0_ ( +const1_40 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -5055,7 +8089,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5114,7 +8148,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5173,7 +8207,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5307,12 +8341,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; const1_0_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -5338,45 +8369,73 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , - top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , - top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , - top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , - top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , - top_grid_pin_30_ , top_grid_pin_31_ , bottom_grid_pin_0_ , ccff_tail ) ; + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , + top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , + top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , + top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , + top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , + top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , + top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_16_ ; -output [0:0] top_grid_pin_17_ ; -output [0:0] top_grid_pin_18_ ; -output [0:0] top_grid_pin_19_ ; -output [0:0] top_grid_pin_20_ ; -output [0:0] top_grid_pin_21_ ; -output [0:0] top_grid_pin_22_ ; -output [0:0] top_grid_pin_23_ ; -output [0:0] top_grid_pin_24_ ; -output [0:0] top_grid_pin_25_ ; -output [0:0] top_grid_pin_26_ ; -output [0:0] top_grid_pin_27_ ; -output [0:0] top_grid_pin_28_ ; -output [0:0] top_grid_pin_29_ ; -output [0:0] top_grid_pin_30_ ; -output [0:0] top_grid_pin_31_ ; output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; output [0:0] ccff_tail ; +input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +wire ropt_net_188 ; +wire ropt_net_186 ; +wire ropt_net_190 ; +wire ropt_net_184 ; +wire ropt_net_185 ; +wire ropt_net_183 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -5389,351 +8448,381 @@ wire [0:3] mux_tree_tapbuf_size10_4_sram ; wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -mux_tree_tapbuf_size10_0_2 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0_2 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_16_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_1_1 mux_bottom_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_177 ) ) ; +mux_tree_tapbuf_size10_1_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_4_1 mux_bottom_ipin_4 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_2_1 mux_top_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_3_1 mux_top_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_4_1 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_5_1 mux_bottom_ipin_5 ( + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_13 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( top_grid_pin_21_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_6_1 mux_bottom_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_7_1 mux_bottom_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_2_1 mux_bottom_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_3_1 mux_bottom_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_12 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_mem_0_2 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_177 ) ) ; +mux_tree_tapbuf_size10_mem_0_2 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_1 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , +mux_tree_tapbuf_size10_mem_2_1 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_1 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_3_1 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_1 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4_1 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7_1 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , +mux_tree_tapbuf_size10_mem_13 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_1 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_1 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_12 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( top_grid_pin_22_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_7 mux_bottom_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_0_2 mux_bottom_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_1_2 mux_bottom_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_2_1 mux_bottom_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_7 mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0_2 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_2 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2_1 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_92 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_672 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_673 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , +logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_12_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( ropt_net_188 ) ) ; +logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_206 } ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , + .p_abuf0 ( ropt_net_186 ) ) ; +logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_14_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , + .p_abuf0 ( ropt_net_190 ) ) ; +logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_15_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , + .p_abuf0 ( ropt_net_184 ) ) ; +logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_16_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , + .p_abuf0 ( ropt_net_185 ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_17_ } ) , + .ccff_tail ( { ropt_net_221 } ) , + .p_abuf0 ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_230 ) , .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_176 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_183 ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_184 ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_185 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_186 ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_187 ) , + .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_188 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_190 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( BUF_net_111 ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_110 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[12] ) , .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_231 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_194 ) , + .X ( ropt_net_247 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_232 ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( BUF_net_109 ) , + .X ( ropt_net_246 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_right_in[15] ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_1_ ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_76 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_77 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_78 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_82 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_233 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_197 ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_234 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_235 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_199 ) , + .X ( ropt_net_251 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_201 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_202 ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_236 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_237 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_238 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_205 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_43__42 ( .A ( aps_rename_14_ ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_44__43 ( .A ( aps_rename_15_ ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_206 ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_208 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_212 ) , + .X ( ropt_net_248 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_213 ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_214 ) , + .X ( ropt_net_243 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_239 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[14] ) , + .X ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_216 ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_242 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_right_in[9] ) , + .X ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( chanx_right_in[10] ) , + .X ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_243 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_244 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_245 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_246 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_218 ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( aps_rename_12_ ) , + .X ( BUF_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_110 ( .A ( aps_rename_13_ ) , + .X ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_111 ( .A ( aps_rename_16_ ) , + .X ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_219 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_220 ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_221 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_222 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_223 ) , + .X ( ropt_net_249 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_224 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_225 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_227 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_247 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_248 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_249 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_250 ) , .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_252 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_253 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_254 ) , .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_255 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_256 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_257 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_146 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_147 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_148 ( .A ( BUF_net_102 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_149 ( .A ( BUF_net_103 ) , + .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_158 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_159 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_161 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_162 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_163 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_164 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_92 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_167 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_173 ( .A ( aps_rename_17_ ) , + .X ( ropt_net_205 ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_15_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem_1_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5745,9 +8834,153 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__39 ( .A ( mem_out[1] ) , - .X ( net_net_59 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( net_net_59 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_39 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( net_net_48 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_48 ( .A ( net_net_48 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5764,12 +8997,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_16_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5781,12 +9014,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_14_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5798,12 +9031,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_13_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5815,12 +9048,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_12_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_18_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5832,12 +9065,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_11_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_17_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5849,12 +9082,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_10_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_16_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5866,12 +9099,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_15_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5883,12 +9116,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_8_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_14_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5900,12 +9133,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_7_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_13_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5917,7 +9150,92 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5934,12 +9252,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_5_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_5_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5951,12 +9269,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_4_5 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5968,7 +9286,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5985,7 +9303,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -6002,7 +9320,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -6019,7 +9337,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -6036,17 +9354,34 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_39 ( const1 ) ; +module mux_tree_tapbuf_size2_mem_9_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_31_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_15_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -6056,7 +9391,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_39 const1_0_ ( +const1_31_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -6068,7 +9403,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_22_7 ( const1 ) ; +module const1_30_3 ( const1 ) ; output [0:0] const1 ; endmodule @@ -6083,7 +9418,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_22_7 const1_0_ ( +const1_30_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -6095,12 +9430,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_21_7 ( const1 ) ; +module const1_29_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_16_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -6110,7 +9445,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_21_7 const1_0_ ( +const1_29_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -6122,12 +9457,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_20_7 ( const1 ) ; +module const1_28_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_14_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -6137,7 +9472,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_20_7 const1_0_ ( +const1_28_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -6149,12 +9484,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_19_7 ( const1 ) ; +module const1_27_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_13_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -6164,7 +9499,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_19_7 const1_0_ ( +const1_27_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -6176,12 +9511,228 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_18_7 ( const1 ) ; +module const1_26_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_12_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_18_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_26_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_25_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_17_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_25_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_24_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_16_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_24_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_23_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_15_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_23_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_22_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_14_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_22_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_21_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_13_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_21_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_20_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_20_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_19_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_11_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_19_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_18_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -6190,7 +9741,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_18_7 const1_0_ ( +const1_18_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -6199,12 +9750,12 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_17_7 ( const1 ) ; +module const1_17_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_11_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -6214,7 +9765,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_17_7 const1_0_ ( +const1_17_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -6226,12 +9777,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_16_8 ( const1 ) ; +module const1_16_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_7_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -6239,102 +9790,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_16_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_15_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_9_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_15_8 const1_0_ ( +const1_16_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module const1_14_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_14_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_13_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_13_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_12_8 ( const1 ) ; +module const1_15_9 ( const1 ) ; output [0:0] const1 ; endmodule @@ -6349,7 +9815,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_12_8 const1_0_ ( +const1_15_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -6361,12 +9827,35 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_11_8 ( const1 ) ; +module const1_14_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_5_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_14_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_13_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -6376,7 +9865,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_11_8 const1_0_ ( +const1_13_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -6388,34 +9877,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_10_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_4_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_10_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_9_8 ( const1 ) ; +module const1_12_9 ( const1 ) ; output [0:0] const1 ; endmodule @@ -6430,7 +9892,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_9_8 const1_0_ ( +const1_12_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -6442,7 +9904,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_8_8 ( const1 ) ; +module const1_11_9 ( const1 ) ; output [0:0] const1 ; endmodule @@ -6457,7 +9919,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_8_8 const1_0_ ( +const1_11_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -6469,7 +9931,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_7_8 ( const1 ) ; +module const1_10_9 ( const1 ) ; output [0:0] const1 ; endmodule @@ -6484,7 +9946,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_7_8 const1_0_ ( +const1_10_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -6496,7 +9958,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_6_9 ( const1 ) ; +module const1_9_9 ( const1 ) ; output [0:0] const1 ; endmodule @@ -6511,7 +9973,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_6_9 const1_0_ ( +const1_9_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -6523,47 +9985,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem_0_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_5_9 ( const1 ) ; +module const1_8_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; +module mux_tree_tapbuf_size2_9_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; @@ -6571,53 +9999,16 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_5_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( BUF_net_41 ) , - .X ( out[0] ) ) ; -endmodule - - -module const1_4_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_4_9 const1_0_ ( +const1_8_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -6635,7 +10026,45 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -6654,12 +10083,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_3_9 ( const1 ) ; +module const1_7_9 ( const1 ) ; output [0:0] const1 ; endmodule @@ -6677,7 +10106,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_3_9 const1_0_ ( +const1_7_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -6698,7 +10127,85 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_2_9 ( const1 ) ; +module const1_6_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_6_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_5_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_5_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_4_9 ( const1 ) ; output [0:0] const1 ; endmodule @@ -6716,8 +10223,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_2_9 const1_0_ ( +const1_4_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -6732,12 +10241,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_87 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_10 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_11 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -6751,12 +10258,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0_6 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_2_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -6770,17 +10277,141 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule +module mux_tree_tapbuf_size6_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_3_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_3_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_2_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_2_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + module const1_1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_1_2 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -6823,7 +10454,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_0_5 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -6862,29 +10493,45 @@ endmodule module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , - bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , - bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , - bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , - bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , - left_top_grid_pin_1_ , ccff_head , chany_bottom_out , chanx_left_out , - ccff_tail ) ; + bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; @@ -6904,8 +10551,20 @@ wire [0:1] mux_tree_tapbuf_size2_16_sram ; wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; @@ -6930,7 +10589,13 @@ wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; @@ -6943,358 +10608,465 @@ wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -mux_tree_tapbuf_size6_0_6 mux_bottom_track_1 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[1] } ) , +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size6_0_5 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size6_10 mux_bottom_track_5 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[3] } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size6_1_2 mux_bottom_track_5 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size6_mem_0_6 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6_2_1 mux_left_track_1 ( + .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6_11 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6_mem_0_5 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_10 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem_1_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_2_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_11 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; mux_tree_tapbuf_size5_0_4 mux_bottom_track_3 ( - .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_123 } ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size5_8 mux_bottom_track_7 ( - .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size5_1_1 mux_bottom_track_7 ( + .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_114 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size5_2_1 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size5_8 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_78 ) ) ; mux_tree_tapbuf_size5_mem_0_4 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_8 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5_mem_1_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_11 mux_bottom_track_9 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , - chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size3_0_6 mux_bottom_track_25 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size3_mem_11 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0_6 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_0_5 mux_bottom_track_11 ( - .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[6] } ) , +mux_tree_tapbuf_size5_mem_2_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_8 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_9_3 mux_bottom_track_9 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_1_5 mux_bottom_track_13 ( - .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_0_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_2_5 mux_bottom_track_15 ( - .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[8] } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_1_5 mux_bottom_track_13 ( + .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_3_5 mux_bottom_track_17 ( - .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[9] } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_2_5 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_4_4 mux_bottom_track_19 ( - .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[10] } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_3_5 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_5_4 mux_bottom_track_21 ( - .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_4_5 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_6_3 mux_bottom_track_23 ( - .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[12] } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_5_3 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_7_2 mux_bottom_track_27 ( - .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[14] } ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( { ropt_net_83 } ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_6_3 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_8_2 mux_bottom_track_29 ( - .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_7_3 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_9_2 mux_bottom_track_31 ( - .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[16] } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_8_3 mux_bottom_track_29 ( + .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( { ropt_net_120 } ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_10_2 mux_bottom_track_33 ( - .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[17] } ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_10_3 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_11_1 mux_bottom_track_35 ( - .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[18] } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_11_3 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_12_1 mux_bottom_track_37 ( - .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[19] } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size2_12_3 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_13_1 mux_bottom_track_39 ( - .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[0] } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_13_3 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_14_1 mux_left_track_1 ( - .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_14_3 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_16_1 mux_left_track_5 ( - .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_81 } ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_15_2 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_22 mux_left_track_9 ( - .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size2_16_2 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_15_1 mux_left_track_25 ( - .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_17_1 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_mem_0_5 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_18_1 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_19 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_20 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_21 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_22 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_23 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_mem_9_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_5 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0_5 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_5 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1_5 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_5 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2_5 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3_5 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4_5 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6_3 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5_3 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7_2 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , +mux_tree_tapbuf_size2_mem_6_3 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8_2 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , +mux_tree_tapbuf_size2_mem_7_3 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9_2 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_8_3 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , +mux_tree_tapbuf_size2_mem_10_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11_1 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_11_3 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12_1 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_12_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13_1 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_15_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_22 mem_left_track_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_16_2 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_128 } ) , +mux_tree_tapbuf_size2_mem_17_1 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_113 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chany_bottom_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( - .A ( chany_bottom_in[16] ) , .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_120 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( - .A ( chany_bottom_in[17] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( chany_bottom_in[8] ) , +mux_tree_tapbuf_size2_mem_18_1 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_23 mem_left_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( { ropt_net_84 } ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) ) ; +mux_tree_tapbuf_size3_0_6 mux_bottom_track_25 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size3_10 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size3_1_4 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size3_mem_0_6 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_10 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_87 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_92 ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( ropt_net_123 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( - .A ( chany_bottom_in[15] ) , .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_bottom_in[0] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( - .A ( chany_bottom_in[12] ) , .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( - .A ( chany_bottom_in[18] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_128 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_129 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chany_bottom_in[4] ) , - .X ( BUF_net_46 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[9] ) , - .X ( BUF_net_51 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chany_bottom_in[10] ) , - .X ( BUF_net_52 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_136 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chany_bottom_in[13] ) , - .X ( BUF_net_54 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[14] ) , - .X ( BUF_net_55 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_131 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_137 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_93 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_88 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_82 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_94 ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chanx_left_in[18] ) , + .X ( BUF_net_46 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( ropt_net_95 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_60 ( .A ( BUF_net_46 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_75 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_76 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_77 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_78 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_667 ( .A ( ropt_net_81 ) , + .X ( ropt_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( ropt_net_82 ) , + .X ( ropt_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_83 ) , + .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_84 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_46 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_98 ( .A ( BUF_net_51 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_99 ( .A ( BUF_net_52 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_54 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_55 ) , - .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_672 ( .A ( ropt_net_86 ) , + .X ( ropt_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_87 ) , + .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_88 ) , + .X ( ropt_net_93 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( ropt_net_96 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_97 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_98 ) , + .X ( chany_bottom_out[16] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_10 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7306,9 +11078,273 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , - .X ( net_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( net_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , + .X ( net_net_91 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_91 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_38 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_31_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_31_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_30_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_30_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_29_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_29_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_28_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_28_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_27_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_27_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -7325,12 +11361,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem_2_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7342,12 +11378,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem_1_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7359,7 +11395,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -7376,17 +11412,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_38 ( const1 ) ; +module const1_26_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_10 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3_9 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -7397,10 +11433,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_38 const1_0_ ( +const1_26_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -7409,6 +11443,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -7448,7 +11484,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_2_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3_2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -7479,7 +11515,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3_1_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -7505,7 +11541,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_22_6 ( const1 ) ; +module const1_22_7 ( const1 ) ; output [0:0] const1 ; endmodule @@ -7521,7 +11557,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_22_6 const1_0_ ( +const1_22_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -7536,7 +11572,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_2_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7550,12 +11586,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_1_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_1_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7569,12 +11605,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_0_3 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_0_5 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7588,12 +11624,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_8 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_9 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7607,17 +11643,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_21_6 ( const1 ) ; +module const1_21_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_2_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -7629,7 +11665,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_21_6 const1_0_ ( +const1_21_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -7647,12 +11683,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_20_6 ( const1 ) ; +module const1_20_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_1_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_1_4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -7664,7 +11700,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_20_6 const1_0_ ( +const1_20_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -7682,12 +11718,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_19_6 ( const1 ) ; +module const1_19_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_0_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_0_5 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -7699,42 +11735,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_19_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_18_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -const1_18_6 const1_0_ ( +const1_19_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -7752,7 +11753,42 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , +module const1_18_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_18_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7768,17 +11804,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_17_6 ( const1 ) ; +module const1_17_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7795,8 +11831,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -const1_17_6 const1_0_ ( +const1_17_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -7823,12 +11861,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_104 ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_1_3 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_1_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7842,12 +11878,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0_5 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_0_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7861,12 +11897,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_9 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7880,17 +11916,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_16_7 ( const1 ) ; +module const1_16_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_1_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_1_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -7904,7 +11940,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_16_7 const1_0_ ( +const1_16_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -7928,12 +11964,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_15_7 ( const1 ) ; +module const1_15_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_0_4 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -7947,7 +11983,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_15_7 const1_0_ ( +const1_15_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -7971,12 +12007,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_14_7 ( const1 ) ; +module const1_14_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -7990,7 +12026,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_14_7 const1_0_ ( +const1_14_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -8014,7 +12050,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_4_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_4_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8028,12 +12064,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_3_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8047,7 +12083,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8066,7 +12102,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8085,7 +12121,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8104,12 +12140,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_8 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8123,12 +12159,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_5_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_5_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8142,17 +12178,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_13_7 ( const1 ) ; +module const1_13_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_4_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -8167,7 +12203,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_13_7 const1_0_ ( +const1_13_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -8194,12 +12230,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_12_7 ( const1 ) ; +module const1_12_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_3_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -8214,10 +12250,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_12_7 const1_0_ ( +const1_12_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -8238,10 +12272,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_11_7 ( const1 ) ; +module const1_11_8 ( const1 ) ; output [0:0] const1 ; endmodule @@ -8261,7 +12297,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_11_7 const1_0_ ( +const1_11_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -8288,7 +12324,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_10_7 ( const1 ) ; +module const1_10_8 ( const1 ) ; output [0:0] const1 ; endmodule @@ -8308,7 +12344,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_10_7 const1_0_ ( +const1_10_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -8335,7 +12371,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_9_7 ( const1 ) ; +module const1_9_8 ( const1 ) ; output [0:0] const1 ; endmodule @@ -8355,7 +12391,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_9_7 const1_0_ ( +const1_9_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -8382,12 +12418,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_8_7 ( const1 ) ; +module const1_8_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_10 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -8402,7 +12438,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_8_7 const1_0_ ( +const1_8_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -8429,12 +12465,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_7_7 ( const1 ) ; +module const1_7_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_5_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_5_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -8449,7 +12485,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_7_7 const1_0_ ( +const1_7_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -8492,7 +12528,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8513,7 +12549,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8668,7 +12704,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_0_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8684,7 +12720,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8705,7 +12741,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8726,7 +12762,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8736,7 +12772,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_0_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -8900,12 +12936,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_11 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_12 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8921,7 +12957,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8951,8 +12987,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; const1_1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -8982,6 +13016,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_61 ) , + .X ( out[0] ) ) ; endmodule @@ -8990,7 +13028,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_11 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_12 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -9044,49 +13082,50 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , top_right_grid_pin_1_ , chany_bottom_in , - bottom_right_grid_pin_1_ , bottom_left_grid_pin_34_ , - bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , - bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , - bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , - bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , - left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , - left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , - left_top_grid_pin_49_ , ccff_head , chany_top_out , chany_bottom_out , +module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , + bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , chanx_left_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:0] top_right_grid_pin_1_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chany_bottom_out ; @@ -9105,6 +13144,23 @@ wire [0:3] mux_tree_tapbuf_size14_1_sram ; wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -9119,6 +13175,7 @@ wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; @@ -9174,23 +13231,24 @@ wire [0:3] mux_tree_tapbuf_size9_0_sram ; wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -mux_tree_tapbuf_size10_11 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , +mux_tree_tapbuf_size10_12 mux_top_track_0 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size10_0_1 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size10_mem_11 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_166 } ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size10_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , @@ -9201,27 +13259,27 @@ mux_tree_tapbuf_size10_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; mux_tree_tapbuf_size8_1_1 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size8_3 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size8_0_1 mux_bottom_track_9 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size8_0_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size8_mem_1_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -9232,31 +13290,31 @@ mux_tree_tapbuf_size8_mem_3 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_0_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; mux_tree_tapbuf_size14_1 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , - top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , - top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , + top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size14_0_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_40_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size14_mem_1 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -9267,61 +13325,62 @@ mux_tree_tapbuf_size14_mem_0_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_5_1 mux_top_track_16 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , +mux_tree_tapbuf_size7_5_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size7_8 mux_top_track_24 ( - .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size7_10 mux_top_track_24 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size7_0_4 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_38_[0] , chanx_left_in[5] , chanx_left_in[12] , + .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_1_4 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , - left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size7_2_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , - left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_3_1 mux_left_track_5 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size7_3_2 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , - left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_4_1 mux_left_track_7 ( + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( { ropt_net_158 } ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size7_4_2 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , - left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_mem_5_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size7_mem_5_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_8 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , @@ -9341,151 +13400,150 @@ mux_tree_tapbuf_size7_mem_2_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_3_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4_1 mem_left_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_4_2 mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size6_9 mux_top_track_32 ( - .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size6_10 mux_top_track_32 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size6_0_5 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_39_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size6_0_4 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size6_1_3 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[0] , chanx_left_in[7] , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size6_1_1 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size6_mem_9 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size6_mem_10 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_5 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem_0_4 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem_1_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size9_1 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[2] , chanx_left_in[9] , +mux_tree_tapbuf_size9_2 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size9_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size9_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_8 mux_left_track_9 ( +mux_tree_tapbuf_size4_9 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , - left_top_grid_pin_42_[0] } ) , + left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size4_0_3 mux_left_track_11 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size4_0_5 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , - left_top_grid_pin_43_[0] } ) , + left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_129 } ) , - .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size4_1_2 mux_left_track_13 ( + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size4_1_4 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , - left_top_grid_pin_44_[0] } ) , + left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size4_2_2 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size4_2_3 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , - left_top_grid_pin_45_[0] } ) , + left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size4_mem_8 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size4_mem_9 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_0_5 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1_2 mem_left_track_13 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_1_4 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_2_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; mux_tree_tapbuf_size3_0_5 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , - left_top_grid_pin_46_[0] } ) , + left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size3_1_4 mux_left_track_19 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size3_1_3 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , - left_top_grid_pin_47_[0] } ) , + left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size3_2_4 mux_left_track_21 ( + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size3_2_3 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , - left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3_3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , - left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size3_10 mux_left_track_25 ( + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size3_9 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , - left_top_grid_pin_42_[0] } ) , + left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_123 ) ) ; + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( { ropt_net_155 } ) , + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3_mem_0_5 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_1_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2_4 mem_left_track_21 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_2_3 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , @@ -9495,165 +13553,406 @@ mux_tree_tapbuf_size3_mem_3_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_10 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( { ropt_net_127 } ) , +mux_tree_tapbuf_size3_mem_9 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_155 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_156 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_126 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( ropt_net_127 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[1] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_129 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_157 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_top_in[4] ) , +mux_tree_tapbuf_size2_0_4 mux_left_track_29 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( { ropt_net_156 } ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_1_4 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_2_4 mux_left_track_33 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_3_4 mux_left_track_35 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_4_4 mux_left_track_37 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_21 mux_left_track_39 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size2_mem_0_4 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_4 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_4 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_4 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_21 mem_left_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( { ropt_net_154 } ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( - .A ( chany_bottom_in[13] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_136 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( left_top_grid_pin_43_[0] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_158 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_140 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_160 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_141 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_142 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_143 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_144 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_162 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_145 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_146 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_151 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_152 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_153 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_164 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_167 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_168 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_170 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_154 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_155 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_156 ) , .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( + .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_158 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_161 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_162 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chany_top_in[16] ) , + .X ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_165 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_168 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_169 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_170 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_179 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_180 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_80 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_89 ) , + .X ( chanx_left_out[13] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_7_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_37 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_28_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_28_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_27_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_27_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_26_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_26_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9665,11 +13964,60 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , - .X ( net_net_49 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_49 ( .A ( net_net_49 ) , - .X ( net_net_48 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( net_net_48 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__35 ( .A ( mem_out[1] ) , + .X ( net_net_71 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( net_net_71 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -9686,12 +14034,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_5_3 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_5_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9703,7 +14051,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -9720,12 +14068,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_3_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9737,12 +14085,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_2_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_2_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9754,12 +14102,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_1_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9771,12 +14119,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_0_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_0_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9788,12 +14136,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_11_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9805,7 +14153,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -9822,24 +14170,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -9856,7 +14187,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -9873,12 +14204,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_16_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9890,12 +14221,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_15_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9907,12 +14238,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_14_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9924,12 +14255,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_13_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9941,12 +14272,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_12_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9958,301 +14289,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_10_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_9_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_8_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_37 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_37 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_32_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_32_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_31_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_5_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_31_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_30_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_4_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_30_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_29_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_3_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_29_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_28_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_28_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_27_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_1_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_27_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_26_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_0_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_26_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - module const1_25_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10279,7 +14326,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_9_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10306,7 +14353,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10328,7 +14375,273 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_22_5 ( const1 ) ; +module const1_22_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_22_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_21_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_21_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_20_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_20_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_19_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_19_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_18_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_18_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_17_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_17_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_16_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_16_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_15_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_15_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_14_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_11_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_14_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_13_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_13_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_12_7 ( const1 ) ; output [0:0] const1 ; endmodule @@ -10343,7 +14656,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_22_5 const1_0_ ( +const1_12_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -10355,7 +14668,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_21_5 ( const1 ) ; +module const1_11_7 ( const1 ) ; output [0:0] const1 ; endmodule @@ -10370,7 +14683,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_21_5 const1_0_ ( +const1_11_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -10382,12 +14695,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_20_5 ( const1 ) ; +module const1_10_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_16_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10397,7 +14710,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_20_5 const1_0_ ( +const1_10_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -10409,12 +14722,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_19_5 ( const1 ) ; +module const1_9_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_15_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10424,7 +14737,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_19_5 const1_0_ ( +const1_9_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -10436,12 +14749,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_18_5 ( const1 ) ; +module const1_8_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_14_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10451,7 +14764,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_18_5 const1_0_ ( +const1_8_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -10463,12 +14776,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_17_5 ( const1 ) ; +module const1_7_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_13_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10478,7 +14791,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_17_5 const1_0_ ( +const1_7_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -10490,12 +14803,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_16_6 ( const1 ) ; +module const1_6_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_12_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10505,115 +14818,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_16_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_15_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_15_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_14_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_14_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_13_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_9_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_13_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_12_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_12_6 const1_0_ ( +const1_6_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -10637,12 +14842,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_3 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem_8 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10654,46 +14859,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_11_6 ( const1 ) ; +module const1_5_7 ( const1 ) ; output [0:0] const1 ; endmodule @@ -10709,7 +14880,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_11_6 const1_0_ ( +const1_5_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -10724,12 +14895,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_10_6 ( const1 ) ; +module const1_4_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10740,7 +14911,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_10_6 const1_0_ ( +const1_4_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -10755,71 +14926,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_9_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_9_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_8_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_8_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_65 ( .A ( BUF_net_41 ) , - .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_1_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem_7 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10833,7 +14940,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -10852,128 +14959,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_7_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5_1_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_7_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module const1_6_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5_0_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_6_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module const1_5_7 ( const1 ) ; +module const1_3_7 ( const1 ) ; output [0:0] const1 ; endmodule @@ -10991,7 +14982,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_5_7 const1_0_ ( +const1_3_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -11012,12 +15003,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_4_7 ( const1 ) ; +module const1_2_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_2_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size5_0_3 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11030,7 +15021,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_4_7 const1_0_ ( +const1_2_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -11051,7 +15042,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_1_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_9 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -11065,12 +15056,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_0_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -11084,141 +15075,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_3_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_1_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_3_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module const1_2_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_0_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_2_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - module const1_1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11261,7 +15128,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_2_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_0_3 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11273,6 +15140,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; const1_0_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; @@ -11289,41 +15157,41 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule -module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , top_right_grid_pin_1_ , chanx_left_in , - left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , - left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , - left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , - ccff_head , chany_top_out , chanx_left_out , ccff_tail ) ; +module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , + chany_top_out , chanx_left_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:0] top_right_grid_pin_1_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_left_out ; @@ -11353,10 +15221,6 @@ wire [0:1] mux_tree_tapbuf_size2_19_sram ; wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; @@ -11383,9 +15247,7 @@ wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; @@ -11398,116 +15260,73 @@ wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -mux_tree_tapbuf_size6_2_2 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , +mux_tree_tapbuf_size6_0_3 mux_top_track_0 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size6_8 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_109 } ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size6_9 mux_top_track_4 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size6_0_4 mux_left_track_1 ( - .in ( { chany_top_in[0] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size6_1_2 mux_left_track_5 ( - .in ( { chany_top_in[18] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size6_mem_2_2 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size6_mem_0_3 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_8 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem_9 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_2_2 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size5_0_3 mux_top_track_2 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_80 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; mux_tree_tapbuf_size5_7 mux_top_track_6 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size5_0_3 mux_left_track_3 ( - .in ( { chany_top_in[19] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_1_2 mux_left_track_7 ( - .in ( { chany_top_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_mem_2_2 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size5_mem_0_3 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , @@ -11517,439 +15336,362 @@ mux_tree_tapbuf_size5_mem_7 mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1_2 mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_9 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , +mux_tree_tapbuf_size3_8 mux_top_track_8 ( + .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( { ropt_net_89 } ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size3_2_3 mux_top_track_24 ( - .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size3_0_4 mux_top_track_24 ( + .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size3_1_3 mux_left_track_9 ( - .in ( { chany_top_in[16] , left_top_grid_pin_42_[0] , - left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_0_4 mux_left_track_25 ( - .in ( { chany_top_in[8] , left_top_grid_pin_42_[0] , - left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size3_mem_9 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size3_mem_8 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2_3 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_0_4 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_3 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_8_1 mux_top_track_10 ( - .in ( { top_left_grid_pin_35_[0] , chanx_left_in[15] } ) , +mux_tree_tapbuf_size2_12_2 mux_top_track_10 ( + .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size2_9_1 mux_top_track_12 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[14] } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_13_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size2_10_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[13] } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_14_2 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_11 mux_top_track_16 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[12] } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_15_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_12 mux_top_track_18 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_16_1 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_20 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[10] } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_17 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_22 ( - .in ( { top_left_grid_pin_41_[0] , chanx_left_in[9] } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_18 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_15 mux_top_track_26 ( - .in ( { top_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_20 mux_top_track_26 ( + .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_16 mux_top_track_28 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[6] } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_11_2 mux_left_track_9 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_17 mux_top_track_30 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[5] } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_0_3 mux_left_track_11 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chany_top_out[15] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_32 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[4] } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_1_3 mux_left_track_13 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_19 mux_top_track_34 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[3] } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_2_3 mux_left_track_15 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chany_top_out[17] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_20 mux_top_track_36 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[2] } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_3_3 mux_left_track_17 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_21 mux_top_track_38 ( - .in ( { top_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_4_3 mux_left_track_19 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_0_4 mux_left_track_11 ( - .in ( { chany_top_in[15] , left_top_grid_pin_43_[0] } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_5_2 mux_left_track_25 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_1_4 mux_left_track_13 ( - .in ( { chany_top_in[14] , left_top_grid_pin_44_[0] } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_6_2 mux_left_track_27 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_2_4 mux_left_track_15 ( - .in ( { chany_top_in[13] , left_top_grid_pin_45_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( { ropt_net_108 } ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_7_2 mux_left_track_29 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_3_4 mux_left_track_17 ( - .in ( { chany_top_in[12] , left_top_grid_pin_46_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( { ropt_net_103 } ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_8_2 mux_left_track_31 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_4_3 mux_left_track_19 ( - .in ( { chany_top_in[11] , left_top_grid_pin_47_[0] } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_9_2 mux_left_track_33 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_5_3 mux_left_track_21 ( - .in ( { chany_top_in[10] , left_top_grid_pin_48_[0] } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size2_10_2 mux_left_track_35 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_6_2 mux_left_track_23 ( - .in ( { chany_top_in[9] , left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_7_1 mux_left_track_27 ( - .in ( { chany_top_in[7] , left_top_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_mem_8_1 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size2_mem_12_2 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9_1 mem_top_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14_2 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_top_track_16 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_15_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_18 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_16_1 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_20 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_top_track_26 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_20 mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_top_track_28 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , +mux_tree_tapbuf_size2_mem_11_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_top_track_30 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_32 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1_3 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_top_track_34 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_top_track_36 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_21 mem_top_track_38 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0_4 mem_left_track_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , +mux_tree_tapbuf_size2_mem_5_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_4 mem_left_track_13 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_6_2 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_4 mem_left_track_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_7_2 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_8_2 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_9_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_3 mem_left_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , +mux_tree_tapbuf_size2_mem_10_2 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( { ropt_net_105 } ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6_2 mem_left_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7_1 mem_left_track_27 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( { ropt_net_88 } ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_676 ( .A ( ropt_net_91 ) , +mux_tree_tapbuf_size4_0_4 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_1_3 mux_left_track_3 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_2_2 mux_left_track_5 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size4_8 mux_left_track_7 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_mem_0_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_8 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_118 ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_79 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_678 ( .A ( ropt_net_93 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_679 ( .A ( ropt_net_94 ) , +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_119 ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_95 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_93 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_84 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_63 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_85 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_85 ) , +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_103 ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_left_in[4] ) , + .X ( BUF_net_56 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_left_in[5] ) , + .X ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_66 ( .A ( BUF_net_56 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_84 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( BUF_net_57 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_86 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_67 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_672 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_88 ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_89 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_90 ) , - .X ( ropt_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_123 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_125 ) , + .X ( chanx_left_out[10] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_8 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_4_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -11959,34 +15701,67 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; const1_36 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module const1_32 ( const1 ) ; +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_26_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_5_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11996,7 +15771,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_32 const1_0_ ( +const1_26_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -12008,13 +15783,115 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_31_1 ( const1 ) ; +module mux_tree_tapbuf_size3_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_25_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; +module mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; @@ -12022,26 +15899,61 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_31_1 const1_0_ ( +const1_25_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_24_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_24_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; endmodule -module const1_30_2 ( const1 ) ; +module const1_23_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; +module mux_tree_tapbuf_size3_3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; @@ -12049,26 +15961,30 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_30_2 const1_0_ ( +const1_23_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; endmodule -module const1_29_2 ( const1 ) ; +module const1_22_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; +module mux_tree_tapbuf_size3_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; @@ -12076,49 +15992,30 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_29_2 const1_0_ ( +const1_22_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; endmodule -module const1_28_2 ( const1 ) ; +module const1_21_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -const1_28_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_27_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_0_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; +module mux_tree_tapbuf_size3_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; @@ -12126,16 +16023,89 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_27_2 const1_0_ ( +const1_21_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_20_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_20_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -12153,73 +16123,82 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__52 ( .A ( mem_out[2] ) , - .X ( net_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_95 ( .A ( net_net_95 ) , - .X ( net_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_130 ( .A ( net_net_94 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; +module const1_19_5 ( const1 ) ; +output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module mux_tree_tapbuf_size4_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_19_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; +module const1_18_6 ( const1 ) ; +output [0:0] const1 ; endmodule -module const1_26_4 ( const1 ) ; +module mux_tree_tapbuf_size4_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_18_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_17_6 ( const1 ) ; output [0:0] const1 ; endmodule @@ -12236,7 +16215,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_26_4 const1_0_ ( +const1_17_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -12254,112 +16233,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_25_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size4_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -const1_25_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module const1_24_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size4_0_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -const1_24_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_23_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size4_2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -const1_23_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem_6 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -12373,7 +16247,103 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_16_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_16_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -12392,7 +16362,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -12411,7 +16381,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -12430,17 +16400,55 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_22_4 ( const1 ) ; +module mux_tree_tapbuf_size7_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_15_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_5_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -12455,7 +16463,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_22_4 const1_0_ ( +const1_15_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -12477,14 +16485,106 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_136 ( .A ( BUF_net_69 ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_21_4 ( const1 ) ; +module const1_14_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_14_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_13_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_13_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_12_6 ( const1 ) ; output [0:0] const1 ; endmodule @@ -12504,7 +16604,54 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_21_4 const1_0_ ( +const1_12_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_11_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_11_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -12526,57 +16673,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_68 ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_20_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size7_1_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_20_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_19_4 ( const1 ) ; +module const1_10_6 ( const1 ) ; output [0:0] const1 ; endmodule @@ -12596,8 +16698,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_19_4 const1_0_ ( +const1_10_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12618,487 +16722,63 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( +endmodule + + +module const1_9_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_9_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_5_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__44 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__43 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__42 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__41 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_18_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_18_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule -module const1_17_4 ( const1 ) ; +module const1_8_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_17_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_16_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_16_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_15_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_15_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_14_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_1_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_14_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_13_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_0_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_13_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_12_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_12_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__32 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__31 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_11_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5_2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; +module mux_tree_tapbuf_size7_6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -13109,37 +16789,87 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_11_5 const1_0_ ( +const1_8_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule -module const1_10_5 ( const1 ) ; +module mux_tree_tapbuf_size8_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_7_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size8_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -13148,142 +16878,37 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_10_5 const1_0_ ( +const1_7_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module const1_9_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5_3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_9_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module const1_8_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5_0_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_8_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module const1_7_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_7_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -13292,10 +16917,10 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -13304,25 +16929,79 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; const1_6_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -13331,10 +17010,223 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module const1_4_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_3_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -13343,8 +17235,66 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -const1_5_6 const1_0_ ( +const1_3_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module const1_2_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_2_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -13354,234 +17304,23 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__30 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__29 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__28 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__27 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__26 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_4_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_4_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module const1_3_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_0_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_3_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module const1_2_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_2_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -13590,49 +17329,10 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_0_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -13642,11 +17342,91 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_0_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; const1_0_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -13657,64 +17437,96 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; endmodule module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - chany_bottom_in , bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , - bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , - bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , - bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , - left_top_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , - chanx_left_out , ccff_tail ) ; + right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -13727,62 +17539,26 @@ wire [0:1] mux_tree_tapbuf_size3_4_sram ; wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_5_sram ; -wire [0:2] mux_tree_tapbuf_size5_5_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_6_sram ; -wire [0:2] mux_tree_tapbuf_size5_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; @@ -13791,522 +17567,542 @@ wire [0:2] mux_tree_tapbuf_size7_2_sram ; wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; -mux_tree_tapbuf_size6_2_1 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[5] , +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_11 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_3_1 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[3] , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size10_mem_11 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size9 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size9_0 mux_left_track_1 ( + .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , + chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size9_1 mux_left_track_3 ( + .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[7] , chany_bottom_in[14] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; +mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; +mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) ) ; +mux_tree_tapbuf_size14 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_7 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[2] , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_2 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_0_3 mux_left_track_5 ( - .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size6_1_1 mux_left_track_9 ( + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size8_0_1 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size6_mem_2_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_3_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_7 mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; -mux_tree_tapbuf_size5_5 mux_right_track_2 ( - .in ( { chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_172 } ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size5_4 mux_right_track_16 ( - .in ( { chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , + chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_6_1 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , + chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size5_6 mux_right_track_24 ( - .in ( { chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size5_0_2 mux_left_track_1 ( - .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , - chany_bottom_in[13] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size5_3_1 mux_left_track_3 ( - .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[7] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size5_1_1 mux_left_track_17 ( - .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_5_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size5_2_1 mux_left_track_25 ( - .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , - chany_bottom_in[11] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_6_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size5_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_6 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_3_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_5_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_2_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_6_sram_inv ) ) ; -mux_tree_tapbuf_size3_8 mux_right_track_32 ( - .in ( { chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size3_0_3 mux_bottom_track_13 ( - .in ( { chanx_right_in[10] , bottom_left_grid_pin_36_[0] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size3_1_2 mux_bottom_track_15 ( - .in ( { chanx_right_in[12] , bottom_left_grid_pin_37_[0] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size3_2_2 mux_bottom_track_17 ( - .in ( { chanx_right_in[13] , bottom_left_grid_pin_38_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size3_3_2 mux_bottom_track_19 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_39_[0] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_4_1 mux_bottom_track_21 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_40_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_5_1 mux_bottom_track_23 ( - .in ( { chanx_right_in[17] , bottom_left_grid_pin_41_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_mem_8 mem_right_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0_3 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3_2 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4_1 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_5_1 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_0_3 mux_bottom_track_1 ( - .in ( { chanx_right_in[2] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( { ropt_net_175 } ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size7_1_3 mux_bottom_track_3 ( - .in ( { chanx_right_in[4] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_9 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , + chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_2_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[5] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_0_3 mux_bottom_track_1 ( + .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( { ropt_net_207 } ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_7 mux_bottom_track_7 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size7_1_3 mux_bottom_track_3 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_mem_0_3 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_175 } ) , + .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_3_1 mux_bottom_track_7 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_4_1 mux_left_track_17 ( + .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_5_1 mux_left_track_25 ( + .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , + chany_bottom_in[11] , chany_bottom_in[18] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( { ropt_net_165 } ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size7_mem_6_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1_3 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_9 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , +mux_tree_tapbuf_size7_mem_0_3 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_7 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_1_3 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size4_2_1 mux_bottom_track_9 ( - .in ( { chanx_right_in[8] , bottom_left_grid_pin_34_[0] , +mux_tree_tapbuf_size7_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_3_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_4_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_5_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; +mux_tree_tapbuf_size5_6 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size5_mem_6 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_7 mux_bottom_track_9 ( + .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size4_0_2 mux_bottom_track_11 ( - .in ( { chanx_right_in[9] , bottom_left_grid_pin_35_[0] , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size4_0_3 mux_bottom_track_11 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_176 } ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size4_1_1 mux_bottom_track_25 ( + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size4_1_2 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , - bottom_left_grid_pin_34_[0] , chanx_left_in[18] } ) , + bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size4_7 mux_left_track_33 ( - .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , - chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size4_mem_2_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size4_mem_7 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_2 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_0_3 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , +mux_tree_tapbuf_size4_mem_1_2 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_7 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_0_3 mux_bottom_track_27 ( - .in ( { chanx_right_in[15] , bottom_left_grid_pin_35_[0] } ) , +mux_tree_tapbuf_size3_0_3 mux_bottom_track_13 ( + .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_1_2 mux_bottom_track_15 ( + .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_2_2 mux_bottom_track_17 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_3_2 mux_bottom_track_19 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_4_1 mux_bottom_track_21 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size3_7 mux_bottom_track_23 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( { ropt_net_176 } ) , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size3_mem_0_3 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3_2 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4_1 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_7 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_19 mux_bottom_track_27 ( + .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size2_1_3 mux_bottom_track_29 ( - .in ( { chanx_right_in[11] , bottom_left_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size2_2_3 mux_bottom_track_31 ( - .in ( { chanx_right_in[7] , bottom_left_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_3_3 mux_bottom_track_33 ( - .in ( { chanx_right_in[3] , bottom_left_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_4_2 mux_bottom_track_35 ( - .in ( { chanx_right_in[1] , bottom_left_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_5_2 mux_bottom_track_37 ( - .in ( { chanx_right_in[0] , bottom_left_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size2_14 mux_bottom_track_39 ( - .in ( { bottom_left_grid_pin_41_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size2_mem_0_3 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_3 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_3 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_2 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_2 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_162 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_164 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_169 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_172 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_left_in[5] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_173 ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_175 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_176 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_197 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_198 ) , +mux_tree_tapbuf_size6_8 mux_left_track_33 ( + .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , + chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size6_mem_8 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_181 } ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_199 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( chanx_left_in[4] ) , - .X ( BUF_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_185 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_187 ) , +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_165 ) , .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , - .X ( BUF_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_188 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[10] ) , .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_190 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_191 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_192 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_204 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( BUF_net_83 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_115 ( .A ( aps_rename_2_ ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_116 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_205 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_206 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_166 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[12] ) , .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_92 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_170 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_172 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_175 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_176 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_200 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[14] ) , + .X ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[17] ) , + .X ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[9] ) , + .X ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_181 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_182 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_183 ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_184 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_186 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_187 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_188 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_189 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_190 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_205 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_206 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_207 ) , .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_208 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_212 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( BUF_net_77 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_79 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_184 ) ) ; endmodule @@ -14324,7 +18120,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_28__79 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__79 ( .A ( mem_out[2] ) , + .X ( net_net_87 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -14367,7 +18165,7 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__77 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_8 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14532,7 +18330,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -14632,7 +18430,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__73 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -14805,7 +18603,7 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__65 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14885,7 +18683,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_22_3 ( const1 ) ; +module const1_22_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -14908,7 +18706,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_22_3 const1_0_ ( +const1_22_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -14944,7 +18742,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_21_3 ( const1 ) ; +module const1_21_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -14967,7 +18765,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_21_3 const1_0_ ( +const1_21_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -15003,7 +18801,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_20_3 ( const1 ) ; +module const1_20_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -15026,7 +18824,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_20_3 const1_0_ ( +const1_20_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -15062,7 +18860,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_19_3 ( const1 ) ; +module const1_19_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -15085,7 +18883,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_19_3 const1_0_ ( +const1_19_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -15121,7 +18919,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_18_3 ( const1 ) ; +module const1_18_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -15144,7 +18942,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_18_3 const1_0_ ( +const1_18_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -15180,7 +18978,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_17_3 ( const1 ) ; +module const1_17_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -15203,7 +19001,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_17_3 const1_0_ ( +const1_17_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -15239,7 +19037,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_16_4 ( const1 ) ; +module const1_16_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -15262,7 +19060,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_16_4 const1_0_ ( +const1_16_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -15298,7 +19096,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_15_4 ( const1 ) ; +module const1_15_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -15321,7 +19119,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_15_4 const1_0_ ( +const1_15_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -15357,7 +19155,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_14_4 ( const1 ) ; +module const1_14_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -15380,7 +19178,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_14_4 const1_0_ ( +const1_14_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -15416,7 +19214,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_13_4 ( const1 ) ; +module const1_13_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -15439,7 +19237,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_13_4 const1_0_ ( +const1_13_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -15475,12 +19273,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_12_4 ( const1 ) ; +module const1_12_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -15498,7 +19296,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_12_4 const1_0_ ( +const1_12_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -15626,7 +19424,7 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__60 ( .A ( mem_out[4] ) , endmodule -module const1_11_4 ( const1 ) ; +module const1_11_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -15655,7 +19453,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_11_4 const1_0_ ( +const1_11_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; @@ -15709,7 +19507,7 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( endmodule -module const1_10_4 ( const1 ) ; +module const1_10_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -15737,7 +19535,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_10_4 const1_0_ ( +const1_10_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -15788,7 +19586,7 @@ sky130_fd_sc_hd__mux2_4 mux_l5_in_0_ ( endmodule -module const1_9_4 ( const1 ) ; +module const1_9_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -15817,7 +19615,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_9_4 const1_0_ ( +const1_9_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; @@ -15871,7 +19669,7 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( endmodule -module const1_8_4 ( const1 ) ; +module const1_8_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -15900,7 +19698,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_8_4 const1_0_ ( +const1_8_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; @@ -16122,7 +19920,7 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__52 ( .A ( mem_out[3] ) , endmodule -module const1_7_4 ( const1 ) ; +module const1_7_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -16147,7 +19945,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_7_4 const1_0_ ( +const1_7_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -16538,6 +20336,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -16550,6 +20349,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; const1_1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -16581,9 +20382,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; endmodule @@ -16654,58 +20456,60 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , - right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , - right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , - right_top_grid_pin_49_ , chany_bottom_in , bottom_left_grid_pin_34_ , - bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , - bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , - bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , - bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , - left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , - left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , - left_top_grid_pin_49_ , ccff_head , chany_top_out , chanx_right_out , +module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , + right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , + bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; @@ -16798,77 +20602,77 @@ wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; mux_tree_tapbuf_size12_6 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size12 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , - right_top_grid_pin_42_[0] , right_top_grid_pin_44_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_48_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , - right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , - bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , - chany_bottom_in[12] , chany_bottom_in[19] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] } ) , + chany_bottom_in[12] , chany_bottom_in[19] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[4] , chany_bottom_in[13] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[4] , chany_bottom_in[13] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -16910,49 +20714,49 @@ mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; mux_tree_tapbuf_size16 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , - top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , - top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , + top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , - right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , - chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_40_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[5] , chanx_left_in[7] , + chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[5] , chany_bottom_in[14] , left_top_grid_pin_42_[0] , - left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[5] , chany_bottom_in[14] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -16973,103 +20777,103 @@ mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_1 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , +mux_tree_tapbuf_size10 mux_top_track_8 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_9 mux_top_track_16 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_10 mux_top_track_24 ( - .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , - right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , - right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , - chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_38_[0] , chanx_left_in[6] , chanx_left_in[11] , + chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_39_[0] , chanx_left_in[8] , chanx_left_in[15] , + chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[9] , chanx_left_in[18] , + chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , - chany_bottom_in[6] , chany_bottom_in[16] , left_top_grid_pin_42_[0] , - left_top_grid_pin_46_[0] } ) , + chany_bottom_in[6] , chany_bottom_in[16] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , - chany_bottom_in[8] , chany_bottom_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_47_[0] } ) , + chany_bottom_in[8] , chany_bottom_in[17] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , - chany_bottom_in[11] , chany_bottom_in[18] , left_top_grid_pin_44_[0] , - left_top_grid_pin_48_[0] } ) , + chany_bottom_in[11] , chany_bottom_in[18] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_147 ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , @@ -17129,35 +20933,35 @@ mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; -mux_tree_tapbuf_size7_6 mux_top_track_32 ( - .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size7_8 mux_top_track_32 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size7_2_1 mux_right_track_32 ( - .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_45_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[10] , - chany_bottom_in[19] , chanx_left_in[10] } ) , + .in ( { chany_top_in[10] , chany_top_in[15] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size7_0_2 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size7_1_2 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , - chany_bottom_in[10] , chany_bottom_in[15] , left_top_grid_pin_45_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[10] , chany_bottom_in[15] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_146 ) ) ; -mux_tree_tapbuf_size7_mem_6 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size7_mem_8 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , @@ -17173,157 +20977,142 @@ mux_tree_tapbuf_size7_mem_0_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; mux_tree_tapbuf_size7_mem_1_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( { ropt_net_130 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__2 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chany_top_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_top_in[16] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_148 ) , - .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[6] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , .X ( chanx_left_out[13] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_130 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_132 ) , + .X ( ropt_net_133 ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_152 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_153 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_155 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_42__41 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_158 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_41__40 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_159 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_44__43 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_87 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[6] ) , - .X ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_100 ( .A ( chany_top_in[6] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_105 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_106 ( .A ( BUF_net_90 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_115 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_121 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_123 ( .A ( aps_rename_3_ ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_112 ( .A ( aps_rename_1_ ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[6] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem_0_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; @@ -17331,9 +21120,28 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( net_net_105 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -17343,10 +21151,10 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; +module mux_tree_tapbuf_size5_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; @@ -17355,45 +21163,64 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; const1_34 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_26_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_26_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; endmodule @@ -17411,12 +21238,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__58 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_6 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_7 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -17430,12 +21257,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_31 ( const1 ) ; +module const1_25_2 ( const1 ) ; output [0:0] const1 ; endmodule @@ -17452,12 +21279,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_31 const1_0_ ( +const1_25_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -17471,19 +21295,18 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule -module const1_30_1 ( const1 ) ; +module const1_24_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -17495,9 +21318,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_30_1 const1_0_ ( +const1_24_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -17512,16 +21334,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -17537,12 +21356,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -17558,530 +21377,138 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_29_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_29_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module const1_28_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_28_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_27_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -const1_27_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module const1_26_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -const1_26_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_25_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_25_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_24_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_24_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - module const1_23_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; const1_23_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; endmodule -module const1_22_2 ( const1 ) ; +module const1_22_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_22_2 const1_0_ ( +const1_22_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; endmodule -module const1_21_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_0_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_21_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_7 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18093,11 +21520,38 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule +module const1_21_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_21_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -18110,7 +21564,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18127,7 +21581,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18144,7 +21598,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18161,7 +21615,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18178,7 +21632,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18195,7 +21649,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18212,43 +21666,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_20_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_20_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_19_2 ( const1 ) ; +module const1_20_3 ( const1 ) ; output [0:0] const1 ; endmodule @@ -18264,7 +21687,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_19_2 const1_0_ ( +const1_20_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -18279,7 +21702,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_18_2 ( const1 ) ; +module const1_19_3 ( const1 ) ; output [0:0] const1 ; endmodule @@ -18295,7 +21718,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_18_2 const1_0_ ( +const1_19_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -18310,7 +21733,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_17_2 ( const1 ) ; +module const1_18_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -18326,8 +21749,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_17_2 const1_0_ ( +const1_18_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -18336,12 +21761,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_16_3 ( const1 ) ; +module const1_17_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -18357,7 +21780,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_16_3 const1_0_ ( +const1_17_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -18372,7 +21795,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_15_3 ( const1 ) ; +module const1_16_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -18388,7 +21811,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_15_3 const1_0_ ( +const1_16_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -18403,7 +21826,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_14_3 ( const1 ) ; +module const1_15_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -18419,7 +21842,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_14_3 const1_0_ ( +const1_15_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -18434,7 +21857,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_13_3 ( const1 ) ; +module const1_14_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -18450,7 +21873,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_13_3 const1_0_ ( +const1_14_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -18465,7 +21888,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_0_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18479,7 +21902,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18498,17 +21921,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_12_3 ( const1 ) ; +module const1_13_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_0_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_0_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18520,7 +21943,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_12_3 const1_0_ ( +const1_13_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -18538,7 +21961,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_11_3 ( const1 ) ; +module const1_12_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -18555,7 +21978,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_11_3 const1_0_ ( +const1_12_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -18573,25 +21996,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size7_mem_0_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -18606,26 +22010,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18644,12 +22029,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_1_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18663,26 +22048,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18701,59 +22067,107 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_10_3 ( const1 ) ; -output [0:0] const1 ; +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_10_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module const1_9_3 ( const1 ) ; +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -18773,7 +22187,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_9_3 const1_0_ ( +const1_11_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -18800,54 +22214,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_8_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_8_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module const1_7_3 ( const1 ) ; +module const1_10_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -18867,7 +22234,148 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_7_3 const1_0_ ( +const1_10_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_9_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_9_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_8_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_8_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_7_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_7_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -18899,7 +22407,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18916,6 +22424,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; const1_6_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -18936,10 +22446,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_104 ( .A ( BUF_net_61 ) , - .X ( out[0] ) ) ; endmodule @@ -18948,7 +22454,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18995,7 +22501,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -19037,24 +22543,50 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module const1_3_4 ( const1 ) ; +output [0:0] const1 ; +endmodule -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + +module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_3_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule @@ -19074,12 +22606,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19095,7 +22627,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19116,62 +22648,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_3_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_3_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - module const1_2_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -19228,7 +22709,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19325,77 +22806,61 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , - right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , - right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , - right_top_grid_pin_49_ , right_bottom_grid_pin_1_ , chanx_left_in , - left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , - left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , - left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , - ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail ) ; +module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , + left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , + left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , + left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -19410,8 +22875,6 @@ wire [0:1] mux_tree_tapbuf_size3_5_sram ; wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_6_sram ; wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_7_sram ; -wire [0:1] mux_tree_tapbuf_size3_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -19419,18 +22882,23 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; @@ -19445,6 +22913,10 @@ wire [0:2] mux_tree_tapbuf_size7_5_sram ; wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -19452,131 +22924,126 @@ wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; + +assign SC_IN_TOP = SC_IN_BOT ; mux_tree_tapbuf_size8 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size8_2 mux_right_track_8 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , - right_bottom_grid_pin_1_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size8_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_3 ( - .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[13] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size8_1 mux_left_track_9 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - chanx_right_in[6] , chanx_right_in[16] , left_top_grid_pin_42_[0] , - left_top_grid_pin_46_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_126 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , +mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_4 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size7_6 mux_top_track_2 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size7_5 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_7 mux_top_track_4 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_130 ) ) ; mux_tree_tapbuf_size7_2 mux_top_track_6 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_2 mux_right_track_16 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , - chanx_left_in[8] , chanx_left_in[17] } ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_3 mux_right_track_0 ( + .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_3 mux_right_track_24 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , - chanx_left_in[9] , chanx_left_in[18] } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size7_5 mux_right_track_8 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , + chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_0_1 mux_left_track_17 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_47_[0] } ) , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , + chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_1_1 mux_left_track_25 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - chanx_right_in[9] , chanx_right_in[18] , left_top_grid_pin_44_[0] , - left_top_grid_pin_48_[0] } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_1_1 mux_left_track_3 ( + .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[13] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_2 mux_left_track_9 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_0_1 mux_left_track_17 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , @@ -19586,96 +23053,100 @@ mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_right_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , +mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , +mux_tree_tapbuf_size7_mem_1_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) ) ; mux_tree_tapbuf_size4_6 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , chanx_right_in[8] , + .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_0_1 mux_top_track_10 ( - .in ( { top_left_grid_pin_35_[0] , chanx_right_in[9] , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size4_0_2 mux_top_track_10 ( + .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_127 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4_mem_6 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_1 mem_top_track_10 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_0_2 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; mux_tree_tapbuf_size3_0_2 mux_top_track_12 ( - .in ( { top_left_grid_pin_36_[0] , chanx_right_in[10] , + .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_1_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_37_[0] , chanx_right_in[12] , + .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_2_1 mux_top_track_16 ( - .in ( { top_left_grid_pin_38_[0] , chanx_right_in[13] , + .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_3_1 mux_top_track_18 ( - .in ( { top_left_grid_pin_39_[0] , chanx_right_in[14] , + .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_4 mux_top_track_20 ( - .in ( { top_left_grid_pin_40_[0] , chanx_right_in[16] , + .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( { ropt_net_134 } ) , - .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_5 mux_top_track_22 ( - .in ( { top_left_grid_pin_41_[0] , chanx_right_in[17] , + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_6 mux_top_track_24 ( - .in ( { top_left_grid_pin_34_[0] , chanx_right_in[18] , + .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3_7 mux_top_track_38 ( - .in ( { top_left_grid_pin_41_[0] , chanx_right_in[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size3_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_7_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size3_mem_0_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -19711,290 +23182,230 @@ mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_7 mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_0_2 mux_top_track_28 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[19] } ) , +mux_tree_tapbuf_size2_18 mux_top_track_38 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_1_2 mux_top_track_30 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[15] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_2_2 mux_top_track_32 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_3_2 mux_top_track_34 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[17] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_36 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_mem_0_2 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size2_mem_18 mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_2 mem_top_track_30 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_2 mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_2 mem_top_track_34 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_36 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size9_0 mux_right_track_0 ( - .in ( { chany_top_in[6] , chany_top_in[13] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size9 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; -mux_tree_tapbuf_size14 mux_right_track_4 ( +mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , - right_bottom_grid_pin_1_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size14_0 mux_left_track_5 ( + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , + chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - chanx_right_in[5] , chanx_right_in[14] , left_top_grid_pin_42_[0] , - left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , - left_top_grid_pin_49_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_6 mux_right_track_32 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - right_top_grid_pin_45_[0] , right_top_grid_pin_49_[0] , - chanx_left_in[10] } ) , + chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) ) ; +mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_7 mux_right_track_24 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_129 } ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size6_0_2 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - chanx_right_in[10] , left_top_grid_pin_45_[0] , - left_top_grid_pin_49_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size6_0_2 mux_left_track_25 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_mem_6 mem_right_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size6_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_131 } ) , +mux_tree_tapbuf_size6_mem_0_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size10 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - chanx_right_in[2] , chanx_right_in[12] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5_5 mux_right_track_32 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size5_0_2 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size5_mem_5 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_35_[0] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[16] ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( { ropt_net_139 } ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_129 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_163 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[7] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_156 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_157 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_134 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_136 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_158 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_159 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_160 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_161 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_162 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_145 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_146 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_164 ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_147 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_148 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_149 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_150 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_168 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_169 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_170 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_171 ) , .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_172 ) , - .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , + .X ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( + .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_153 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_176 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_154 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_155 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_107 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_157 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_114 ( .A ( BUF_net_70 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , + .X ( ropt_net_164 ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_1_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20006,14 +23417,14 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__39 ( .A ( mem_out[1] ) , - .X ( net_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_71 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_59 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( net_net_59 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_3_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20025,12 +23436,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_2_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_2_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20042,12 +23453,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_0_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20059,12 +23470,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_5_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20076,12 +23487,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20093,7 +23504,160 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20110,12 +23674,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_5_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20127,7 +23691,24 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20137,7 +23718,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_1_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20159,12 +23740,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_6_3 ( const1 ) ; +module const1_22_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20174,7 +23755,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_6_3 const1_0_ ( +const1_22_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -20186,12 +23767,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_5_3 ( const1 ) ; +module const1_21_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20201,7 +23782,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_5_3 const1_0_ ( +const1_21_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -20213,12 +23794,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_4_3 ( const1 ) ; +module const1_20_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_0_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_0_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20228,7 +23809,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_4_3 const1_0_ ( +const1_20_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -20240,12 +23821,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_3_3 ( const1 ) ; +module const1_19_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_5_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20255,7 +23836,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_3_3 const1_0_ ( +const1_19_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -20267,12 +23848,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_2_3 ( const1 ) ; +module const1_18_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20282,7 +23863,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_2_3 const1_0_ ( +const1_18_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -20294,7 +23875,250 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_1_3 ( const1 ) ; +module const1_17_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_17_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_16_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_14_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_16_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_15_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_13_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_15_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_14_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_14_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_13_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_11_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_13_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_12_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_12_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_11_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_11_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_10_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_10_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_9_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_9_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_8_3 ( const1 ) ; output [0:0] const1 ; endmodule @@ -20309,7 +24133,36 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_1_3 const1_0_ ( +const1_8_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_75 ( .A ( BUF_net_43 ) , + .X ( out[0] ) ) ; +endmodule + + +module const1_7_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_7_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -20321,12 +24174,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_0_3 ( const1 ) ; +module const1_6_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20336,329 +24189,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_0_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , - chany_bottom_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; - -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; - -mux_tree_tapbuf_size2_4_1 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_6_1 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_12 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_5_1 mux_right_track_24 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_0_1 mux_bottom_track_1 ( - .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_2_1 mux_bottom_track_5 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_3_1 mux_bottom_track_9 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_1_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_mem_4_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_1 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_103 } ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_133 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_135 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_136 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_102 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_103 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[3] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_702 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chany_bottom_in[5] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_113 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_114 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_116 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_117 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_118 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_120 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_121 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_122 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( .A ( chanx_right_in[2] ) , - .X ( BUF_net_42 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_140 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_123 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_143 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_124 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_145 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_146 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_57 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_148 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_125 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_126 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_127 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_128 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_129 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( BUF_net_42 ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_83 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_91 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_92 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_126 ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_32 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_32 const1_0_ ( +const1_6_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -20682,9 +24213,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__57 ( .A ( mem_out[1] ) , - .X ( net_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( net_net_101 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20701,7 +24230,1039 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_5_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_5_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_4_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_4_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_3_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_3_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_2_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_2_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_0_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_0_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; + +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size6_0_1 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size6_6 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size6_mem_0_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_6 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size5_4 mux_right_track_6 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size5_mem_0_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_4 mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_4 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size3_0_1 mux_right_track_24 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0_1 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_4_2 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_5_1 mux_right_track_12 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_6_1 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_7_1 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_8_1 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_9_1 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size2_10_1 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_11_1 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_12_1 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_13_1 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_14_1 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_15 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_16 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_17 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_0_2 mux_bottom_track_1 ( + .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_3_2 mux_bottom_track_9 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_1_2 mux_bottom_track_25 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_mem_4_2 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6_1 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_8_1 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9_1 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10_1 mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_11_1 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13_1 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_17 mem_right_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0_2 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_2 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( { ropt_net_106 } ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( ropt_net_98 ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[7] ) , + .X ( BUF_net_52 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_115 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_101 ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_102 ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_106 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_72 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_78 ( .A ( BUF_net_52 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_79 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_80 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , + .X ( ropt_net_114 ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_30_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_30_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_29_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_29_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_28_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_28_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_27_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_27_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , + .X ( net_net_82 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( net_net_82 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20718,7 +25279,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20735,7 +25296,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20752,7 +25313,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20762,7 +25323,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20793,7 +25354,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20926,7 +25487,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20945,7 +25506,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20964,7 +25525,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21124,12 +25685,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21143,12 +25704,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_1_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21162,12 +25723,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_0_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21181,7 +25742,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21200,12 +25761,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21219,7 +25780,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21238,12 +25799,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_18_1 ( const1 ) ; +module const1_18_2 ( const1 ) ; output [0:0] const1 ; endmodule @@ -21260,7 +25821,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_18_1 const1_0_ ( +const1_18_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -21278,12 +25839,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_17_1 ( const1 ) ; +module const1_17_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21295,7 +25856,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_17_1 const1_0_ ( +const1_17_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -21318,7 +25879,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_1_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21332,8 +25893,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; const1_16_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -21345,6 +25904,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -21353,7 +25914,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_0_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21423,7 +25984,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21502,12 +26063,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21521,7 +26082,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21540,7 +26101,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21559,12 +26120,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21578,7 +26139,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__38 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21627,7 +26188,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_0_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21744,7 +26305,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21792,7 +26353,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__37 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21811,12 +26372,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__36 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21830,7 +26391,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__35 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21849,12 +26410,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__34 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21868,7 +26429,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__33 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21887,7 +26448,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__32 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21906,7 +26467,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__31 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22002,7 +26563,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22088,7 +26649,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22213,23 +26774,24 @@ endmodule module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , - right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , - right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , - chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , - chanx_right_out , chany_bottom_out , ccff_tail ) ; + chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_left_grid_pin_1_ ; input [0:0] ccff_head ; @@ -22240,7 +26802,22 @@ output [0:0] ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -22327,44 +26904,44 @@ mux_tree_tapbuf_size6_4 mux_top_track_0 ( chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size6_1 mux_top_track_8 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size6_3 mux_right_track_0 ( - .in ( { chany_top_in[2] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , chany_bottom_in[2] } ) , + .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size6_0_1 mux_bottom_track_1 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_121 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_121 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -22375,7 +26952,7 @@ mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_top_track_8 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , @@ -22385,8 +26962,8 @@ mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , +mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; @@ -22400,37 +26977,37 @@ mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; -mux_tree_tapbuf_size5_1 mux_top_track_2 ( +mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size5_0_1 mux_bottom_track_17 ( + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , @@ -22445,7 +27022,7 @@ mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0_1 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , @@ -22460,49 +27037,50 @@ mux_tree_tapbuf_size4_5 mux_top_track_24 ( chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size4 mux_top_track_32 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size4_3 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size4_4 mux_right_track_8 ( - .in ( { chany_top_in[7] , chany_top_in[8] , right_top_grid_pin_42_[0] , + .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size4_0 mux_right_track_10 ( - .in ( { chany_top_in[9] , chany_top_in[11] , right_top_grid_pin_43_[0] , - chany_bottom_in[9] } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size4_0_1 mux_right_track_10 ( + .in ( { chany_top_in[9] , chany_top_in[11] , + right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size4_1 mux_right_track_12 ( - .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_44_[0] , - chany_bottom_in[10] } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size4_1_1 mux_right_track_12 ( + .in ( { chany_top_in[10] , chany_top_in[15] , + right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size4_2 mux_right_track_14 ( - .in ( { chany_top_in[12] , chany_top_in[19] , right_top_grid_pin_45_[0] , - chany_bottom_in[12] } ) , + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( { ropt_net_130 } ) , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size4_2_1 mux_right_track_14 ( + .in ( { chany_top_in[12] , chany_top_in[19] , + right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size4_3 mux_right_track_24 ( - .in ( { chany_top_in[18] , right_top_grid_pin_42_[0] , + .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_3 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , @@ -22512,17 +27090,17 @@ mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_0_1 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_1_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_2_1 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_5_sram ) , @@ -22533,26 +27111,26 @@ mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; mux_tree_tapbuf_size7_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[4] } ) , + .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size7_1 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , chany_bottom_in[5] } ) , + .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size7 mux_right_track_6 ( - .in ( { chany_top_in[3] , chany_top_in[6] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[6] } ) , + .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -22569,34 +27147,34 @@ mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; mux_tree_tapbuf_size3_1 mux_right_track_16 ( - .in ( { chany_top_in[13] , right_top_grid_pin_46_[0] , + .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size3_2 mux_right_track_18 ( - .in ( { chany_top_in[14] , right_top_grid_pin_47_[0] , + .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size3_3 mux_right_track_20 ( - .in ( { chany_top_in[16] , right_top_grid_pin_48_[0] , + .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3_4 mux_right_track_22 ( - .in ( { chany_top_in[17] , right_top_grid_pin_49_[0] , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size3 mux_right_track_22 ( + .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3_0_1 mux_bottom_track_33 ( + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -22612,195 +27190,251 @@ mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_right_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_127 } ) , + .ccff_tail ( { ropt_net_131 } ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_11 mux_right_track_26 ( - .in ( { right_top_grid_pin_43_[0] , chany_bottom_in[15] } ) , +mux_tree_tapbuf_size2_0_1 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_1_1 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_2_1 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_3_1 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_4_1 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size2_mem_0_1 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_123 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_127 ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_129 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[4] ) , +mux_tree_tapbuf_size2_mem_1_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_1 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4_1 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[2] ) , .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_140 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_142 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_143 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[17] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_152 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_153 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_155 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_144 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chany_bottom_in[13] ) , +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_157 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( BUF_net_69 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[2] ) , .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_158 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_139 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_161 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_162 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_bottom_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[4] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_148 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[14] ) , + .X ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_149 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_150 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_151 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_152 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_153 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( BUF_net_69 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( chany_top_in[8] ) , .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_75 ) , + .X ( ropt_net_153 ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__39 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22810,29 +27444,103 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_18_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_18_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_17_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_17_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -22841,273 +27549,37 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; const1_16_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_15_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_15_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module const1_14_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_14_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_13_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_13_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module const1_12_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_12_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -23119,128 +27591,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__33 ( .A ( mem_out[1] ) , - .X ( net_aps_33 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( net_aps_33 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , + .X ( net_aps_35 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23257,41 +27610,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23308,17 +27627,346 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_15_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_15_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_14_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_14_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_83 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_13_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_13_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_12_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_12_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + module const1_11_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23345,7 +27993,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23372,7 +28020,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23399,7 +28047,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23426,7 +28074,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23453,7 +28101,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23480,7 +28128,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23507,7 +28155,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23534,7 +28182,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23546,13 +28194,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; const1_3_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_81 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -23569,13 +28217,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; const1_2_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -23584,7 +28236,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23611,7 +28263,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23634,24 +28286,20 @@ endmodule module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , - right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , - right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , - right_bottom_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - ccff_tail ) ; + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , + chany_top_out , chanx_right_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; @@ -23663,6 +28311,14 @@ wire [0:1] mux_tree_tapbuf_size2_10_sram ; wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; @@ -23683,6 +28339,10 @@ wire [0:1] mux_tree_tapbuf_size2_9_sram ; wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; @@ -23692,92 +28352,106 @@ wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -mux_tree_tapbuf_size2_8 mux_top_track_0 ( +mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_10 mux_top_track_4 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_9 mux_top_track_24 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( { ropt_net_107 } ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_10 ( - .in ( { chany_top_in[4] , right_top_grid_pin_43_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_11 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_12 ( - .in ( { chany_top_in[5] , right_top_grid_pin_44_[0] } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_14 ( - .in ( { chany_top_in[6] , right_top_grid_pin_45_[0] } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_16 ( - .in ( { chany_top_in[7] , right_top_grid_pin_46_[0] } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_18 ( - .in ( { chany_top_in[8] , right_top_grid_pin_47_[0] } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_20 ( - .in ( { chany_top_in[9] , right_top_grid_pin_48_[0] } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_22 ( - .in ( { chany_top_in[10] , right_top_grid_pin_49_[0] } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_26 ( - .in ( { chany_top_in[12] , right_top_grid_pin_43_[0] } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_106 } ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , @@ -23787,780 +28461,208 @@ mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , +mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_105 } ) , +mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size6_0 mux_right_track_0 ( - .in ( { chany_top_in[19] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size6 mux_right_track_4 ( - .in ( { chany_top_in[1] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , +mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( { ropt_net_110 } ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( { ropt_net_118 } ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_right_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size5 mux_right_track_6 ( - .in ( { chany_top_in[2] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3 mux_right_track_8 ( - .in ( { chany_top_in[3] , right_top_grid_pin_42_[0] , - right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_0 mux_right_track_24 ( - .in ( { chany_top_in[11] , right_top_grid_pin_42_[0] , - right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_right_in[7] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_697 ( .A ( ropt_net_113 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_114 ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_44 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_47 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , - .X ( BUF_net_49 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_115 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_116 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[17] ) , .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_117 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , - .X ( BUF_net_56 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_132 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_69 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_76 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_77 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( aps_rename_2_ ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( BUF_net_49 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_right_in[8] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_56 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_125 ) , .X ( chany_top_out[11] ) ) ; -endmodule - - -module direct_interc_4 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module GPIO_3 ( A , IE , OE , Y , in , out , mem_out ) ; -output A ; -output IE ; -output OE ; -output Y ; -input in ; -output out ; -input mem_out ; - -wire aps_rename_1_ ; - -assign A = in ; -assign out = Y ; - -sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( IE ) , .Y ( OE ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__1 ( .A ( mem_out ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_3 ( .A ( aps_rename_1_ ) , .X ( IE ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_3 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , - ccff_head , iopad_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; - -wire [0:0] GPIO_0_en ; - -GPIO_3 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , - .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , - .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , - .mem_out ( GPIO_0_en[0] ) ) ; -GPIO_sky130_fd_sc_hd__dfxbp_1_mem_3 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -endmodule - - -module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , - ccff_head , io_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , - .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , - .ccff_tail ( ccff_tail ) ) ; -direct_interc_4 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_4 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module grid_io_left ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , - gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , right_width_0_height_0__pin_0_ , - ccff_head , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] right_width_0_height_0__pin_0_ ; -input [0:0] ccff_head ; -output [0:0] right_width_0_height_0__pin_1_upper ; -output [0:0] right_width_0_height_0__pin_1_lower ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_io__3 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , - .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , - .io_inpad ( right_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_9 } ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( - .A ( right_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_5 ( .A ( aps_rename_2_ ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_569 ( .A ( ropt_net_9 ) , - .X ( ropt_net_11 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_570 ( .A ( ropt_net_11 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module direct_interc_3 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , - .X ( net_net_8 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_13 ( .A ( net_net_8 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module GPIO_2 ( A , IE , OE , Y , in , out , mem_out ) ; -output A ; -output IE ; -output OE ; -output Y ; -input in ; -output out ; -input mem_out ; - -wire aps_rename_1_ ; - -assign A = in ; -assign out = Y ; - -sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__1 ( .A ( mem_out ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_5 ( .A ( aps_rename_1_ ) , .X ( IE ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , - ccff_head , iopad_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; - -wire [0:0] GPIO_0_en ; - -GPIO_2 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , - .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , - .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , - .mem_out ( GPIO_0_en[0] ) ) ; -GPIO_sky130_fd_sc_hd__dfxbp_1_mem_2 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -endmodule - - -module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , - ccff_head , io_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , - .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , - .ccff_tail ( ccff_tail ) ) ; -direct_interc_3 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_3 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module grid_io_bottom ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , - gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , top_width_0_height_0__pin_0_ , - ccff_head , top_width_0_height_0__pin_1_upper , - top_width_0_height_0__pin_1_lower , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] top_width_0_height_0__pin_0_ ; -input [0:0] ccff_head ; -output [0:0] top_width_0_height_0__pin_1_upper ; -output [0:0] top_width_0_height_0__pin_1_lower ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_io__2 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( { ropt_net_16 } ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , - .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , - .io_inpad ( top_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_17 } ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( - .A ( top_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_6 ( .A ( aps_rename_2_ ) , - .X ( BUF_net_6 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_574 ( .A ( BUF_net_6 ) , - .X ( ropt_net_18 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_577 ( .A ( ropt_net_18 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_575 ( .A ( ropt_net_16 ) , - .X ( ropt_net_19 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_576 ( .A ( ropt_net_17 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( ropt_net_19 ) , - .X ( gfpga_pad_GPIO_IE[0] ) ) ; -endmodule - - -module direct_interc_2 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , - .X ( net_net_7 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_9 ( .A ( net_net_7 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module GPIO_1 ( A , IE , OE , Y , in , out , mem_out ) ; -output A ; -output IE ; -output OE ; -output Y ; -input in ; -output out ; -input mem_out ; - -assign A = in ; -assign out = Y ; - -sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( IE ) , .Y ( OE ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_1__1 ( .A ( mem_out ) , .X ( IE ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_1 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , - ccff_head , iopad_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; - -wire [0:0] GPIO_0_en ; - -GPIO_1 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , - .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , - .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , - .mem_out ( GPIO_0_en[0] ) ) ; -GPIO_sky130_fd_sc_hd__dfxbp_1_mem_1 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -endmodule - - -module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , - ccff_head , io_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , - .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , - .ccff_tail ( ccff_tail ) ) ; -direct_interc_2 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_2 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module grid_io_right ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , - gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , left_width_0_height_0__pin_0_ , - ccff_head , left_width_0_height_0__pin_1_upper , - left_width_0_height_0__pin_1_lower , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] left_width_0_height_0__pin_0_ ; -input [0:0] ccff_head ; -output [0:0] left_width_0_height_0__pin_1_upper ; -output [0:0] left_width_0_height_0__pin_1_lower ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_io__1 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , - .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , - .io_inpad ( left_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_11 } ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( - .A ( left_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_572 ( .A ( ropt_net_12 ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_8 ( .A ( aps_rename_1_ ) , - .X ( ropt_net_10 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_570 ( .A ( ropt_net_10 ) , - .X ( ropt_net_12 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_571 ( .A ( ropt_net_11 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module direct_interc_1 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , - .X ( net_net_7 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_13 ( .A ( net_net_7 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module GPIO ( A , IE , OE , Y , in , out , mem_out ) ; -output A ; -output IE ; -output OE ; -output Y ; -input in ; -output out ; -input mem_out ; - -wire aps_rename_1_ ; - -assign A = in ; -assign out = Y ; - -sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__1 ( .A ( mem_out ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_12 ( .A ( aps_rename_1_ ) , .X ( IE ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , - ccff_head , iopad_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; - -wire [0:0] GPIO_0_en ; - -GPIO GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , - .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , - .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , - .mem_out ( GPIO_0_en[0] ) ) ; -GPIO_sky130_fd_sc_hd__dfxbp_1_mem GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -endmodule - - -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , - ccff_head , io_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , - .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , - .ccff_tail ( ccff_tail ) ) ; -direct_interc_1 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module grid_io_top ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , - gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , bottom_width_0_height_0__pin_0_ , - ccff_head , bottom_width_0_height_0__pin_1_upper , - bottom_width_0_height_0__pin_1_lower , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] bottom_width_0_height_0__pin_0_ ; -input [0:0] ccff_head ; -output [0:0] bottom_width_0_height_0__pin_1_upper ; -output [0:0] bottom_width_0_height_0__pin_1_lower ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( { ropt_net_16 } ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , - .io_outpad ( bottom_width_0_height_0__pin_0_ ) , - .ccff_head ( ccff_head ) , - .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_15 } ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( - .A ( bottom_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_5 ( .A ( aps_rename_2_ ) , - .X ( BUF_net_5 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_574 ( .A ( BUF_net_5 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_576 ( .A ( ropt_net_16 ) , - .X ( gfpga_pad_GPIO_IE[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_575 ( .A ( ropt_net_15 ) , - .X ( ropt_net_17 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_577 ( .A ( ropt_net_17 ) , +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_127 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_110 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[4] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_78 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( BUF_net_58 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , + .X ( chanx_right_out[18] ) ) ; endmodule @@ -24576,9 +28678,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__55 ( .A ( mem_out[1] ) , - .X ( net_aps_55 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( .A ( net_aps_55 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__56 ( .A ( mem_out[1] ) , + .X ( net_aps_56 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_aps_56 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24595,7 +28697,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24612,7 +28714,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24645,12 +28747,13 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_22 ( in , sram , sram_inv , out , p2 ) ; +module mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +output p_abuf0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -24658,8 +28761,9 @@ const1_30 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; endmodule @@ -24668,12 +28772,13 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_21 ( in , sram , sram_inv , out , p2 ) ; +module mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +output p_abuf0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -24681,25 +28786,34 @@ const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , p_abuf2 ) ; + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , p_abuf0 , p_abuf1 , + p_abuf2 ) ; input [0:0] Test_en ; input [0:0] clk ; input [0:0] ff_D ; input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; +output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( p_abuf2 ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; + .Q ( p_abuf2 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( net_net_100 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_101 ( .A ( p_abuf2 ) , + .X ( net_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( .A ( p_abuf2 ) , .X ( p_abuf1 ) ) ; endmodule @@ -24712,9 +28826,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -24730,7 +28844,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24800,7 +28914,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb7_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__51 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__52 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25039,23 +29153,27 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , - p_abuf1 , p_abuf2 , p2 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , + p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p1 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; +output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; +output p_abuf4 ; +input p1 ; input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -25081,15 +29199,16 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .p2 ( p2 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_regout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .p_abuf0 ( fabric_regout[0] ) , .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) ) ; mux_tree_size2_21 mux_fabric_out_0 ( .in ( { @@ -25098,14 +29217,14 @@ mux_tree_size2_21 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf3 ) , .p1 ( p1 ) ) ; mux_tree_size2_22 mux_fabric_out_1 ( - .in ( { fabric_regout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf4 ) , .p1 ( p1 ) ) ; mux_tree_size2_23 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , @@ -25147,7 +29266,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -25162,50 +29281,52 @@ direct_interc direct_interc_9_ ( direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__256 ( .A ( fabric_regout[0] ) , - .X ( fabric_scout[0] ) ) ; endmodule module logical_tile_clb_mode_default__fle ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 , + p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +output p_abuf2 ; +input p1 ; input p2 ; logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , - .p2 ( p2 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p_abuf4 ( p_abuf4 ) , + .p1 ( p1 ) , .p2 ( p2 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; + .out ( { p_abuf3 } ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; + .out ( { p_abuf4 } ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf0 } ) ) ; + .out ( { p_abuf1 } ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf1 } ) ) ; + .out ( { p_abuf2 } ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -25223,7 +29344,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -25242,7 +29363,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25259,7 +29380,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25276,7 +29397,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25286,12 +29407,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_20 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_20 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -25299,7 +29420,7 @@ const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -25309,12 +29430,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_19 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_19 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -25322,7 +29443,7 @@ const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -25332,12 +29453,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_18 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_18 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -25345,7 +29466,7 @@ const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -25359,9 +29480,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -25374,9 +29495,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -25392,7 +29513,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25402,12 +29523,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_30 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_30 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -25415,7 +29536,7 @@ const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -25462,7 +29583,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb6_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__46 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__47 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25494,11 +29615,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , @@ -25588,11 +29709,11 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , @@ -25647,13 +29768,13 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p1 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -25677,7 +29798,7 @@ mux_tree_size2_30 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -25701,21 +29822,21 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p1 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p1 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -25730,24 +29851,24 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_18 mux_fabric_out_0 ( .in ( { @@ -25756,21 +29877,21 @@ mux_tree_size2_18 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; mux_tree_size2_19 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; mux_tree_size2_20 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -25787,10 +29908,10 @@ mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -25805,7 +29926,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -25824,29 +29945,29 @@ endmodule module logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p1 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p1 ; +input p2 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p1 ( p1 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p2 ( p2 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -25858,7 +29979,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -25876,7 +29997,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -25895,7 +30016,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__45 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25912,7 +30033,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25929,7 +30050,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25939,12 +30060,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_17 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -25952,7 +30073,7 @@ const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -25962,12 +30083,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_16 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_16 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -25975,7 +30096,7 @@ const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -25985,12 +30106,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_15 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_15 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -25998,7 +30119,7 @@ const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -26012,9 +30133,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -26027,9 +30148,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -26045,7 +30166,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__42 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26055,12 +30176,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_29 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_29 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -26068,7 +30189,7 @@ const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -26115,7 +30236,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb5_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__41 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__42 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26241,9 +30362,9 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; @@ -26300,13 +30421,13 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p1 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -26330,7 +30451,7 @@ mux_tree_size2_29 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p1 ( p1 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -26354,21 +30475,23 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p1 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 , + p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p1 ; +input p0 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -26383,24 +30506,24 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p1 ( p1 ) ) ; + .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_15 mux_fabric_out_0 ( .in ( { @@ -26409,21 +30532,21 @@ mux_tree_size2_15 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; mux_tree_size2_16 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; mux_tree_size2_17 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p1 ( p1 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -26440,10 +30563,10 @@ mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -26458,7 +30581,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -26477,29 +30600,30 @@ endmodule module logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p1 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p1 ; +input p0 ; +input p2 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p1 ( p1 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -26511,7 +30635,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -26529,7 +30653,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -26548,7 +30672,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26565,7 +30689,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__39 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26582,7 +30706,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26592,12 +30716,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_14 ( in , sram , sram_inv , out , p3 ) ; +module mux_tree_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -26605,7 +30729,7 @@ const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -26615,12 +30739,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_13 ( in , sram , sram_inv , out , p3 ) ; +module mux_tree_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -26628,7 +30752,7 @@ const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -26638,12 +30762,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_12 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -26651,7 +30775,7 @@ const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -26665,9 +30789,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -26680,9 +30804,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -26698,7 +30822,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26708,12 +30832,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_28 ( in , sram , sram_inv , out , p3 ) ; +module mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -26721,7 +30845,7 @@ const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -26768,7 +30892,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__36 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26809,13 +30933,13 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -26900,7 +31024,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , @@ -26953,13 +31077,13 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -26983,7 +31107,7 @@ mux_tree_size2_28 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -27007,23 +31131,21 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p1 , - p3 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p1 ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -27038,24 +31160,24 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_12 mux_fabric_out_0 ( .in ( { @@ -27064,21 +31186,21 @@ mux_tree_size2_12 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p1 ( p1 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_13 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_14 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -27095,10 +31217,10 @@ mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -27113,7 +31235,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -27132,30 +31254,29 @@ endmodule module logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p1 , p3 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p1 ; -input p3 ; +input p0 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p1 ( p1 ) , .p3 ( p3 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -27167,7 +31288,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -27185,7 +31306,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -27204,7 +31325,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27221,7 +31342,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27238,7 +31359,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27248,12 +31369,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_11 ( in , sram , sram_inv , out , p3 ) ; +module mux_tree_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -27261,7 +31382,7 @@ const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -27271,12 +31392,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_10 ( in , sram , sram_inv , out , p3 ) ; +module mux_tree_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -27284,7 +31405,7 @@ const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -27294,12 +31415,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_9 ( in , sram , sram_inv , out , p3 ) ; +module mux_tree_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -27307,7 +31428,7 @@ const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -27321,9 +31442,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -27336,9 +31457,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -27354,7 +31475,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27424,7 +31545,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27462,7 +31583,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( @@ -27663,23 +31784,21 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 , - p3 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input p0 ; -input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -27694,7 +31813,7 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , @@ -27704,14 +31823,14 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_9 mux_fabric_out_0 ( .in ( { @@ -27720,21 +31839,21 @@ mux_tree_size2_9 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_10 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_11 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -27751,10 +31870,10 @@ mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -27769,7 +31888,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -27788,30 +31907,29 @@ endmodule module logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p0 , p3 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input p0 ; -input p3 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -27823,7 +31941,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -27841,7 +31959,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -27860,7 +31978,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27877,7 +31995,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27894,7 +32012,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27904,12 +32022,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_size2_8 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -27917,7 +32035,7 @@ const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -27927,12 +32045,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_size2_7 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -27940,7 +32058,7 @@ const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -27950,12 +32068,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_size2_6 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -27963,7 +32081,7 @@ const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -27977,9 +32095,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -27992,9 +32110,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -28010,7 +32128,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28020,12 +32138,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_26 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_size2_26 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -28033,7 +32151,7 @@ const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -28080,7 +32198,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb2_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__27 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28116,7 +32234,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , @@ -28265,13 +32383,13 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p0 ; +input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -28295,7 +32413,7 @@ mux_tree_size2_26 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; + .p1 ( p1 ) ) ; mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -28319,21 +32437,23 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p1 , + p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p0 ; +input p1 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -28348,24 +32468,24 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; + .p1 ( p1 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_6 mux_fabric_out_0 ( .in ( { @@ -28374,21 +32494,21 @@ mux_tree_size2_6 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p0 ( p0 ) ) ; + .p1 ( p1 ) ) ; mux_tree_size2_7 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p0 ( p0 ) ) ; + .p1 ( p1 ) ) ; mux_tree_size2_8 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; + .p3 ( p3 ) ) ; mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -28405,10 +32525,10 @@ mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -28423,7 +32543,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -28442,29 +32562,30 @@ endmodule module logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p0 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p1 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p0 ; +input p1 ; +input p3 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p1 ( p1 ) , .p3 ( p3 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -28476,7 +32597,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -28494,7 +32615,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -28513,7 +32634,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28530,7 +32651,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28547,7 +32668,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28557,12 +32678,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_size2_5 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -28570,7 +32691,7 @@ const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -28580,12 +32701,12 @@ output [0:0] const1 ; endmodule -module mux_tree_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_size2_4 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -28593,7 +32714,7 @@ const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -28630,9 +32751,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -28645,9 +32766,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -28663,7 +32784,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28733,7 +32854,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb1_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__21 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28771,16 +32892,16 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -28859,13 +32980,13 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , @@ -28972,23 +33093,23 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 , - p1 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 , + p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input p0 ; -input p1 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -29003,7 +33124,7 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , @@ -29013,14 +33134,14 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_3 mux_fabric_out_0 ( .in ( { @@ -29031,19 +33152,19 @@ mux_tree_size2_3 mux_fabric_out_0 ( .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , .p0 ( p0 ) ) ; mux_tree_size2_4 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p0 ( p0 ) ) ; + .p3 ( p3 ) ) ; mux_tree_size2_5 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p1 ) ) ; + .p3 ( p3 ) ) ; mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -29060,10 +33181,10 @@ mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -29078,7 +33199,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -29097,30 +33218,30 @@ endmodule module logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p0 , p1 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p0 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input p0 ; -input p1 ; +input p3 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -29132,7 +33253,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -29150,7 +33271,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -29169,7 +33290,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__20 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29186,7 +33307,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__19 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29203,7 +33324,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29273,7 +33394,10 @@ const1_1 const1_0_ ( sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( net_net_61 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( net_net_61 ) , + .X ( out[0] ) ) ; endmodule @@ -29286,9 +33410,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -29301,9 +33425,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -29327,7 +33451,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__17 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29397,7 +33521,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb0_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__16 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__17 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29431,9 +33555,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , @@ -29444,7 +33568,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -29523,11 +33647,11 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , @@ -29636,21 +33760,21 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p1 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p1 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -29665,24 +33789,24 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p1 ) ) ; + .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_0 mux_fabric_out_0 ( .in ( { @@ -29691,21 +33815,21 @@ mux_tree_size2_0 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p0 ( p1 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_1 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p0 ( p1 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_2 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p1 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -29722,10 +33846,10 @@ mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -29740,7 +33864,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -29759,29 +33883,29 @@ endmodule module logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p1 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p1 ; +input p0 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p1 ( p1 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -29793,7 +33917,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -29811,7 +33935,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -29819,33 +33943,41 @@ endmodule module logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , clb_I0 , - clb_I1 , clb_I2 , clb_I3 , clb_I4 , clb_I5 , clb_I6 , clb_I7 , clb_regin , - clb_scin , clb_clk , ccff_head , clb_O , clb_regout , clb_scout , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 , - p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , p_abuf12 , - p_abuf13 , p_abuf14 , p_abuf15 , p0 , p1 , p2 , p3 , p4 ) ; + clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , clb_I3i , + clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , clb_I7 , + clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , + clb_regout , clb_sc_out , ccff_tail , p_abuf0 , p_abuf3 , p_abuf4 , + p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , + p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p_abuf16 , p0 , p1 , p2 , p3 , + p4 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; -input [0:3] clb_I0 ; -input [0:3] clb_I1 ; -input [0:3] clb_I2 ; -input [0:3] clb_I3 ; -input [0:3] clb_I4 ; -input [0:3] clb_I5 ; -input [0:3] clb_I6 ; -input [0:3] clb_I7 ; +input [0:2] clb_I0 ; +input [0:0] clb_I0i ; +input [0:2] clb_I1 ; +input [0:0] clb_I1i ; +input [0:2] clb_I2 ; +input [0:0] clb_I2i ; +input [0:2] clb_I3 ; +input [0:0] clb_I3i ; +input [0:2] clb_I4 ; +input [0:0] clb_I4i ; +input [0:2] clb_I5 ; +input [0:0] clb_I5i ; +input [0:2] clb_I6 ; +input [0:0] clb_I6i ; +input [0:2] clb_I7 ; +input [0:0] clb_I7i ; input [0:0] clb_regin ; -input [0:0] clb_scin ; +input [0:0] clb_sc_in ; input [0:0] clb_clk ; input [0:0] ccff_head ; output [0:15] clb_O ; output [0:0] clb_regout ; -output [0:0] clb_scout ; +output [0:0] clb_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; output p_abuf3 ; output p_abuf4 ; output p_abuf5 ; @@ -29859,6 +33991,7 @@ output p_abuf12 ; output p_abuf13 ; output p_abuf14 ; output p_abuf15 ; +output p_abuf16 ; input p0 ; input p1 ; input p2 ; @@ -29866,149 +33999,146 @@ input p3 ; input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; -wire [1:1] logical_tile_clb_mode_default__fle_0_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; -wire [1:1] logical_tile_clb_mode_default__fle_1_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; wire [1:1] logical_tile_clb_mode_default__fle_4_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I0 ) , .fle_regin ( clb_regin ) , .fle_scin ( clb_scin ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I0[2] , clb_I0[1] , clb_I0[0] , clb_I0i[0] } ) , + .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , - .fle_out ( { clb_O[1] , logical_tile_clb_mode_default__fle_0_fle_out[1] } ) , + .fle_out ( { p_abuf16 , p_abuf3 } ) , .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_0_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .p1 ( p1 ) ) ; + .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I1 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I1[2] , clb_I1[1] , clb_I1[0] , clb_I1i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_0_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .fle_out ( { clb_O[3] , logical_tile_clb_mode_default__fle_1_fle_out[1] } ) , + .fle_out ( { p_abuf4 , clb_O[2] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_1_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .p0 ( p0 ) , .p1 ( p1 ) ) ; + .p0 ( p0 ) , .p3 ( p4 ) ) ; logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I2 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I2[2] , clb_I2[1] , clb_I2[0] , clb_I2i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_1_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .fle_out ( { clb_O[5] , clb_O[4] } ) , + .fle_out ( { p_abuf6 , p_abuf7 } ) , .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_2_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p0 ( p0 ) ) ; + .p1 ( p2 ) , .p3 ( p4 ) ) ; logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I3 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I3[2] , clb_I3[1] , clb_I3[0] , clb_I3i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_2_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .fle_out ( logical_tile_clb_mode_default__fle_3_fle_out ) , + .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .fle_out ( { logical_tile_clb_mode_default__fle_3_fle_out[0] , clb_O[6] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_3_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .p0 ( p0 ) , .p3 ( p4 ) ) ; + .p0 ( p1 ) ) ; logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I4 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I4[2] , clb_I4[1] , clb_I4[0] , clb_I4i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_3_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , .fle_out ( { clb_O[9] , logical_tile_clb_mode_default__fle_4_fle_out[1] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_4_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p1 ( p2 ) , .p3 ( p4 ) ) ; + .p0 ( p1 ) ) ; logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I5 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I5[2] , clb_I5[1] , clb_I5[0] , clb_I5i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_4_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .fle_out ( { logical_tile_clb_mode_default__fle_5_fle_out[0] , clb_O[10] } ) , + .fle_out ( { clb_O[11] , clb_O[10] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_5_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p1 ( p2 ) ) ; + .p0 ( p1 ) , .p2 ( p3 ) ) ; logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I6 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I6[2] , clb_I6[1] , clb_I6[0] , clb_I6i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_5_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .fle_out ( { logical_tile_clb_mode_default__fle_6_fle_out[0] , clb_O[12] } ) , + .fle_out ( { p_abuf14 , p_abuf15 } ) , .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_6_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p1 ( p2 ) ) ; + .p2 ( p3 ) ) ; logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I7 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I7[2] , clb_I7[1] , clb_I7[0] , clb_I7i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_6_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .fle_out ( { p_abuf14 , clb_O[14] } ) , - .fle_regout ( clb_regout ) , .fle_scout ( clb_scout ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf16 ) , .p_abuf1 ( p_abuf17 ) , - .p2 ( p3 ) ) ; + .fle_out ( { clb_O[15] , clb_O[14] } ) , + .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p1 ( p2 ) , .p2 ( p3 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_out ) ) ; + .out ( { p_abuf3 } ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( clb_O[1] ) ) ; + .out ( { p_abuf16 } ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_out ) ) ; + .out ( clb_O[2] ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( clb_O[3] ) ) ; + .out ( { p_abuf4 } ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( clb_O[4] ) ) ; + .out ( { p_abuf7 } ) ) ; direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( clb_O[5] ) ) ; + .out ( { p_abuf6 } ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) ) ; + .out ( clb_O[6] ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) ) ; + .out ( logical_tile_clb_mode_default__fle_3_fle_out ) ) ; direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_out ) ) ; @@ -30020,924 +34150,947 @@ direct_interc direct_interc_10_ ( .out ( clb_O[10] ) ) ; direct_interc direct_interc_11_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_out ) ) ; + .out ( clb_O[11] ) ) ; direct_interc direct_interc_12_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( clb_O[12] ) ) ; + .out ( { p_abuf15 } ) ) ; direct_interc direct_interc_13_ ( .in ( { SYNOPSYS_UNCONNECTED_14 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_out ) ) ; + .out ( { p_abuf14 } ) ) ; direct_interc direct_interc_14_ ( .in ( { SYNOPSYS_UNCONNECTED_15 } ) , .out ( clb_O[14] ) ) ; direct_interc direct_interc_15_ ( .in ( { SYNOPSYS_UNCONNECTED_16 } ) , - .out ( { p_abuf14 } ) ) ; + .out ( clb_O[15] ) ) ; direct_interc direct_interc_16_ ( .in ( { SYNOPSYS_UNCONNECTED_17 } ) , - .out ( { p_abuf16 } ) ) ; + .out ( { p_abuf1 } ) ) ; direct_interc direct_interc_17_ ( .in ( { SYNOPSYS_UNCONNECTED_18 } ) , - .out ( { p_abuf17 } ) ) ; + .out ( { p_abuf2 } ) ) ; direct_interc direct_interc_18_ ( .in ( { SYNOPSYS_UNCONNECTED_19 } ) , - .out ( clb_I0[0] ) ) ; + .out ( clb_I0[2] ) ) ; direct_interc direct_interc_19_ ( .in ( { SYNOPSYS_UNCONNECTED_20 } ) , .out ( clb_I0[1] ) ) ; direct_interc direct_interc_20_ ( .in ( { SYNOPSYS_UNCONNECTED_21 } ) , - .out ( clb_I0[2] ) ) ; + .out ( clb_I0[0] ) ) ; direct_interc direct_interc_21_ ( .in ( { SYNOPSYS_UNCONNECTED_22 } ) , - .out ( clb_I0[3] ) ) ; + .out ( clb_I0i ) ) ; direct_interc direct_interc_22_ ( .in ( { SYNOPSYS_UNCONNECTED_23 } ) , .out ( clb_regin ) ) ; direct_interc direct_interc_23_ ( .in ( { SYNOPSYS_UNCONNECTED_24 } ) , - .out ( clb_scin ) ) ; + .out ( clb_sc_in ) ) ; direct_interc direct_interc_24_ ( .in ( { SYNOPSYS_UNCONNECTED_25 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_25_ ( .in ( { SYNOPSYS_UNCONNECTED_26 } ) , - .out ( clb_I1[0] ) ) ; + .out ( clb_I1[2] ) ) ; direct_interc direct_interc_26_ ( .in ( { SYNOPSYS_UNCONNECTED_27 } ) , .out ( clb_I1[1] ) ) ; direct_interc direct_interc_27_ ( .in ( { SYNOPSYS_UNCONNECTED_28 } ) , - .out ( clb_I1[2] ) ) ; + .out ( clb_I1[0] ) ) ; direct_interc direct_interc_28_ ( .in ( { SYNOPSYS_UNCONNECTED_29 } ) , - .out ( clb_I1[3] ) ) ; + .out ( clb_I1i ) ) ; direct_interc direct_interc_29_ ( .in ( { SYNOPSYS_UNCONNECTED_30 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; direct_interc direct_interc_30_ ( .in ( { SYNOPSYS_UNCONNECTED_31 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; direct_interc direct_interc_31_ ( .in ( { SYNOPSYS_UNCONNECTED_32 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_32_ ( .in ( { SYNOPSYS_UNCONNECTED_33 } ) , - .out ( clb_I2[0] ) ) ; + .out ( clb_I2[2] ) ) ; direct_interc direct_interc_33_ ( .in ( { SYNOPSYS_UNCONNECTED_34 } ) , .out ( clb_I2[1] ) ) ; direct_interc direct_interc_34_ ( .in ( { SYNOPSYS_UNCONNECTED_35 } ) , - .out ( clb_I2[2] ) ) ; + .out ( clb_I2[0] ) ) ; direct_interc direct_interc_35_ ( .in ( { SYNOPSYS_UNCONNECTED_36 } ) , - .out ( clb_I2[3] ) ) ; + .out ( clb_I2i ) ) ; direct_interc direct_interc_36_ ( .in ( { SYNOPSYS_UNCONNECTED_37 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; direct_interc direct_interc_37_ ( .in ( { SYNOPSYS_UNCONNECTED_38 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; direct_interc direct_interc_38_ ( .in ( { SYNOPSYS_UNCONNECTED_39 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_39_ ( .in ( { SYNOPSYS_UNCONNECTED_40 } ) , - .out ( clb_I3[0] ) ) ; + .out ( clb_I3[2] ) ) ; direct_interc direct_interc_40_ ( .in ( { SYNOPSYS_UNCONNECTED_41 } ) , .out ( clb_I3[1] ) ) ; direct_interc direct_interc_41_ ( .in ( { SYNOPSYS_UNCONNECTED_42 } ) , - .out ( clb_I3[2] ) ) ; + .out ( clb_I3[0] ) ) ; direct_interc direct_interc_42_ ( .in ( { SYNOPSYS_UNCONNECTED_43 } ) , - .out ( clb_I3[3] ) ) ; + .out ( clb_I3i ) ) ; direct_interc direct_interc_43_ ( .in ( { SYNOPSYS_UNCONNECTED_44 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; direct_interc direct_interc_44_ ( .in ( { SYNOPSYS_UNCONNECTED_45 } ) , - .out ( logical_tile_clb_mode_default__fle_2_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; direct_interc direct_interc_45_ ( .in ( { SYNOPSYS_UNCONNECTED_46 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_46_ ( .in ( { SYNOPSYS_UNCONNECTED_47 } ) , - .out ( clb_I4[0] ) ) ; + .out ( clb_I4[2] ) ) ; direct_interc direct_interc_47_ ( .in ( { SYNOPSYS_UNCONNECTED_48 } ) , .out ( clb_I4[1] ) ) ; direct_interc direct_interc_48_ ( .in ( { SYNOPSYS_UNCONNECTED_49 } ) , - .out ( clb_I4[2] ) ) ; + .out ( clb_I4[0] ) ) ; direct_interc direct_interc_49_ ( .in ( { SYNOPSYS_UNCONNECTED_50 } ) , - .out ( clb_I4[3] ) ) ; + .out ( clb_I4i ) ) ; direct_interc direct_interc_50_ ( .in ( { SYNOPSYS_UNCONNECTED_51 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; direct_interc direct_interc_51_ ( .in ( { SYNOPSYS_UNCONNECTED_52 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; direct_interc direct_interc_52_ ( .in ( { SYNOPSYS_UNCONNECTED_53 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_53_ ( .in ( { SYNOPSYS_UNCONNECTED_54 } ) , - .out ( clb_I5[0] ) ) ; + .out ( clb_I5[2] ) ) ; direct_interc direct_interc_54_ ( .in ( { SYNOPSYS_UNCONNECTED_55 } ) , .out ( clb_I5[1] ) ) ; direct_interc direct_interc_55_ ( .in ( { SYNOPSYS_UNCONNECTED_56 } ) , - .out ( clb_I5[2] ) ) ; + .out ( clb_I5[0] ) ) ; direct_interc direct_interc_56_ ( .in ( { SYNOPSYS_UNCONNECTED_57 } ) , - .out ( clb_I5[3] ) ) ; + .out ( clb_I5i ) ) ; direct_interc direct_interc_57_ ( .in ( { SYNOPSYS_UNCONNECTED_58 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; direct_interc direct_interc_58_ ( .in ( { SYNOPSYS_UNCONNECTED_59 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; direct_interc direct_interc_59_ ( .in ( { SYNOPSYS_UNCONNECTED_60 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_60_ ( .in ( { SYNOPSYS_UNCONNECTED_61 } ) , - .out ( clb_I6[0] ) ) ; + .out ( clb_I6[2] ) ) ; direct_interc direct_interc_61_ ( .in ( { SYNOPSYS_UNCONNECTED_62 } ) , .out ( clb_I6[1] ) ) ; direct_interc direct_interc_62_ ( .in ( { SYNOPSYS_UNCONNECTED_63 } ) , - .out ( clb_I6[2] ) ) ; + .out ( clb_I6[0] ) ) ; direct_interc direct_interc_63_ ( .in ( { SYNOPSYS_UNCONNECTED_64 } ) , - .out ( clb_I6[3] ) ) ; + .out ( clb_I6i ) ) ; direct_interc direct_interc_64_ ( .in ( { SYNOPSYS_UNCONNECTED_65 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; direct_interc direct_interc_65_ ( .in ( { SYNOPSYS_UNCONNECTED_66 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; direct_interc direct_interc_66_ ( .in ( { SYNOPSYS_UNCONNECTED_67 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_67_ ( .in ( { SYNOPSYS_UNCONNECTED_68 } ) , - .out ( clb_I7[0] ) ) ; + .out ( clb_I7[2] ) ) ; direct_interc direct_interc_68_ ( .in ( { SYNOPSYS_UNCONNECTED_69 } ) , .out ( clb_I7[1] ) ) ; direct_interc direct_interc_69_ ( .in ( { SYNOPSYS_UNCONNECTED_70 } ) , - .out ( clb_I7[2] ) ) ; + .out ( clb_I7[0] ) ) ; direct_interc direct_interc_70_ ( .in ( { SYNOPSYS_UNCONNECTED_71 } ) , - .out ( clb_I7[3] ) ) ; + .out ( clb_I7i ) ) ; direct_interc direct_interc_71_ ( .in ( { SYNOPSYS_UNCONNECTED_72 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; direct_interc direct_interc_72_ ( .in ( { SYNOPSYS_UNCONNECTED_73 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; direct_interc direct_interc_73_ ( .in ( { SYNOPSYS_UNCONNECTED_74 } ) , .out ( clb_clk ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( - .A ( logical_tile_clb_mode_default__fle_0_fle_out[1] ) , .X ( clb_O[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( clb_O[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( - .A ( logical_tile_clb_mode_default__fle_0_fle_out[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( - .A ( logical_tile_clb_mode_default__fle_1_fle_out[1] ) , .X ( clb_O[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( clb_O[3] ) , .X ( p_abuf2 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( - .A ( logical_tile_clb_mode_default__fle_1_fle_out[1] ) , .X ( p_abuf3 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( p_abuf3 ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( p_abuf4 ) , + .X ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( p_abuf6 ) , + .X ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( clb_O[2] ) , + .X ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( p_abuf7 ) , + .X ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , .X ( clb_O[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( clb_O[5] ) , .X ( p_abuf4 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( clb_O[4] ) , .X ( p_abuf5 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , .X ( p_abuf6 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) , .X ( clb_O[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) , .X ( p_abuf7 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( + .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , .X ( clb_O[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( clb_O[9] ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( - .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , - .X ( BUF_net_76 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( - .A ( logical_tile_clb_mode_default__fle_5_fle_out[0] ) , - .X ( clb_O[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( - .A ( logical_tile_clb_mode_default__fle_5_fle_out[0] ) , - .X ( BUF_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_81 ( - .A ( logical_tile_clb_mode_default__fle_6_fle_out[0] ) , - .X ( clb_O[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( clb_O[10] ) , - .X ( BUF_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( - .A ( logical_tile_clb_mode_default__fle_6_fle_out[0] ) , - .X ( BUF_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( p_abuf14 ) , - .X ( BUF_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( clb_O[12] ) , - .X ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( BUF_net_74 ) , - .X ( p_abuf8 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( clb_O[14] ) , - .X ( BUF_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( BUF_net_78 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( clb_O[6] ) , + .X ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( clb_O[9] ) , .X ( p_abuf10 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( BUF_net_85 ) , - .X ( clb_O[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_104 ( .A ( BUF_net_84 ) , - .X ( p_abuf13 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_87 ) , - .X ( p_abuf15 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( BUF_net_76 ) , - .X ( p_abuf9 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( + .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , + .X ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( p_abuf14 ) , + .X ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_77 ( .A ( clb_O[11] ) , + .X ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( clb_O[10] ) , + .X ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_81 ( .A ( p_abuf15 ) , + .X ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( BUF_net_62 ) , + .X ( clb_O[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_103 ( .A ( BUF_net_66 ) , + .X ( clb_O[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( BUF_net_75 ) , .X ( p_abuf11 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( BUF_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_80 ) , + .X ( clb_O[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( BUF_net_77 ) , .X ( p_abuf12 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_107 ( .A ( BUF_net_79 ) , + .X ( p_abuf13 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_108 ( .A ( BUF_net_81 ) , + .X ( clb_O[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_110 ( .A ( p_abuf16 ) , + .X ( clb_O[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( BUF_net_63 ) , + .X ( clb_O[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( BUF_net_65 ) , + .X ( p_abuf5 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( BUF_net_67 ) , + .X ( clb_O[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( BUF_net_69 ) , + .X ( p_abuf8 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( BUF_net_71 ) , + .X ( p_abuf9 ) ) ; endmodule -module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_32_ , - top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_0_ , - right_width_0_height_0__pin_1_ , right_width_0_height_0__pin_2_ , - right_width_0_height_0__pin_3_ , right_width_0_height_0__pin_4_ , - right_width_0_height_0__pin_5_ , right_width_0_height_0__pin_6_ , - right_width_0_height_0__pin_7_ , right_width_0_height_0__pin_8_ , - right_width_0_height_0__pin_9_ , right_width_0_height_0__pin_10_ , - right_width_0_height_0__pin_11_ , right_width_0_height_0__pin_12_ , - right_width_0_height_0__pin_13_ , right_width_0_height_0__pin_14_ , - right_width_0_height_0__pin_15_ , bottom_width_0_height_0__pin_16_ , - bottom_width_0_height_0__pin_17_ , bottom_width_0_height_0__pin_18_ , - bottom_width_0_height_0__pin_19_ , bottom_width_0_height_0__pin_20_ , - bottom_width_0_height_0__pin_21_ , bottom_width_0_height_0__pin_22_ , - bottom_width_0_height_0__pin_23_ , bottom_width_0_height_0__pin_24_ , - bottom_width_0_height_0__pin_25_ , bottom_width_0_height_0__pin_26_ , - bottom_width_0_height_0__pin_27_ , bottom_width_0_height_0__pin_28_ , - bottom_width_0_height_0__pin_29_ , bottom_width_0_height_0__pin_30_ , - bottom_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , - ccff_head , right_width_0_height_0__pin_34_upper , - right_width_0_height_0__pin_34_lower , - right_width_0_height_0__pin_35_upper , - right_width_0_height_0__pin_35_lower , - right_width_0_height_0__pin_36_upper , - right_width_0_height_0__pin_36_lower , - right_width_0_height_0__pin_37_upper , - right_width_0_height_0__pin_37_lower , - right_width_0_height_0__pin_38_upper , - right_width_0_height_0__pin_38_lower , - right_width_0_height_0__pin_39_upper , - right_width_0_height_0__pin_39_lower , - right_width_0_height_0__pin_40_upper , - right_width_0_height_0__pin_40_lower , - right_width_0_height_0__pin_41_upper , - right_width_0_height_0__pin_41_lower , - bottom_width_0_height_0__pin_42_upper , - bottom_width_0_height_0__pin_42_lower , - bottom_width_0_height_0__pin_43_upper , - bottom_width_0_height_0__pin_43_lower , - bottom_width_0_height_0__pin_44_upper , - bottom_width_0_height_0__pin_44_lower , - bottom_width_0_height_0__pin_45_upper , - bottom_width_0_height_0__pin_45_lower , - bottom_width_0_height_0__pin_46_upper , - bottom_width_0_height_0__pin_46_lower , - bottom_width_0_height_0__pin_47_upper , - bottom_width_0_height_0__pin_47_lower , - bottom_width_0_height_0__pin_48_upper , - bottom_width_0_height_0__pin_48_lower , - bottom_width_0_height_0__pin_49_upper , - bottom_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , - bottom_width_0_height_0__pin_51_ , ccff_tail ) ; +module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ , + top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ , + top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ , + top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ , + top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ , + top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_16_ , + right_width_0_height_0__pin_17_ , right_width_0_height_0__pin_18_ , + right_width_0_height_0__pin_19_ , right_width_0_height_0__pin_20_ , + right_width_0_height_0__pin_21_ , right_width_0_height_0__pin_22_ , + right_width_0_height_0__pin_23_ , right_width_0_height_0__pin_24_ , + right_width_0_height_0__pin_25_ , right_width_0_height_0__pin_26_ , + right_width_0_height_0__pin_27_ , right_width_0_height_0__pin_28_ , + right_width_0_height_0__pin_29_ , right_width_0_height_0__pin_30_ , + right_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , + ccff_head , top_width_0_height_0__pin_34_upper , + top_width_0_height_0__pin_34_lower , top_width_0_height_0__pin_35_upper , + top_width_0_height_0__pin_35_lower , top_width_0_height_0__pin_36_upper , + top_width_0_height_0__pin_36_lower , top_width_0_height_0__pin_37_upper , + top_width_0_height_0__pin_37_lower , top_width_0_height_0__pin_38_upper , + top_width_0_height_0__pin_38_lower , top_width_0_height_0__pin_39_upper , + top_width_0_height_0__pin_39_lower , top_width_0_height_0__pin_40_upper , + top_width_0_height_0__pin_40_lower , top_width_0_height_0__pin_41_upper , + top_width_0_height_0__pin_41_lower , + right_width_0_height_0__pin_42_upper , + right_width_0_height_0__pin_42_lower , + right_width_0_height_0__pin_43_upper , + right_width_0_height_0__pin_43_lower , + right_width_0_height_0__pin_44_upper , + right_width_0_height_0__pin_44_lower , + right_width_0_height_0__pin_45_upper , + right_width_0_height_0__pin_45_lower , + right_width_0_height_0__pin_46_upper , + right_width_0_height_0__pin_46_lower , + right_width_0_height_0__pin_47_upper , + right_width_0_height_0__pin_47_lower , + right_width_0_height_0__pin_48_upper , + right_width_0_height_0__pin_48_lower , + right_width_0_height_0__pin_49_upper , + right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , + bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_1_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_3_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_5_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_7_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_9_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_11_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_13_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_15_ ; input [0:0] top_width_0_height_0__pin_32_ ; input [0:0] top_width_0_height_0__pin_33_ ; -input [0:0] right_width_0_height_0__pin_0_ ; -input [0:0] right_width_0_height_0__pin_1_ ; -input [0:0] right_width_0_height_0__pin_2_ ; -input [0:0] right_width_0_height_0__pin_3_ ; -input [0:0] right_width_0_height_0__pin_4_ ; -input [0:0] right_width_0_height_0__pin_5_ ; -input [0:0] right_width_0_height_0__pin_6_ ; -input [0:0] right_width_0_height_0__pin_7_ ; -input [0:0] right_width_0_height_0__pin_8_ ; -input [0:0] right_width_0_height_0__pin_9_ ; -input [0:0] right_width_0_height_0__pin_10_ ; -input [0:0] right_width_0_height_0__pin_11_ ; -input [0:0] right_width_0_height_0__pin_12_ ; -input [0:0] right_width_0_height_0__pin_13_ ; -input [0:0] right_width_0_height_0__pin_14_ ; -input [0:0] right_width_0_height_0__pin_15_ ; -input [0:0] bottom_width_0_height_0__pin_16_ ; -input [0:0] bottom_width_0_height_0__pin_17_ ; -input [0:0] bottom_width_0_height_0__pin_18_ ; -input [0:0] bottom_width_0_height_0__pin_19_ ; -input [0:0] bottom_width_0_height_0__pin_20_ ; -input [0:0] bottom_width_0_height_0__pin_21_ ; -input [0:0] bottom_width_0_height_0__pin_22_ ; -input [0:0] bottom_width_0_height_0__pin_23_ ; -input [0:0] bottom_width_0_height_0__pin_24_ ; -input [0:0] bottom_width_0_height_0__pin_25_ ; -input [0:0] bottom_width_0_height_0__pin_26_ ; -input [0:0] bottom_width_0_height_0__pin_27_ ; -input [0:0] bottom_width_0_height_0__pin_28_ ; -input [0:0] bottom_width_0_height_0__pin_29_ ; -input [0:0] bottom_width_0_height_0__pin_30_ ; -input [0:0] bottom_width_0_height_0__pin_31_ ; +input [0:0] right_width_0_height_0__pin_16_ ; +input [0:0] right_width_0_height_0__pin_17_ ; +input [0:0] right_width_0_height_0__pin_18_ ; +input [0:0] right_width_0_height_0__pin_19_ ; +input [0:0] right_width_0_height_0__pin_20_ ; +input [0:0] right_width_0_height_0__pin_21_ ; +input [0:0] right_width_0_height_0__pin_22_ ; +input [0:0] right_width_0_height_0__pin_23_ ; +input [0:0] right_width_0_height_0__pin_24_ ; +input [0:0] right_width_0_height_0__pin_25_ ; +input [0:0] right_width_0_height_0__pin_26_ ; +input [0:0] right_width_0_height_0__pin_27_ ; +input [0:0] right_width_0_height_0__pin_28_ ; +input [0:0] right_width_0_height_0__pin_29_ ; +input [0:0] right_width_0_height_0__pin_30_ ; +input [0:0] right_width_0_height_0__pin_31_ ; input [0:0] left_width_0_height_0__pin_52_ ; input [0:0] ccff_head ; -output [0:0] right_width_0_height_0__pin_34_upper ; -output [0:0] right_width_0_height_0__pin_34_lower ; -output [0:0] right_width_0_height_0__pin_35_upper ; -output [0:0] right_width_0_height_0__pin_35_lower ; -output [0:0] right_width_0_height_0__pin_36_upper ; -output [0:0] right_width_0_height_0__pin_36_lower ; -output [0:0] right_width_0_height_0__pin_37_upper ; -output [0:0] right_width_0_height_0__pin_37_lower ; -output [0:0] right_width_0_height_0__pin_38_upper ; -output [0:0] right_width_0_height_0__pin_38_lower ; -output [0:0] right_width_0_height_0__pin_39_upper ; -output [0:0] right_width_0_height_0__pin_39_lower ; -output [0:0] right_width_0_height_0__pin_40_upper ; -output [0:0] right_width_0_height_0__pin_40_lower ; -output [0:0] right_width_0_height_0__pin_41_upper ; -output [0:0] right_width_0_height_0__pin_41_lower ; -output [0:0] bottom_width_0_height_0__pin_42_upper ; -output [0:0] bottom_width_0_height_0__pin_42_lower ; -output [0:0] bottom_width_0_height_0__pin_43_upper ; -output [0:0] bottom_width_0_height_0__pin_43_lower ; -output [0:0] bottom_width_0_height_0__pin_44_upper ; -output [0:0] bottom_width_0_height_0__pin_44_lower ; -output [0:0] bottom_width_0_height_0__pin_45_upper ; -output [0:0] bottom_width_0_height_0__pin_45_lower ; -output [0:0] bottom_width_0_height_0__pin_46_upper ; -output [0:0] bottom_width_0_height_0__pin_46_lower ; -output [0:0] bottom_width_0_height_0__pin_47_upper ; -output [0:0] bottom_width_0_height_0__pin_47_lower ; -output [0:0] bottom_width_0_height_0__pin_48_upper ; -output [0:0] bottom_width_0_height_0__pin_48_lower ; -output [0:0] bottom_width_0_height_0__pin_49_upper ; -output [0:0] bottom_width_0_height_0__pin_49_lower ; +output [0:0] top_width_0_height_0__pin_34_upper ; +output [0:0] top_width_0_height_0__pin_34_lower ; +output [0:0] top_width_0_height_0__pin_35_upper ; +output [0:0] top_width_0_height_0__pin_35_lower ; +output [0:0] top_width_0_height_0__pin_36_upper ; +output [0:0] top_width_0_height_0__pin_36_lower ; +output [0:0] top_width_0_height_0__pin_37_upper ; +output [0:0] top_width_0_height_0__pin_37_lower ; +output [0:0] top_width_0_height_0__pin_38_upper ; +output [0:0] top_width_0_height_0__pin_38_lower ; +output [0:0] top_width_0_height_0__pin_39_upper ; +output [0:0] top_width_0_height_0__pin_39_lower ; +output [0:0] top_width_0_height_0__pin_40_upper ; +output [0:0] top_width_0_height_0__pin_40_lower ; +output [0:0] top_width_0_height_0__pin_41_upper ; +output [0:0] top_width_0_height_0__pin_41_lower ; +output [0:0] right_width_0_height_0__pin_42_upper ; +output [0:0] right_width_0_height_0__pin_42_lower ; +output [0:0] right_width_0_height_0__pin_43_upper ; +output [0:0] right_width_0_height_0__pin_43_lower ; +output [0:0] right_width_0_height_0__pin_44_upper ; +output [0:0] right_width_0_height_0__pin_44_lower ; +output [0:0] right_width_0_height_0__pin_45_upper ; +output [0:0] right_width_0_height_0__pin_45_lower ; +output [0:0] right_width_0_height_0__pin_46_upper ; +output [0:0] right_width_0_height_0__pin_46_lower ; +output [0:0] right_width_0_height_0__pin_47_upper ; +output [0:0] right_width_0_height_0__pin_47_lower ; +output [0:0] right_width_0_height_0__pin_48_upper ; +output [0:0] right_width_0_height_0__pin_48_lower ; +output [0:0] right_width_0_height_0__pin_49_upper ; +output [0:0] right_width_0_height_0__pin_49_lower ; output [0:0] bottom_width_0_height_0__pin_50_ ; output [0:0] bottom_width_0_height_0__pin_51_ ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; -wire ropt_net_128 ; -wire ropt_net_134 ; -wire ropt_net_136 ; -wire ropt_net_147 ; -wire ropt_net_133 ; -wire ropt_net_144 ; -wire ropt_net_126 ; -wire ropt_net_130 ; -wire ropt_net_135 ; +wire p_abuf1 ; wire p_abuf14 ; +wire p_abuf2 ; +wire p_abuf5 ; +wire p_abuf4 ; +wire ropt_net_143 ; +wire ropt_net_148 ; +wire ropt_net_144 ; +wire p_abuf13 ; +wire p_abuf12 ; +wire ropt_net_131 ; +wire ropt_net_130 ; +wire ropt_net_133 ; + +assign SC_IN_TOP = SC_IN_BOT ; logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .clb_I0 ( { right_width_0_height_0__pin_0_[0] , - right_width_0_height_0__pin_1_[0] , - right_width_0_height_0__pin_2_[0] , - right_width_0_height_0__pin_3_[0] } ) , - .clb_I1 ( { right_width_0_height_0__pin_4_[0] , - right_width_0_height_0__pin_5_[0] , - right_width_0_height_0__pin_6_[0] , - right_width_0_height_0__pin_7_[0] } ) , - .clb_I2 ( { right_width_0_height_0__pin_8_[0] , - right_width_0_height_0__pin_9_[0] , - right_width_0_height_0__pin_10_[0] , - right_width_0_height_0__pin_11_[0] } ) , - .clb_I3 ( { right_width_0_height_0__pin_12_[0] , - right_width_0_height_0__pin_13_[0] , - right_width_0_height_0__pin_14_[0] , - right_width_0_height_0__pin_15_[0] } ) , - .clb_I4 ( { bottom_width_0_height_0__pin_16_[0] , - bottom_width_0_height_0__pin_17_[0] , - bottom_width_0_height_0__pin_18_[0] , - bottom_width_0_height_0__pin_19_[0] } ) , - .clb_I5 ( { bottom_width_0_height_0__pin_20_[0] , - bottom_width_0_height_0__pin_21_[0] , - bottom_width_0_height_0__pin_22_[0] , - bottom_width_0_height_0__pin_23_[0] } ) , - .clb_I6 ( { bottom_width_0_height_0__pin_24_[0] , - bottom_width_0_height_0__pin_25_[0] , - bottom_width_0_height_0__pin_26_[0] , - bottom_width_0_height_0__pin_27_[0] } ) , - .clb_I7 ( { bottom_width_0_height_0__pin_28_[0] , - bottom_width_0_height_0__pin_29_[0] , - bottom_width_0_height_0__pin_30_[0] , - bottom_width_0_height_0__pin_31_[0] } ) , - .clb_regin ( top_width_0_height_0__pin_32_ ) , - .clb_scin ( top_width_0_height_0__pin_33_ ) , + .clb_I0 ( { top_width_0_height_0__pin_0_[0] , + top_width_0_height_0__pin_1_[0] , top_width_0_height_0__pin_2_[0] } ) , + .clb_I0i ( top_width_0_height_0__pin_3_ ) , + .clb_I1 ( { top_width_0_height_0__pin_4_[0] , + top_width_0_height_0__pin_5_[0] , top_width_0_height_0__pin_6_[0] } ) , + .clb_I1i ( top_width_0_height_0__pin_7_ ) , + .clb_I2 ( { top_width_0_height_0__pin_8_[0] , + top_width_0_height_0__pin_9_[0] , top_width_0_height_0__pin_10_[0] } ) , + .clb_I2i ( top_width_0_height_0__pin_11_ ) , + .clb_I3 ( { top_width_0_height_0__pin_12_[0] , + top_width_0_height_0__pin_13_[0] , top_width_0_height_0__pin_14_[0] } ) , + .clb_I3i ( top_width_0_height_0__pin_15_ ) , + .clb_I4 ( { right_width_0_height_0__pin_16_[0] , + right_width_0_height_0__pin_17_[0] , + right_width_0_height_0__pin_18_[0] } ) , + .clb_I4i ( right_width_0_height_0__pin_19_ ) , + .clb_I5 ( { right_width_0_height_0__pin_20_[0] , + right_width_0_height_0__pin_21_[0] , + right_width_0_height_0__pin_22_[0] } ) , + .clb_I5i ( right_width_0_height_0__pin_23_ ) , + .clb_I6 ( { right_width_0_height_0__pin_24_[0] , + right_width_0_height_0__pin_25_[0] , + right_width_0_height_0__pin_26_[0] } ) , + .clb_I6i ( right_width_0_height_0__pin_27_ ) , + .clb_I7 ( { right_width_0_height_0__pin_28_[0] , + right_width_0_height_0__pin_29_[0] , + right_width_0_height_0__pin_30_[0] } ) , + .clb_I7i ( right_width_0_height_0__pin_31_ ) , + .clb_regin ( top_width_0_height_0__pin_32_ ) , + .clb_sc_in ( { SC_IN_BOT } ) , .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_129_ , aps_rename_130_ , aps_rename_132_ , - aps_rename_134_ , aps_rename_136_ , aps_rename_138_ , - aps_rename_140_ , aps_rename_141_ , aps_rename_143_ , - aps_rename_145_ , aps_rename_147_ , aps_rename_149_ , - aps_rename_151_ , aps_rename_153_ , aps_rename_155_ , - bottom_width_0_height_0__pin_49_upper[0] } ) , - .clb_regout ( bottom_width_0_height_0__pin_50_ ) , - .clb_scout ( bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( { ropt_net_124 } ) , - .p_abuf0 ( right_width_0_height_0__pin_35_upper[0] ) , - .p_abuf1 ( right_width_0_height_0__pin_34_upper[0] ) , - .p_abuf2 ( ropt_net_134 ) , .p_abuf3 ( ropt_net_128 ) , - .p_abuf4 ( right_width_0_height_0__pin_39_upper[0] ) , - .p_abuf5 ( ropt_net_136 ) , .p_abuf6 ( ropt_net_133 ) , - .p_abuf7 ( ropt_net_147 ) , .p_abuf8 ( ropt_net_144 ) , - .p_abuf9 ( bottom_width_0_height_0__pin_42_upper[0] ) , - .p_abuf10 ( ropt_net_126 ) , - .p_abuf11 ( bottom_width_0_height_0__pin_44_upper[0] ) , - .p_abuf12 ( bottom_width_0_height_0__pin_47_upper[0] ) , - .p_abuf13 ( ropt_net_130 ) , .p_abuf14 ( p_abuf14 ) , - .p_abuf15 ( ropt_net_135 ) , .p0 ( optlc_net_118 ) , - .p1 ( optlc_net_119 ) , .p2 ( optlc_net_120 ) , .p3 ( optlc_net_121 ) , - .p4 ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( aps_rename_129_ ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( aps_rename_130_ ) , + .clb_O ( { ropt_net_145 , ropt_net_137 , aps_rename_132_ , + top_width_0_height_0__pin_37_upper[0] , + top_width_0_height_0__pin_38_upper[0] , ropt_net_141 , + aps_rename_137_ , aps_rename_139_ , aps_rename_141_ , + aps_rename_143_ , aps_rename_145_ , aps_rename_147_ , + right_width_0_height_0__pin_46_upper[0] , ropt_net_146 , + ropt_net_131 , ropt_net_130 } ) , + .clb_regout ( { ropt_net_134 } ) , + .clb_sc_out ( { aps_rename_153_ } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_133 ) , + .p_abuf3 ( p_abuf1 ) , .p_abuf4 ( p_abuf2 ) , + .p_abuf5 ( top_width_0_height_0__pin_36_upper[0] ) , + .p_abuf6 ( p_abuf4 ) , .p_abuf7 ( p_abuf5 ) , + .p_abuf8 ( top_width_0_height_0__pin_41_upper[0] ) , + .p_abuf9 ( ropt_net_143 ) , .p_abuf10 ( ropt_net_148 ) , + .p_abuf11 ( right_width_0_height_0__pin_42_upper[0] ) , + .p_abuf12 ( right_width_0_height_0__pin_45_upper[0] ) , + .p_abuf13 ( ropt_net_144 ) , .p_abuf14 ( p_abuf12 ) , + .p_abuf15 ( p_abuf13 ) , .p_abuf16 ( p_abuf14 ) , .p0 ( optlc_net_125 ) , + .p1 ( optlc_net_126 ) , .p2 ( optlc_net_127 ) , .p3 ( optlc_net_128 ) , + .p4 ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( p_abuf1 ) , + .X ( aps_rename_130_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( p_abuf14 ) , .X ( aps_rename_131_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( aps_rename_132_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( aps_rename_132_ ) , .X ( aps_rename_133_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( aps_rename_134_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( p_abuf2 ) , + .X ( aps_rename_134_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( p_abuf5 ) , .X ( aps_rename_135_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( aps_rename_136_ ) , - .X ( aps_rename_137_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( aps_rename_138_ ) , - .X ( aps_rename_139_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_140_ ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( aps_rename_141_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( p_abuf4 ) , + .X ( aps_rename_136_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_137_ ) , + .X ( aps_rename_138_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( aps_rename_139_ ) , + .X ( aps_rename_140_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( aps_rename_141_ ) , .X ( aps_rename_142_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( aps_rename_143_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( aps_rename_143_ ) , .X ( aps_rename_144_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( aps_rename_145_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( aps_rename_145_ ) , .X ( aps_rename_146_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( aps_rename_147_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( aps_rename_147_ ) , .X ( aps_rename_148_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( aps_rename_149_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( p_abuf13 ) , + .X ( aps_rename_149_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( p_abuf12 ) , .X ( aps_rename_150_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( aps_rename_151_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( ropt_net_131 ) , + .X ( aps_rename_151_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( ropt_net_130 ) , .X ( aps_rename_152_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( aps_rename_153_ ) , - .X ( aps_rename_154_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( aps_rename_155_ ) , - .X ( bottom_width_0_height_0__pin_48_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( p_abuf14 ) , - .X ( bottom_width_0_height_0__pin_49_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_89 ( .A ( aps_rename_131_ ) , - .X ( BUF_net_89 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( aps_rename_133_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( aps_rename_153_ ) , .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( .A ( aps_rename_135_ ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( aps_rename_137_ ) , - .X ( right_width_0_height_0__pin_38_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( aps_rename_139_ ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( aps_rename_142_ ) , - .X ( right_width_0_height_0__pin_41_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( aps_rename_144_ ) , - .X ( bottom_width_0_height_0__pin_42_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( aps_rename_146_ ) , - .X ( BUF_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( aps_rename_148_ ) , - .X ( BUF_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( .A ( aps_rename_150_ ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_99 ( .A ( aps_rename_152_ ) , - .X ( BUF_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_154_ ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_110 ( .A ( BUF_net_89 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_111 ( .A ( BUF_net_96 ) , - .X ( bottom_width_0_height_0__pin_43_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( BUF_net_97 ) , - .X ( bottom_width_0_height_0__pin_44_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( BUF_net_99 ) , - .X ( bottom_width_0_height_0__pin_46_lower[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_118 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_119 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_120 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( aps_rename_130_ ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( aps_rename_131_ ) , + .X ( top_width_0_height_0__pin_35_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( aps_rename_133_ ) , + .X ( top_width_0_height_0__pin_36_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_134_ ) , + .X ( top_width_0_height_0__pin_37_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( aps_rename_135_ ) , + .X ( BUF_net_88 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( aps_rename_136_ ) , + .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( aps_rename_138_ ) , + .X ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( .A ( aps_rename_140_ ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_142_ ) , .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_879 ( .A ( ropt_net_125 ) , - .X ( right_width_0_height_0__pin_37_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_880 ( .A ( ropt_net_126 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_93 ( .A ( aps_rename_144_ ) , + .X ( right_width_0_height_0__pin_43_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_146_ ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( aps_rename_148_ ) , + .X ( right_width_0_height_0__pin_45_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( aps_rename_149_ ) , .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_881 ( .A ( ropt_net_127 ) , - .X ( bottom_width_0_height_0__pin_47_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_882 ( .A ( ropt_net_128 ) , - .X ( right_width_0_height_0__pin_36_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_884 ( .A ( ropt_net_129 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_885 ( .A ( ropt_net_130 ) , - .X ( bottom_width_0_height_0__pin_46_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_886 ( .A ( ropt_net_131 ) , - .X ( right_width_0_height_0__pin_40_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_887 ( .A ( ropt_net_132 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( aps_rename_150_ ) , .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_888 ( .A ( ropt_net_133 ) , - .X ( right_width_0_height_0__pin_41_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_890 ( .A ( ropt_net_134 ) , - .X ( right_width_0_height_0__pin_37_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_892 ( .A ( ropt_net_135 ) , - .X ( bottom_width_0_height_0__pin_48_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_895 ( .A ( ropt_net_136 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_898 ( .A ( ropt_net_137 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_909 ( .A ( ropt_net_138 ) , - .X ( bottom_width_0_height_0__pin_45_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_913 ( .A ( ropt_net_139 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_914 ( .A ( ropt_net_140 ) , - .X ( bottom_width_0_height_0__pin_45_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_915 ( .A ( ropt_net_141 ) , - .X ( right_width_0_height_0__pin_39_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_916 ( .A ( ropt_net_142 ) , - .X ( right_width_0_height_0__pin_36_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_917 ( .A ( ropt_net_143 ) , - .X ( right_width_0_height_0__pin_34_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_918 ( .A ( ropt_net_144 ) , - .X ( bottom_width_0_height_0__pin_43_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_919 ( .A ( ropt_net_145 ) , - .X ( right_width_0_height_0__pin_38_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_920 ( .A ( ropt_net_146 ) , - .X ( right_width_0_height_0__pin_35_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_921 ( .A ( ropt_net_147 ) , - .X ( right_width_0_height_0__pin_40_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_98 ( .A ( aps_rename_151_ ) , + .X ( right_width_0_height_0__pin_48_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( aps_rename_152_ ) , + .X ( right_width_0_height_0__pin_49_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( BUF_net_119 ) , + .X ( top_width_0_height_0__pin_38_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( BUF_net_88 ) , + .X ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_120 ( .A ( BUF_net_89 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( BUF_net_122 ) , + .X ( top_width_0_height_0__pin_40_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_122 ( .A ( BUF_net_90 ) , + .X ( BUF_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_884 ( .A ( ropt_net_130 ) , + .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_885 ( .A ( ropt_net_131 ) , + .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_886 ( .A ( ropt_net_132 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_133 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_134 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_889 ( .A ( ropt_net_135 ) , + .X ( top_width_0_height_0__pin_34_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_890 ( .A ( ropt_net_136 ) , + .X ( top_width_0_height_0__pin_41_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_893 ( .A ( ropt_net_137 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_896 ( .A ( ropt_net_138 ) , + .X ( right_width_0_height_0__pin_44_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_897 ( .A ( ropt_net_139 ) , + .X ( right_width_0_height_0__pin_42_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_898 ( .A ( ropt_net_140 ) , + .X ( right_width_0_height_0__pin_46_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_899 ( .A ( ropt_net_141 ) , + .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_900 ( .A ( ropt_net_142 ) , + .X ( right_width_0_height_0__pin_47_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_901 ( .A ( ropt_net_143 ) , + .X ( top_width_0_height_0__pin_40_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_903 ( .A ( ropt_net_144 ) , + .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_906 ( .A ( ropt_net_145 ) , + .X ( top_width_0_height_0__pin_34_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_908 ( .A ( ropt_net_146 ) , + .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_910 ( .A ( ropt_net_147 ) , + .X ( top_width_0_height_0__pin_39_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_914 ( .A ( ropt_net_148 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_915 ( .A ( ropt_net_150 ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_916 ( .A ( ropt_net_151 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_919 ( .A ( ropt_net_152 ) , + .X ( top_width_0_height_0__pin_35_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_920 ( .A ( ropt_net_153 ) , + .X ( right_width_0_height_0__pin_43_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_154 ) , + .X ( bottom_width_0_height_0__pin_50_[0] ) ) ; endmodule -module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , ccff_head , - ccff_tail ) ; +module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + ccff_head , ccff_tail , sc_head , sc_tail ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; -output [0:7] gfpga_pad_GPIO_A ; -output [0:7] gfpga_pad_GPIO_IE ; -output [0:7] gfpga_pad_GPIO_OE ; -inout [0:7] gfpga_pad_GPIO_Y ; +input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] ccff_head ; output [0:0] ccff_tail ; +input sc_head ; +output sc_tail ; wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__0__0_ccff_tail ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ; wire [0:19] cbx_1__0__0_chanx_left_out ; wire [0:19] cbx_1__0__0_chanx_right_out ; -wire [0:0] cbx_1__0__0_top_grid_pin_16_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_17_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_18_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_19_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_20_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_21_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_22_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_23_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_24_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_25_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_26_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_27_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_28_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_29_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_30_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_31_ ; wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__0__1_ccff_tail ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ; wire [0:19] cbx_1__0__1_chanx_left_out ; wire [0:19] cbx_1__0__1_chanx_right_out ; -wire [0:0] cbx_1__0__1_top_grid_pin_16_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_17_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_18_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_19_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_20_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_21_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_22_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_23_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_24_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_25_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_26_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_27_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_28_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_29_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_30_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_31_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ; wire [0:0] cbx_1__1__0_ccff_tail ; wire [0:19] cbx_1__1__0_chanx_left_out ; wire [0:19] cbx_1__1__0_chanx_right_out ; -wire [0:0] cbx_1__1__0_top_grid_pin_16_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_17_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_18_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_19_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_20_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_21_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_22_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_23_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_24_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_25_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_26_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_27_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_28_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_29_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_30_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_31_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ; wire [0:0] cbx_1__1__1_ccff_tail ; wire [0:19] cbx_1__1__1_chanx_left_out ; wire [0:19] cbx_1__1__1_chanx_right_out ; -wire [0:0] cbx_1__1__1_top_grid_pin_16_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_17_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_18_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_19_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_20_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_21_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_22_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_23_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_24_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_25_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_26_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_27_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_28_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_29_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_30_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_31_ ; -wire [0:0] cbx_1__2__0_ccff_tail ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_9_ ; wire [0:19] cbx_1__2__0_chanx_left_out ; wire [0:19] cbx_1__2__0_chanx_right_out ; wire [0:0] cbx_1__2__0_top_grid_pin_0_ ; -wire [0:0] cbx_1__2__1_ccff_tail ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_9_ ; wire [0:19] cbx_1__2__1_chanx_left_out ; wire [0:19] cbx_1__2__1_chanx_right_out ; wire [0:0] cbx_1__2__1_top_grid_pin_0_ ; -wire [0:0] cby_0__1__0_ccff_tail ; wire [0:19] cby_0__1__0_chany_bottom_out ; wire [0:19] cby_0__1__0_chany_top_out ; wire [0:0] cby_0__1__0_left_grid_pin_0_ ; -wire [0:0] cby_0__1__0_right_grid_pin_52_ ; -wire [0:0] cby_0__1__1_ccff_tail ; wire [0:19] cby_0__1__1_chany_bottom_out ; wire [0:19] cby_0__1__1_chany_top_out ; wire [0:0] cby_0__1__1_left_grid_pin_0_ ; -wire [0:0] cby_0__1__1_right_grid_pin_52_ ; wire [0:0] cby_1__1__0_ccff_tail ; wire [0:19] cby_1__1__0_chany_bottom_out ; wire [0:19] cby_1__1__0_chany_top_out ; -wire [0:0] cby_1__1__0_left_grid_pin_0_ ; -wire [0:0] cby_1__1__0_left_grid_pin_10_ ; -wire [0:0] cby_1__1__0_left_grid_pin_11_ ; -wire [0:0] cby_1__1__0_left_grid_pin_12_ ; -wire [0:0] cby_1__1__0_left_grid_pin_13_ ; -wire [0:0] cby_1__1__0_left_grid_pin_14_ ; -wire [0:0] cby_1__1__0_left_grid_pin_15_ ; -wire [0:0] cby_1__1__0_left_grid_pin_1_ ; -wire [0:0] cby_1__1__0_left_grid_pin_2_ ; -wire [0:0] cby_1__1__0_left_grid_pin_3_ ; -wire [0:0] cby_1__1__0_left_grid_pin_4_ ; -wire [0:0] cby_1__1__0_left_grid_pin_5_ ; -wire [0:0] cby_1__1__0_left_grid_pin_6_ ; -wire [0:0] cby_1__1__0_left_grid_pin_7_ ; -wire [0:0] cby_1__1__0_left_grid_pin_8_ ; -wire [0:0] cby_1__1__0_left_grid_pin_9_ ; -wire [0:0] cby_1__1__0_right_grid_pin_52_ ; +wire [0:0] cby_1__1__0_left_grid_pin_16_ ; +wire [0:0] cby_1__1__0_left_grid_pin_17_ ; +wire [0:0] cby_1__1__0_left_grid_pin_18_ ; +wire [0:0] cby_1__1__0_left_grid_pin_19_ ; +wire [0:0] cby_1__1__0_left_grid_pin_20_ ; +wire [0:0] cby_1__1__0_left_grid_pin_21_ ; +wire [0:0] cby_1__1__0_left_grid_pin_22_ ; +wire [0:0] cby_1__1__0_left_grid_pin_23_ ; +wire [0:0] cby_1__1__0_left_grid_pin_24_ ; +wire [0:0] cby_1__1__0_left_grid_pin_25_ ; +wire [0:0] cby_1__1__0_left_grid_pin_26_ ; +wire [0:0] cby_1__1__0_left_grid_pin_27_ ; +wire [0:0] cby_1__1__0_left_grid_pin_28_ ; +wire [0:0] cby_1__1__0_left_grid_pin_29_ ; +wire [0:0] cby_1__1__0_left_grid_pin_30_ ; +wire [0:0] cby_1__1__0_left_grid_pin_31_ ; wire [0:0] cby_1__1__1_ccff_tail ; wire [0:19] cby_1__1__1_chany_bottom_out ; wire [0:19] cby_1__1__1_chany_top_out ; -wire [0:0] cby_1__1__1_left_grid_pin_0_ ; -wire [0:0] cby_1__1__1_left_grid_pin_10_ ; -wire [0:0] cby_1__1__1_left_grid_pin_11_ ; -wire [0:0] cby_1__1__1_left_grid_pin_12_ ; -wire [0:0] cby_1__1__1_left_grid_pin_13_ ; -wire [0:0] cby_1__1__1_left_grid_pin_14_ ; -wire [0:0] cby_1__1__1_left_grid_pin_15_ ; -wire [0:0] cby_1__1__1_left_grid_pin_1_ ; -wire [0:0] cby_1__1__1_left_grid_pin_2_ ; -wire [0:0] cby_1__1__1_left_grid_pin_3_ ; -wire [0:0] cby_1__1__1_left_grid_pin_4_ ; -wire [0:0] cby_1__1__1_left_grid_pin_5_ ; -wire [0:0] cby_1__1__1_left_grid_pin_6_ ; -wire [0:0] cby_1__1__1_left_grid_pin_7_ ; -wire [0:0] cby_1__1__1_left_grid_pin_8_ ; -wire [0:0] cby_1__1__1_left_grid_pin_9_ ; -wire [0:0] cby_1__1__1_right_grid_pin_52_ ; -wire [0:0] cby_1__1__2_ccff_tail ; -wire [0:19] cby_1__1__2_chany_bottom_out ; -wire [0:19] cby_1__1__2_chany_top_out ; -wire [0:0] cby_1__1__2_left_grid_pin_0_ ; -wire [0:0] cby_1__1__2_left_grid_pin_10_ ; -wire [0:0] cby_1__1__2_left_grid_pin_11_ ; -wire [0:0] cby_1__1__2_left_grid_pin_12_ ; -wire [0:0] cby_1__1__2_left_grid_pin_13_ ; -wire [0:0] cby_1__1__2_left_grid_pin_14_ ; -wire [0:0] cby_1__1__2_left_grid_pin_15_ ; -wire [0:0] cby_1__1__2_left_grid_pin_1_ ; -wire [0:0] cby_1__1__2_left_grid_pin_2_ ; -wire [0:0] cby_1__1__2_left_grid_pin_3_ ; -wire [0:0] cby_1__1__2_left_grid_pin_4_ ; -wire [0:0] cby_1__1__2_left_grid_pin_5_ ; -wire [0:0] cby_1__1__2_left_grid_pin_6_ ; -wire [0:0] cby_1__1__2_left_grid_pin_7_ ; -wire [0:0] cby_1__1__2_left_grid_pin_8_ ; -wire [0:0] cby_1__1__2_left_grid_pin_9_ ; -wire [0:0] cby_1__1__2_right_grid_pin_52_ ; -wire [0:0] cby_1__1__3_ccff_tail ; -wire [0:19] cby_1__1__3_chany_bottom_out ; -wire [0:19] cby_1__1__3_chany_top_out ; -wire [0:0] cby_1__1__3_left_grid_pin_0_ ; -wire [0:0] cby_1__1__3_left_grid_pin_10_ ; -wire [0:0] cby_1__1__3_left_grid_pin_11_ ; -wire [0:0] cby_1__1__3_left_grid_pin_12_ ; -wire [0:0] cby_1__1__3_left_grid_pin_13_ ; -wire [0:0] cby_1__1__3_left_grid_pin_14_ ; -wire [0:0] cby_1__1__3_left_grid_pin_15_ ; -wire [0:0] cby_1__1__3_left_grid_pin_1_ ; -wire [0:0] cby_1__1__3_left_grid_pin_2_ ; -wire [0:0] cby_1__1__3_left_grid_pin_3_ ; -wire [0:0] cby_1__1__3_left_grid_pin_4_ ; -wire [0:0] cby_1__1__3_left_grid_pin_5_ ; -wire [0:0] cby_1__1__3_left_grid_pin_6_ ; -wire [0:0] cby_1__1__3_left_grid_pin_7_ ; -wire [0:0] cby_1__1__3_left_grid_pin_8_ ; -wire [0:0] cby_1__1__3_left_grid_pin_9_ ; -wire [0:0] cby_1__1__3_right_grid_pin_52_ ; +wire [0:0] cby_1__1__1_left_grid_pin_16_ ; +wire [0:0] cby_1__1__1_left_grid_pin_17_ ; +wire [0:0] cby_1__1__1_left_grid_pin_18_ ; +wire [0:0] cby_1__1__1_left_grid_pin_19_ ; +wire [0:0] cby_1__1__1_left_grid_pin_20_ ; +wire [0:0] cby_1__1__1_left_grid_pin_21_ ; +wire [0:0] cby_1__1__1_left_grid_pin_22_ ; +wire [0:0] cby_1__1__1_left_grid_pin_23_ ; +wire [0:0] cby_1__1__1_left_grid_pin_24_ ; +wire [0:0] cby_1__1__1_left_grid_pin_25_ ; +wire [0:0] cby_1__1__1_left_grid_pin_26_ ; +wire [0:0] cby_1__1__1_left_grid_pin_27_ ; +wire [0:0] cby_1__1__1_left_grid_pin_28_ ; +wire [0:0] cby_1__1__1_left_grid_pin_29_ ; +wire [0:0] cby_1__1__1_left_grid_pin_30_ ; +wire [0:0] cby_1__1__1_left_grid_pin_31_ ; +wire [0:19] cby_2__1__0_chany_bottom_out ; +wire [0:19] cby_2__1__0_chany_top_out ; +wire [0:0] cby_2__1__0_left_grid_pin_16_ ; +wire [0:0] cby_2__1__0_left_grid_pin_17_ ; +wire [0:0] cby_2__1__0_left_grid_pin_18_ ; +wire [0:0] cby_2__1__0_left_grid_pin_19_ ; +wire [0:0] cby_2__1__0_left_grid_pin_20_ ; +wire [0:0] cby_2__1__0_left_grid_pin_21_ ; +wire [0:0] cby_2__1__0_left_grid_pin_22_ ; +wire [0:0] cby_2__1__0_left_grid_pin_23_ ; +wire [0:0] cby_2__1__0_left_grid_pin_24_ ; +wire [0:0] cby_2__1__0_left_grid_pin_25_ ; +wire [0:0] cby_2__1__0_left_grid_pin_26_ ; +wire [0:0] cby_2__1__0_left_grid_pin_27_ ; +wire [0:0] cby_2__1__0_left_grid_pin_28_ ; +wire [0:0] cby_2__1__0_left_grid_pin_29_ ; +wire [0:0] cby_2__1__0_left_grid_pin_30_ ; +wire [0:0] cby_2__1__0_left_grid_pin_31_ ; +wire [0:0] cby_2__1__0_right_grid_pin_0_ ; +wire [0:19] cby_2__1__1_chany_bottom_out ; +wire [0:19] cby_2__1__1_chany_top_out ; +wire [0:0] cby_2__1__1_left_grid_pin_16_ ; +wire [0:0] cby_2__1__1_left_grid_pin_17_ ; +wire [0:0] cby_2__1__1_left_grid_pin_18_ ; +wire [0:0] cby_2__1__1_left_grid_pin_19_ ; +wire [0:0] cby_2__1__1_left_grid_pin_20_ ; +wire [0:0] cby_2__1__1_left_grid_pin_21_ ; +wire [0:0] cby_2__1__1_left_grid_pin_22_ ; +wire [0:0] cby_2__1__1_left_grid_pin_23_ ; +wire [0:0] cby_2__1__1_left_grid_pin_24_ ; +wire [0:0] cby_2__1__1_left_grid_pin_25_ ; +wire [0:0] cby_2__1__1_left_grid_pin_26_ ; +wire [0:0] cby_2__1__1_left_grid_pin_27_ ; +wire [0:0] cby_2__1__1_left_grid_pin_28_ ; +wire [0:0] cby_2__1__1_left_grid_pin_29_ ; +wire [0:0] cby_2__1__1_left_grid_pin_30_ ; +wire [0:0] cby_2__1__1_left_grid_pin_31_ ; +wire [0:0] cby_2__1__1_right_grid_pin_0_ ; wire [0:0] direct_interc_0_out ; wire [0:0] direct_interc_1_out ; wire [0:0] direct_interc_2_out ; -wire [0:0] direct_interc_3_out ; -wire [0:0] direct_interc_4_out ; wire [0:0] direct_interc_5_out ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_upper ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_0_ccff_tail ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_upper ; wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_1_ccff_tail ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_2_ccff_tail ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_3_ccff_tail ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_io_bottom_0_ccff_tail ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ; wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ; wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ; wire [0:0] grid_io_bottom_1_ccff_tail ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ; wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ; wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ; wire [0:0] grid_io_left_0_ccff_tail ; wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ; wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ; @@ -30991,422 +35144,337 @@ wire [0:19] sb_2__2__0_chany_bottom_out ; // grid_clb grid_clb_1__1_ ( - .prog_clk ( { ctsbuf_net_1722 } ) , + .prog_clk ( { ctsbuf_net_1113 } ) , .Test_en ( Test_en ) , .clk ( clk ) , - .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , - .top_width_0_height_0__pin_33_ ( direct_interc_3_out ) , - .right_width_0_height_0__pin_0_ ( cby_1__1__0_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_ ( cby_1__1__0_left_grid_pin_1_ ) , - .right_width_0_height_0__pin_2_ ( cby_1__1__0_left_grid_pin_2_ ) , - .right_width_0_height_0__pin_3_ ( cby_1__1__0_left_grid_pin_3_ ) , - .right_width_0_height_0__pin_4_ ( cby_1__1__0_left_grid_pin_4_ ) , - .right_width_0_height_0__pin_5_ ( cby_1__1__0_left_grid_pin_5_ ) , - .right_width_0_height_0__pin_6_ ( cby_1__1__0_left_grid_pin_6_ ) , - .right_width_0_height_0__pin_7_ ( cby_1__1__0_left_grid_pin_7_ ) , - .right_width_0_height_0__pin_8_ ( cby_1__1__0_left_grid_pin_8_ ) , - .right_width_0_height_0__pin_9_ ( cby_1__1__0_left_grid_pin_9_ ) , - .right_width_0_height_0__pin_10_ ( cby_1__1__0_left_grid_pin_10_ ) , - .right_width_0_height_0__pin_11_ ( cby_1__1__0_left_grid_pin_11_ ) , - .right_width_0_height_0__pin_12_ ( cby_1__1__0_left_grid_pin_12_ ) , - .right_width_0_height_0__pin_13_ ( cby_1__1__0_left_grid_pin_13_ ) , - .right_width_0_height_0__pin_14_ ( cby_1__1__0_left_grid_pin_14_ ) , - .right_width_0_height_0__pin_15_ ( cby_1__1__0_left_grid_pin_15_ ) , - .bottom_width_0_height_0__pin_16_ ( cbx_1__0__0_top_grid_pin_16_ ) , - .bottom_width_0_height_0__pin_17_ ( cbx_1__0__0_top_grid_pin_17_ ) , - .bottom_width_0_height_0__pin_18_ ( cbx_1__0__0_top_grid_pin_18_ ) , - .bottom_width_0_height_0__pin_19_ ( cbx_1__0__0_top_grid_pin_19_ ) , - .bottom_width_0_height_0__pin_20_ ( cbx_1__0__0_top_grid_pin_20_ ) , - .bottom_width_0_height_0__pin_21_ ( cbx_1__0__0_top_grid_pin_21_ ) , - .bottom_width_0_height_0__pin_22_ ( cbx_1__0__0_top_grid_pin_22_ ) , - .bottom_width_0_height_0__pin_23_ ( cbx_1__0__0_top_grid_pin_23_ ) , - .bottom_width_0_height_0__pin_24_ ( cbx_1__0__0_top_grid_pin_24_ ) , - .bottom_width_0_height_0__pin_25_ ( cbx_1__0__0_top_grid_pin_25_ ) , - .bottom_width_0_height_0__pin_26_ ( cbx_1__0__0_top_grid_pin_26_ ) , - .bottom_width_0_height_0__pin_27_ ( cbx_1__0__0_top_grid_pin_27_ ) , - .bottom_width_0_height_0__pin_28_ ( cbx_1__0__0_top_grid_pin_28_ ) , - .bottom_width_0_height_0__pin_29_ ( cbx_1__0__0_top_grid_pin_29_ ) , - .bottom_width_0_height_0__pin_30_ ( cbx_1__0__0_top_grid_pin_30_ ) , - .bottom_width_0_height_0__pin_31_ ( cbx_1__0__0_top_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( cby_0__1__0_right_grid_pin_52_ ) , - .ccff_head ( { ropt_net_31 } ) , - - .right_width_0_height_0__pin_34_upper ( grid_clb_0_right_width_0_height_0__pin_34_upper ) , - .right_width_0_height_0__pin_34_lower ( grid_clb_0_right_width_0_height_0__pin_34_lower ) , - .right_width_0_height_0__pin_35_upper ( grid_clb_0_right_width_0_height_0__pin_35_upper ) , - .right_width_0_height_0__pin_35_lower ( grid_clb_0_right_width_0_height_0__pin_35_lower ) , - .right_width_0_height_0__pin_36_upper ( grid_clb_0_right_width_0_height_0__pin_36_upper ) , - .right_width_0_height_0__pin_36_lower ( grid_clb_0_right_width_0_height_0__pin_36_lower ) , - .right_width_0_height_0__pin_37_upper ( grid_clb_0_right_width_0_height_0__pin_37_upper ) , - .right_width_0_height_0__pin_37_lower ( grid_clb_0_right_width_0_height_0__pin_37_lower ) , - .right_width_0_height_0__pin_38_upper ( grid_clb_0_right_width_0_height_0__pin_38_upper ) , - .right_width_0_height_0__pin_38_lower ( grid_clb_0_right_width_0_height_0__pin_38_lower ) , - .right_width_0_height_0__pin_39_upper ( grid_clb_0_right_width_0_height_0__pin_39_upper ) , - .right_width_0_height_0__pin_39_lower ( grid_clb_0_right_width_0_height_0__pin_39_lower ) , - .right_width_0_height_0__pin_40_upper ( grid_clb_0_right_width_0_height_0__pin_40_upper ) , - .right_width_0_height_0__pin_40_lower ( grid_clb_0_right_width_0_height_0__pin_40_lower ) , - .right_width_0_height_0__pin_41_upper ( grid_clb_0_right_width_0_height_0__pin_41_upper ) , - .right_width_0_height_0__pin_41_lower ( grid_clb_0_right_width_0_height_0__pin_41_lower ) , - .bottom_width_0_height_0__pin_42_upper ( grid_clb_0_bottom_width_0_height_0__pin_42_upper ) , - .bottom_width_0_height_0__pin_42_lower ( grid_clb_0_bottom_width_0_height_0__pin_42_lower ) , - .bottom_width_0_height_0__pin_43_upper ( grid_clb_0_bottom_width_0_height_0__pin_43_upper ) , - .bottom_width_0_height_0__pin_43_lower ( grid_clb_0_bottom_width_0_height_0__pin_43_lower ) , - .bottom_width_0_height_0__pin_44_upper ( grid_clb_0_bottom_width_0_height_0__pin_44_upper ) , - .bottom_width_0_height_0__pin_44_lower ( grid_clb_0_bottom_width_0_height_0__pin_44_lower ) , - .bottom_width_0_height_0__pin_45_upper ( grid_clb_0_bottom_width_0_height_0__pin_45_upper ) , - .bottom_width_0_height_0__pin_45_lower ( grid_clb_0_bottom_width_0_height_0__pin_45_lower ) , - .bottom_width_0_height_0__pin_46_upper ( grid_clb_0_bottom_width_0_height_0__pin_46_upper ) , - .bottom_width_0_height_0__pin_46_lower ( grid_clb_0_bottom_width_0_height_0__pin_46_lower ) , - .bottom_width_0_height_0__pin_47_upper ( grid_clb_0_bottom_width_0_height_0__pin_47_upper ) , - .bottom_width_0_height_0__pin_47_lower ( grid_clb_0_bottom_width_0_height_0__pin_47_lower ) , - .bottom_width_0_height_0__pin_48_upper ( grid_clb_0_bottom_width_0_height_0__pin_48_upper ) , - .bottom_width_0_height_0__pin_48_lower ( grid_clb_0_bottom_width_0_height_0__pin_48_lower ) , - .bottom_width_0_height_0__pin_49_upper ( grid_clb_0_bottom_width_0_height_0__pin_49_upper ) , - .bottom_width_0_height_0__pin_49_lower ( grid_clb_0_bottom_width_0_height_0__pin_49_lower ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , + .top_width_0_height_0__pin_33_ ( { sc_in_wires_0_ } ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ) , + .ccff_head ( grid_io_left_0_ccff_tail ) , + .top_width_0_height_0__pin_34_upper ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , + .top_width_0_height_0__pin_34_lower ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , + .top_width_0_height_0__pin_35_upper ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , + .top_width_0_height_0__pin_35_lower ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , + .right_width_0_height_0__pin_42_upper ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , + .right_width_0_height_0__pin_42_lower ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , + .right_width_0_height_0__pin_43_upper ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , + .right_width_0_height_0__pin_43_lower ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , .bottom_width_0_height_0__pin_51_ ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( grid_clb_0_ccff_tail ) ) ; + .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_3_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2 ) , .SC_OUT_BOT ( scff_Wires_5_ ) ) ; grid_clb grid_clb_1__2_ ( - .prog_clk ( { ctsbuf_net_1318 } ) , + .prog_clk ( { ctsbuf_net_1517 } ) , .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__2__0_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__2__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__2__0_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__2__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__2__0_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__2__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__2__0_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__2__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__2__0_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__2__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , .top_width_0_height_0__pin_33_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ) , - .right_width_0_height_0__pin_0_ ( cby_1__1__1_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_ ( cby_1__1__1_left_grid_pin_1_ ) , - .right_width_0_height_0__pin_2_ ( cby_1__1__1_left_grid_pin_2_ ) , - .right_width_0_height_0__pin_3_ ( cby_1__1__1_left_grid_pin_3_ ) , - .right_width_0_height_0__pin_4_ ( cby_1__1__1_left_grid_pin_4_ ) , - .right_width_0_height_0__pin_5_ ( cby_1__1__1_left_grid_pin_5_ ) , - .right_width_0_height_0__pin_6_ ( cby_1__1__1_left_grid_pin_6_ ) , - .right_width_0_height_0__pin_7_ ( cby_1__1__1_left_grid_pin_7_ ) , - .right_width_0_height_0__pin_8_ ( cby_1__1__1_left_grid_pin_8_ ) , - .right_width_0_height_0__pin_9_ ( cby_1__1__1_left_grid_pin_9_ ) , - .right_width_0_height_0__pin_10_ ( cby_1__1__1_left_grid_pin_10_ ) , - .right_width_0_height_0__pin_11_ ( cby_1__1__1_left_grid_pin_11_ ) , - .right_width_0_height_0__pin_12_ ( cby_1__1__1_left_grid_pin_12_ ) , - .right_width_0_height_0__pin_13_ ( cby_1__1__1_left_grid_pin_13_ ) , - .right_width_0_height_0__pin_14_ ( cby_1__1__1_left_grid_pin_14_ ) , - .right_width_0_height_0__pin_15_ ( cby_1__1__1_left_grid_pin_15_ ) , - .bottom_width_0_height_0__pin_16_ ( cbx_1__1__0_top_grid_pin_16_ ) , - .bottom_width_0_height_0__pin_17_ ( cbx_1__1__0_top_grid_pin_17_ ) , - .bottom_width_0_height_0__pin_18_ ( cbx_1__1__0_top_grid_pin_18_ ) , - .bottom_width_0_height_0__pin_19_ ( cbx_1__1__0_top_grid_pin_19_ ) , - .bottom_width_0_height_0__pin_20_ ( cbx_1__1__0_top_grid_pin_20_ ) , - .bottom_width_0_height_0__pin_21_ ( cbx_1__1__0_top_grid_pin_21_ ) , - .bottom_width_0_height_0__pin_22_ ( cbx_1__1__0_top_grid_pin_22_ ) , - .bottom_width_0_height_0__pin_23_ ( cbx_1__1__0_top_grid_pin_23_ ) , - .bottom_width_0_height_0__pin_24_ ( cbx_1__1__0_top_grid_pin_24_ ) , - .bottom_width_0_height_0__pin_25_ ( cbx_1__1__0_top_grid_pin_25_ ) , - .bottom_width_0_height_0__pin_26_ ( cbx_1__1__0_top_grid_pin_26_ ) , - .bottom_width_0_height_0__pin_27_ ( cbx_1__1__0_top_grid_pin_27_ ) , - .bottom_width_0_height_0__pin_28_ ( cbx_1__1__0_top_grid_pin_28_ ) , - .bottom_width_0_height_0__pin_29_ ( cbx_1__1__0_top_grid_pin_29_ ) , - .bottom_width_0_height_0__pin_30_ ( cbx_1__1__0_top_grid_pin_30_ ) , - .bottom_width_0_height_0__pin_31_ ( cbx_1__1__0_top_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( cby_0__1__1_right_grid_pin_52_ ) , - .ccff_head ( { ropt_net_27 } ) , - - .right_width_0_height_0__pin_34_upper ( grid_clb_1_right_width_0_height_0__pin_34_upper ) , - .right_width_0_height_0__pin_34_lower ( grid_clb_1_right_width_0_height_0__pin_34_lower ) , - .right_width_0_height_0__pin_35_upper ( grid_clb_1_right_width_0_height_0__pin_35_upper ) , - .right_width_0_height_0__pin_35_lower ( grid_clb_1_right_width_0_height_0__pin_35_lower ) , - .right_width_0_height_0__pin_36_upper ( grid_clb_1_right_width_0_height_0__pin_36_upper ) , - .right_width_0_height_0__pin_36_lower ( grid_clb_1_right_width_0_height_0__pin_36_lower ) , - .right_width_0_height_0__pin_37_upper ( grid_clb_1_right_width_0_height_0__pin_37_upper ) , - .right_width_0_height_0__pin_37_lower ( grid_clb_1_right_width_0_height_0__pin_37_lower ) , - .right_width_0_height_0__pin_38_upper ( grid_clb_1_right_width_0_height_0__pin_38_upper ) , - .right_width_0_height_0__pin_38_lower ( grid_clb_1_right_width_0_height_0__pin_38_lower ) , - .right_width_0_height_0__pin_39_upper ( grid_clb_1_right_width_0_height_0__pin_39_upper ) , - .right_width_0_height_0__pin_39_lower ( grid_clb_1_right_width_0_height_0__pin_39_lower ) , - .right_width_0_height_0__pin_40_upper ( grid_clb_1_right_width_0_height_0__pin_40_upper ) , - .right_width_0_height_0__pin_40_lower ( grid_clb_1_right_width_0_height_0__pin_40_lower ) , - .right_width_0_height_0__pin_41_upper ( grid_clb_1_right_width_0_height_0__pin_41_upper ) , - .right_width_0_height_0__pin_41_lower ( grid_clb_1_right_width_0_height_0__pin_41_lower ) , - .bottom_width_0_height_0__pin_42_upper ( grid_clb_1_bottom_width_0_height_0__pin_42_upper ) , - .bottom_width_0_height_0__pin_42_lower ( grid_clb_1_bottom_width_0_height_0__pin_42_lower ) , - .bottom_width_0_height_0__pin_43_upper ( grid_clb_1_bottom_width_0_height_0__pin_43_upper ) , - .bottom_width_0_height_0__pin_43_lower ( grid_clb_1_bottom_width_0_height_0__pin_43_lower ) , - .bottom_width_0_height_0__pin_44_upper ( grid_clb_1_bottom_width_0_height_0__pin_44_upper ) , - .bottom_width_0_height_0__pin_44_lower ( grid_clb_1_bottom_width_0_height_0__pin_44_lower ) , - .bottom_width_0_height_0__pin_45_upper ( grid_clb_1_bottom_width_0_height_0__pin_45_upper ) , - .bottom_width_0_height_0__pin_45_lower ( grid_clb_1_bottom_width_0_height_0__pin_45_lower ) , - .bottom_width_0_height_0__pin_46_upper ( grid_clb_1_bottom_width_0_height_0__pin_46_upper ) , - .bottom_width_0_height_0__pin_46_lower ( grid_clb_1_bottom_width_0_height_0__pin_46_lower ) , - .bottom_width_0_height_0__pin_47_upper ( grid_clb_1_bottom_width_0_height_0__pin_47_upper ) , - .bottom_width_0_height_0__pin_47_lower ( grid_clb_1_bottom_width_0_height_0__pin_47_lower ) , - .bottom_width_0_height_0__pin_48_upper ( grid_clb_1_bottom_width_0_height_0__pin_48_upper ) , - .bottom_width_0_height_0__pin_48_lower ( grid_clb_1_bottom_width_0_height_0__pin_48_lower ) , - .bottom_width_0_height_0__pin_49_upper ( grid_clb_1_bottom_width_0_height_0__pin_49_upper ) , - .bottom_width_0_height_0__pin_49_lower ( grid_clb_1_bottom_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( grid_clb_1_bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( grid_clb_1_ccff_tail ) ) ; + .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ) , + .ccff_head ( grid_io_left_1_ccff_tail ) , + .top_width_0_height_0__pin_34_upper ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , + .top_width_0_height_0__pin_34_lower ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , + .top_width_0_height_0__pin_35_upper ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , + .top_width_0_height_0__pin_35_lower ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , + .right_width_0_height_0__pin_42_upper ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , + .right_width_0_height_0__pin_42_lower ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , + .right_width_0_height_0__pin_43_upper ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , + .right_width_0_height_0__pin_43_lower ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( { sc_out_wires_0_ } ) , + .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_2_ ) ) ; grid_clb grid_clb_2__1_ ( - .prog_clk ( { ctsbuf_net_1116 } ) , + .prog_clk ( { ctsbuf_net_57 } ) , .Test_en ( Test_en ) , .clk ( clk ) , - .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , - .top_width_0_height_0__pin_33_ ( direct_interc_4_out ) , - .right_width_0_height_0__pin_0_ ( cby_1__1__2_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_ ( cby_1__1__2_left_grid_pin_1_ ) , - .right_width_0_height_0__pin_2_ ( cby_1__1__2_left_grid_pin_2_ ) , - .right_width_0_height_0__pin_3_ ( cby_1__1__2_left_grid_pin_3_ ) , - .right_width_0_height_0__pin_4_ ( cby_1__1__2_left_grid_pin_4_ ) , - .right_width_0_height_0__pin_5_ ( cby_1__1__2_left_grid_pin_5_ ) , - .right_width_0_height_0__pin_6_ ( cby_1__1__2_left_grid_pin_6_ ) , - .right_width_0_height_0__pin_7_ ( cby_1__1__2_left_grid_pin_7_ ) , - .right_width_0_height_0__pin_8_ ( cby_1__1__2_left_grid_pin_8_ ) , - .right_width_0_height_0__pin_9_ ( cby_1__1__2_left_grid_pin_9_ ) , - .right_width_0_height_0__pin_10_ ( cby_1__1__2_left_grid_pin_10_ ) , - .right_width_0_height_0__pin_11_ ( cby_1__1__2_left_grid_pin_11_ ) , - .right_width_0_height_0__pin_12_ ( cby_1__1__2_left_grid_pin_12_ ) , - .right_width_0_height_0__pin_13_ ( cby_1__1__2_left_grid_pin_13_ ) , - .right_width_0_height_0__pin_14_ ( cby_1__1__2_left_grid_pin_14_ ) , - .right_width_0_height_0__pin_15_ ( cby_1__1__2_left_grid_pin_15_ ) , - .bottom_width_0_height_0__pin_16_ ( cbx_1__0__1_top_grid_pin_16_ ) , - .bottom_width_0_height_0__pin_17_ ( cbx_1__0__1_top_grid_pin_17_ ) , - .bottom_width_0_height_0__pin_18_ ( cbx_1__0__1_top_grid_pin_18_ ) , - .bottom_width_0_height_0__pin_19_ ( cbx_1__0__1_top_grid_pin_19_ ) , - .bottom_width_0_height_0__pin_20_ ( cbx_1__0__1_top_grid_pin_20_ ) , - .bottom_width_0_height_0__pin_21_ ( cbx_1__0__1_top_grid_pin_21_ ) , - .bottom_width_0_height_0__pin_22_ ( cbx_1__0__1_top_grid_pin_22_ ) , - .bottom_width_0_height_0__pin_23_ ( cbx_1__0__1_top_grid_pin_23_ ) , - .bottom_width_0_height_0__pin_24_ ( cbx_1__0__1_top_grid_pin_24_ ) , - .bottom_width_0_height_0__pin_25_ ( cbx_1__0__1_top_grid_pin_25_ ) , - .bottom_width_0_height_0__pin_26_ ( cbx_1__0__1_top_grid_pin_26_ ) , - .bottom_width_0_height_0__pin_27_ ( cbx_1__0__1_top_grid_pin_27_ ) , - .bottom_width_0_height_0__pin_28_ ( cbx_1__0__1_top_grid_pin_28_ ) , - .bottom_width_0_height_0__pin_29_ ( cbx_1__0__1_top_grid_pin_29_ ) , - .bottom_width_0_height_0__pin_30_ ( cbx_1__0__1_top_grid_pin_30_ ) , - .bottom_width_0_height_0__pin_31_ ( cbx_1__0__1_top_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( cby_1__1__0_right_grid_pin_52_ ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , + .top_width_0_height_0__pin_33_ ( { sc_in_wires_1_ } ) , + .right_width_0_height_0__pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_2__1__0_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_2__1__0_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_2__1__0_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_2__1__0_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_2__1__0_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_2__1__0_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_2__1__0_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_2__1__0_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_2__1__0_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_2__1__0_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_2__1__0_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_2__1__0_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_2__1__0_left_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ) , .ccff_head ( cby_1__1__0_ccff_tail ) , - .right_width_0_height_0__pin_34_upper ( grid_clb_2_right_width_0_height_0__pin_34_upper ) , - .right_width_0_height_0__pin_34_lower ( grid_clb_2_right_width_0_height_0__pin_34_lower ) , - .right_width_0_height_0__pin_35_upper ( grid_clb_2_right_width_0_height_0__pin_35_upper ) , - .right_width_0_height_0__pin_35_lower ( grid_clb_2_right_width_0_height_0__pin_35_lower ) , - .right_width_0_height_0__pin_36_upper ( grid_clb_2_right_width_0_height_0__pin_36_upper ) , - .right_width_0_height_0__pin_36_lower ( grid_clb_2_right_width_0_height_0__pin_36_lower ) , - .right_width_0_height_0__pin_37_upper ( grid_clb_2_right_width_0_height_0__pin_37_upper ) , - .right_width_0_height_0__pin_37_lower ( grid_clb_2_right_width_0_height_0__pin_37_lower ) , - .right_width_0_height_0__pin_38_upper ( grid_clb_2_right_width_0_height_0__pin_38_upper ) , - .right_width_0_height_0__pin_38_lower ( grid_clb_2_right_width_0_height_0__pin_38_lower ) , - .right_width_0_height_0__pin_39_upper ( grid_clb_2_right_width_0_height_0__pin_39_upper ) , - .right_width_0_height_0__pin_39_lower ( grid_clb_2_right_width_0_height_0__pin_39_lower ) , - .right_width_0_height_0__pin_40_upper ( grid_clb_2_right_width_0_height_0__pin_40_upper ) , - .right_width_0_height_0__pin_40_lower ( grid_clb_2_right_width_0_height_0__pin_40_lower ) , - .right_width_0_height_0__pin_41_upper ( grid_clb_2_right_width_0_height_0__pin_41_upper ) , - .right_width_0_height_0__pin_41_lower ( grid_clb_2_right_width_0_height_0__pin_41_lower ) , - .bottom_width_0_height_0__pin_42_upper ( grid_clb_2_bottom_width_0_height_0__pin_42_upper ) , - .bottom_width_0_height_0__pin_42_lower ( grid_clb_2_bottom_width_0_height_0__pin_42_lower ) , - .bottom_width_0_height_0__pin_43_upper ( grid_clb_2_bottom_width_0_height_0__pin_43_upper ) , - .bottom_width_0_height_0__pin_43_lower ( grid_clb_2_bottom_width_0_height_0__pin_43_lower ) , - .bottom_width_0_height_0__pin_44_upper ( grid_clb_2_bottom_width_0_height_0__pin_44_upper ) , - .bottom_width_0_height_0__pin_44_lower ( grid_clb_2_bottom_width_0_height_0__pin_44_lower ) , - .bottom_width_0_height_0__pin_45_upper ( grid_clb_2_bottom_width_0_height_0__pin_45_upper ) , - .bottom_width_0_height_0__pin_45_lower ( grid_clb_2_bottom_width_0_height_0__pin_45_lower ) , - .bottom_width_0_height_0__pin_46_upper ( grid_clb_2_bottom_width_0_height_0__pin_46_upper ) , - .bottom_width_0_height_0__pin_46_lower ( grid_clb_2_bottom_width_0_height_0__pin_46_lower ) , - .bottom_width_0_height_0__pin_47_upper ( grid_clb_2_bottom_width_0_height_0__pin_47_upper ) , - .bottom_width_0_height_0__pin_47_lower ( grid_clb_2_bottom_width_0_height_0__pin_47_lower ) , - .bottom_width_0_height_0__pin_48_upper ( grid_clb_2_bottom_width_0_height_0__pin_48_upper ) , - .bottom_width_0_height_0__pin_48_lower ( grid_clb_2_bottom_width_0_height_0__pin_48_lower ) , - .bottom_width_0_height_0__pin_49_upper ( grid_clb_2_bottom_width_0_height_0__pin_49_upper ) , - .bottom_width_0_height_0__pin_49_lower ( grid_clb_2_bottom_width_0_height_0__pin_49_lower ) , + .top_width_0_height_0__pin_34_upper ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , + .top_width_0_height_0__pin_34_lower ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , + .top_width_0_height_0__pin_35_upper ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , + .top_width_0_height_0__pin_35_lower ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , + .right_width_0_height_0__pin_42_upper ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , + .right_width_0_height_0__pin_42_lower ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , + .right_width_0_height_0__pin_43_upper ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , + .right_width_0_height_0__pin_43_lower ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , .bottom_width_0_height_0__pin_51_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( grid_clb_2_ccff_tail ) ) ; + .ccff_tail ( grid_clb_2_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_5 ) , .SC_IN_BOT ( scff_Wires_8_ ) , + .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6 ) ) ; grid_clb grid_clb_2__2_ ( - .prog_clk ( { ctsbuf_net_510 } ) , + .prog_clk ( { ctsbuf_net_911 } ) , .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__2__1_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__2__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__2__1_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__2__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__2__1_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__2__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__2__1_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__2__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__2__1_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__2__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , .top_width_0_height_0__pin_33_ ( direct_interc_5_out ) , - .right_width_0_height_0__pin_0_ ( cby_1__1__3_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_ ( cby_1__1__3_left_grid_pin_1_ ) , - .right_width_0_height_0__pin_2_ ( cby_1__1__3_left_grid_pin_2_ ) , - .right_width_0_height_0__pin_3_ ( cby_1__1__3_left_grid_pin_3_ ) , - .right_width_0_height_0__pin_4_ ( cby_1__1__3_left_grid_pin_4_ ) , - .right_width_0_height_0__pin_5_ ( cby_1__1__3_left_grid_pin_5_ ) , - .right_width_0_height_0__pin_6_ ( cby_1__1__3_left_grid_pin_6_ ) , - .right_width_0_height_0__pin_7_ ( cby_1__1__3_left_grid_pin_7_ ) , - .right_width_0_height_0__pin_8_ ( cby_1__1__3_left_grid_pin_8_ ) , - .right_width_0_height_0__pin_9_ ( cby_1__1__3_left_grid_pin_9_ ) , - .right_width_0_height_0__pin_10_ ( cby_1__1__3_left_grid_pin_10_ ) , - .right_width_0_height_0__pin_11_ ( cby_1__1__3_left_grid_pin_11_ ) , - .right_width_0_height_0__pin_12_ ( cby_1__1__3_left_grid_pin_12_ ) , - .right_width_0_height_0__pin_13_ ( cby_1__1__3_left_grid_pin_13_ ) , - .right_width_0_height_0__pin_14_ ( cby_1__1__3_left_grid_pin_14_ ) , - .right_width_0_height_0__pin_15_ ( cby_1__1__3_left_grid_pin_15_ ) , - .bottom_width_0_height_0__pin_16_ ( cbx_1__1__1_top_grid_pin_16_ ) , - .bottom_width_0_height_0__pin_17_ ( cbx_1__1__1_top_grid_pin_17_ ) , - .bottom_width_0_height_0__pin_18_ ( cbx_1__1__1_top_grid_pin_18_ ) , - .bottom_width_0_height_0__pin_19_ ( cbx_1__1__1_top_grid_pin_19_ ) , - .bottom_width_0_height_0__pin_20_ ( cbx_1__1__1_top_grid_pin_20_ ) , - .bottom_width_0_height_0__pin_21_ ( cbx_1__1__1_top_grid_pin_21_ ) , - .bottom_width_0_height_0__pin_22_ ( cbx_1__1__1_top_grid_pin_22_ ) , - .bottom_width_0_height_0__pin_23_ ( cbx_1__1__1_top_grid_pin_23_ ) , - .bottom_width_0_height_0__pin_24_ ( cbx_1__1__1_top_grid_pin_24_ ) , - .bottom_width_0_height_0__pin_25_ ( cbx_1__1__1_top_grid_pin_25_ ) , - .bottom_width_0_height_0__pin_26_ ( cbx_1__1__1_top_grid_pin_26_ ) , - .bottom_width_0_height_0__pin_27_ ( cbx_1__1__1_top_grid_pin_27_ ) , - .bottom_width_0_height_0__pin_28_ ( cbx_1__1__1_top_grid_pin_28_ ) , - .bottom_width_0_height_0__pin_29_ ( cbx_1__1__1_top_grid_pin_29_ ) , - .bottom_width_0_height_0__pin_30_ ( cbx_1__1__1_top_grid_pin_30_ ) , - .bottom_width_0_height_0__pin_31_ ( cbx_1__1__1_top_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( cby_1__1__1_right_grid_pin_52_ ) , + .right_width_0_height_0__pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_2__1__1_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_2__1__1_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_2__1__1_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_2__1__1_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_2__1__1_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_2__1__1_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_2__1__1_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_2__1__1_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_2__1__1_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_2__1__1_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_2__1__1_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_2__1__1_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_2__1__1_left_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ) , .ccff_head ( cby_1__1__1_ccff_tail ) , - .right_width_0_height_0__pin_34_upper ( grid_clb_3_right_width_0_height_0__pin_34_upper ) , - .right_width_0_height_0__pin_34_lower ( grid_clb_3_right_width_0_height_0__pin_34_lower ) , - .right_width_0_height_0__pin_35_upper ( grid_clb_3_right_width_0_height_0__pin_35_upper ) , - .right_width_0_height_0__pin_35_lower ( grid_clb_3_right_width_0_height_0__pin_35_lower ) , - .right_width_0_height_0__pin_36_upper ( grid_clb_3_right_width_0_height_0__pin_36_upper ) , - .right_width_0_height_0__pin_36_lower ( grid_clb_3_right_width_0_height_0__pin_36_lower ) , - .right_width_0_height_0__pin_37_upper ( grid_clb_3_right_width_0_height_0__pin_37_upper ) , - .right_width_0_height_0__pin_37_lower ( grid_clb_3_right_width_0_height_0__pin_37_lower ) , - .right_width_0_height_0__pin_38_upper ( grid_clb_3_right_width_0_height_0__pin_38_upper ) , - .right_width_0_height_0__pin_38_lower ( grid_clb_3_right_width_0_height_0__pin_38_lower ) , - .right_width_0_height_0__pin_39_upper ( grid_clb_3_right_width_0_height_0__pin_39_upper ) , - .right_width_0_height_0__pin_39_lower ( grid_clb_3_right_width_0_height_0__pin_39_lower ) , - .right_width_0_height_0__pin_40_upper ( grid_clb_3_right_width_0_height_0__pin_40_upper ) , - .right_width_0_height_0__pin_40_lower ( grid_clb_3_right_width_0_height_0__pin_40_lower ) , - .right_width_0_height_0__pin_41_upper ( grid_clb_3_right_width_0_height_0__pin_41_upper ) , - .right_width_0_height_0__pin_41_lower ( grid_clb_3_right_width_0_height_0__pin_41_lower ) , - .bottom_width_0_height_0__pin_42_upper ( grid_clb_3_bottom_width_0_height_0__pin_42_upper ) , - .bottom_width_0_height_0__pin_42_lower ( grid_clb_3_bottom_width_0_height_0__pin_42_lower ) , - .bottom_width_0_height_0__pin_43_upper ( grid_clb_3_bottom_width_0_height_0__pin_43_upper ) , - .bottom_width_0_height_0__pin_43_lower ( grid_clb_3_bottom_width_0_height_0__pin_43_lower ) , - .bottom_width_0_height_0__pin_44_upper ( grid_clb_3_bottom_width_0_height_0__pin_44_upper ) , - .bottom_width_0_height_0__pin_44_lower ( grid_clb_3_bottom_width_0_height_0__pin_44_lower ) , - .bottom_width_0_height_0__pin_45_upper ( grid_clb_3_bottom_width_0_height_0__pin_45_upper ) , - .bottom_width_0_height_0__pin_45_lower ( grid_clb_3_bottom_width_0_height_0__pin_45_lower ) , - .bottom_width_0_height_0__pin_46_upper ( grid_clb_3_bottom_width_0_height_0__pin_46_upper ) , - .bottom_width_0_height_0__pin_46_lower ( grid_clb_3_bottom_width_0_height_0__pin_46_lower ) , - .bottom_width_0_height_0__pin_47_upper ( grid_clb_3_bottom_width_0_height_0__pin_47_upper ) , - .bottom_width_0_height_0__pin_47_lower ( grid_clb_3_bottom_width_0_height_0__pin_47_lower ) , - .bottom_width_0_height_0__pin_48_upper ( grid_clb_3_bottom_width_0_height_0__pin_48_upper ) , - .bottom_width_0_height_0__pin_48_lower ( grid_clb_3_bottom_width_0_height_0__pin_48_lower ) , - .bottom_width_0_height_0__pin_49_upper ( grid_clb_3_bottom_width_0_height_0__pin_49_upper ) , - .bottom_width_0_height_0__pin_49_lower ( grid_clb_3_bottom_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( grid_clb_3_bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( grid_clb_3_ccff_tail ) ) ; -grid_io_top grid_io_top_1__3_ ( - .prog_clk ( { ctsbuf_net_914 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[0] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[0] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[0] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[0] ) , - .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , - .ccff_head ( cbx_1__2__0_ccff_tail ) , - .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , - .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_top_0_ccff_tail ) ) ; -grid_io_top grid_io_top_2__3_ ( - .prog_clk ( { ctsbuf_net_38 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[1] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[1] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[1] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[1] ) , - .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , - .ccff_head ( cbx_1__2__1_ccff_tail ) , - .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , - .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_top_1_ccff_tail ) ) ; -grid_io_right grid_io_right_3__1_ ( - .prog_clk ( { ctsbuf_net_49 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[2] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[2] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[2] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[2] ) , - .left_width_0_height_0__pin_0_ ( cby_1__1__2_right_grid_pin_52_ ) , - .ccff_head ( cby_1__1__2_ccff_tail ) , - .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_right_0_ccff_tail ) ) ; -grid_io_right grid_io_right_3__2_ ( - .prog_clk ( { ctsbuf_net_16 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[3] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[3] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[3] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[3] ) , - .left_width_0_height_0__pin_0_ ( cby_1__1__3_right_grid_pin_52_ ) , - .ccff_head ( cby_1__1__3_ccff_tail ) , - .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_right_1_ccff_tail ) ) ; -grid_io_bottom grid_io_bottom_1__0_ ( - .prog_clk ( { ctsbuf_net_611 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[4] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[4] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[4] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[4] ) , - .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , - .ccff_head ( cbx_1__0__0_ccff_tail ) , - .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , - .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_bottom_0_ccff_tail ) ) ; -grid_io_bottom grid_io_bottom_2__0_ ( - .prog_clk ( { ctsbuf_net_27 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[5] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[5] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[5] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[5] ) , - .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , - .ccff_head ( cbx_1__0__1_ccff_tail ) , - .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , - .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_bottom_1_ccff_tail ) ) ; -grid_io_left grid_io_left_0__1_ ( - .prog_clk ( { ctsbuf_net_1520 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[6] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[6] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[6] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[6] ) , - .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , - .ccff_head ( cby_0__1__0_ccff_tail ) , - .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_left_0_ccff_tail ) ) ; -grid_io_left grid_io_left_0__2_ ( - .prog_clk ( { ctsbuf_net_1419 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[7] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[7] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[7] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[7] ) , - .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , - .ccff_head ( cby_0__1__1_ccff_tail ) , - .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_left_1_ccff_tail ) ) ; + .top_width_0_height_0__pin_34_upper ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , + .top_width_0_height_0__pin_34_lower ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , + .top_width_0_height_0__pin_35_upper ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , + .top_width_0_height_0__pin_35_lower ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , + .right_width_0_height_0__pin_42_upper ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , + .right_width_0_height_0__pin_42_lower ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , + .right_width_0_height_0__pin_43_upper ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , + .right_width_0_height_0__pin_43_lower ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( { sc_out_wires_1_ } ) , + .ccff_tail ( grid_clb_3_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7 ) , .SC_IN_BOT ( scff_Wires_10_ ) , + .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8 ) ) ; sb_0__0_ sb_0__0_ ( - .prog_clk ( { ctsbuf_net_1520 } ) , + .prog_clk ( { ctsbuf_net_1315 } ) , .chany_top_in ( cby_0__1__0_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , - .right_top_grid_pin_42_ ( grid_clb_0_bottom_width_0_height_0__pin_42_upper ) , - .right_top_grid_pin_43_ ( grid_clb_0_bottom_width_0_height_0__pin_43_upper ) , - .right_top_grid_pin_44_ ( grid_clb_0_bottom_width_0_height_0__pin_44_upper ) , - .right_top_grid_pin_45_ ( grid_clb_0_bottom_width_0_height_0__pin_45_upper ) , - .right_top_grid_pin_46_ ( grid_clb_0_bottom_width_0_height_0__pin_46_upper ) , - .right_top_grid_pin_47_ ( grid_clb_0_bottom_width_0_height_0__pin_47_upper ) , - .right_top_grid_pin_48_ ( grid_clb_0_bottom_width_0_height_0__pin_48_upper ) , - .right_top_grid_pin_49_ ( grid_clb_0_bottom_width_0_height_0__pin_49_upper ) , .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , .ccff_head ( grid_io_bottom_0_ccff_tail ) , .chany_top_out ( sb_0__0__0_chany_top_out ) , .chanx_right_out ( sb_0__0__0_chanx_right_out ) , .ccff_tail ( ccff_tail ) ) ; sb_0__1_ sb_0__1_ ( - .prog_clk ( { p_abuf0 } ) , + .prog_clk ( { ctsbuf_net_1315 } ) , .chany_top_in ( cby_0__1__1_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , - .right_top_grid_pin_42_ ( grid_clb_1_bottom_width_0_height_0__pin_42_upper ) , - .right_top_grid_pin_43_ ( grid_clb_1_bottom_width_0_height_0__pin_43_upper ) , - .right_top_grid_pin_44_ ( grid_clb_1_bottom_width_0_height_0__pin_44_upper ) , - .right_top_grid_pin_45_ ( grid_clb_1_bottom_width_0_height_0__pin_45_upper ) , - .right_top_grid_pin_46_ ( grid_clb_1_bottom_width_0_height_0__pin_46_upper ) , - .right_top_grid_pin_47_ ( grid_clb_1_bottom_width_0_height_0__pin_47_upper ) , - .right_top_grid_pin_48_ ( grid_clb_1_bottom_width_0_height_0__pin_48_upper ) , - .right_top_grid_pin_49_ ( grid_clb_1_bottom_width_0_height_0__pin_49_upper ) , + .right_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , + .right_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , .chany_bottom_in ( cby_0__1__0_chany_top_out ) , .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , .ccff_head ( cbx_1__1__0_ccff_tail ) , @@ -31415,89 +35483,95 @@ sb_0__1_ sb_0__1_ ( .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , .ccff_tail ( sb_0__1__0_ccff_tail ) ) ; sb_0__2_ sb_0__2_ ( - .prog_clk ( { ctsbuf_net_1419 } ) , + .prog_clk ( { ctsbuf_net_1012 } ) , .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , + .right_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , .chany_bottom_in ( cby_0__1__1_chany_top_out ) , .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , .ccff_head ( grid_io_top_0_ccff_tail ) , .chanx_right_out ( sb_0__2__0_chanx_right_out ) , .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , - .ccff_tail ( sb_0__2__0_ccff_tail ) ) ; + .ccff_tail ( sb_0__2__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_9 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_10 ) , .SC_OUT_BOT ( scff_Wires_0_ ) ) ; sb_1__0_ sb_1__0_ ( - .prog_clk ( { ctsbuf_net_813 } ) , + .prog_clk ( { ctsbuf_net_79 } ) , .chany_top_in ( cby_1__1__0_chany_bottom_out ) , - .top_left_grid_pin_34_ ( grid_clb_0_right_width_0_height_0__pin_34_lower ) , - .top_left_grid_pin_35_ ( grid_clb_0_right_width_0_height_0__pin_35_lower ) , - .top_left_grid_pin_36_ ( grid_clb_0_right_width_0_height_0__pin_36_lower ) , - .top_left_grid_pin_37_ ( grid_clb_0_right_width_0_height_0__pin_37_lower ) , - .top_left_grid_pin_38_ ( grid_clb_0_right_width_0_height_0__pin_38_lower ) , - .top_left_grid_pin_39_ ( grid_clb_0_right_width_0_height_0__pin_39_lower ) , - .top_left_grid_pin_40_ ( grid_clb_0_right_width_0_height_0__pin_40_lower ) , - .top_left_grid_pin_41_ ( grid_clb_0_right_width_0_height_0__pin_41_lower ) , + .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , + .top_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , + .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , - .right_top_grid_pin_42_ ( grid_clb_2_bottom_width_0_height_0__pin_42_upper ) , - .right_top_grid_pin_43_ ( grid_clb_2_bottom_width_0_height_0__pin_43_upper ) , - .right_top_grid_pin_44_ ( grid_clb_2_bottom_width_0_height_0__pin_44_upper ) , - .right_top_grid_pin_45_ ( grid_clb_2_bottom_width_0_height_0__pin_45_upper ) , - .right_top_grid_pin_46_ ( grid_clb_2_bottom_width_0_height_0__pin_46_upper ) , - .right_top_grid_pin_47_ ( grid_clb_2_bottom_width_0_height_0__pin_47_upper ) , - .right_top_grid_pin_48_ ( grid_clb_2_bottom_width_0_height_0__pin_48_upper ) , - .right_top_grid_pin_49_ ( grid_clb_2_bottom_width_0_height_0__pin_49_upper ) , .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , - .left_top_grid_pin_42_ ( grid_clb_0_bottom_width_0_height_0__pin_42_lower ) , - .left_top_grid_pin_43_ ( grid_clb_0_bottom_width_0_height_0__pin_43_lower ) , - .left_top_grid_pin_44_ ( grid_clb_0_bottom_width_0_height_0__pin_44_lower ) , - .left_top_grid_pin_45_ ( grid_clb_0_bottom_width_0_height_0__pin_45_lower ) , - .left_top_grid_pin_46_ ( grid_clb_0_bottom_width_0_height_0__pin_46_lower ) , - .left_top_grid_pin_47_ ( grid_clb_0_bottom_width_0_height_0__pin_47_lower ) , - .left_top_grid_pin_48_ ( grid_clb_0_bottom_width_0_height_0__pin_48_lower ) , - .left_top_grid_pin_49_ ( grid_clb_0_bottom_width_0_height_0__pin_49_lower ) , .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , .ccff_head ( grid_io_bottom_1_ccff_tail ) , .chany_top_out ( sb_1__0__0_chany_top_out ) , .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , - .ccff_tail ( sb_1__0__0_ccff_tail ) ) ; + .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_11 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_12 ) , .SC_OUT_BOT ( scff_Wires_7_ ) ) ; sb_1__1_ sb_1__1_ ( - .prog_clk ( { ctsbuf_net_1217 } ) , + .prog_clk ( { ctsbuf_net_1214 } ) , .chany_top_in ( cby_1__1__1_chany_bottom_out ) , - .top_left_grid_pin_34_ ( grid_clb_1_right_width_0_height_0__pin_34_lower ) , - .top_left_grid_pin_35_ ( grid_clb_1_right_width_0_height_0__pin_35_lower ) , - .top_left_grid_pin_36_ ( grid_clb_1_right_width_0_height_0__pin_36_lower ) , - .top_left_grid_pin_37_ ( grid_clb_1_right_width_0_height_0__pin_37_lower ) , - .top_left_grid_pin_38_ ( grid_clb_1_right_width_0_height_0__pin_38_lower ) , - .top_left_grid_pin_39_ ( grid_clb_1_right_width_0_height_0__pin_39_lower ) , - .top_left_grid_pin_40_ ( grid_clb_1_right_width_0_height_0__pin_40_lower ) , - .top_left_grid_pin_41_ ( grid_clb_1_right_width_0_height_0__pin_41_lower ) , + .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , + .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , + .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , - .right_top_grid_pin_42_ ( grid_clb_3_bottom_width_0_height_0__pin_42_upper ) , - .right_top_grid_pin_43_ ( grid_clb_3_bottom_width_0_height_0__pin_43_upper ) , - .right_top_grid_pin_44_ ( grid_clb_3_bottom_width_0_height_0__pin_44_upper ) , - .right_top_grid_pin_45_ ( grid_clb_3_bottom_width_0_height_0__pin_45_upper ) , - .right_top_grid_pin_46_ ( grid_clb_3_bottom_width_0_height_0__pin_46_upper ) , - .right_top_grid_pin_47_ ( grid_clb_3_bottom_width_0_height_0__pin_47_upper ) , - .right_top_grid_pin_48_ ( grid_clb_3_bottom_width_0_height_0__pin_48_upper ) , - .right_top_grid_pin_49_ ( grid_clb_3_bottom_width_0_height_0__pin_49_upper ) , + .right_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , + .right_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , .chany_bottom_in ( cby_1__1__0_chany_top_out ) , - .bottom_left_grid_pin_34_ ( grid_clb_0_right_width_0_height_0__pin_34_upper ) , - .bottom_left_grid_pin_35_ ( grid_clb_0_right_width_0_height_0__pin_35_upper ) , - .bottom_left_grid_pin_36_ ( grid_clb_0_right_width_0_height_0__pin_36_upper ) , - .bottom_left_grid_pin_37_ ( grid_clb_0_right_width_0_height_0__pin_37_upper ) , - .bottom_left_grid_pin_38_ ( grid_clb_0_right_width_0_height_0__pin_38_upper ) , - .bottom_left_grid_pin_39_ ( grid_clb_0_right_width_0_height_0__pin_39_upper ) , - .bottom_left_grid_pin_40_ ( grid_clb_0_right_width_0_height_0__pin_40_upper ) , - .bottom_left_grid_pin_41_ ( grid_clb_0_right_width_0_height_0__pin_41_upper ) , + .bottom_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , + .bottom_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , - .left_top_grid_pin_42_ ( grid_clb_1_bottom_width_0_height_0__pin_42_lower ) , - .left_top_grid_pin_43_ ( grid_clb_1_bottom_width_0_height_0__pin_43_lower ) , - .left_top_grid_pin_44_ ( grid_clb_1_bottom_width_0_height_0__pin_44_lower ) , - .left_top_grid_pin_45_ ( grid_clb_1_bottom_width_0_height_0__pin_45_lower ) , - .left_top_grid_pin_46_ ( grid_clb_1_bottom_width_0_height_0__pin_46_lower ) , - .left_top_grid_pin_47_ ( grid_clb_1_bottom_width_0_height_0__pin_47_lower ) , - .left_top_grid_pin_48_ ( grid_clb_1_bottom_width_0_height_0__pin_48_lower ) , - .left_top_grid_pin_49_ ( grid_clb_1_bottom_width_0_height_0__pin_49_lower ) , + .left_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , + .left_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , .ccff_head ( cbx_1__1__1_ccff_tail ) , .chany_top_out ( sb_1__1__0_chany_top_out ) , .chanx_right_out ( sb_1__1__0_chanx_right_out ) , @@ -31505,411 +35579,518 @@ sb_1__1_ sb_1__1_ ( .chanx_left_out ( sb_1__1__0_chanx_left_out ) , .ccff_tail ( sb_1__1__0_ccff_tail ) ) ; sb_1__2_ sb_1__2_ ( - .prog_clk ( { ctsbuf_net_712 } ) , + .prog_clk ( { ctsbuf_net_810 } ) , .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , + .right_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , .chany_bottom_in ( cby_1__1__1_chany_top_out ) , - .bottom_left_grid_pin_34_ ( grid_clb_1_right_width_0_height_0__pin_34_upper ) , - .bottom_left_grid_pin_35_ ( grid_clb_1_right_width_0_height_0__pin_35_upper ) , - .bottom_left_grid_pin_36_ ( grid_clb_1_right_width_0_height_0__pin_36_upper ) , - .bottom_left_grid_pin_37_ ( grid_clb_1_right_width_0_height_0__pin_37_upper ) , - .bottom_left_grid_pin_38_ ( grid_clb_1_right_width_0_height_0__pin_38_upper ) , - .bottom_left_grid_pin_39_ ( grid_clb_1_right_width_0_height_0__pin_39_upper ) , - .bottom_left_grid_pin_40_ ( grid_clb_1_right_width_0_height_0__pin_40_upper ) , - .bottom_left_grid_pin_41_ ( grid_clb_1_right_width_0_height_0__pin_41_upper ) , + .bottom_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , + .bottom_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , .chanx_left_in ( cbx_1__2__0_chanx_right_out ) , - .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .ccff_head ( { ropt_net_29 } ) , + .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , + .left_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , + .ccff_head ( grid_io_top_1_ccff_tail ) , .chanx_right_out ( sb_1__2__0_chanx_right_out ) , .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , .chanx_left_out ( sb_1__2__0_chanx_left_out ) , - .ccff_tail ( sb_1__2__0_ccff_tail ) ) ; + .ccff_tail ( sb_1__2__0_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_13 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_14 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_15 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_16 ) ) ; sb_2__0_ sb_2__0_ ( - .prog_clk ( { ctsbuf_net_27 } ) , - .chany_top_in ( cby_1__1__2_chany_bottom_out ) , - .top_left_grid_pin_34_ ( grid_clb_2_right_width_0_height_0__pin_34_lower ) , - .top_left_grid_pin_35_ ( grid_clb_2_right_width_0_height_0__pin_35_lower ) , - .top_left_grid_pin_36_ ( grid_clb_2_right_width_0_height_0__pin_36_lower ) , - .top_left_grid_pin_37_ ( grid_clb_2_right_width_0_height_0__pin_37_lower ) , - .top_left_grid_pin_38_ ( grid_clb_2_right_width_0_height_0__pin_38_lower ) , - .top_left_grid_pin_39_ ( grid_clb_2_right_width_0_height_0__pin_39_lower ) , - .top_left_grid_pin_40_ ( grid_clb_2_right_width_0_height_0__pin_40_lower ) , - .top_left_grid_pin_41_ ( grid_clb_2_right_width_0_height_0__pin_41_lower ) , + .prog_clk ( { ctsbuf_net_13 } ) , + .chany_top_in ( cby_2__1__0_chany_bottom_out ) , + .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , + .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , + .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , - .left_top_grid_pin_42_ ( grid_clb_2_bottom_width_0_height_0__pin_42_lower ) , - .left_top_grid_pin_43_ ( grid_clb_2_bottom_width_0_height_0__pin_43_lower ) , - .left_top_grid_pin_44_ ( grid_clb_2_bottom_width_0_height_0__pin_44_lower ) , - .left_top_grid_pin_45_ ( grid_clb_2_bottom_width_0_height_0__pin_45_lower ) , - .left_top_grid_pin_46_ ( grid_clb_2_bottom_width_0_height_0__pin_46_lower ) , - .left_top_grid_pin_47_ ( grid_clb_2_bottom_width_0_height_0__pin_47_lower ) , - .left_top_grid_pin_48_ ( grid_clb_2_bottom_width_0_height_0__pin_48_lower ) , - .left_top_grid_pin_49_ ( grid_clb_2_bottom_width_0_height_0__pin_49_lower ) , .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , .ccff_head ( grid_io_right_0_ccff_tail ) , .chany_top_out ( sb_2__0__0_chany_top_out ) , .chanx_left_out ( sb_2__0__0_chanx_left_out ) , .ccff_tail ( sb_2__0__0_ccff_tail ) ) ; sb_2__1_ sb_2__1_ ( - .prog_clk ( { ctsbuf_net_49 } ) , - .chany_top_in ( cby_1__1__3_chany_bottom_out ) , - .top_left_grid_pin_34_ ( grid_clb_3_right_width_0_height_0__pin_34_lower ) , - .top_left_grid_pin_35_ ( grid_clb_3_right_width_0_height_0__pin_35_lower ) , - .top_left_grid_pin_36_ ( grid_clb_3_right_width_0_height_0__pin_36_lower ) , - .top_left_grid_pin_37_ ( grid_clb_3_right_width_0_height_0__pin_37_lower ) , - .top_left_grid_pin_38_ ( grid_clb_3_right_width_0_height_0__pin_38_lower ) , - .top_left_grid_pin_39_ ( grid_clb_3_right_width_0_height_0__pin_39_lower ) , - .top_left_grid_pin_40_ ( grid_clb_3_right_width_0_height_0__pin_40_lower ) , - .top_left_grid_pin_41_ ( grid_clb_3_right_width_0_height_0__pin_41_lower ) , + .prog_clk ( { ctsbuf_net_68 } ) , + .chany_top_in ( cby_2__1__1_chany_bottom_out ) , + .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , + .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , + .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .chany_bottom_in ( cby_1__1__2_chany_top_out ) , + .chany_bottom_in ( cby_2__1__0_chany_top_out ) , .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .bottom_left_grid_pin_34_ ( grid_clb_2_right_width_0_height_0__pin_34_upper ) , - .bottom_left_grid_pin_35_ ( grid_clb_2_right_width_0_height_0__pin_35_upper ) , - .bottom_left_grid_pin_36_ ( grid_clb_2_right_width_0_height_0__pin_36_upper ) , - .bottom_left_grid_pin_37_ ( grid_clb_2_right_width_0_height_0__pin_37_upper ) , - .bottom_left_grid_pin_38_ ( grid_clb_2_right_width_0_height_0__pin_38_upper ) , - .bottom_left_grid_pin_39_ ( grid_clb_2_right_width_0_height_0__pin_39_upper ) , - .bottom_left_grid_pin_40_ ( grid_clb_2_right_width_0_height_0__pin_40_upper ) , - .bottom_left_grid_pin_41_ ( grid_clb_2_right_width_0_height_0__pin_41_upper ) , + .bottom_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , + .bottom_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , - .left_top_grid_pin_42_ ( grid_clb_3_bottom_width_0_height_0__pin_42_lower ) , - .left_top_grid_pin_43_ ( grid_clb_3_bottom_width_0_height_0__pin_43_lower ) , - .left_top_grid_pin_44_ ( grid_clb_3_bottom_width_0_height_0__pin_44_lower ) , - .left_top_grid_pin_45_ ( grid_clb_3_bottom_width_0_height_0__pin_45_lower ) , - .left_top_grid_pin_46_ ( grid_clb_3_bottom_width_0_height_0__pin_46_lower ) , - .left_top_grid_pin_47_ ( grid_clb_3_bottom_width_0_height_0__pin_47_lower ) , - .left_top_grid_pin_48_ ( grid_clb_3_bottom_width_0_height_0__pin_48_lower ) , - .left_top_grid_pin_49_ ( grid_clb_3_bottom_width_0_height_0__pin_49_lower ) , + .left_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , + .left_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , .ccff_head ( grid_io_right_1_ccff_tail ) , .chany_top_out ( sb_2__1__0_chany_top_out ) , .chany_bottom_out ( sb_2__1__0_chany_bottom_out ) , .chanx_left_out ( sb_2__1__0_chanx_left_out ) , .ccff_tail ( sb_2__1__0_ccff_tail ) ) ; sb_2__2_ sb_2__2_ ( - .prog_clk ( { ctsbuf_net_16 } ) , - .chany_bottom_in ( cby_1__1__3_chany_top_out ) , + .prog_clk ( { ctsbuf_net_24 } ) , + .chany_bottom_in ( cby_2__1__1_chany_top_out ) , .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .bottom_left_grid_pin_34_ ( grid_clb_3_right_width_0_height_0__pin_34_upper ) , - .bottom_left_grid_pin_35_ ( grid_clb_3_right_width_0_height_0__pin_35_upper ) , - .bottom_left_grid_pin_36_ ( grid_clb_3_right_width_0_height_0__pin_36_upper ) , - .bottom_left_grid_pin_37_ ( grid_clb_3_right_width_0_height_0__pin_37_upper ) , - .bottom_left_grid_pin_38_ ( grid_clb_3_right_width_0_height_0__pin_38_upper ) , - .bottom_left_grid_pin_39_ ( grid_clb_3_right_width_0_height_0__pin_39_upper ) , - .bottom_left_grid_pin_40_ ( grid_clb_3_right_width_0_height_0__pin_40_upper ) , - .bottom_left_grid_pin_41_ ( grid_clb_3_right_width_0_height_0__pin_41_upper ) , + .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , + .bottom_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , .chanx_left_in ( cbx_1__2__1_chanx_right_out ) , .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , + .left_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , .ccff_head ( ccff_head ) , .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , .chanx_left_out ( sb_2__2__0_chanx_left_out ) , - .ccff_tail ( sb_2__2__0_ccff_tail ) ) ; + .ccff_tail ( sb_2__2__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_17 ) , .SC_OUT_TOP ( sc_tail ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_18 ) ) ; cbx_1__0_ cbx_1__0_ ( - .prog_clk ( { ctsbuf_net_611 } ) , + .prog_clk ( { ctsbuf_net_79 } ) , .chanx_left_in ( sb_0__0__0_chanx_right_out ) , .chanx_right_in ( sb_1__0__0_chanx_left_out ) , .ccff_head ( sb_1__0__0_ccff_tail ) , .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , - .top_grid_pin_16_ ( cbx_1__0__0_top_grid_pin_16_ ) , - .top_grid_pin_17_ ( cbx_1__0__0_top_grid_pin_17_ ) , - .top_grid_pin_18_ ( cbx_1__0__0_top_grid_pin_18_ ) , - .top_grid_pin_19_ ( cbx_1__0__0_top_grid_pin_19_ ) , - .top_grid_pin_20_ ( cbx_1__0__0_top_grid_pin_20_ ) , - .top_grid_pin_21_ ( cbx_1__0__0_top_grid_pin_21_ ) , - .top_grid_pin_22_ ( cbx_1__0__0_top_grid_pin_22_ ) , - .top_grid_pin_23_ ( cbx_1__0__0_top_grid_pin_23_ ) , - .top_grid_pin_24_ ( cbx_1__0__0_top_grid_pin_24_ ) , - .top_grid_pin_25_ ( cbx_1__0__0_top_grid_pin_25_ ) , - .top_grid_pin_26_ ( cbx_1__0__0_top_grid_pin_26_ ) , - .top_grid_pin_27_ ( cbx_1__0__0_top_grid_pin_27_ ) , - .top_grid_pin_28_ ( cbx_1__0__0_top_grid_pin_28_ ) , - .top_grid_pin_29_ ( cbx_1__0__0_top_grid_pin_29_ ) , - .top_grid_pin_30_ ( cbx_1__0__0_top_grid_pin_30_ ) , - .top_grid_pin_31_ ( cbx_1__0__0_top_grid_pin_31_ ) , .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , - .ccff_tail ( cbx_1__0__0_ccff_tail ) ) ; + .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , + .ccff_tail ( grid_io_bottom_0_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4:9] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4:9] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4:9] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , + .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_19 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_20 ) , .SC_OUT_BOT ( scff_Wires_6_ ) ) ; cbx_1__0_ cbx_2__0_ ( - .prog_clk ( { ctsbuf_net_27 } ) , + .prog_clk ( { ctsbuf_net_35 } ) , .chanx_left_in ( sb_1__0__0_chanx_right_out ) , .chanx_right_in ( sb_2__0__0_chanx_left_out ) , .ccff_head ( sb_2__0__0_ccff_tail ) , .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , - .top_grid_pin_16_ ( cbx_1__0__1_top_grid_pin_16_ ) , - .top_grid_pin_17_ ( cbx_1__0__1_top_grid_pin_17_ ) , - .top_grid_pin_18_ ( cbx_1__0__1_top_grid_pin_18_ ) , - .top_grid_pin_19_ ( cbx_1__0__1_top_grid_pin_19_ ) , - .top_grid_pin_20_ ( cbx_1__0__1_top_grid_pin_20_ ) , - .top_grid_pin_21_ ( cbx_1__0__1_top_grid_pin_21_ ) , - .top_grid_pin_22_ ( cbx_1__0__1_top_grid_pin_22_ ) , - .top_grid_pin_23_ ( cbx_1__0__1_top_grid_pin_23_ ) , - .top_grid_pin_24_ ( cbx_1__0__1_top_grid_pin_24_ ) , - .top_grid_pin_25_ ( cbx_1__0__1_top_grid_pin_25_ ) , - .top_grid_pin_26_ ( cbx_1__0__1_top_grid_pin_26_ ) , - .top_grid_pin_27_ ( cbx_1__0__1_top_grid_pin_27_ ) , - .top_grid_pin_28_ ( cbx_1__0__1_top_grid_pin_28_ ) , - .top_grid_pin_29_ ( cbx_1__0__1_top_grid_pin_29_ ) , - .top_grid_pin_30_ ( cbx_1__0__1_top_grid_pin_30_ ) , - .top_grid_pin_31_ ( cbx_1__0__1_top_grid_pin_31_ ) , .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , - .ccff_tail ( cbx_1__0__1_ccff_tail ) ) ; + .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , + .ccff_tail ( grid_io_bottom_1_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[10:15] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[10:15] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[10:15] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , + .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_21 ) , + .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_22 ) ) ; cbx_1__1_ cbx_1__1_ ( - .prog_clk ( { ctsbuf_net_1621 } ) , + .prog_clk ( { ctsbuf_net_1416 } ) , .chanx_left_in ( sb_0__1__0_chanx_right_out ) , .chanx_right_in ( sb_1__1__0_chanx_left_out ) , .ccff_head ( sb_1__1__0_ccff_tail ) , .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , - .top_grid_pin_16_ ( cbx_1__1__0_top_grid_pin_16_ ) , - .top_grid_pin_17_ ( cbx_1__1__0_top_grid_pin_17_ ) , - .top_grid_pin_18_ ( cbx_1__1__0_top_grid_pin_18_ ) , - .top_grid_pin_19_ ( cbx_1__1__0_top_grid_pin_19_ ) , - .top_grid_pin_20_ ( cbx_1__1__0_top_grid_pin_20_ ) , - .top_grid_pin_21_ ( cbx_1__1__0_top_grid_pin_21_ ) , - .top_grid_pin_22_ ( cbx_1__1__0_top_grid_pin_22_ ) , - .top_grid_pin_23_ ( cbx_1__1__0_top_grid_pin_23_ ) , - .top_grid_pin_24_ ( cbx_1__1__0_top_grid_pin_24_ ) , - .top_grid_pin_25_ ( cbx_1__1__0_top_grid_pin_25_ ) , - .top_grid_pin_26_ ( cbx_1__1__0_top_grid_pin_26_ ) , - .top_grid_pin_27_ ( cbx_1__1__0_top_grid_pin_27_ ) , - .top_grid_pin_28_ ( cbx_1__1__0_top_grid_pin_28_ ) , - .top_grid_pin_29_ ( cbx_1__1__0_top_grid_pin_29_ ) , - .top_grid_pin_30_ ( cbx_1__1__0_top_grid_pin_30_ ) , - .top_grid_pin_31_ ( cbx_1__1__0_top_grid_pin_31_ ) , - .ccff_tail ( cbx_1__1__0_ccff_tail ) ) ; + .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__0_ccff_tail ) , .CLB_SC_IN ( sc_out_wires_0_ ) , + .CLB_SC_OUT ( sc_in_wires_0_ ) , .SC_IN_TOP ( scff_Wires_2_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_23 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_24 ) , .SC_OUT_BOT ( scff_Wires_3_ ) ) ; cbx_1__1_ cbx_2__1_ ( - .prog_clk ( { ctsbuf_net_1015 } ) , + .prog_clk ( { ctsbuf_net_68 } ) , .chanx_left_in ( sb_1__1__0_chanx_right_out ) , .chanx_right_in ( sb_2__1__0_chanx_left_out ) , .ccff_head ( sb_2__1__0_ccff_tail ) , .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , - .top_grid_pin_16_ ( cbx_1__1__1_top_grid_pin_16_ ) , - .top_grid_pin_17_ ( cbx_1__1__1_top_grid_pin_17_ ) , - .top_grid_pin_18_ ( cbx_1__1__1_top_grid_pin_18_ ) , - .top_grid_pin_19_ ( cbx_1__1__1_top_grid_pin_19_ ) , - .top_grid_pin_20_ ( cbx_1__1__1_top_grid_pin_20_ ) , - .top_grid_pin_21_ ( cbx_1__1__1_top_grid_pin_21_ ) , - .top_grid_pin_22_ ( cbx_1__1__1_top_grid_pin_22_ ) , - .top_grid_pin_23_ ( cbx_1__1__1_top_grid_pin_23_ ) , - .top_grid_pin_24_ ( cbx_1__1__1_top_grid_pin_24_ ) , - .top_grid_pin_25_ ( cbx_1__1__1_top_grid_pin_25_ ) , - .top_grid_pin_26_ ( cbx_1__1__1_top_grid_pin_26_ ) , - .top_grid_pin_27_ ( cbx_1__1__1_top_grid_pin_27_ ) , - .top_grid_pin_28_ ( cbx_1__1__1_top_grid_pin_28_ ) , - .top_grid_pin_29_ ( cbx_1__1__1_top_grid_pin_29_ ) , - .top_grid_pin_30_ ( cbx_1__1__1_top_grid_pin_30_ ) , - .top_grid_pin_31_ ( cbx_1__1__1_top_grid_pin_31_ ) , - .ccff_tail ( cbx_1__1__1_ccff_tail ) ) ; + .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__1_ccff_tail ) , .CLB_SC_IN ( sc_out_wires_1_ ) , + .CLB_SC_OUT ( sc_in_wires_1_ ) , .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_25 ) , + .SC_IN_BOT ( scff_Wires_9_ ) , .SC_OUT_TOP ( scff_Wires_10_ ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_26 ) ) ; cbx_1__2_ cbx_1__2_ ( - .prog_clk ( { ctsbuf_net_914 } ) , + .prog_clk ( { ctsbuf_net_1012 } ) , .chanx_left_in ( sb_0__2__0_chanx_right_out ) , .chanx_right_in ( sb_1__2__0_chanx_left_out ) , .ccff_head ( sb_1__2__0_ccff_tail ) , .chanx_left_out ( cbx_1__2__0_chanx_left_out ) , .chanx_right_out ( cbx_1__2__0_chanx_right_out ) , .top_grid_pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , - .ccff_tail ( cbx_1__2__0_ccff_tail ) ) ; + .bottom_grid_pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__2__0_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__2__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__2__0_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__2__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__2__0_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__2__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__2__0_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__2__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__2__0_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__2__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_0_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_27 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_28 ) , .SC_OUT_BOT ( scff_Wires_1_ ) ) ; cbx_1__2_ cbx_2__2_ ( - .prog_clk ( { ctsbuf_net_16 } ) , + .prog_clk ( { ctsbuf_net_24 } ) , .chanx_left_in ( sb_1__2__0_chanx_right_out ) , .chanx_right_in ( sb_2__2__0_chanx_left_out ) , .ccff_head ( sb_2__2__0_ccff_tail ) , .chanx_left_out ( cbx_1__2__1_chanx_left_out ) , .chanx_right_out ( cbx_1__2__1_chanx_right_out ) , .top_grid_pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , - .ccff_tail ( cbx_1__2__1_ccff_tail ) ) ; + .bottom_grid_pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__2__1_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__2__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__2__1_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__2__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__2__1_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__2__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__2__1_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__2__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__2__1_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__2__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_1_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_29 ) , .SC_IN_BOT ( scff_Wires_11_ ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_30 ) , .SC_OUT_BOT ( scff_Wires_12_ ) ) ; cby_0__1_ cby_0__1_ ( - .prog_clk ( { ctsbuf_net_1520 } ) , + .prog_clk ( { ctsbuf_net_1315 } ) , .chany_bottom_in ( sb_0__0__0_chany_top_out ) , .chany_top_in ( sb_0__1__0_chany_bottom_out ) , .ccff_head ( sb_0__1__0_ccff_tail ) , .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , .chany_top_out ( cby_0__1__0_chany_top_out ) , - .right_grid_pin_52_ ( cby_0__1__0_right_grid_pin_52_ ) , .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , - .ccff_tail ( cby_0__1__0_ccff_tail ) ) ; + .ccff_tail ( grid_io_left_0_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[16] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[16] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[16] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ) ; cby_0__1_ cby_0__2_ ( - .prog_clk ( { ctsbuf_net_1419 } ) , + .prog_clk ( { ctsbuf_net_1315 } ) , .chany_bottom_in ( sb_0__1__0_chany_top_out ) , .chany_top_in ( sb_0__2__0_chany_bottom_out ) , .ccff_head ( sb_0__2__0_ccff_tail ) , .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , .chany_top_out ( cby_0__1__1_chany_top_out ) , - .right_grid_pin_52_ ( cby_0__1__1_right_grid_pin_52_ ) , .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , - .ccff_tail ( cby_0__1__1_ccff_tail ) ) ; + .ccff_tail ( grid_io_left_1_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[17] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[17] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[17] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ) ; cby_1__1_ cby_1__1_ ( - .prog_clk ( { ctsbuf_net_1217 } ) , + .prog_clk ( { ctsbuf_net_79 } ) , .chany_bottom_in ( sb_1__0__0_chany_top_out ) , .chany_top_in ( sb_1__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_0_ccff_tail ) , .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , .chany_top_out ( cby_1__1__0_chany_top_out ) , - .right_grid_pin_52_ ( cby_1__1__0_right_grid_pin_52_ ) , - .left_grid_pin_0_ ( cby_1__1__0_left_grid_pin_0_ ) , - .left_grid_pin_1_ ( cby_1__1__0_left_grid_pin_1_ ) , - .left_grid_pin_2_ ( cby_1__1__0_left_grid_pin_2_ ) , - .left_grid_pin_3_ ( cby_1__1__0_left_grid_pin_3_ ) , - .left_grid_pin_4_ ( cby_1__1__0_left_grid_pin_4_ ) , - .left_grid_pin_5_ ( cby_1__1__0_left_grid_pin_5_ ) , - .left_grid_pin_6_ ( cby_1__1__0_left_grid_pin_6_ ) , - .left_grid_pin_7_ ( cby_1__1__0_left_grid_pin_7_ ) , - .left_grid_pin_8_ ( cby_1__1__0_left_grid_pin_8_ ) , - .left_grid_pin_9_ ( cby_1__1__0_left_grid_pin_9_ ) , - .left_grid_pin_10_ ( cby_1__1__0_left_grid_pin_10_ ) , - .left_grid_pin_11_ ( cby_1__1__0_left_grid_pin_11_ ) , - .left_grid_pin_12_ ( cby_1__1__0_left_grid_pin_12_ ) , - .left_grid_pin_13_ ( cby_1__1__0_left_grid_pin_13_ ) , - .left_grid_pin_14_ ( cby_1__1__0_left_grid_pin_14_ ) , - .left_grid_pin_15_ ( cby_1__1__0_left_grid_pin_15_ ) , + .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__0_ccff_tail ) ) ; cby_1__1_ cby_1__2_ ( - .prog_clk ( { ctsbuf_net_712 } ) , + .prog_clk ( { ctsbuf_net_810 } ) , .chany_bottom_in ( sb_1__1__0_chany_top_out ) , .chany_top_in ( sb_1__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_1_ccff_tail ) , .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , .chany_top_out ( cby_1__1__1_chany_top_out ) , - .right_grid_pin_52_ ( cby_1__1__1_right_grid_pin_52_ ) , - .left_grid_pin_0_ ( cby_1__1__1_left_grid_pin_0_ ) , - .left_grid_pin_1_ ( cby_1__1__1_left_grid_pin_1_ ) , - .left_grid_pin_2_ ( cby_1__1__1_left_grid_pin_2_ ) , - .left_grid_pin_3_ ( cby_1__1__1_left_grid_pin_3_ ) , - .left_grid_pin_4_ ( cby_1__1__1_left_grid_pin_4_ ) , - .left_grid_pin_5_ ( cby_1__1__1_left_grid_pin_5_ ) , - .left_grid_pin_6_ ( cby_1__1__1_left_grid_pin_6_ ) , - .left_grid_pin_7_ ( cby_1__1__1_left_grid_pin_7_ ) , - .left_grid_pin_8_ ( cby_1__1__1_left_grid_pin_8_ ) , - .left_grid_pin_9_ ( cby_1__1__1_left_grid_pin_9_ ) , - .left_grid_pin_10_ ( cby_1__1__1_left_grid_pin_10_ ) , - .left_grid_pin_11_ ( cby_1__1__1_left_grid_pin_11_ ) , - .left_grid_pin_12_ ( cby_1__1__1_left_grid_pin_12_ ) , - .left_grid_pin_13_ ( cby_1__1__1_left_grid_pin_13_ ) , - .left_grid_pin_14_ ( cby_1__1__1_left_grid_pin_14_ ) , - .left_grid_pin_15_ ( cby_1__1__1_left_grid_pin_15_ ) , + .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__1_ccff_tail ) ) ; -cby_1__1_ cby_2__1_ ( - .prog_clk ( { ctsbuf_net_49 } ) , +cby_2__1_ cby_2__1_ ( + .prog_clk ( { ctsbuf_net_13 } ) , .chany_bottom_in ( sb_2__0__0_chany_top_out ) , .chany_top_in ( sb_2__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_2_ccff_tail ) , - .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) , - .chany_top_out ( cby_1__1__2_chany_top_out ) , - .right_grid_pin_52_ ( cby_1__1__2_right_grid_pin_52_ ) , - .left_grid_pin_0_ ( cby_1__1__2_left_grid_pin_0_ ) , - .left_grid_pin_1_ ( cby_1__1__2_left_grid_pin_1_ ) , - .left_grid_pin_2_ ( cby_1__1__2_left_grid_pin_2_ ) , - .left_grid_pin_3_ ( cby_1__1__2_left_grid_pin_3_ ) , - .left_grid_pin_4_ ( cby_1__1__2_left_grid_pin_4_ ) , - .left_grid_pin_5_ ( cby_1__1__2_left_grid_pin_5_ ) , - .left_grid_pin_6_ ( cby_1__1__2_left_grid_pin_6_ ) , - .left_grid_pin_7_ ( cby_1__1__2_left_grid_pin_7_ ) , - .left_grid_pin_8_ ( cby_1__1__2_left_grid_pin_8_ ) , - .left_grid_pin_9_ ( cby_1__1__2_left_grid_pin_9_ ) , - .left_grid_pin_10_ ( cby_1__1__2_left_grid_pin_10_ ) , - .left_grid_pin_11_ ( cby_1__1__2_left_grid_pin_11_ ) , - .left_grid_pin_12_ ( cby_1__1__2_left_grid_pin_12_ ) , - .left_grid_pin_13_ ( cby_1__1__2_left_grid_pin_13_ ) , - .left_grid_pin_14_ ( cby_1__1__2_left_grid_pin_14_ ) , - .left_grid_pin_15_ ( cby_1__1__2_left_grid_pin_15_ ) , - .ccff_tail ( cby_1__1__2_ccff_tail ) ) ; -cby_1__1_ cby_2__2_ ( - .prog_clk ( { ctsbuf_net_16 } ) , + .chany_bottom_out ( cby_2__1__0_chany_bottom_out ) , + .chany_top_out ( cby_2__1__0_chany_top_out ) , + .right_grid_pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_2__1__0_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_2__1__0_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_2__1__0_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_2__1__0_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_2__1__0_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_2__1__0_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_2__1__0_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_2__1__0_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_2__1__0_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_2__1__0_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_2__1__0_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_2__1__0_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_2__1__0_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_0_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .left_width_0_height_0__pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ) ; +cby_2__1_ cby_2__2_ ( + .prog_clk ( { ctsbuf_net_46 } ) , .chany_bottom_in ( sb_2__1__0_chany_top_out ) , .chany_top_in ( sb_2__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_3_ccff_tail ) , - .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) , - .chany_top_out ( cby_1__1__3_chany_top_out ) , - .right_grid_pin_52_ ( cby_1__1__3_right_grid_pin_52_ ) , - .left_grid_pin_0_ ( cby_1__1__3_left_grid_pin_0_ ) , - .left_grid_pin_1_ ( cby_1__1__3_left_grid_pin_1_ ) , - .left_grid_pin_2_ ( cby_1__1__3_left_grid_pin_2_ ) , - .left_grid_pin_3_ ( cby_1__1__3_left_grid_pin_3_ ) , - .left_grid_pin_4_ ( cby_1__1__3_left_grid_pin_4_ ) , - .left_grid_pin_5_ ( cby_1__1__3_left_grid_pin_5_ ) , - .left_grid_pin_6_ ( cby_1__1__3_left_grid_pin_6_ ) , - .left_grid_pin_7_ ( cby_1__1__3_left_grid_pin_7_ ) , - .left_grid_pin_8_ ( cby_1__1__3_left_grid_pin_8_ ) , - .left_grid_pin_9_ ( cby_1__1__3_left_grid_pin_9_ ) , - .left_grid_pin_10_ ( cby_1__1__3_left_grid_pin_10_ ) , - .left_grid_pin_11_ ( cby_1__1__3_left_grid_pin_11_ ) , - .left_grid_pin_12_ ( cby_1__1__3_left_grid_pin_12_ ) , - .left_grid_pin_13_ ( cby_1__1__3_left_grid_pin_13_ ) , - .left_grid_pin_14_ ( cby_1__1__3_left_grid_pin_14_ ) , - .left_grid_pin_15_ ( cby_1__1__3_left_grid_pin_15_ ) , - .ccff_tail ( cby_1__1__3_ccff_tail ) ) ; -direct_interc_0 direct_interc_0_ ( + .chany_bottom_out ( cby_2__1__1_chany_bottom_out ) , + .chany_top_out ( cby_2__1__1_chany_top_out ) , + .right_grid_pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_2__1__1_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_2__1__1_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_2__1__1_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_2__1__1_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_2__1__1_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_2__1__1_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_2__1__1_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_2__1__1_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_2__1__1_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_2__1__1_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_2__1__1_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_2__1__1_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_2__1__1_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_1_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .left_width_0_height_0__pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ) ; +direct_interc_0_1 direct_interc_0_ ( .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_0_out ) ) ; -direct_interc_1 direct_interc_1_ ( +direct_interc_1_1 direct_interc_1_ ( .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_1_out ) ) ; direct_interc_2 direct_interc_2_ ( .in ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_2_out ) ) ; -direct_interc_3 direct_interc_3_ ( - .in ( grid_clb_1_bottom_width_0_height_0__pin_51_ ) , - .out ( direct_interc_3_out ) ) ; -direct_interc_4 direct_interc_4_ ( - .in ( grid_clb_3_bottom_width_0_height_0__pin_51_ ) , - .out ( direct_interc_4_out ) ) ; +direct_interc_3 direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_31 } ) , + .out ( { SYNOPSYS_UNCONNECTED_32 } ) ) ; +direct_interc_4 direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_33 } ) , + .out ( { SYNOPSYS_UNCONNECTED_34 } ) ) ; direct_interc_5 direct_interc_5_ ( .in ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , .out ( direct_interc_5_out ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7301 ( - .A ( grid_io_left_1_ccff_tail[0] ) , .X ( ropt_net_25 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69097180 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_16 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69107181 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_27 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69117182 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_38 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69127183 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_49 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69137184 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_510 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69147185 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_611 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69157186 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_712 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69167187 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_813 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69177188 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_914 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7302 ( .A ( ropt_net_25 ) , - .X ( ropt_net_26 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69197190 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_1116 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69207191 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_1217 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69217192 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_1318 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69227193 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_1419 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69237194 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_1520 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7303 ( .A ( ropt_net_26 ) , - .X ( ropt_net_27 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69257196 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_1722 ) ) ; -sky130_fd_sc_hd__bufinv_8 cts_inv_69247195_69267197 ( - .A ( SYNOPSYS_UNCONNECTED_1 ) , .Y ( SYNOPSYS_UNCONNECTED_2 ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_69187189_69277198 ( - .A ( SYNOPSYS_UNCONNECTED_3 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69397210 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_1823 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69407211 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_1924 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7304 ( - .A ( grid_io_top_1_ccff_tail[0] ) , .X ( ropt_net_28 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_7305 ( .A ( ropt_net_28 ) , - .X ( ropt_net_29 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7306 ( - .A ( grid_io_left_0_ccff_tail[0] ) , .X ( ropt_net_30 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_7307 ( .A ( ropt_net_30 ) , - .X ( ropt_net_31 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78798147 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_13 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78808148 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_24 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78838151 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_57 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78848152 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_68 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78858153 ( .A ( ctsbuf_net_1719 ) , + .Y ( ctsbuf_net_79 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78868154 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_810 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78878155 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_911 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78888156 ( .A ( ctsbuf_net_1719 ) , + .Y ( ctsbuf_net_1012 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78898157 ( .A ( ctsbuf_net_1719 ) , + .Y ( ctsbuf_net_1113 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78918159 ( .A ( ctsbuf_net_1719 ) , + .Y ( ctsbuf_net_1315 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78938161 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_1517 ) ) ; +sky130_fd_sc_hd__inv_8 cts_inv_78828150_78948162 ( + .A ( SYNOPSYS_UNCONNECTED_35 ) , .Y ( SYNOPSYS_UNCONNECTED_36 ) ) ; +sky130_fd_sc_hd__inv_6 cts_inv_78818149_78958163 ( + .A ( SYNOPSYS_UNCONNECTED_37 ) , .Y ( SYNOPSYS_UNCONNECTED_38 ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_78908158_78968164 ( + .A ( SYNOPSYS_UNCONNECTED_39 ) , .Y ( SYNOPSYS_UNCONNECTED_40 ) ) ; +sky130_fd_sc_hd__bufinv_8 cts_inv_78928160_78978165 ( + .A ( SYNOPSYS_UNCONNECTED_41 ) , .Y ( SYNOPSYS_UNCONNECTED_42 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_79058173 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_1618 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_79068174 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_1719 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds index f0b5fc0..9da9fb3 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f86fdd7b261d52a0cf702389cb486ccdeec4d16c0b34ed0da55b5523a29a5abb -size 13289472 +oid sha256:535427e1e95a2d00f9d3401478d5ce61f7bcb2e4608b0b9af9f00a7965479f82 +size 10821632 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lef b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lef index f844858..bc1a90d 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell VIA L1M1_PR LAYER li1 ; @@ -352,6 +340,7 @@ END M4M5_PR_C SITE unit CLASS CORE ; + SYMMETRY Y ; SIZE 0.46 BY 2.72 ; END unit diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v index 53b60aa..8a140ff 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v @@ -4,45 +4,11 @@ // // // -module direct_interc_5 ( in , out , VDD , VSS ) ; +module direct_interc_5 ( in , out ) ; input [0:0] in ; output [0:0] out ; -input VDD ; -input VSS ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( in[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module direct_interc_4 ( in , out , VDD , VSS ) ; -input [0:0] in ; -output [0:0] out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( in[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module direct_interc_3 ( in , out , VDD , VSS ) ; -input [0:0] in ; -output [0:0] out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( in[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +assign out[0] = in[0] ; endmodule @@ -88,6 +54,2600 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) , endmodule +module direct_interc_4 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[0] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module EMBEDDED_IO_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; + +assign FPGA_IN = SOC_IN ; +assign SOC_OUT = FPGA_OUT ; +assign SOC_DIR = FPGA_DIR ; +endmodule + + +module logical_tile_io_mode_physical__iopad_7 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_0_en ; +wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO_7 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_7 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__7 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +direct_interc_4 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_4 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_10 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0_6 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_18 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7_2 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6_4 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5_4 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_6 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , + VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign chany_bottom_out[0] = chany_top_in[0] ; +assign chany_bottom_out[1] = chany_top_in[1] ; +assign chany_bottom_out[2] = chany_top_in[2] ; +assign chany_bottom_out[3] = chany_top_in[3] ; +assign chany_bottom_out[4] = chany_top_in[4] ; +assign chany_bottom_out[5] = chany_top_in[5] ; +assign chany_bottom_out[6] = chany_top_in[6] ; +assign chany_bottom_out[7] = chany_top_in[7] ; +assign chany_bottom_out[8] = chany_top_in[8] ; +assign chany_bottom_out[9] = chany_top_in[9] ; +assign chany_bottom_out[10] = chany_top_in[10] ; +assign chany_bottom_out[11] = chany_top_in[11] ; +assign chany_bottom_out[12] = chany_top_in[12] ; +assign chany_bottom_out[13] = chany_top_in[13] ; +assign chany_bottom_out[14] = chany_top_in[14] ; +assign chany_bottom_out[15] = chany_top_in[15] ; +assign chany_bottom_out[16] = chany_top_in[16] ; +assign chany_bottom_out[17] = chany_top_in[17] ; +assign chany_bottom_out[18] = chany_top_in[18] ; +assign chany_bottom_out[19] = chany_top_in[19] ; +assign chany_top_out[0] = chany_bottom_in[0] ; +assign chany_top_out[1] = chany_bottom_in[1] ; +assign chany_top_out[2] = chany_bottom_in[2] ; +assign chany_top_out[3] = chany_bottom_in[3] ; +assign chany_top_out[4] = chany_bottom_in[4] ; +assign chany_top_out[5] = chany_bottom_in[5] ; +assign chany_top_out[6] = chany_bottom_in[6] ; +assign chany_top_out[7] = chany_bottom_in[7] ; +assign chany_top_out[8] = chany_bottom_in[8] ; +assign chany_top_out[9] = chany_bottom_in[9] ; +assign chany_top_out[10] = chany_bottom_in[10] ; +assign chany_top_out[11] = chany_bottom_in[11] ; +assign chany_top_out[12] = chany_bottom_in[12] ; +assign chany_top_out[13] = chany_bottom_in[13] ; +assign chany_top_out[14] = chany_bottom_in[14] ; +assign chany_top_out[15] = chany_bottom_in[15] ; +assign chany_top_out[16] = chany_bottom_in[16] ; +assign chany_top_out[17] = chany_bottom_in[17] ; +assign chany_top_out[18] = chany_bottom_in[18] ; +assign chany_top_out[19] = chany_bottom_in[19] ; + +mux_tree_tapbuf_size10_0_6 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_1_5 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_5_4 mux_right_ipin_3 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_6_4 mux_right_ipin_4 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_7_2 mux_right_ipin_7 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_18 mux_right_ipin_8 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_2_5 mux_right_ipin_11 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_3_5 mux_right_ipin_12 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_4_5 mux_right_ipin_15 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_0_6 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_1_5 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_5_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_6_4 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_7_2 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_18 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_2_5 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_3_5 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_4_5 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_0_6 mux_right_ipin_1 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_4_3 mux_right_ipin_2 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_5_3 mux_right_ipin_5 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_6_3 mux_right_ipin_6 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_10 mux_right_ipin_9 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_1_5 mux_right_ipin_10 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_2_3 mux_right_ipin_13 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_3_3 mux_right_ipin_14 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_0_6 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_4_3 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_5_3 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_6_3 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_10 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_1_5 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_2_3 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_3_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +logical_tile_io_mode_io__7 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_41 } ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_42 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1494 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1495 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1496 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1497 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1498 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1499 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1500 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1501 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1502 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1503 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1504 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1505 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1506 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1507 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1508 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 FTB_41__40 ( + .A ( left_width_0_height_0__pin_1_upper[0] ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_731 ( .A ( ropt_net_41 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_732 ( .A ( ropt_net_42 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x69000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x87400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x69000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x87400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size8_mem_3_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -113,14 +2673,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__56 ( .A ( mem_out[3] ) , - .X ( net_aps_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( net_aps_56 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_3 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_2_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -145,7 +2703,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -175,37 +2733,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -235,7 +2763,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -265,7 +2793,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -295,7 +2823,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -325,7 +2853,37 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -347,13 +2905,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -377,14 +2931,14 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_2_3 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size8_2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -492,56 +3046,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size8_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -757,37 +3261,61 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module mux_tree_tapbuf_size8_0_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_3 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_3_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -813,11 +3341,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( net_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_90 ( .A ( net_net_70 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_16 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_2_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -842,12 +3372,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_1_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -872,7 +3402,37 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -902,7 +3462,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -932,12 +3492,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_3 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_4_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -962,37 +3522,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1022,12 +3552,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_4_3 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_3_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -1090,7 +3620,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3_3 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -1153,7 +3683,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_16 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_1_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -1216,7 +3746,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7_2 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_17 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -1405,70 +3935,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_1_3 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_4_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -1595,36 +4062,34 @@ endmodule module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , - left_grid_pin_1_ , left_grid_pin_2_ , left_grid_pin_3_ , - left_grid_pin_4_ , left_grid_pin_5_ , left_grid_pin_6_ , - left_grid_pin_7_ , left_grid_pin_8_ , left_grid_pin_9_ , - left_grid_pin_10_ , left_grid_pin_11_ , left_grid_pin_12_ , - left_grid_pin_13_ , left_grid_pin_14_ , left_grid_pin_15_ , ccff_tail , - VDD , VSS ) ; + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chany_top_out ; -output [0:0] right_grid_pin_52_ ; -output [0:0] left_grid_pin_0_ ; -output [0:0] left_grid_pin_1_ ; -output [0:0] left_grid_pin_2_ ; -output [0:0] left_grid_pin_3_ ; -output [0:0] left_grid_pin_4_ ; -output [0:0] left_grid_pin_5_ ; -output [0:0] left_grid_pin_6_ ; -output [0:0] left_grid_pin_7_ ; -output [0:0] left_grid_pin_8_ ; -output [0:0] left_grid_pin_9_ ; -output [0:0] left_grid_pin_10_ ; -output [0:0] left_grid_pin_11_ ; -output [0:0] left_grid_pin_12_ ; -output [0:0] left_grid_pin_13_ ; -output [0:0] left_grid_pin_14_ ; -output [0:0] left_grid_pin_15_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; input VDD ; input VSS ; @@ -1645,8 +4110,6 @@ wire [0:3] mux_tree_tapbuf_size10_6_sram ; wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1654,8 +4117,6 @@ wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; @@ -1679,363 +4140,405 @@ wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size10_0_5 mux_left_ipin_0 ( +mux_tree_tapbuf_size10_0_5 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_52_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size10_1_3 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_2_3 mux_right_ipin_1 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_6_3 mux_right_ipin_5 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_7_2 mux_right_ipin_8 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_16 mux_right_ipin_9 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_3_3 mux_right_ipin_12 ( + .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_4_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size10_6_3 mux_right_ipin_7 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size10_4_3 mux_right_ipin_13 ( + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_98 ) ) ; +mux_tree_tapbuf_size10_17 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[14] , chany_top_in[14] , chany_bottom_in[18] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_mem_0_5 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_1_4 mux_right_ipin_11 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_2_4 mux_right_ipin_12 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_3_4 mux_right_ipin_15 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_mem_0_5 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1_3 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2_3 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem_5_3 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5_3 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_6_3 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6_3 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem_17 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_7_2 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1_4 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_16 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem_2_4 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +mux_tree_tapbuf_size10_mem_3_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4_3 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_4_2 mux_right_ipin_2 ( +mux_tree_tapbuf_size8_0_5 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size8_5_2 mux_right_ipin_3 ( + .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size8_4_2 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[16] , chany_top_in[16] } ) , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_6_2 mux_right_ipin_6 ( + .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size8_5_2 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size8_9 mux_right_ipin_7 ( + .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_98 ) ) ; +mux_tree_tapbuf_size8_6_2 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[12] , chany_top_in[12] } ) , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_0_4 mux_right_ipin_10 ( + .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_9 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size8_1_4 mux_right_ipin_11 ( + .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size8_1_4 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[16] , chany_top_in[16] } ) , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size8_2_3 mux_right_ipin_14 ( + .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size8_2_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size8_3_2 mux_right_ipin_15 ( + .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_3_2 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[12] , chany_top_in[12] } ) , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_mem_4_2 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size8_mem_0_5 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5_2 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_4_2 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6_2 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size8_mem_5_2 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_9 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_6_2 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0_4 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , +mux_tree_tapbuf_size8_mem_9 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1_4 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_1_4 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , +mux_tree_tapbuf_size8_mem_2_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3_2 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_3_2 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2476 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1478 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2477 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1479 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2478 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1480 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2479 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1481 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2480 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1482 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2481 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1483 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2482 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1484 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2483 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1485 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2484 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1486 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2485 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1487 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2486 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1488 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2487 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1489 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2488 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1490 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2489 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1491 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2490 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1492 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_113 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , + .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( aps_rename_4_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( aps_rename_5_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chany_top_in[1] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_111 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__27 ( .A ( chany_top_in[7] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( + .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_111 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_29__28 ( .A ( chany_top_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , + .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_113 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_114 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_115 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , + .X ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_117 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( aps_rename_1_ ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_59 ) , + .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( @@ -2044,60 +4547,22 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_bottom_in[19] ) , - .X ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_top_in[16] ) , - .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_1_ ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( aps_rename_2_ ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( aps_rename_4_ ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_5_ ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_98 ( .A ( BUF_net_68 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_71 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( @@ -2108,6 +4573,14 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( @@ -2116,32 +4589,22 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( @@ -2150,6 +4613,8 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y136000 ( @@ -2158,8 +4623,6 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y163200 ( @@ -2168,13 +4631,27 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2184,10 +4661,12 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y244800 ( @@ -2196,11 +4675,9 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2210,45 +4687,47 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2266,15 +4745,33 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2284,14 +4781,36 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( @@ -2300,13 +4819,9 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2316,8 +4831,8 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x82800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( @@ -2326,13 +4841,13 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2342,6 +4857,10 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x59800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y598400 ( @@ -2350,13 +4869,15 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2366,7 +4887,7 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2376,9 +4897,9 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2388,7 +4909,9 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2416,14 +4939,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y734400 ( @@ -2441,132 +4964,168 @@ sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( endmodule -module mux_tree_tapbuf_size10_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( net_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( net_net_76 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_15 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; +module direct_interc_3 ( in , out ) ; +input [0:0] in ; output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +assign out[0] = in[0] ; endmodule -module mux_tree_tapbuf_size10_0_4 ( in , sram , sram_inv , out , VDD , VSS , +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module EMBEDDED_IO_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; +input VDD ; +input VSS ; + +supply1 VDD ; +wire aps_rename_2_ ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , + .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_6 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO_6 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__6 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_3 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_3 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_16 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -2630,243 +5189,259 @@ endmodule module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , - ccff_tail , VDD , VSS ) ; + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , + right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chany_top_out ; -output [0:0] right_grid_pin_52_ ; output [0:0] left_grid_pin_0_ ; output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; input VDD ; input VSS ; +wire ropt_net_162 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size10_0_4 mux_left_ipin_0 ( +mux_tree_tapbuf_size10_16 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_52_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; -mux_tree_tapbuf_size10_15 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -mux_tree_tapbuf_size10_mem_0_4 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size10_mem_16 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_15 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2460 ( .VNB ( VSS ) , +logical_tile_io_mode_io__6 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_163 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1462 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2461 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1463 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2462 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1464 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2463 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1465 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2464 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1466 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2465 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1467 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2466 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1468 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2467 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1469 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2468 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1470 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2469 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1471 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2470 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1472 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2471 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1473 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2472 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1474 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2473 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1475 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2474 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1476 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_177 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_153 ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_154 ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_155 ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_156 ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_157 ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_158 ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_159 ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_164 ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_166 ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_167 ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_168 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_169 ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_172 ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_175 ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_176 ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_180 ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_45 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_182 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_183 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_184 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_185 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_186 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_188 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_189 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_190 ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_191 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_192 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_193 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_194 ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_65 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chany_top_in[9] ) , - .X ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_196 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_197 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_198 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_200 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_202 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) , + .X ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_203 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) , + .X ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_204 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( @@ -2881,26 +5456,24 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( @@ -2909,74 +5482,84 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_111 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_115 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_117 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y27200 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_131 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_66 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( @@ -2987,15 +5570,9 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3009,11 +5586,7 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3025,36 +5598,34 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( @@ -3067,32 +5638,32 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( @@ -3109,30 +5680,30 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( @@ -3145,31 +5716,29 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3179,35 +5748,33 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3217,37 +5784,43 @@ sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x87400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3257,36 +5830,40 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( @@ -3299,25 +5876,25 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3347,20 +5924,20 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( @@ -3371,17 +5948,17 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3389,19 +5966,19 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3417,63 +5994,63 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3481,24 +6058,36 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y462400 ( @@ -3519,29 +6108,31 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3559,31 +6150,29 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3595,68 +6184,66 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x96600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y571200 ( @@ -3677,31 +6264,29 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3709,33 +6294,35 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3743,30 +6330,28 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x128800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( @@ -3793,14 +6378,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y734400 ( @@ -3818,13 +6403,21 @@ sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( endmodule -module mux_tree_tapbuf_size10_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module direct_interc_2 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; input VDD ; input VSS ; @@ -3832,1341 +6425,107 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( net_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_115 ( .A ( net_net_74 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( net_aps_61 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_14 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; +module EMBEDDED_IO_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; input VDD ; input VSS ; -input p0 ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( p_abuf0 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_0_ , ccff_tail , VDD , - VSS ) ; +module logical_tile_io_mode_physical__iopad_5 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_0_ ; +output [0:0] iopad_inpad ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output p_abuf0 ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size10_14 mux_bottom_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; -mux_tree_tapbuf_size10_mem_14 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ropt_net_181 } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , +EMBEDDED_IO_5 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2446 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2447 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2448 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2449 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2450 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2451 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2452 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2453 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2454 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2455 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2456 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2457 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2458 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_144 ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_148 ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_149 ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_152 ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_155 ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_167 ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_172 ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_44 ( .A ( chanx_left_in[8] ) , - .X ( BUF_net_44 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_197 ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_198 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_199 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_200 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_203 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_204 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_207 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_209 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_214 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_216 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_103 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_104 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_116 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_44 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_132 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__5 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +direct_interc_2 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf0 } ) ) ; +direct_interc_2 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; endmodule @@ -5195,14 +6554,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( net_net_72 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_2_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5227,7 +6584,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5257,37 +6614,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5317,7 +6644,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5347,7 +6674,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5377,7 +6704,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5407,7 +6734,37 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5466,7 +6823,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2_2 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size8_2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -5483,13 +6840,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -5513,10 +6866,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5574,60 +6927,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size8_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -5637,56 +6936,6 @@ input VDD ; input VSS ; input p0 ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -5731,6 +6980,56 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size8_6_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size8_5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; @@ -5839,7 +7138,57 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_3_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_0_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5864,12 +7213,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_3_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5894,12 +7243,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_13 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_2_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5924,7 +7273,67 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5954,7 +7363,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5984,12 +7393,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_1_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -6014,12 +7423,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_0_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -6044,42 +7453,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_3_2 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_4_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -6142,7 +7521,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_2 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_3_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -6205,7 +7584,133 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_13 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_2_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_15 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -6394,7 +7899,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4_2 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_1_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -6457,7 +7962,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1_2 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_0_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -6520,102 +8025,56 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , - top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , - top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , - top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , - top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , - top_grid_pin_30_ , top_grid_pin_31_ , ccff_tail , VDD , VSS ) ; +module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , + bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_16_ ; -output [0:0] top_grid_pin_17_ ; -output [0:0] top_grid_pin_18_ ; -output [0:0] top_grid_pin_19_ ; -output [0:0] top_grid_pin_20_ ; -output [0:0] top_grid_pin_21_ ; -output [0:0] top_grid_pin_22_ ; -output [0:0] top_grid_pin_23_ ; -output [0:0] top_grid_pin_24_ ; -output [0:0] top_grid_pin_25_ ; -output [0:0] top_grid_pin_26_ ; -output [0:0] top_grid_pin_27_ ; -output [0:0] top_grid_pin_28_ ; -output [0:0] top_grid_pin_29_ ; -output [0:0] top_grid_pin_30_ ; -output [0:0] top_grid_pin_31_ ; +output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; input VDD ; input VSS ; +wire p_abuf0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -6632,6 +8091,8 @@ wire [0:3] mux_tree_tapbuf_size10_6_sram ; wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -6663,407 +8124,422 @@ wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size10_0_3 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0_4 mux_bottom_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_1_2 mux_bottom_ipin_1 ( + .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_1_3 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( top_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_4_2 mux_bottom_ipin_4 ( + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_5_2 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( top_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_5_2 mux_bottom_ipin_5 ( + .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_6_2 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( top_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_6_2 mux_bottom_ipin_8 ( + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_7_1 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( top_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_13 mux_bottom_ipin_9 ( + .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_15 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( top_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_2_2 mux_bottom_ipin_12 ( + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_2_3 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( top_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_3_2 mux_bottom_ipin_13 ( + .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_3_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( top_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_mem_0_3 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_4_3 mux_top_ipin_15 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_mem_0_4 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1_2 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1_3 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4_2 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , +mux_tree_tapbuf_size10_mem_5_2 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5_2 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_6_2 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6_2 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size10_mem_7_1 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_13 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , +mux_tree_tapbuf_size10_mem_15 mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , +mux_tree_tapbuf_size10_mem_2_3 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3_2 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , +mux_tree_tapbuf_size10_mem_3_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_4_1 mux_bottom_ipin_2 ( +mux_tree_tapbuf_size10_mem_4_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_0_4 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( top_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_5_1 mux_bottom_ipin_3 ( + .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_4_1 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( top_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_6_1 mux_bottom_ipin_6 ( + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_5_1 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( top_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_8 mux_bottom_ipin_7 ( + .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_6_1 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( top_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_0_3 mux_bottom_ipin_10 ( + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size8_8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( top_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_1_3 mux_bottom_ipin_11 ( + .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_1_3 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( top_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_2_2 mux_bottom_ipin_14 ( + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_2_1 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( top_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_3_1 mux_bottom_ipin_15 ( + .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_3_1 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( top_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_mem_4_1 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size8_mem_0_4 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5_1 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size8_mem_4_1 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6_1 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , +mux_tree_tapbuf_size8_mem_5_1 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_8 mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size8_mem_6_1 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0_3 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , +mux_tree_tapbuf_size8_mem_8 mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1_3 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , +mux_tree_tapbuf_size8_mem_1_3 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , +mux_tree_tapbuf_size8_mem_2_1 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3_1 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_3_1 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_97 } ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2432 ( .VNB ( VSS ) , +logical_tile_io_mode_io__5 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1448 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2433 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1449 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2434 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1450 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2435 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1451 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2436 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1452 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2437 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1453 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2438 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1454 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2439 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1455 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2440 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1456 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2441 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1457 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2442 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1458 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2443 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1459 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2444 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1460 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_105 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_673 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_106 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_107 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_675 ( .A ( ropt_net_97 ) , - .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_108 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_98 ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_102 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_682 ( .A ( ropt_net_103 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_104 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_59 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chanx_left_in[9] ) , - .X ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chanx_left_in[19] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_119 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( BUF_net_61 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( aps_rename_3_ ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_82 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_2_ ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( p_abuf0 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_2_ ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_3_ ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( @@ -7086,26 +8562,34 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y81600 ( @@ -7114,12 +8598,8 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y108800 ( @@ -7128,11 +8608,13 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -7140,22 +8622,6 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y163200 ( @@ -7164,35 +8630,25 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -7202,9 +8658,7 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -7214,12 +8668,12 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y299200 ( @@ -7228,23 +8682,19 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -7254,45 +8704,29 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -7302,30 +8736,6 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y462400 ( @@ -7334,28 +8744,14 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y516800 ( @@ -7364,24 +8760,18 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y571200 ( @@ -7390,7 +8780,13 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -7418,14 +8814,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( @@ -7474,12 +8870,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7504,7 +8900,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7534,37 +8930,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7594,7 +8960,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7624,7 +8990,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7654,7 +9020,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7684,7 +9050,37 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7742,8 +9138,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7850,8 +9245,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module mux_tree_tapbuf_size8_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7904,55 +9298,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -8108,7 +9453,61 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_12 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8133,14 +9532,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( net_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( net_net_69 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_2_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8165,12 +9562,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_1_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8195,12 +9592,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_14 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8225,7 +9622,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8255,7 +9652,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8285,12 +9682,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_4_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8315,12 +9712,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_0_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8345,42 +9742,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_12 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -8443,7 +9810,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -8506,7 +9873,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_1_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -8569,7 +9936,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -8758,6 +10125,1989 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size10_4_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , CLB_SC_IN , CLB_SC_OUT , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input CLB_SC_IN ; +output CLB_SC_OUT ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0_3 mux_top_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_4_2 mux_top_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_5_1 mux_top_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_6_1 mux_top_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_14 mux_top_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_1_2 mux_top_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_2_2 mux_top_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_3_2 mux_top_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_mem_0_3 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_4_2 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_5_1 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_6_1 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_14 mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_1_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_2_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_3_2 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_0_3 mux_top_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_7 mux_top_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_1_2 mux_top_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_mem_0_3 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_7 mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_1_2 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1434 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1435 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1436 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1437 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1438 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1439 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1440 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1441 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1442 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1443 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1444 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1445 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1446 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( ropt_net_105 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( aps_rename_6_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( ropt_net_106 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_107 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_108 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_109 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( aps_rename_4_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[19] ) , + .X ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chanx_right_in[12] ) , + .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chanx_right_in[16] ) , + .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( aps_rename_6_ ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( BUF_net_65 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( BUF_net_69 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_71 ) , + .X ( ropt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( CLB_SC_IN ) , + .X ( CLB_SC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( aps_rename_4_ ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb15_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__70 ( .A ( mem_out[0] ) , + .X ( net_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_114 ( .A ( net_net_114 ) , + .X ( net_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_152 ( .A ( net_net_113 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb14_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( net_aps_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb11_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( net_aps_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__63 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb8_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_14__60 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_155 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb5_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( net_aps_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module direct_interc_1 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb2_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( net_aps_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_13 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size10_4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; @@ -8821,6 +12171,132 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size10_3_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size10_1_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; @@ -8903,13 +12379,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -8940,48 +12412,76 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , - top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , - top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , - top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , - top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , - top_grid_pin_30_ , top_grid_pin_31_ , bottom_grid_pin_0_ , ccff_tail , - VDD , VSS ) ; + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , + top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , + top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , + top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , + top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , + top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , + top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_16_ ; -output [0:0] top_grid_pin_17_ ; -output [0:0] top_grid_pin_18_ ; -output [0:0] top_grid_pin_19_ ; -output [0:0] top_grid_pin_20_ ; -output [0:0] top_grid_pin_21_ ; -output [0:0] top_grid_pin_22_ ; -output [0:0] top_grid_pin_23_ ; -output [0:0] top_grid_pin_24_ ; -output [0:0] top_grid_pin_25_ ; -output [0:0] top_grid_pin_26_ ; -output [0:0] top_grid_pin_27_ ; -output [0:0] top_grid_pin_28_ ; -output [0:0] top_grid_pin_29_ ; -output [0:0] top_grid_pin_30_ ; -output [0:0] top_grid_pin_31_ ; output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; output [0:0] ccff_tail ; +input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; input VDD ; input VSS ; +wire ropt_net_188 ; +wire ropt_net_186 ; +wire ropt_net_190 ; +wire ropt_net_184 ; +wire ropt_net_185 ; +wire ropt_net_183 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -8994,397 +12494,439 @@ wire [0:3] mux_tree_tapbuf_size10_4_sram ; wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size10_0_2 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0_2 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_1_1 mux_bottom_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_177 ) ) ; +mux_tree_tapbuf_size10_1_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( top_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_4_1 mux_bottom_ipin_4 ( + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_2_1 mux_top_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_3_1 mux_top_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_4_1 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( top_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_5_1 mux_bottom_ipin_5 ( + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_13 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( top_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_6_1 mux_bottom_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( top_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_7_1 mux_bottom_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( top_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_2_1 mux_bottom_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( top_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_3_1 mux_bottom_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( top_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_12 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_mem_0_2 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_177 ) ) ; +mux_tree_tapbuf_size10_mem_0_2 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4_1 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , +mux_tree_tapbuf_size10_mem_2_1 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5_1 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_3_1 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6_1 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4_1 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_7_1 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , +mux_tree_tapbuf_size10_mem_13 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2_1 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3_1 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_12 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( top_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( top_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( top_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_7 mux_bottom_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( top_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_0_2 mux_bottom_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( top_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_1_2 mux_bottom_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( top_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_2_1 mux_bottom_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( top_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( top_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_7 mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0_2 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1_2 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2_1 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2418 ( .VNB ( VSS ) , +logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_12_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_188 ) ) ; +logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_206 } ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_186 ) ) ; +logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_14_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_190 ) ) ; +logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_15_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_184 ) ) ; +logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_16_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_185 ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_17_ } ) , + .ccff_tail ( { ropt_net_221 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1420 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2419 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1421 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2420 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1422 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2421 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1423 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2422 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1424 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2423 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1425 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2424 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1426 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2425 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1427 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2426 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1428 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2427 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1429 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2428 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1430 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2429 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1431 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2430 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1432 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_92 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_672 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_230 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_673 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_183 ) , + .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_184 ) , + .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_185 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_186 ) , + .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_187 ) , + .X ( ropt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_188 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_190 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( BUF_net_111 ) , + .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_110 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_231 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_194 ) , + .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_232 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( BUF_net_109 ) , + .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_233 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_197 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_234 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_235 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_199 ) , + .X ( ropt_net_251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_201 ) , + .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_202 ) , + .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_236 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_237 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_238 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_205 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_43__42 ( .A ( aps_rename_14_ ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_44__43 ( .A ( aps_rename_15_ ) , + .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_206 ) , + .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_208 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_212 ) , + .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_213 ) , + .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_214 ) , + .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_239 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[14] ) , + .X ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_216 ) , + .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_242 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_right_in[9] ) , + .X ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( chanx_right_in[10] ) , + .X ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_243 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_244 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_245 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_246 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_218 ) , + .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( aps_rename_12_ ) , + .X ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_110 ( .A ( aps_rename_13_ ) , + .X ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_111 ( .A ( aps_rename_16_ ) , + .X ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_219 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_220 ) , + .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_221 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_222 ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_223 ) , + .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_224 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_225 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_227 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_247 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_248 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_249 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_250 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_252 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_253 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_254 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_255 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_256 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_257 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_146 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_147 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_148 ( .A ( BUF_net_102 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_149 ( .A ( BUF_net_103 ) , + .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_158 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_159 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_161 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_162 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_163 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_164 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_92 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_167 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_173 ( .A ( aps_rename_17_ ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( @@ -9395,38 +12937,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_1_ ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_76 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_77 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_78 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_82 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( aps_rename_2_ ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( @@ -9451,11 +12971,13 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -9465,6 +12987,10 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y54400 ( @@ -9473,42 +12999,84 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x78200y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x87400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y136000 ( @@ -9517,21 +13085,45 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -9541,10 +13133,28 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y217600 ( @@ -9553,48 +13163,78 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y299200 ( @@ -9603,11 +13243,25 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -9617,7 +13271,25 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -9627,6 +13299,24 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y380800 ( @@ -9635,11 +13325,23 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -9649,7 +13351,31 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -9659,15 +13385,29 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -9677,32 +13417,58 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y516800 ( @@ -9711,39 +13477,95 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x59800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -9771,14 +13593,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( @@ -9802,7 +13624,7 @@ sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y625600 ( endmodule -module mux_tree_tapbuf_size2_mem_15_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem_1_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9821,9 +13643,177 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__39 ( .A ( mem_out[1] ) , - .X ( net_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( net_net_59 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_6 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( net_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_48 ( .A ( net_net_48 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9847,12 +13837,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_16_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9871,12 +13861,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_14_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9895,12 +13885,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_13_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9919,12 +13909,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_12_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_18_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9943,12 +13933,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_11_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_17_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9967,12 +13957,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_10_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_16_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9991,12 +13981,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_15_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10015,12 +14005,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_8_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_14_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10039,12 +14029,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_7_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_13_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10063,7 +14053,127 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10087,12 +14197,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_5_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_5_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10111,12 +14221,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_4_5 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10135,7 +14245,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10159,7 +14269,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10183,7 +14293,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10207,7 +14317,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10231,12 +14341,36 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_15_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_mem_9_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -10290,7 +14424,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_16_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -10317,7 +14451,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_14_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -10344,7 +14478,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_13_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -10371,7 +14505,223 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_12_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_18_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_17_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_16_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -10394,7 +14744,7 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -10421,7 +14771,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_10_2 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_7_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -10432,100 +14782,15 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_8_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_7_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10556,7 +14821,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_5_4 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_5_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -10567,23 +14832,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_4_4 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_4_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -10718,57 +14979,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem_0_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_0_6 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_9_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; +input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; @@ -10778,57 +14991,18 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( BUF_net_41 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_11 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10854,7 +15028,61 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10881,7 +15109,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10926,6 +15154,88 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module mux_tree_tapbuf_size5_2_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size5_0_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:4] in ; @@ -10944,6 +15254,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -10961,13 +15274,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_87 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_10 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_11 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10989,12 +15299,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0_6 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_2_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -11016,2047 +15326,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_0_6 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , - bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , - bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , - bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , - bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , - left_top_grid_pin_1_ , ccff_head , chany_bottom_out , chanx_left_out , - ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -mux_tree_tapbuf_size6_0_6 mux_bottom_track_1 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size6_10 mux_bottom_track_5 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size6_mem_0_6 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_10 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_0_4 mux_bottom_track_3 ( - .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_123 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size5_8 mux_bottom_track_7 ( - .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , - chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size5_mem_0_4 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_8 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_11 mux_bottom_track_9 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , - chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size3_0_6 mux_bottom_track_25 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( { ropt_net_130 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size3_mem_11 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0_6 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_0_5 mux_bottom_track_11 ( - .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_1_5 mux_bottom_track_13 ( - .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_2_5 mux_bottom_track_15 ( - .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_3_5 mux_bottom_track_17 ( - .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_4_4 mux_bottom_track_19 ( - .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_5_4 mux_bottom_track_21 ( - .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_6_3 mux_bottom_track_23 ( - .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_7_2 mux_bottom_track_27 ( - .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_8_2 mux_bottom_track_29 ( - .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_9_2 mux_bottom_track_31 ( - .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( { ropt_net_120 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_10_2 mux_bottom_track_33 ( - .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_11_1 mux_bottom_track_35 ( - .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_12_1 mux_bottom_track_37 ( - .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_13_1 mux_bottom_track_39 ( - .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_14_1 mux_left_track_1 ( - .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_16_1 mux_left_track_5 ( - .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_22 mux_left_track_9 ( - .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_15_1 mux_left_track_25 ( - .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_mem_0_5 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1_5 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2_5 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3_5 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6_3 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7_2 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_8_2 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_9_2 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_11_1 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_12_1 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13_1 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_16_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_22 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_15_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_128 } ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2401 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2402 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2403 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2404 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2405 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2406 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2407 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2408 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2409 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2410 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2411 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2412 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2413 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2414 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2415 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2416 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chany_bottom_in[2] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( - .A ( chany_bottom_in[16] ) , .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_120 ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( - .A ( chany_bottom_in[17] ) , .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( chany_bottom_in[8] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( ropt_net_123 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( - .A ( chany_bottom_in[15] ) , .X ( ropt_net_135 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_bottom_in[0] ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( - .A ( chany_bottom_in[12] ) , .X ( ropt_net_134 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( - .A ( chany_bottom_in[18] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_128 ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_129 ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chany_bottom_in[4] ) , - .X ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[9] ) , - .X ( BUF_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chany_bottom_in[10] ) , - .X ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_136 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chany_bottom_in[13] ) , - .X ( BUF_net_54 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[14] ) , - .X ( BUF_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_131 ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_140 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_46 ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_98 ( .A ( BUF_net_51 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_99 ( .A ( BUF_net_52 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_54 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_55 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x55200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , - .X ( net_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( net_net_80 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_2_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_3_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_2_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_1_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_0_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_2_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_1_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13078,346 +15353,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_2_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_1_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_104 ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13444,39 +15380,102 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module mux_tree_tapbuf_size6_11 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_1_3 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size6_2_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; @@ -13566,7 +15565,2699 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size6_0_5 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size6_1_2 mux_bottom_track_5 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6_2_1 mux_left_track_1 ( + .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6_11 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6_mem_0_5 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_1_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_2_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_11 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_0_4 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size5_1_1 mux_bottom_track_7 ( + .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , + chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size5_2_1 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size5_8 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size5_mem_0_4 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_1_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_2_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_8 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_9_3 mux_bottom_track_9 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_0_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_1_5 mux_bottom_track_13 ( + .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_2_5 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_3_5 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_4_5 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_5_3 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( { ropt_net_83 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_6_3 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_7_3 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_8_3 mux_bottom_track_29 ( + .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_10_3 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_11_3 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size2_12_3 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_13_3 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_14_3 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_81 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_15_2 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size2_16_2 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_17_1 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_18_1 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_19 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_20 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_21 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_22 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_23 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , + .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_mem_9_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_0_5 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1_5 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2_5 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3_5 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4_5 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5_3 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_6_3 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_7_3 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_8_3 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_10_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_11_3 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_12_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_13_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_14_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_15_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_16_2 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_17_1 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_18_1 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_23 mem_left_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( { ropt_net_84 } ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_0_6 mux_bottom_track_25 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size3_10 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size3_1_4 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size3_mem_0_6 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_10 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_1_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1403 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1404 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1405 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1406 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1407 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1408 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1409 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1410 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1411 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1412 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1413 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1414 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1415 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1416 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1417 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1418 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_92 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_93 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_94 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chanx_left_in[18] ) , + .X ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( ropt_net_95 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_60 ( .A ( BUF_net_46 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_667 ( .A ( ropt_net_81 ) , + .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( ropt_net_82 ) , + .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_83 ) , + .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_84 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_672 ( .A ( ropt_net_86 ) , + .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_87 ) , + .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_88 ) , + .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( ropt_net_96 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_97 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_98 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x87400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x87400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x55200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x82800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x87400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x55200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x138000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , + .X ( net_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_91 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -13610,7 +18301,97 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_4_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_0_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13632,12 +18413,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_3_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13659,7 +18440,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13686,7 +18467,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13713,7 +18494,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13740,12 +18521,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_8 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13767,12 +18548,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_5_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_5_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13794,12 +18575,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_4_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size7_4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; @@ -13849,7 +18630,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size7_3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; @@ -13869,9 +18650,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -13896,6 +18674,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -14049,7 +18830,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size7_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -14098,7 +18880,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_5_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size7_5_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; @@ -14173,7 +18955,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14203,7 +18985,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14370,7 +19152,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_0_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14395,7 +19177,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14425,7 +19207,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14455,12 +19237,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_0_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size8_0_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -14646,12 +19428,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_11 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_12 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14676,7 +19458,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14704,9 +19486,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -14741,10 +19520,15 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_61 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_61 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_11 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_12 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -14807,49 +19591,50 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , top_right_grid_pin_1_ , chany_bottom_in , - bottom_right_grid_pin_1_ , bottom_left_grid_pin_34_ , - bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , - bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , - bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , - bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , - left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , - left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , - left_top_grid_pin_49_ , ccff_head , chany_top_out , chany_bottom_out , +module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , + bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:0] top_right_grid_pin_1_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chany_bottom_out ; @@ -14870,6 +19655,23 @@ wire [0:3] mux_tree_tapbuf_size14_1_sram ; wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -14884,6 +19686,7 @@ wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; @@ -14941,25 +19744,25 @@ wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size10_11 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , +mux_tree_tapbuf_size10_12 mux_top_track_0 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size10_0_1 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size10_mem_11 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_166 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size10_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , @@ -14972,30 +19775,30 @@ mux_tree_tapbuf_size10_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size8_1_1 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size8_3 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size8_0_1 mux_bottom_track_9 ( + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size8_0_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size8_mem_1_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -15008,34 +19811,34 @@ mux_tree_tapbuf_size8_mem_3 mem_top_track_8 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_0_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size14_1 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , - top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , - top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , + top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size14_0_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_40_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size14_mem_1 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -15048,69 +19851,69 @@ mux_tree_tapbuf_size14_mem_0_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_5_1 mux_top_track_16 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , +mux_tree_tapbuf_size7_5_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size7_8 mux_top_track_24 ( - .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size7_10 mux_top_track_24 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size7_0_4 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_38_[0] , chanx_left_in[5] , chanx_left_in[12] , + .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_1_4 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , - left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size7_2_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , - left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_3_1 mux_left_track_5 ( + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size7_3_2 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , - left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_4_1 mux_left_track_7 ( + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( { ropt_net_158 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size7_4_2 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , - left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_mem_5_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size7_mem_5_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_8 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , @@ -15134,121 +19937,121 @@ mux_tree_tapbuf_size7_mem_2_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_3_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_3_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_4_1 mem_left_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_4_2 mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_9 mux_top_track_32 ( - .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size6_10 mux_top_track_32 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size6_0_5 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_39_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size6_0_4 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size6_1_3 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[0] , chanx_left_in[7] , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size6_1_1 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size6_mem_9 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size6_mem_10 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0_5 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem_0_4 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_1_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem_1_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9_1 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[2] , chanx_left_in[9] , +mux_tree_tapbuf_size9_2 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( { ropt_net_130 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size9_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size9_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_8 mux_left_track_9 ( +mux_tree_tapbuf_size4_9 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , - left_top_grid_pin_42_[0] } ) , + left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size4_0_3 mux_left_track_11 ( + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size4_0_5 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , - left_top_grid_pin_43_[0] } ) , + left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_129 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size4_1_2 mux_left_track_13 ( + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size4_1_4 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , - left_top_grid_pin_44_[0] } ) , + left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size4_2_2 mux_left_track_15 ( + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size4_2_3 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , - left_top_grid_pin_45_[0] } ) , + left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size4_mem_8 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size4_mem_9 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_0_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_0_5 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1_2 mem_left_track_13 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_1_4 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_2_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_2_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , @@ -15256,52 +20059,52 @@ mux_tree_tapbuf_size4_mem_2_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size3_0_5 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , - left_top_grid_pin_46_[0] } ) , + left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size3_1_4 mux_left_track_19 ( + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size3_1_3 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , - left_top_grid_pin_47_[0] } ) , + left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size3_2_4 mux_left_track_21 ( + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size3_2_3 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , - left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3_3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , - left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size3_10 mux_left_track_25 ( + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size3_9 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , - left_top_grid_pin_42_[0] } ) , + left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( { ropt_net_155 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3_mem_0_5 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_1_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2_4 mem_left_track_21 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_2_3 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , @@ -15313,202 +20116,240 @@ mux_tree_tapbuf_size3_mem_3_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_10 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( { ropt_net_127 } ) , +mux_tree_tapbuf_size3_mem_9 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2381 ( .VNB ( VSS ) , +mux_tree_tapbuf_size2_0_4 mux_left_track_29 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( { ropt_net_156 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_1_4 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_2_4 mux_left_track_33 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_3_4 mux_left_track_35 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_4_4 mux_left_track_37 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_21 mux_left_track_39 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size2_mem_0_4 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1_4 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2_4 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3_4 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_21 mem_left_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( { ropt_net_154 } ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1383 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2382 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1384 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2383 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1385 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2384 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1386 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2385 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1387 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2386 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1388 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2387 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1389 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2388 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1390 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2389 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1391 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2390 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1392 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2391 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1393 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2392 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1394 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2393 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1395 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2394 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1396 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2395 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1397 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2396 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1398 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2397 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1399 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2398 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1400 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2399 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1401 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_155 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_156 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_126 ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( ropt_net_127 ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[1] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_129 ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_157 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( - .A ( chany_bottom_in[13] ) , .X ( chany_top_out[14] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_136 ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( left_top_grid_pin_43_[0] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_158 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_140 ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_160 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_141 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_142 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_143 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_144 ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_162 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_145 ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_146 ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_151 ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_152 ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_153 ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_164 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_167 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_168 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_170 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_154 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_155 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_156 ) , .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( + .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_158 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_161 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_162 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chany_top_in[16] ) , + .X ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( BUF_net_89 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_173 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_165 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_168 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_169 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_170 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_179 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_180 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_80 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_89 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( @@ -15521,14 +20362,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( @@ -15557,34 +20398,44 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y81600 ( @@ -15597,43 +20448,27 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -15645,198 +20480,156 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x87400y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y272000 ( 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) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( @@ -15845,93 +20638,93 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x69000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x69000y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -15939,32 +20732,36 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x87400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y408000 ( @@ -15975,231 +20772,213 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x138000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x128800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x92000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x138000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x78200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x96600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -16211,34 +20990,20 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y625600 ( @@ -16247,153 +21012,135 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -16409,78 +21156,66 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y870400 ( @@ -16489,22 +21224,40 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( @@ -16517,14 +21270,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y952000 ( @@ -16552,7 +21305,258 @@ sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y952000 ( endmodule -module mux_tree_tapbuf_size2_mem_7_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16571,11 +21575,81 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , - .X ( net_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_49 ( .A ( net_net_49 ) , - .X ( net_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( net_net_48 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__35 ( .A ( mem_out[1] ) , + .X ( net_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( net_net_71 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16599,3599 +21673,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_10_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_9_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_8_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_7_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_6_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_5_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_4_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_3_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_2_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_1_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_10_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_8_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_0_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_1_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_2_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_65 ( .A ( BUF_net_41 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_1_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_2_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_1_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_0_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_2_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , top_right_grid_pin_1_ , chanx_left_in , - left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , - left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , - left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , - ccff_head , chany_top_out , chanx_left_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -mux_tree_tapbuf_size6_2_2 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size6_8 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size6_0_4 mux_left_track_1 ( - .in ( { chany_top_in[0] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size6_1_2 mux_left_track_5 ( - .in ( { chany_top_in[18] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size6_mem_2_2 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_8 mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_1_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_2_2 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_7 mux_top_track_6 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size5_0_3 mux_left_track_3 ( - .in ( { chany_top_in[19] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_1_2 mux_left_track_7 ( - .in ( { chany_top_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_mem_2_2 mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_7 mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_0_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_1_2 mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_9 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( { ropt_net_89 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size3_2_3 mux_top_track_24 ( - .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size3_1_3 mux_left_track_9 ( - .in ( { chany_top_in[16] , left_top_grid_pin_42_[0] , - left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_0_4 mux_left_track_25 ( - .in ( { chany_top_in[8] , left_top_grid_pin_42_[0] , - left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size3_mem_9 mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2_3 mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1_3 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_8_1 mux_top_track_10 ( - .in ( { top_left_grid_pin_35_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size2_9_1 mux_top_track_12 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size2_10_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_11 mux_top_track_16 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_12 mux_top_track_18 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_20 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_22 ( - .in ( { top_left_grid_pin_41_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_15 mux_top_track_26 ( - .in ( { top_left_grid_pin_35_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_16 mux_top_track_28 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_17 mux_top_track_30 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_32 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_19 mux_top_track_34 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_20 mux_top_track_36 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_21 mux_top_track_38 ( - .in ( { top_left_grid_pin_41_[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_0_4 mux_left_track_11 ( - .in ( { chany_top_in[15] , left_top_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_1_4 mux_left_track_13 ( - .in ( { chany_top_in[14] , left_top_grid_pin_44_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_2_4 mux_left_track_15 ( - .in ( { chany_top_in[13] , left_top_grid_pin_45_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_3_4 mux_left_track_17 ( - .in ( { chany_top_in[12] , left_top_grid_pin_46_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_4_3 mux_left_track_19 ( - .in ( { chany_top_in[11] , left_top_grid_pin_47_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_5_3 mux_left_track_21 ( - .in ( { chany_top_in[10] , left_top_grid_pin_48_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_6_2 mux_left_track_23 ( - .in ( { chany_top_in[9] , left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_7_1 mux_left_track_27 ( - .in ( { chany_top_in[7] , left_top_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_mem_8_1 mem_top_track_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_9_1 mem_top_track_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_top_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_18 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_20 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_22 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_top_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_top_track_28 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_top_track_30 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_top_track_34 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_top_track_36 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_21 mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0_4 mem_left_track_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1_4 mem_left_track_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2_4 mem_left_track_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5_3 mem_left_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6_2 mem_left_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7_1 mem_left_track_27 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( { ropt_net_88 } ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2364 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2365 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2366 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2367 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2368 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2369 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2370 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2371 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2372 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2373 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2374 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2375 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2376 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2377 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2378 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2379 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_676 ( .A ( ropt_net_91 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_678 ( .A ( ropt_net_93 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_679 ( .A ( ropt_net_94 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_95 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_84 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_63 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_85 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_67 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_672 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_88 ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_89 ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_90 ) , - .X ( ropt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x87400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x96600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x64400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20215,12 +21697,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_4_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20239,7 +21721,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20263,7 +21745,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20287,7 +21769,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20311,7 +21793,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20335,12 +21817,228 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_mem_11_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -20367,6 +22065,110 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_9_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size2_5_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -20394,7 +22196,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4_2 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_4_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -20486,15 +22288,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20513,134 +22319,50 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( +endmodule + + +module mux_tree_tapbuf_size2_11_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__52 ( .A ( mem_out[2] ) , - .X ( net_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_95 ( .A ( net_net_95 ) , - .X ( net_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_130 ( .A ( net_net_94 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -20648,35 +22370,26 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_1_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -20684,35 +22397,26 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_0_2 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -20720,230 +22424,26 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_2_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_69 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_136 ( .A ( BUF_net_69 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_2_2 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_16_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -20951,51 +22451,26 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_68 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_68 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_1_3 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_15_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -21003,45 +22478,26 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_0_3 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_14_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -21049,45 +22505,76 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_5_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_12_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21106,127 +22593,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__44 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__43 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__42 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__41 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__39 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21250,12 +22617,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_5_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size3_0_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -21287,6 +22654,2324 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule +module mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , + chany_top_out , chanx_left_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size6_0_3 mux_top_track_0 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_109 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size6_9 mux_top_track_4 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size6_mem_0_3 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_9 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_0_3 mux_top_track_2 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size5_7 mux_top_track_6 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size5_mem_0_3 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_7 mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_8 mux_top_track_8 ( + .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size3_0_4 mux_top_track_24 ( + .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size3_mem_8 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0_4 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_12_2 mux_top_track_10 ( + .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_13_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_14_2 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_15_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_16_1 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_17 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_18 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_20 mux_top_track_26 ( + .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_11_2 mux_left_track_9 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_0_3 mux_left_track_11 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_1_3 mux_left_track_13 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_2_3 mux_left_track_15 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_3_3 mux_left_track_17 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_4_3 mux_left_track_19 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_5_2 mux_left_track_25 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_6_2 mux_left_track_27 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( { ropt_net_108 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_7_2 mux_left_track_29 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( { ropt_net_103 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_8_2 mux_left_track_31 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_9_2 mux_left_track_33 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size2_10_2 mux_left_track_35 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size2_mem_12_2 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_13_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_14_2 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_15_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_16_1 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_top_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_11_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_0_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1_3 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_6_2 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_7_2 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_8_2 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_9_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_10_2 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( { ropt_net_105 } ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_0_4 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_1_3 mux_left_track_3 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_2_2 mux_left_track_5 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size4_8 mux_left_track_7 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_mem_0_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_1_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_2_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_8 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1366 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1367 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1368 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1369 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1370 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1371 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1372 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1373 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1374 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1375 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1376 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1377 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1378 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1379 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1380 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1381 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_118 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_119 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_103 ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_left_in[4] ) , + .X ( BUF_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_left_in[5] ) , + .X ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_66 ( .A ( BUF_net_56 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_84 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( BUF_net_57 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_86 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_123 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_125 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x59800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x78200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x96600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x92000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x87400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( net_net_89 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size3_4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; @@ -21447,10 +25132,92 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size4_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -21459,130 +25226,97 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module mux_tree_tapbuf_size4_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21608,229 +25342,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__33 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__32 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__31 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_2_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_1_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_3_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; @@ -21871,8 +25387,225 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; +module mux_tree_tapbuf_size7_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -21885,11 +25618,891 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_4_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_6_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , @@ -21901,20 +26514,34 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -21925,6 +26552,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; @@ -21938,159 +26568,34 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__30 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__29 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__28 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__27 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__26 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_1_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -22102,11 +26607,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , @@ -22114,28 +26622,69 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_0_3 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size10_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_11 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -22147,11 +26696,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , @@ -22166,192 +26719,100 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_3_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_2_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - chany_bottom_in , bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , - bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , - bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , - bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , - left_top_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , - chanx_left_out , ccff_tail , VDD , VSS ) ; + right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; input VDD ; input VSS ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -22364,62 +26825,26 @@ wire [0:1] mux_tree_tapbuf_size3_4_sram ; wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_5_sram ; -wire [0:2] mux_tree_tapbuf_size5_5_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_6_sram ; -wire [0:2] mux_tree_tapbuf_size5_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; @@ -22428,645 +26853,655 @@ wire [0:2] mux_tree_tapbuf_size7_2_sram ; wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size6_2_1 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[5] , +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_11 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_3_1 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[3] , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size10_mem_11 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size9 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size9_0 mux_left_track_1 ( + .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , + chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size9_1 mux_left_track_3 ( + .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[7] , chany_bottom_in[14] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size14 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_7 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[2] , + .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_2 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_0_3 mux_left_track_5 ( - .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size6_1_1 mux_left_track_9 ( + .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size8_0_1 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size6_mem_2_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_3_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size8_mem_0_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_7 mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_1_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_5 mux_right_track_2 ( - .in ( { chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_172 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size5_4 mux_right_track_16 ( - .in ( { chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , +mux_tree_tapbuf_size7_6_1 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , + chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size5_6 mux_right_track_24 ( - .in ( { chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size5_0_2 mux_left_track_1 ( - .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , - chany_bottom_in[13] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size5_3_1 mux_left_track_3 ( - .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[7] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size5_1_1 mux_left_track_17 ( - .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_5_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size5_2_1 mux_left_track_25 ( - .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , - chany_bottom_in[11] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_6_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size5_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_6 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_0_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_3_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_1_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_2_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_8 mux_right_track_32 ( - .in ( { chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size3_0_3 mux_bottom_track_13 ( - .in ( { chanx_right_in[10] , bottom_left_grid_pin_36_[0] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size3_1_2 mux_bottom_track_15 ( - .in ( { chanx_right_in[12] , bottom_left_grid_pin_37_[0] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size3_2_2 mux_bottom_track_17 ( - .in ( { chanx_right_in[13] , bottom_left_grid_pin_38_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size3_3_2 mux_bottom_track_19 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_39_[0] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_4_1 mux_bottom_track_21 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_40_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_5_1 mux_bottom_track_23 ( - .in ( { chanx_right_in[17] , bottom_left_grid_pin_41_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_mem_8 mem_right_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0_3 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_3_2 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_4_1 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_5_1 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_0_3 mux_bottom_track_1 ( - .in ( { chanx_right_in[2] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( { ropt_net_175 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size7_1_3 mux_bottom_track_3 ( - .in ( { chanx_right_in[4] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_9 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , + chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_2_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[5] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_0_3 mux_bottom_track_1 ( + .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( { ropt_net_207 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_7 mux_bottom_track_7 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size7_1_3 mux_bottom_track_3 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_175 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_3_1 mux_bottom_track_7 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_mem_0_3 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_4_1 mux_left_track_17 ( + .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_5_1 mux_left_track_25 ( + .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , + chany_bottom_in[11] , chany_bottom_in[18] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( { ropt_net_165 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size7_mem_6_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1_3 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_9 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , +mux_tree_tapbuf_size7_mem_0_3 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_7 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_1_3 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_2_1 mux_bottom_track_9 ( - .in ( { chanx_right_in[8] , bottom_left_grid_pin_34_[0] , +mux_tree_tapbuf_size7_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_3_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_4_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_5_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_6 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size5_mem_6 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_7 mux_bottom_track_9 ( + .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size4_0_2 mux_bottom_track_11 ( - .in ( { chanx_right_in[9] , bottom_left_grid_pin_35_[0] , + .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size4_0_3 mux_bottom_track_11 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_176 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size4_1_1 mux_bottom_track_25 ( + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size4_1_2 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , - bottom_left_grid_pin_34_[0] , chanx_left_in[18] } ) , + bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size4_7 mux_left_track_33 ( - .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , - chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size4_mem_2_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size4_mem_7 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_0_2 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_0_3 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , +mux_tree_tapbuf_size4_mem_1_2 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_7 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size3_0_3 mux_bottom_track_13 ( + .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_1_2 mux_bottom_track_15 ( + .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_2_2 mux_bottom_track_17 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_3_2 mux_bottom_track_19 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_4_1 mux_bottom_track_21 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size3_7 mux_bottom_track_23 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( { ropt_net_176 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size3_mem_0_3 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_0_3 mux_bottom_track_27 ( - .in ( { chanx_right_in[15] , bottom_left_grid_pin_35_[0] } ) , +mux_tree_tapbuf_size3_mem_1_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_2_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_3_2 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_4_1 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_7 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_19 mux_bottom_track_27 ( + .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_169 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size2_1_3 mux_bottom_track_29 ( - .in ( { chanx_right_in[11] , bottom_left_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size2_2_3 mux_bottom_track_31 ( - .in ( { chanx_right_in[7] , bottom_left_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_3_3 mux_bottom_track_33 ( - .in ( { chanx_right_in[3] , bottom_left_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_4_2 mux_bottom_track_35 ( - .in ( { chanx_right_in[1] , bottom_left_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_5_2 mux_bottom_track_37 ( - .in ( { chanx_right_in[0] , bottom_left_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size2_14 mux_bottom_track_39 ( - .in ( { bottom_left_grid_pin_41_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size2_mem_0_3 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1_3 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size6_8 mux_left_track_33 ( + .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , + chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size6_mem_8 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_181 } ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2_3 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4_2 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5_2 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2334 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1336 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2335 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1337 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2336 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1338 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2337 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1339 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2338 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1340 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2339 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1341 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2340 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1342 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2341 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1343 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2342 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1344 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2343 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1345 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2344 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1346 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2345 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1347 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2346 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1348 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2347 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1349 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2348 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1350 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2349 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1351 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2350 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1352 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2351 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1353 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2352 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1354 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2353 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1355 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2354 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1356 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2355 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1357 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2356 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1358 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2357 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1359 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2358 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1360 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2359 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1361 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2360 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1362 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2361 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1363 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2362 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1364 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_169 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_172 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_left_in[5] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_173 ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_175 ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_176 ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_197 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_198 ) , +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_199 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( chanx_left_in[4] ) , - .X ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_185 ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_187 ) , +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_165 ) , .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , - .X ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_188 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[10] ) , .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_190 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_191 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_192 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_204 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( BUF_net_83 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_115 ( .A ( aps_rename_2_ ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_116 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_205 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_206 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_166 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[12] ) , .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_92 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_170 ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_172 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_175 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_176 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_200 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[14] ) , + .X ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[17] ) , + .X ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[9] ) , + .X ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_181 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_182 ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_183 ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_184 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_186 ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_187 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_188 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_189 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_190 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_205 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_206 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_207 ) , .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_208 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_212 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( BUF_net_77 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_79 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( @@ -23079,14 +27514,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( @@ -23111,104 +27546,58 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y108800 ( @@ -23217,34 +27606,30 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( @@ -23259,27 +27644,21 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23287,11 +27666,11 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23303,29 +27682,37 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x55200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23335,74 +27722,66 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y244800 ( @@ -23411,31 +27790,25 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23445,29 +27818,27 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23477,62 +27848,70 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x133400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y353600 ( @@ -23541,63 +27920,65 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23607,129 +27988,135 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23739,35 +28126,23 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23777,100 +28152,124 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x96600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y625600 ( @@ -23879,15 +28278,39 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23897,33 +28320,29 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23933,116 +28352,80 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x87400y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( @@ -24065,14 +28448,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( @@ -24097,7 +28480,7 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -24130,7 +28513,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_28__79 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__79 ( .A ( mem_out[2] ) , + .X ( net_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24189,7 +28574,7 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__77 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_8 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -24366,7 +28751,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24500,7 +28885,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__73 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24745,7 +29130,7 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__65 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -25468,8 +29853,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -26701,6 +31085,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -26713,6 +31098,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -26750,10 +31138,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26829,58 +31217,60 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , - right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , - right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , - right_top_grid_pin_49_ , chany_bottom_in , bottom_left_grid_pin_34_ , - bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , - bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , - bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , - bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , - left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , - left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , - left_top_grid_pin_49_ , ccff_head , chany_top_out , chanx_right_out , +module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , + right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , + bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; @@ -26977,85 +31367,85 @@ supply1 VDD ; supply0 VSS ; mux_tree_tapbuf_size12_6 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size12 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , - right_top_grid_pin_42_[0] , right_top_grid_pin_44_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_48_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , - right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , - bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , - chany_bottom_in[12] , chany_bottom_in[19] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] } ) , + chany_bottom_in[12] , chany_bottom_in[19] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[4] , chany_bottom_in[13] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[4] , chany_bottom_in[13] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -27105,53 +31495,53 @@ mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size16 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , - top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , - top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , + top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , - right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , - chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_40_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[5] , chanx_left_in[7] , + chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[5] , chany_bottom_in[14] , left_top_grid_pin_42_[0] , - left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[5] , chany_bottom_in[14] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -27176,115 +31566,115 @@ mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_1 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , +mux_tree_tapbuf_size10 mux_top_track_8 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_9 mux_top_track_16 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_10 mux_top_track_24 ( - .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , - right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , - right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , - chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_38_[0] , chanx_left_in[6] , chanx_left_in[11] , + chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_39_[0] , chanx_left_in[8] , chanx_left_in[15] , + chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[9] , chanx_left_in[18] , + chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , - chany_bottom_in[6] , chany_bottom_in[16] , left_top_grid_pin_42_[0] , - left_top_grid_pin_46_[0] } ) , + chany_bottom_in[6] , chany_bottom_in[16] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , - chany_bottom_in[8] , chany_bottom_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_47_[0] } ) , + chany_bottom_in[8] , chany_bottom_in[17] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , - chany_bottom_in[11] , chany_bottom_in[18] , left_top_grid_pin_44_[0] , - left_top_grid_pin_48_[0] } ) , + chany_bottom_in[11] , chany_bottom_in[18] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , @@ -27356,39 +31746,39 @@ mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_6 mux_top_track_32 ( - .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size7_8 mux_top_track_32 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size7_2_1 mux_right_track_32 ( - .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_45_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[10] , - chany_bottom_in[19] , chanx_left_in[10] } ) , + .in ( { chany_top_in[10] , chany_top_in[15] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size7_0_2 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size7_1_2 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , - chany_bottom_in[10] , chany_bottom_in[15] , left_top_grid_pin_45_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[10] , chany_bottom_in[15] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -mux_tree_tapbuf_size7_mem_6 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size7_mem_8 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , @@ -27407,234 +31797,219 @@ mux_tree_tapbuf_size7_mem_0_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size7_mem_1_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( { ropt_net_130 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2301 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1303 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2302 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1304 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2303 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1305 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2304 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1306 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2305 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1307 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2306 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1308 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2307 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1309 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2308 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1310 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2309 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1311 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2310 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1312 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2311 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1313 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2312 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1314 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2313 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1315 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2314 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1316 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2315 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1317 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2316 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1318 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2317 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1319 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2318 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1320 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2319 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1321 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2320 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1322 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2321 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1323 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2322 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1324 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2323 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1325 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2324 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1326 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2325 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1327 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2326 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1328 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2327 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1329 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2328 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1330 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2329 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1331 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2330 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1332 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2331 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1333 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2332 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1334 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__2 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chany_top_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_top_in[16] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_148 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[6] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_130 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_132 ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_152 ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_153 ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_155 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_42__41 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_158 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_41__40 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_159 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_44__43 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_87 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[6] ) , - .X ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_100 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_105 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_106 ( .A ( BUF_net_90 ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_115 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_121 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_123 ( .A ( aps_rename_3_ ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_112 ( .A ( aps_rename_1_ ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( @@ -27661,11 +32036,15 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -27675,8 +32054,8 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y54400 ( @@ -27685,19 +32064,21 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -27707,11 +32088,11 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -27727,65 +32108,55 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x82800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x78200y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x901600y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -27795,83 +32166,73 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x878600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -27881,43 +32242,71 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -27927,16 +32316,22 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y408000 ( @@ -27945,37 +32340,47 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -27985,50 +32390,42 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y516800 ( @@ -28037,29 +32434,29 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -28069,11 +32466,13 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -28083,14 +32482,14 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y625600 ( @@ -28099,67 +32498,67 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x59800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x69000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x87400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -28169,11 +32568,21 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -28195,30 +32604,24 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y788800 ( @@ -28229,52 +32632,64 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y924800 ( @@ -28291,14 +32706,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y952000 ( @@ -28326,13 +32741,13 @@ sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y952000 ( endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem_0_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; input VDD ; input VSS ; @@ -28348,18 +32763,45 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( net_net_105 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; +module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -28370,16 +32812,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , @@ -28387,34 +32824,57 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28440,12 +32900,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__58 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_6 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_7 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -28467,7 +32927,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28487,13 +32947,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -28510,14 +32966,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -28531,7 +32987,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; @@ -28551,79 +33006,143 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:13] in ; +module mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; @@ -28633,9 +33152,6 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -28649,7 +33165,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , @@ -28663,298 +33179,36 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -28973,108 +33227,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -29101,138 +33259,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_2_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_1_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -29252,7 +33278,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29276,7 +33302,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29300,7 +33326,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29324,7 +33350,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29348,7 +33374,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29372,7 +33398,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29396,42 +33422,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -29509,6 +33504,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -29519,9 +33517,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -29653,7 +33648,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_0_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -29675,7 +33670,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29702,12 +33697,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_0_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size4_0_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; @@ -29778,33 +33773,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size7_mem_0_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -29827,34 +33795,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29881,12 +33822,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_1_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -29908,34 +33849,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29962,11 +33876,245 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size7_1_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:6] in ; @@ -30017,8 +34165,56 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -30165,58 +34361,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_61 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_104 ( .A ( BUF_net_61 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -30265,7 +34410,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -30314,36 +34459,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -30369,12 +34484,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -30399,7 +34514,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30429,64 +34544,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -30540,7 +34602,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -30646,80 +34708,63 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , - right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , - right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , - right_top_grid_pin_49_ , right_bottom_grid_pin_1_ , chanx_left_in , - left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , - left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , - left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , - ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , - VDD , VSS ) ; +module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , + left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , + left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , + left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; input VDD ; input VSS ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -30734,8 +34779,6 @@ wire [0:1] mux_tree_tapbuf_size3_5_sram ; wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_6_sram ; wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_7_sram ; -wire [0:1] mux_tree_tapbuf_size3_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -30743,18 +34786,23 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; @@ -30769,6 +34817,10 @@ wire [0:2] mux_tree_tapbuf_size7_5_sram ; wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -30776,148 +34828,144 @@ wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; supply1 VDD ; supply0 VSS ; +assign SC_IN_TOP = SC_IN_BOT ; + mux_tree_tapbuf_size8 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size8_2 mux_right_track_8 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , - right_bottom_grid_pin_1_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , + .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size8_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_3 ( - .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[13] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size8_1 mux_left_track_9 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - chanx_right_in[6] , chanx_right_in[16] , left_top_grid_pin_42_[0] , - left_top_grid_pin_46_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , +mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_4 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size7_6 mux_top_track_2 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size7_5 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_7 mux_top_track_4 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .p0 ( optlc_net_130 ) ) ; mux_tree_tapbuf_size7_2 mux_top_track_6 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( { ropt_net_169 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_2 mux_right_track_16 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , - chanx_left_in[8] , chanx_left_in[17] } ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_3 mux_right_track_0 ( + .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_3 mux_right_track_24 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , - chanx_left_in[9] , chanx_left_in[18] } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size7_5 mux_right_track_8 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , + chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_0_1 mux_left_track_17 ( + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_47_[0] } ) , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , + chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_1_1 mux_left_track_25 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - chanx_right_in[9] , chanx_right_in[18] , left_top_grid_pin_44_[0] , - left_top_grid_pin_48_[0] } ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_1_1 mux_left_track_3 ( + .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[13] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_2 mux_left_track_9 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_0_1 mux_left_track_17 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , @@ -30929,111 +34977,117 @@ mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_right_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , +mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_0_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , +mux_tree_tapbuf_size7_mem_1_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_0_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; mux_tree_tapbuf_size4_6 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , chanx_right_in[8] , + .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_0_1 mux_top_track_10 ( - .in ( { top_left_grid_pin_35_[0] , chanx_right_in[9] , + .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size4_0_2 mux_top_track_10 ( + .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4_mem_6 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_0_1 mem_top_track_10 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_0_2 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size3_0_2 mux_top_track_12 ( - .in ( { top_left_grid_pin_36_[0] , chanx_right_in[10] , + .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_1_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_37_[0] , chanx_right_in[12] , + .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_2_1 mux_top_track_16 ( - .in ( { top_left_grid_pin_38_[0] , chanx_right_in[13] , + .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_3_1 mux_top_track_18 ( - .in ( { top_left_grid_pin_39_[0] , chanx_right_in[14] , + .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_4 mux_top_track_20 ( - .in ( { top_left_grid_pin_40_[0] , chanx_right_in[16] , + .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( { ropt_net_134 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_5 mux_top_track_22 ( - .in ( { top_left_grid_pin_41_[0] , chanx_right_in[17] , + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_6 mux_top_track_24 ( - .in ( { top_left_grid_pin_34_[0] , chanx_right_in[18] , + .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3_7 mux_top_track_38 ( - .in ( { top_left_grid_pin_41_[0] , chanx_right_in[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size3_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_7_sram_inv ) , - .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size3_mem_0_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -31076,379 +35130,311 @@ mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_7 mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_0_2 mux_top_track_28 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[19] } ) , +mux_tree_tapbuf_size2_18 mux_top_track_38 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_1_2 mux_top_track_30 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_2_2 mux_top_track_32 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( { ropt_net_130 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_3_2 mux_top_track_34 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_36 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_mem_0_2 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size2_mem_18 mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1_2 mem_top_track_30 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2_2 mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3_2 mem_top_track_34 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_36 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9_0 mux_right_track_0 ( - .in ( { chany_top_in[6] , chany_top_in[13] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size9 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size14 mux_right_track_4 ( +mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , - right_bottom_grid_pin_1_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , + chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - chanx_right_in[5] , chanx_right_in[14] , left_top_grid_pin_42_[0] , - left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , - left_top_grid_pin_49_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_6 mux_right_track_32 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - right_top_grid_pin_45_[0] , right_top_grid_pin_49_[0] , - chanx_left_in[10] } ) , +mux_tree_tapbuf_size6_7 mux_right_track_24 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_129 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size6_0_2 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - chanx_right_in[10] , left_top_grid_pin_45_[0] , - left_top_grid_pin_49_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size6_0_2 mux_left_track_25 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_mem_6 mem_right_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size6_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_131 } ) , +mux_tree_tapbuf_size6_mem_0_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - chanx_right_in[2] , chanx_right_in[12] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5_5 mux_right_track_32 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size5_0_2 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size5_mem_5 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2271 ( .VNB ( VSS ) , +mux_tree_tapbuf_size5_mem_0_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( { ropt_net_139 } ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1273 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2272 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1274 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2273 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1275 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2274 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1276 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2275 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1277 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2276 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1278 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2277 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1279 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2278 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1280 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2279 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1281 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2280 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1282 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2281 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1283 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2282 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1284 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2283 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1285 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2284 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1286 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2285 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1287 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2286 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1288 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2287 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1289 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2288 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1290 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2289 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1291 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2290 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1292 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2291 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1293 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2292 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1294 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2293 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1295 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2294 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1296 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2295 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1297 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2296 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1298 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2297 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1299 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2298 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1300 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2299 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1301 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_35_[0] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[16] ) , +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_129 ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_163 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_156 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_157 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_134 ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_136 ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_158 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_159 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_160 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_161 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_162 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_145 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_146 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_164 ) , .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_147 ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_148 ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_149 ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_150 ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_168 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_169 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_170 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_171 ) , .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_172 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , + .X ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( + .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_173 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_153 ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_176 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_154 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_155 ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_107 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_157 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_114 ( .A ( BUF_net_70 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( @@ -31459,14 +35445,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( @@ -31491,7 +35477,7 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -31499,33 +35485,45 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x837200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -31535,68 +35533,76 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y81600 ( @@ -31605,77 +35611,71 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x124200y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -31685,72 +35685,62 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y190400 ( @@ -31759,77 +35749,105 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1012000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -31839,17 +35857,33 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -31859,54 +35893,80 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y353600 ( @@ -31915,51 +35975,81 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -31969,36 +36059,82 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y462400 ( @@ -32007,16 +36143,34 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y489600 ( @@ -32025,32 +36179,32 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x69000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y516800 ( @@ -32059,74 +36213,122 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x138000y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x82800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y598400 ( @@ -32145,31 +36347,39 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -32177,94 +36387,112 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y761600 ( @@ -32281,14 +36509,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( @@ -32316,7 +36544,7 @@ sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( endmodule -module mux_tree_tapbuf_size2_mem_1_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_1_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -32335,14 +36563,14 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__39 ( .A ( mem_out[1] ) , - .X ( net_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_71 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( net_net_59 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_3_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -32361,12 +36589,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_2_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_2_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -32385,12 +36613,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_0_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -32409,12 +36637,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_5_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -32433,12 +36661,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -32457,7 +36685,223 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32481,7 +36925,2604 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_43 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_75 ( .A ( BUF_net_43 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size6_0_1 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size6_6 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size6_mem_0_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_6 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_0_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size5_4 mux_right_track_6 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size5_mem_0_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_4 mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_4 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size3_0_1 mux_right_track_24 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0_1 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_4_2 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_5_1 mux_right_track_12 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_6_1 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_7_1 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_8_1 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_9_1 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size2_10_1 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_11_1 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_12_1 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_13_1 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_14_1 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_15 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_16 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_17 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_0_2 mux_bottom_track_1 ( + .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_3_2 mux_bottom_track_9 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_1_2 mux_bottom_track_25 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_mem_4_2 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_6_1 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_7_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_8_1 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_9_1 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_10_1 mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_11_1 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_12_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_13_1 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_14_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_17 mem_right_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_0_2 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1_2 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( { ropt_net_106 } ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1256 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1257 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1258 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1259 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1260 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1261 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1262 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1263 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1264 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1265 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1266 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1267 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1268 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1269 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1270 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1271 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( ropt_net_98 ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[7] ) , + .X ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_115 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_101 ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_102 ) , + .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , + .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , + .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_106 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_72 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_78 ( .A ( BUF_net_52 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_79 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_80 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , + .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32505,12 +39546,135 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_1_1 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -32591,6 +39755,33 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_1_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size2_0_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -32618,1673 +39809,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_5_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_6_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_4_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , - chany_bottom_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -mux_tree_tapbuf_size2_4_1 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_6_1 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_12 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_5_1 mux_right_track_24 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_0_1 mux_bottom_track_1 ( - .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_2_1 mux_bottom_track_5 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_3_1 mux_bottom_track_9 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_1_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_mem_4_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5_1 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_103 } ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2254 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2255 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2256 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2257 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2258 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2259 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2260 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2261 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2262 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2263 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2264 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2265 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2266 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2267 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2268 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2269 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_133 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_135 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_154 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_136 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_102 ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_103 ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[3] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_702 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_152 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chany_bottom_in[5] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_113 ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_114 ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_116 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_117 ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_118 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_120 ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_121 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_122 ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( .A ( chanx_right_in[2] ) , - .X ( BUF_net_42 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_140 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_123 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_143 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_124 ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_145 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_146 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_57 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_148 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_125 ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_126 ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_127 ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_128 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_129 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( BUF_net_42 ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_83 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_91 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_92 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -34303,39 +39828,14 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , + .X ( net_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( net_net_82 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -34354,33 +39854,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__57 ( .A ( mem_out[1] ) , - .X ( net_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( net_net_101 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34404,7 +39878,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34428,7 +39902,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34452,13 +39926,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -34489,7 +39962,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -34635,7 +40108,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34662,7 +40135,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34689,7 +40162,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34863,12 +40336,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -34890,12 +40363,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_1_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -34917,12 +40390,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_0_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -34944,7 +40417,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34971,12 +40444,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -34998,7 +40471,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35025,7 +40498,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35065,7 +40538,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size4_2_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -35100,7 +40574,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size4_1_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -35116,9 +40591,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -35132,10 +40604,14 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size4_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -35205,7 +40681,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -35297,12 +40773,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -35324,7 +40800,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35351,7 +40827,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35378,12 +40854,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -35405,7 +40881,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__38 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35450,8 +40926,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -35571,7 +41046,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -35633,7 +41108,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__37 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35660,12 +41135,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__36 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -35687,7 +41162,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__35 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35714,12 +41189,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__34 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -35741,7 +41216,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__33 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35768,7 +41243,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__32 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35795,7 +41270,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__31 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35888,8 +41363,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -35977,7 +41451,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -36110,23 +41584,24 @@ endmodule module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , - right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , - right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , - chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , - chanx_right_out , chany_bottom_out , ccff_tail , VDD , VSS ) ; + chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_left_grid_pin_1_ ; input [0:0] ccff_head ; @@ -36139,7 +41614,22 @@ input VSS ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -36229,50 +41719,50 @@ mux_tree_tapbuf_size6_4 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size6_1 mux_top_track_8 ( + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size6_3 mux_right_track_0 ( - .in ( { chany_top_in[2] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , chany_bottom_in[2] } ) , + .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size6_0_1 mux_bottom_track_1 ( + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -36285,7 +41775,7 @@ mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_top_track_8 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , @@ -36297,8 +41787,8 @@ mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , +mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) , .VDD ( VDD ) , @@ -36315,42 +41805,42 @@ mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_1 mux_top_track_2 ( +mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size5_0_1 mux_bottom_track_17 ( + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , @@ -36368,7 +41858,7 @@ mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_0_1 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , @@ -36386,56 +41876,56 @@ mux_tree_tapbuf_size4_5 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size4 mux_top_track_32 ( + .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size4_3 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size4_4 mux_right_track_8 ( - .in ( { chany_top_in[7] , chany_top_in[8] , right_top_grid_pin_42_[0] , + .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size4_0 mux_right_track_10 ( - .in ( { chany_top_in[9] , chany_top_in[11] , right_top_grid_pin_43_[0] , - chany_bottom_in[9] } ) , + .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size4_0_1 mux_right_track_10 ( + .in ( { chany_top_in[9] , chany_top_in[11] , + right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size4_1 mux_right_track_12 ( - .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_44_[0] , - chany_bottom_in[10] } ) , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size4_1_1 mux_right_track_12 ( + .in ( { chany_top_in[10] , chany_top_in[15] , + right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size4_2 mux_right_track_14 ( - .in ( { chany_top_in[12] , chany_top_in[19] , right_top_grid_pin_45_[0] , - chany_bottom_in[12] } ) , + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( { ropt_net_130 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size4_2_1 mux_right_track_14 ( + .in ( { chany_top_in[12] , chany_top_in[19] , + right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size4_3 mux_right_track_24 ( - .in ( { chany_top_in[18] , right_top_grid_pin_42_[0] , + .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_3 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , @@ -36447,19 +41937,19 @@ mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_0_1 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_1_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_2_1 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_5_sram ) , @@ -36472,29 +41962,29 @@ mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size7_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[4] } ) , + .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size7_1 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , chany_bottom_in[5] } ) , + .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size7 mux_right_track_6 ( - .in ( { chany_top_in[3] , chany_top_in[6] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[6] } ) , + .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -36514,39 +42004,39 @@ mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size3_1 mux_right_track_16 ( - .in ( { chany_top_in[13] , right_top_grid_pin_46_[0] , + .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size3_2 mux_right_track_18 ( - .in ( { chany_top_in[14] , right_top_grid_pin_47_[0] , + .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size3_3 mux_right_track_20 ( - .in ( { chany_top_in[16] , right_top_grid_pin_48_[0] , + .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3_4 mux_right_track_22 ( - .in ( { chany_top_in[17] , right_top_grid_pin_49_[0] , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size3 mux_right_track_22 ( + .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3_0_1 mux_bottom_track_33 ( + .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -36565,212 +42055,236 @@ mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_right_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_127 } ) , + .ccff_tail ( { ropt_net_131 } ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_11 mux_right_track_26 ( - .in ( { right_top_grid_pin_43_[0] , chany_bottom_in[15] } ) , +mux_tree_tapbuf_size2_0_1 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_1_1 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_2_1 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_3_1 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_4_1 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size2_mem_0_1 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2234 ( .VNB ( VSS ) , +mux_tree_tapbuf_size2_mem_1_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2_1 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4_1 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1236 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2235 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1237 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2236 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1238 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2237 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1239 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2238 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1240 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2239 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1241 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2240 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1242 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2241 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1243 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2242 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1244 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2243 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1245 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2244 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1246 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2245 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1247 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2246 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1248 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2247 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1249 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2248 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1250 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2249 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1251 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2250 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1252 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2251 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1253 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2252 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1254 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_164 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_127 ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_129 ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[2] ) , .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_140 ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_142 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_143 ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[17] ) , - .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_152 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_153 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_155 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_144 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chany_bottom_in[13] ) , +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_157 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( BUF_net_69 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[2] ) , .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_158 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_139 ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_161 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_162 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[4] ) , + .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_148 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[14] ) , + .X ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_141 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_149 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_150 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_151 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_152 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_153 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( BUF_net_69 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_75 ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( @@ -36787,14 +42301,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( @@ -36809,365 +42323,383 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x64400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y136000 ( + .VGND ( VSS ) , .VPWR ( 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y190400 ( +sky130_fd_sc_hd__fill_2 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) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 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( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y244800 ( +sky130_fd_sc_hd__fill_8 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( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x64400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -37175,223 +42707,229 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x593400y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x96600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -37401,139 +42939,151 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x69000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x105800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x69000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x87400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x96600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -37541,59 +43091,61 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -37601,280 +43153,262 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x841800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x96600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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\xofiller!sky130_fd_sc_hd__fill_1!x676200y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y761600 ( +sky130_fd_sc_hd__fill_8 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_1!x69000y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( @@ -37897,14 +43431,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y952000 ( @@ -37922,117 +43456,7 @@ sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y952000 ( endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -38054,12 +43478,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__37 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -38081,13 +43505,67 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__36 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -38099,173 +43577,30 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -38277,38 +43612,99 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -38327,177 +43723,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__33 ( .A ( mem_out[1] ) , - .X ( net_aps_33 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( net_aps_33 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , + .X ( net_aps_35 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38521,55 +43749,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38593,11 +43773,402 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_83 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -38806,55 +44377,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_81 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -38881,7 +44404,88 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -38908,24 +44512,20 @@ endmodule module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , - right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , - right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , - right_bottom_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - ccff_tail , VDD , VSS ) ; + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , + chany_top_out , chanx_right_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; @@ -38939,6 +44539,14 @@ wire [0:1] mux_tree_tapbuf_size2_10_sram ; wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; @@ -38959,6 +44567,10 @@ wire [0:1] mux_tree_tapbuf_size2_9_sram ; wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; @@ -38968,106 +44580,124 @@ wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size2_8 mux_top_track_0 ( +mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_10 mux_top_track_4 ( + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_102 ) ) ; mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_9 mux_top_track_24 ( + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( { ropt_net_107 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_10 ( - .in ( { chany_top_in[4] , right_top_grid_pin_43_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_11 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_12 ( - .in ( { chany_top_in[5] , right_top_grid_pin_44_[0] } ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_14 ( - .in ( { chany_top_in[6] , right_top_grid_pin_45_[0] } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_16 ( - .in ( { chany_top_in[7] , right_top_grid_pin_46_[0] } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_18 ( - .in ( { chany_top_in[8] , right_top_grid_pin_47_[0] } ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_20 ( - .in ( { chany_top_in[9] , right_top_grid_pin_48_[0] } ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_22 ( - .in ( { chany_top_in[10] , right_top_grid_pin_49_[0] } ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_26 ( - .in ( { chany_top_in[12] , right_top_grid_pin_43_[0] } ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_top_track_0 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_106 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , @@ -39079,300 +44709,274 @@ mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , +mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_105 } ) , +mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_0 mux_right_track_0 ( - .in ( { chany_top_in[19] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , +mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( { ropt_net_110 } ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size6 mux_right_track_4 ( - .in ( { chany_top_in[1] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( { ropt_net_118 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size5 mux_right_track_6 ( - .in ( { chany_top_in[2] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , +mux_tree_tapbuf_size4 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3 mux_right_track_8 ( - .in ( { chany_top_in[3] , right_top_grid_pin_42_[0] , - right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_0 mux_right_track_24 ( - .in ( { chany_top_in[11] , right_top_grid_pin_42_[0] , - right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2217 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1219 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2218 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1220 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2219 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1221 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2220 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1222 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2221 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1223 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2222 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1224 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2223 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1225 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2224 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1226 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2225 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1227 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2226 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1228 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2227 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1229 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2228 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1230 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2229 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1231 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2230 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1232 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2231 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1233 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2232 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1234 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_right_in[7] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_697 ( .A ( ropt_net_113 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_114 ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_44 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_47 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , - .X ( BUF_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_115 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_116 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[17] ) , .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_117 ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , - .X ( BUF_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_132 ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_69 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_76 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_77 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( aps_rename_2_ ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( BUF_net_49 ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_right_in[8] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_56 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_125 ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_127 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_110 ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , + .X ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[4] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_78 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( BUF_net_58 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( @@ -39381,14 +44985,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( @@ -39435,14 +45039,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y27200 ( @@ -39457,16 +45061,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( @@ -39509,13 +45113,13 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -39535,14 +45139,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y81600 ( @@ -39551,1857 +45155,13 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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-sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module direct_interc_4 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module GPIO_3 ( A , IE , OE , Y , in , out , mem_out , VDD , VSS ) ; -output A ; -output IE ; -output OE ; -output Y ; -input in ; -output out ; -input mem_out ; -input VDD ; -input VSS ; - -wire aps_rename_1_ ; -supply1 VDD ; -supply0 VSS ; - -assign A = in ; -assign out = Y ; - -sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( IE ) , .Y ( OE ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__1 ( .A ( mem_out ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_3 ( .A ( aps_rename_1_ ) , .X ( IE ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_3 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , - ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:0] GPIO_0_en ; -supply1 VDD ; -supply0 VSS ; - -GPIO_3 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , - .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , - .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , - .mem_out ( GPIO_0_en[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -GPIO_sky130_fd_sc_hd__dfxbp_1_mem_3 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , - ccff_head , io_inpad , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , - .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc_4 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_4 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module grid_io_left ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , - gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , right_width_0_height_0__pin_0_ , - ccff_head , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] right_width_0_height_0__pin_0_ ; -input [0:0] ccff_head ; -output [0:0] right_width_0_height_0__pin_1_upper ; -output [0:0] right_width_0_height_0__pin_1_lower ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_io__3 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , - .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , - .io_inpad ( right_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_9 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2201 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2202 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2203 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2204 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2205 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2206 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2207 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2208 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2209 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2210 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2211 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2212 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2213 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2214 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2215 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( - .A ( right_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) , +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_5 ( .A ( aps_rename_2_ ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_569 ( .A ( ropt_net_9 ) , - .X ( ropt_net_11 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_570 ( .A ( ropt_net_11 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x82800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x9200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x41400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x78200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x78200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x82800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -endmodule - - -module direct_interc_3 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , - .X ( net_net_8 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_13 ( .A ( net_net_8 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module GPIO_2 ( A , IE , OE , Y , in , out , mem_out , VDD , VSS ) ; -output A ; -output IE ; -output OE ; -output Y ; -input in ; -output out ; -input mem_out ; -input VDD ; -input VSS ; - -wire aps_rename_1_ ; -supply1 VDD ; -supply0 VSS ; - -assign A = in ; -assign out = Y ; - -sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__1 ( .A ( mem_out ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_5 ( .A ( aps_rename_1_ ) , .X ( IE ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , - ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:0] GPIO_0_en ; -supply1 VDD ; -supply0 VSS ; - -GPIO_2 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , - .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , - .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , - .mem_out ( GPIO_0_en[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -GPIO_sky130_fd_sc_hd__dfxbp_1_mem_2 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , - ccff_head , io_inpad , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , - .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc_3 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_3 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module grid_io_bottom ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , - gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , top_width_0_height_0__pin_0_ , - ccff_head , top_width_0_height_0__pin_1_upper , - top_width_0_height_0__pin_1_lower , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] top_width_0_height_0__pin_0_ ; -input [0:0] ccff_head ; -output [0:0] top_width_0_height_0__pin_1_upper ; -output [0:0] top_width_0_height_0__pin_1_lower ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_io__2 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( { ropt_net_16 } ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , - .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , - .io_inpad ( top_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_17 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2195 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2196 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2197 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2198 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2199 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( - .A ( top_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_6 ( .A ( aps_rename_2_ ) , - .X ( BUF_net_6 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_574 ( .A ( BUF_net_6 ) , - .X ( ropt_net_18 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_577 ( .A ( ropt_net_18 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_575 ( .A ( ropt_net_16 ) , - .X ( ropt_net_19 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_576 ( .A ( ropt_net_17 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( ropt_net_19 ) , - .X ( gfpga_pad_GPIO_IE[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -41409,25 +45169,29 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -41455,1048 +45219,10 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module direct_interc_2 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , - .X ( net_net_7 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_9 ( .A ( net_net_7 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module GPIO_1 ( A , IE , OE , Y , in , out , mem_out , VDD , VSS ) ; -output A ; -output IE ; -output OE ; -output Y ; -input in ; -output out ; -input mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign A = in ; -assign out = Y ; - -sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( IE ) , .Y ( OE ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_1__1 ( .A ( mem_out ) , .X ( IE ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_1 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , - ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:0] GPIO_0_en ; -supply1 VDD ; -supply0 VSS ; - -GPIO_1 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , - .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , - .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , - .mem_out ( GPIO_0_en[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -GPIO_sky130_fd_sc_hd__dfxbp_1_mem_1 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , - ccff_head , io_inpad , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , - .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc_2 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_2 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module grid_io_right ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , - gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , left_width_0_height_0__pin_0_ , - ccff_head , left_width_0_height_0__pin_1_upper , - left_width_0_height_0__pin_1_lower , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] left_width_0_height_0__pin_0_ ; -input [0:0] ccff_head ; -output [0:0] left_width_0_height_0__pin_1_upper ; -output [0:0] left_width_0_height_0__pin_1_lower ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_io__1 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , - .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , - .io_inpad ( left_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_11 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2179 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2180 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2181 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2182 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2183 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2184 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2185 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2186 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2187 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2188 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2189 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2190 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2191 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2192 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2193 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( - .A ( left_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_1_ ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_572 ( .A ( ropt_net_12 ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_8 ( .A ( aps_rename_1_ ) , - .X ( ropt_net_10 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_570 ( .A ( ropt_net_10 ) , - .X ( ropt_net_12 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_571 ( .A ( ropt_net_11 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x9200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x9200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x27600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x9200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x46000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x9200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -endmodule - - -module direct_interc_1 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , - .X ( net_net_7 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_13 ( .A ( net_net_7 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module GPIO ( A , IE , OE , Y , in , out , mem_out , VDD , VSS ) ; -output A ; -output IE ; -output OE ; -output Y ; -input in ; -output out ; -input mem_out ; -input VDD ; -input VSS ; - -wire aps_rename_1_ ; -supply1 VDD ; -supply0 VSS ; - -assign A = in ; -assign out = Y ; - -sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__1 ( .A ( mem_out ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_12 ( .A ( aps_rename_1_ ) , .X ( IE ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , - ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:0] GPIO_0_en ; -supply1 VDD ; -supply0 VSS ; - -GPIO GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , - .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , - .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , - .mem_out ( GPIO_0_en[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -GPIO_sky130_fd_sc_hd__dfxbp_1_mem GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , - ccff_head , io_inpad , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , - .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc_1 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module grid_io_top ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , - gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , bottom_width_0_height_0__pin_0_ , - ccff_head , bottom_width_0_height_0__pin_1_upper , - bottom_width_0_height_0__pin_1_lower , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] bottom_width_0_height_0__pin_0_ ; -input [0:0] ccff_head ; -output [0:0] bottom_width_0_height_0__pin_1_upper ; -output [0:0] bottom_width_0_height_0__pin_1_lower ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( { ropt_net_16 } ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , - .io_outpad ( bottom_width_0_height_0__pin_0_ ) , - .ccff_head ( ccff_head ) , - .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_15 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2173 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2174 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2175 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2176 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2177 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( - .A ( bottom_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_5 ( .A ( aps_rename_2_ ) , - .X ( BUF_net_5 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_574 ( .A ( BUF_net_5 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_576 ( .A ( ropt_net_16 ) , - .X ( gfpga_pad_GPIO_IE[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_575 ( .A ( ropt_net_15 ) , - .X ( ropt_net_17 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_577 ( .A ( ropt_net_17 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( @@ -42519,34 +45245,36 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( @@ -42561,35 +45289,27 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -42613,33 +45333,833 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42663,9 +46183,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__55 ( .A ( mem_out[1] ) , - .X ( net_aps_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( .A ( net_aps_55 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__56 ( .A ( mem_out[1] ) , + .X ( net_aps_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_aps_56 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42689,7 +46209,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42713,7 +46233,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42740,14 +46260,16 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module mux_tree_size2_22 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +module mux_tree_size2_22 ( in , sram , sram_inv , out , VDD , VSS , p_abuf0 , + p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +output p_abuf0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -42756,20 +46278,24 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( p_abuf0 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_21 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +module mux_tree_size2_21 ( in , sram , sram_inv , out , VDD , VSS , p_abuf0 , + p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +output p_abuf0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -42778,14 +46304,17 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( p_abuf0 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS , p_abuf2 ) ; + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS , p_abuf0 , + p_abuf1 , p_abuf2 ) ; input [0:0] Test_en ; input [0:0] clk ; input [0:0] ff_D ; @@ -42794,16 +46323,23 @@ output [0:0] ff_Q ; input [0:0] ff_clk ; input VDD ; input VSS ; +output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( p_abuf2 ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) , + .Q ( p_abuf2 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( net_net_100 ) , + .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_101 ( .A ( p_abuf2 ) , + .X ( net_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( .A ( p_abuf2 ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42822,10 +46358,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42848,7 +46383,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42939,7 +46474,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb7_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__51 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__52 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43212,25 +46747,29 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , - VSS , p_abuf1 , p_abuf2 , p2 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , + VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p1 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; +output p_abuf4 ; +input p1 ; input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -43258,7 +46797,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -43266,9 +46805,10 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logica .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_regout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf2 ( p_abuf2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( fabric_regout[0] ) , + .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) ) ; mux_tree_size2_21 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , @@ -43276,14 +46816,14 @@ mux_tree_size2_21 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf3 ) , .p1 ( p1 ) ) ; mux_tree_size2_22 mux_fabric_out_1 ( - .in ( { fabric_regout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf4 ) , .p1 ( p1 ) ) ; mux_tree_size2_23 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , @@ -43325,7 +46865,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -43340,30 +46880,31 @@ direct_interc direct_interc_9_ ( direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__256 ( .A ( fabric_regout[0] ) , - .X ( fabric_scout[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module logical_tile_clb_mode_default__fle ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p2 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , + p_abuf2 , p1 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; +output p_abuf2 ; +input p1 ; input p2 ; supply1 VDD ; @@ -43372,23 +46913,24 @@ supply0 VSS ; logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , + .p_abuf3 ( p_abuf3 ) , .p_abuf4 ( p_abuf4 ) , .p1 ( p1 ) , .p2 ( p2 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; + .out ( { p_abuf3 } ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; + .out ( { p_abuf4 } ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf0 } ) ) ; + .out ( { p_abuf1 } ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf1 } ) ) ; + .out ( { p_abuf2 } ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -43406,7 +46948,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -43432,7 +46974,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43456,7 +46998,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43480,19 +47022,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_20 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +module mux_tree_size2_20 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -43501,20 +47043,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_19 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +module mux_tree_size2_19 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -43523,20 +47065,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_18 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +module mux_tree_size2_18 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -43545,7 +47087,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43565,10 +47107,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43586,10 +47127,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43612,19 +47152,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_30 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +module mux_tree_size2_30 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -43633,7 +47173,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43703,7 +47243,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb6_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__46 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__47 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43740,13 +47280,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( @@ -43850,11 +47390,11 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , @@ -43917,7 +47457,7 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p1 ) ; + VSS , p2 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -43925,7 +47465,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -43952,7 +47492,7 @@ mux_tree_size2_30 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -43976,24 +47516,24 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , - VSS , p1 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , + VSS , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -44010,17 +47550,17 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -44028,7 +47568,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 log .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_size2_18 mux_fabric_out_0 ( @@ -44038,21 +47578,21 @@ mux_tree_size2_18 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; mux_tree_size2_19 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; mux_tree_size2_20 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -44069,10 +47609,10 @@ mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -44087,7 +47627,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -44106,23 +47646,23 @@ endmodule module logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , VDD , VSS , p1 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; +input p2 ; supply1 VDD ; supply0 VSS ; @@ -44130,10 +47670,10 @@ supply0 VSS ; logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -44145,7 +47685,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -44163,7 +47703,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -44189,7 +47729,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__45 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44213,7 +47753,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44237,19 +47777,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_17 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +module mux_tree_size2_17 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -44258,20 +47798,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_16 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +module mux_tree_size2_16 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -44280,20 +47820,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_15 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +module mux_tree_size2_15 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -44302,7 +47842,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44322,10 +47862,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44343,10 +47882,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44369,19 +47907,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__42 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_29 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +module mux_tree_size2_29 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -44390,7 +47928,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44460,7 +47998,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb5_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__41 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__42 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44607,9 +48145,9 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -44674,7 +48212,7 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p1 ) ; + VSS , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -44682,7 +48220,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -44709,7 +48247,7 @@ mux_tree_size2_29 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -44733,24 +48271,25 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , - VSS , p1 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , + VSS , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; +input p0 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -44767,17 +48306,17 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -44785,7 +48324,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 log .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_size2_15 mux_fabric_out_0 ( @@ -44795,21 +48334,21 @@ mux_tree_size2_15 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; mux_tree_size2_16 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; mux_tree_size2_17 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -44826,10 +48365,10 @@ mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -44844,7 +48383,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -44863,23 +48402,24 @@ endmodule module logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , VDD , VSS , p1 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; +input p0 ; +input p2 ; supply1 VDD ; supply0 VSS ; @@ -44887,10 +48427,11 @@ supply0 VSS ; logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , + .p2 ( p2 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -44902,7 +48443,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -44920,7 +48461,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -44946,7 +48487,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44970,7 +48511,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__39 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44994,19 +48535,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_14 ( in , sram , sram_inv , out , VDD , VSS , p3 ) ; +module mux_tree_size2_14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -45015,20 +48556,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_13 ( in , sram , sram_inv , out , VDD , VSS , p3 ) ; +module mux_tree_size2_13 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -45037,20 +48578,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_12 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +module mux_tree_size2_12 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -45059,7 +48600,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45079,10 +48620,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45100,10 +48640,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45126,19 +48665,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_28 ( in , sram , sram_inv , out , VDD , VSS , p3 ) ; +module mux_tree_size2_28 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -45147,7 +48686,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45217,7 +48756,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__36 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45266,13 +48805,13 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -45370,7 +48909,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , @@ -45431,7 +48970,7 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p3 ) ; + VSS , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -45439,7 +48978,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -45466,7 +49005,7 @@ mux_tree_size2_28 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -45490,25 +49029,24 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , - VSS , p1 , p3 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , + VSS , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -45525,17 +49063,17 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -45543,7 +49081,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logi .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_size2_12 mux_fabric_out_0 ( @@ -45553,21 +49091,21 @@ mux_tree_size2_12 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_13 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_14 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -45584,10 +49122,10 @@ mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -45602,7 +49140,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -45621,24 +49159,23 @@ endmodule module logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , VDD , VSS , p1 , p3 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; -input p3 ; +input p0 ; supply1 VDD ; supply0 VSS ; @@ -45646,11 +49183,10 @@ supply0 VSS ; logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) , - .p3 ( p3 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -45662,7 +49198,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -45680,7 +49216,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -45706,7 +49242,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45730,7 +49266,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45754,19 +49290,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_11 ( in , sram , sram_inv , out , VDD , VSS , p3 ) ; +module mux_tree_size2_11 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -45775,20 +49311,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_10 ( in , sram , sram_inv , out , VDD , VSS , p3 ) ; +module mux_tree_size2_10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -45797,20 +49333,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p3 ) ; +module mux_tree_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -45819,7 +49355,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45839,10 +49375,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45860,10 +49395,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45886,7 +49420,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45977,7 +49511,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46023,7 +49557,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( @@ -46250,25 +49784,24 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , - VSS , p0 , p3 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , + VSS , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; input p0 ; -input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -46285,7 +49818,7 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , @@ -46295,7 +49828,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -46303,7 +49836,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logi .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_size2_9 mux_fabric_out_0 ( @@ -46313,21 +49846,21 @@ mux_tree_size2_9 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_10 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_11 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -46344,10 +49877,10 @@ mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -46362,7 +49895,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -46381,24 +49914,23 @@ endmodule module logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , VDD , VSS , p0 , p3 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; input p0 ; -input p3 ; supply1 VDD ; supply0 VSS ; @@ -46406,11 +49938,10 @@ supply0 VSS ; logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , - .p3 ( p3 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -46422,7 +49953,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -46440,7 +49971,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -46466,7 +49997,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46490,7 +50021,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46514,19 +50045,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -46535,20 +50066,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -46557,20 +50088,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -46579,7 +50110,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46599,10 +50130,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46620,10 +50150,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46646,19 +50175,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_26 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_size2_26 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -46667,7 +50196,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46737,7 +50266,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb2_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__27 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46780,7 +50309,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( @@ -46951,7 +50480,7 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p0 ) ; + VSS , p1 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -46959,7 +50488,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -46986,7 +50515,7 @@ mux_tree_size2_26 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -47010,24 +50539,25 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , - VSS , p0 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , + VSS , p1 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +input p1 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -47044,17 +50574,17 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -47062,7 +50592,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logi .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_size2_6 mux_fabric_out_0 ( @@ -47072,21 +50602,21 @@ mux_tree_size2_6 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; mux_tree_size2_7 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; mux_tree_size2_8 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -47103,10 +50633,10 @@ mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -47121,7 +50651,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -47140,23 +50670,24 @@ endmodule module logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , VDD , VSS , p0 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p1 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +input p1 ; +input p3 ; supply1 VDD ; supply0 VSS ; @@ -47164,10 +50695,11 @@ supply0 VSS ; logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) , + .p3 ( p3 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -47179,7 +50711,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -47197,7 +50729,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -47223,7 +50755,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47247,7 +50779,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47271,19 +50803,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47292,20 +50824,20 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47314,7 +50846,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47356,10 +50888,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47377,10 +50908,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47403,7 +50933,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47494,7 +51024,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb1_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__21 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47540,16 +51070,16 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -47641,13 +51171,13 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , @@ -47767,25 +51297,25 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , - VSS , p0 , p1 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , + VSS , p0 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; input p0 ; -input p1 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -47802,7 +51332,7 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , @@ -47812,7 +51342,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -47820,7 +51350,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logi .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_size2_3 mux_fabric_out_0 ( @@ -47832,19 +51362,19 @@ mux_tree_size2_3 mux_fabric_out_0 ( .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_4 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; mux_tree_size2_5 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -47861,10 +51391,10 @@ mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -47879,7 +51409,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -47898,24 +51428,24 @@ endmodule module logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , VDD , VSS , p0 , p1 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p0 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; input p0 ; -input p1 ; +input p3 ; supply1 VDD ; supply0 VSS ; @@ -47923,11 +51453,11 @@ supply0 VSS ; logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , - .p1 ( p1 ) ) ; + .p3 ( p3 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -47939,7 +51469,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -47957,7 +51487,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -47983,7 +51513,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__20 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48007,7 +51537,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__19 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48031,7 +51561,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48097,8 +51627,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( net_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( net_net_61 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48116,10 +51648,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48137,10 +51668,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48171,7 +51701,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__17 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48262,7 +51792,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb0_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__16 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__17 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48302,10 +51832,10 @@ supply0 VSS ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( @@ -48317,7 +51847,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -48409,11 +51939,11 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , @@ -48535,24 +52065,24 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , - VSS , p1 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , + VSS , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -48569,17 +52099,17 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -48587,7 +52117,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logi .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_size2_0 mux_fabric_out_0 ( @@ -48597,21 +52127,21 @@ mux_tree_size2_0 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_1 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_2 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -48628,10 +52158,10 @@ mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -48646,7 +52176,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -48665,23 +52195,23 @@ endmodule module logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , VDD , VSS , p1 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; +input p0 ; supply1 VDD ; supply0 VSS ; @@ -48689,10 +52219,10 @@ supply0 VSS ; logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -48704,7 +52234,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -48722,7 +52252,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -48730,35 +52260,43 @@ endmodule module logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , clb_I0 , - clb_I1 , clb_I2 , clb_I3 , clb_I4 , clb_I5 , clb_I6 , clb_I7 , clb_regin , - clb_scin , clb_clk , ccff_head , clb_O , clb_regout , clb_scout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , - p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , - p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p0 , p1 , p2 , p3 , p4 ) ; + clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , clb_I3i , + clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , clb_I7 , + clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , + clb_regout , clb_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf3 , + p_abuf4 , p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , + p_abuf11 , p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p_abuf16 , p0 , + p1 , p2 , p3 , p4 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; -input [0:3] clb_I0 ; -input [0:3] clb_I1 ; -input [0:3] clb_I2 ; -input [0:3] clb_I3 ; -input [0:3] clb_I4 ; -input [0:3] clb_I5 ; -input [0:3] clb_I6 ; -input [0:3] clb_I7 ; +input [0:2] clb_I0 ; +input [0:0] clb_I0i ; +input [0:2] clb_I1 ; +input [0:0] clb_I1i ; +input [0:2] clb_I2 ; +input [0:0] clb_I2i ; +input [0:2] clb_I3 ; +input [0:0] clb_I3i ; +input [0:2] clb_I4 ; +input [0:0] clb_I4i ; +input [0:2] clb_I5 ; +input [0:0] clb_I5i ; +input [0:2] clb_I6 ; +input [0:0] clb_I6i ; +input [0:2] clb_I7 ; +input [0:0] clb_I7i ; input [0:0] clb_regin ; -input [0:0] clb_scin ; +input [0:0] clb_sc_in ; input [0:0] clb_clk ; input [0:0] ccff_head ; output [0:15] clb_O ; output [0:0] clb_regout ; -output [0:0] clb_scout ; +output [0:0] clb_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; output p_abuf3 ; output p_abuf4 ; output p_abuf5 ; @@ -48772,6 +52310,7 @@ output p_abuf12 ; output p_abuf13 ; output p_abuf14 ; output p_abuf15 ; +output p_abuf16 ; input p0 ; input p1 ; input p2 ; @@ -48779,151 +52318,149 @@ input p3 ; input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; -wire [1:1] logical_tile_clb_mode_default__fle_0_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; -wire [1:1] logical_tile_clb_mode_default__fle_1_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; wire [1:1] logical_tile_clb_mode_default__fle_4_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; supply1 VDD ; supply0 VSS ; logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I0 ) , .fle_regin ( clb_regin ) , .fle_scin ( clb_scin ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I0[2] , clb_I0[1] , clb_I0[0] , clb_I0i[0] } ) , + .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , - .fle_out ( { clb_O[1] , logical_tile_clb_mode_default__fle_0_fle_out[1] } ) , + .fle_out ( { p_abuf16 , p_abuf3 } ) , .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_0_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I1 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I1[2] , clb_I1[1] , clb_I1[0] , clb_I1i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_0_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .fle_out ( { clb_O[3] , logical_tile_clb_mode_default__fle_1_fle_out[1] } ) , + .fle_out ( { p_abuf4 , clb_O[2] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_1_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , .p3 ( p4 ) ) ; logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I2 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I2[2] , clb_I2[1] , clb_I2[0] , clb_I2i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_1_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .fle_out ( { clb_O[5] , clb_O[4] } ) , + .fle_out ( { p_abuf6 , p_abuf7 } ) , .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_2_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p2 ) , .p3 ( p4 ) ) ; logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I3 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I3[2] , clb_I3[1] , clb_I3[0] , clb_I3i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_2_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .fle_out ( logical_tile_clb_mode_default__fle_3_fle_out ) , + .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .fle_out ( { logical_tile_clb_mode_default__fle_3_fle_out[0] , clb_O[6] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_3_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , .p3 ( p4 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I4 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I4[2] , clb_I4[1] , clb_I4[0] , clb_I4i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_3_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , .fle_out ( { clb_O[9] , logical_tile_clb_mode_default__fle_4_fle_out[1] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_4_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p2 ) , .p3 ( p4 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I5 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I5[2] , clb_I5[1] , clb_I5[0] , clb_I5i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_4_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .fle_out ( { logical_tile_clb_mode_default__fle_5_fle_out[0] , clb_O[10] } ) , + .fle_out ( { clb_O[11] , clb_O[10] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_5_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) , .p2 ( p3 ) ) ; logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I6 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I6[2] , clb_I6[1] , clb_I6[0] , clb_I6i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_5_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .fle_out ( { logical_tile_clb_mode_default__fle_6_fle_out[0] , clb_O[12] } ) , + .fle_out ( { p_abuf14 , p_abuf15 } ) , .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_6_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p3 ) ) ; logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I7 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I7[2] , clb_I7[1] , clb_I7[0] , clb_I7i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_6_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .fle_out ( { p_abuf14 , clb_O[14] } ) , - .fle_regout ( clb_regout ) , .fle_scout ( clb_scout ) , + .fle_out ( { clb_O[15] , clb_O[14] } ) , + .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf16 ) , .p_abuf1 ( p_abuf17 ) , .p2 ( p3 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , + .p1 ( p2 ) , .p2 ( p3 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_out ) ) ; + .out ( { p_abuf3 } ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( clb_O[1] ) ) ; + .out ( { p_abuf16 } ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_out ) ) ; + .out ( clb_O[2] ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( clb_O[3] ) ) ; + .out ( { p_abuf4 } ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( clb_O[4] ) ) ; + .out ( { p_abuf7 } ) ) ; direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( clb_O[5] ) ) ; + .out ( { p_abuf6 } ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) ) ; + .out ( clb_O[6] ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) ) ; + .out ( logical_tile_clb_mode_default__fle_3_fle_out ) ) ; direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_out ) ) ; @@ -48935,704 +52472,697 @@ direct_interc direct_interc_10_ ( .out ( clb_O[10] ) ) ; direct_interc direct_interc_11_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_out ) ) ; + .out ( clb_O[11] ) ) ; direct_interc direct_interc_12_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( clb_O[12] ) ) ; + .out ( { p_abuf15 } ) ) ; direct_interc direct_interc_13_ ( .in ( { SYNOPSYS_UNCONNECTED_14 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_out ) ) ; + .out ( { p_abuf14 } ) ) ; direct_interc direct_interc_14_ ( .in ( { SYNOPSYS_UNCONNECTED_15 } ) , .out ( clb_O[14] ) ) ; direct_interc direct_interc_15_ ( .in ( { SYNOPSYS_UNCONNECTED_16 } ) , - .out ( { p_abuf14 } ) ) ; + .out ( clb_O[15] ) ) ; direct_interc direct_interc_16_ ( .in ( { SYNOPSYS_UNCONNECTED_17 } ) , - .out ( { p_abuf16 } ) ) ; + .out ( { p_abuf1 } ) ) ; direct_interc direct_interc_17_ ( .in ( { SYNOPSYS_UNCONNECTED_18 } ) , - .out ( { p_abuf17 } ) ) ; + .out ( { p_abuf2 } ) ) ; direct_interc direct_interc_18_ ( .in ( { SYNOPSYS_UNCONNECTED_19 } ) , - .out ( clb_I0[0] ) ) ; + .out ( clb_I0[2] ) ) ; direct_interc direct_interc_19_ ( .in ( { SYNOPSYS_UNCONNECTED_20 } ) , .out ( clb_I0[1] ) ) ; direct_interc direct_interc_20_ ( .in ( { SYNOPSYS_UNCONNECTED_21 } ) , - .out ( clb_I0[2] ) ) ; + .out ( clb_I0[0] ) ) ; direct_interc direct_interc_21_ ( .in ( { SYNOPSYS_UNCONNECTED_22 } ) , - .out ( clb_I0[3] ) ) ; + .out ( clb_I0i ) ) ; direct_interc direct_interc_22_ ( .in ( { SYNOPSYS_UNCONNECTED_23 } ) , .out ( clb_regin ) ) ; direct_interc direct_interc_23_ ( .in ( { SYNOPSYS_UNCONNECTED_24 } ) , - .out ( clb_scin ) ) ; + .out ( clb_sc_in ) ) ; direct_interc direct_interc_24_ ( .in ( { SYNOPSYS_UNCONNECTED_25 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_25_ ( .in ( { SYNOPSYS_UNCONNECTED_26 } ) , - .out ( clb_I1[0] ) ) ; + .out ( clb_I1[2] ) ) ; direct_interc direct_interc_26_ ( .in ( { SYNOPSYS_UNCONNECTED_27 } ) , .out ( clb_I1[1] ) ) ; direct_interc direct_interc_27_ ( .in ( { SYNOPSYS_UNCONNECTED_28 } ) , - .out ( clb_I1[2] ) ) ; + .out ( clb_I1[0] ) ) ; direct_interc direct_interc_28_ ( .in ( { SYNOPSYS_UNCONNECTED_29 } ) , - .out ( clb_I1[3] ) ) ; + .out ( clb_I1i ) ) ; direct_interc direct_interc_29_ ( .in ( { SYNOPSYS_UNCONNECTED_30 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; direct_interc direct_interc_30_ ( .in ( { SYNOPSYS_UNCONNECTED_31 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; direct_interc direct_interc_31_ ( .in ( { SYNOPSYS_UNCONNECTED_32 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_32_ ( .in ( { SYNOPSYS_UNCONNECTED_33 } ) , - .out ( clb_I2[0] ) ) ; + .out ( clb_I2[2] ) ) ; direct_interc direct_interc_33_ ( .in ( { SYNOPSYS_UNCONNECTED_34 } ) , .out ( clb_I2[1] ) ) ; direct_interc direct_interc_34_ ( .in ( { SYNOPSYS_UNCONNECTED_35 } ) , - .out ( clb_I2[2] ) ) ; + .out ( clb_I2[0] ) ) ; direct_interc direct_interc_35_ ( .in ( { SYNOPSYS_UNCONNECTED_36 } ) , - .out ( clb_I2[3] ) ) ; + .out ( clb_I2i ) ) ; direct_interc direct_interc_36_ ( .in ( { SYNOPSYS_UNCONNECTED_37 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; direct_interc direct_interc_37_ ( .in ( { SYNOPSYS_UNCONNECTED_38 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; direct_interc direct_interc_38_ ( .in ( { SYNOPSYS_UNCONNECTED_39 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_39_ ( .in ( { SYNOPSYS_UNCONNECTED_40 } ) , - .out ( clb_I3[0] ) ) ; + .out ( clb_I3[2] ) ) ; direct_interc direct_interc_40_ ( .in ( { SYNOPSYS_UNCONNECTED_41 } ) , .out ( clb_I3[1] ) ) ; direct_interc direct_interc_41_ ( .in ( { SYNOPSYS_UNCONNECTED_42 } ) , - .out ( clb_I3[2] ) ) ; + .out ( clb_I3[0] ) ) ; direct_interc direct_interc_42_ ( .in ( { SYNOPSYS_UNCONNECTED_43 } ) , - .out ( clb_I3[3] ) ) ; + .out ( clb_I3i ) ) ; direct_interc direct_interc_43_ ( .in ( { SYNOPSYS_UNCONNECTED_44 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; direct_interc direct_interc_44_ ( .in ( { SYNOPSYS_UNCONNECTED_45 } ) , - .out ( logical_tile_clb_mode_default__fle_2_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; direct_interc direct_interc_45_ ( .in ( { SYNOPSYS_UNCONNECTED_46 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_46_ ( .in ( { SYNOPSYS_UNCONNECTED_47 } ) , - .out ( clb_I4[0] ) ) ; + .out ( clb_I4[2] ) ) ; direct_interc direct_interc_47_ ( .in ( { SYNOPSYS_UNCONNECTED_48 } ) , .out ( clb_I4[1] ) ) ; direct_interc direct_interc_48_ ( .in ( { SYNOPSYS_UNCONNECTED_49 } ) , - .out ( clb_I4[2] ) ) ; + .out ( clb_I4[0] ) ) ; direct_interc direct_interc_49_ ( .in ( { SYNOPSYS_UNCONNECTED_50 } ) , - .out ( clb_I4[3] ) ) ; + .out ( clb_I4i ) ) ; direct_interc direct_interc_50_ ( .in ( { SYNOPSYS_UNCONNECTED_51 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; direct_interc direct_interc_51_ ( .in ( { SYNOPSYS_UNCONNECTED_52 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; direct_interc direct_interc_52_ ( .in ( { SYNOPSYS_UNCONNECTED_53 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_53_ ( .in ( { SYNOPSYS_UNCONNECTED_54 } ) , - .out ( clb_I5[0] ) ) ; + .out ( clb_I5[2] ) ) ; direct_interc direct_interc_54_ ( .in ( { SYNOPSYS_UNCONNECTED_55 } ) , .out ( clb_I5[1] ) ) ; direct_interc direct_interc_55_ ( .in ( { SYNOPSYS_UNCONNECTED_56 } ) , - .out ( clb_I5[2] ) ) ; + .out ( clb_I5[0] ) ) ; direct_interc direct_interc_56_ ( .in ( { SYNOPSYS_UNCONNECTED_57 } ) , - .out ( clb_I5[3] ) ) ; + .out ( clb_I5i ) ) ; direct_interc direct_interc_57_ ( .in ( { SYNOPSYS_UNCONNECTED_58 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; direct_interc direct_interc_58_ ( .in ( { SYNOPSYS_UNCONNECTED_59 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; direct_interc direct_interc_59_ ( .in ( { SYNOPSYS_UNCONNECTED_60 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_60_ ( .in ( { SYNOPSYS_UNCONNECTED_61 } ) , - .out ( clb_I6[0] ) ) ; + .out ( clb_I6[2] ) ) ; direct_interc direct_interc_61_ ( .in ( { SYNOPSYS_UNCONNECTED_62 } ) , .out ( clb_I6[1] ) ) ; direct_interc direct_interc_62_ ( .in ( { SYNOPSYS_UNCONNECTED_63 } ) , - .out ( clb_I6[2] ) ) ; + .out ( clb_I6[0] ) ) ; direct_interc direct_interc_63_ ( .in ( { SYNOPSYS_UNCONNECTED_64 } ) , - .out ( clb_I6[3] ) ) ; + .out ( clb_I6i ) ) ; direct_interc direct_interc_64_ ( .in ( { SYNOPSYS_UNCONNECTED_65 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; direct_interc direct_interc_65_ ( .in ( { SYNOPSYS_UNCONNECTED_66 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; direct_interc direct_interc_66_ ( .in ( { SYNOPSYS_UNCONNECTED_67 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_67_ ( .in ( { SYNOPSYS_UNCONNECTED_68 } ) , - .out ( clb_I7[0] ) ) ; + .out ( clb_I7[2] ) ) ; direct_interc direct_interc_68_ ( .in ( { SYNOPSYS_UNCONNECTED_69 } ) , .out ( clb_I7[1] ) ) ; direct_interc direct_interc_69_ ( .in ( { SYNOPSYS_UNCONNECTED_70 } ) , - .out ( clb_I7[2] ) ) ; + .out ( clb_I7[0] ) ) ; direct_interc direct_interc_70_ ( .in ( { SYNOPSYS_UNCONNECTED_71 } ) , - .out ( clb_I7[3] ) ) ; + .out ( clb_I7i ) ) ; direct_interc direct_interc_71_ ( .in ( { SYNOPSYS_UNCONNECTED_72 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; direct_interc direct_interc_72_ ( .in ( { SYNOPSYS_UNCONNECTED_73 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; direct_interc direct_interc_73_ ( .in ( { SYNOPSYS_UNCONNECTED_74 } ) , .out ( clb_clk ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( - .A ( logical_tile_clb_mode_default__fle_0_fle_out[1] ) , .X ( clb_O[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( clb_O[1] ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( - .A ( logical_tile_clb_mode_default__fle_0_fle_out[1] ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( - .A ( logical_tile_clb_mode_default__fle_1_fle_out[1] ) , .X ( clb_O[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( clb_O[3] ) , .X ( p_abuf2 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( - .A ( logical_tile_clb_mode_default__fle_1_fle_out[1] ) , .X ( p_abuf3 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( p_abuf3 ) , + .X ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( p_abuf4 ) , + .X ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( p_abuf6 ) , + .X ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( clb_O[2] ) , + .X ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( p_abuf7 ) , + .X ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , .X ( clb_O[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( clb_O[5] ) , .X ( p_abuf4 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( clb_O[4] ) , .X ( p_abuf5 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , .X ( p_abuf6 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) , .X ( clb_O[6] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) , .X ( p_abuf7 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( + .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , + .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , .X ( clb_O[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( clb_O[9] ) , - .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( - .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , - .X ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( - .A ( logical_tile_clb_mode_default__fle_5_fle_out[0] ) , - .X ( clb_O[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( - .A ( logical_tile_clb_mode_default__fle_5_fle_out[0] ) , - .X ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_81 ( - .A ( logical_tile_clb_mode_default__fle_6_fle_out[0] ) , - .X ( clb_O[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( clb_O[10] ) , - .X ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( - .A ( logical_tile_clb_mode_default__fle_6_fle_out[0] ) , - .X ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( p_abuf14 ) , - .X ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( clb_O[12] ) , - .X ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( BUF_net_74 ) , - .X ( p_abuf8 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( clb_O[14] ) , - .X ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( BUF_net_78 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( clb_O[6] ) , + .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( clb_O[9] ) , .X ( p_abuf10 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( BUF_net_85 ) , - .X ( clb_O[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_104 ( .A ( BUF_net_84 ) , - .X ( p_abuf13 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_87 ) , - .X ( p_abuf15 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( BUF_net_76 ) , - .X ( p_abuf9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( + .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , + .X ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( p_abuf14 ) , + .X ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_77 ( .A ( clb_O[11] ) , + .X ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( clb_O[10] ) , + .X ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_81 ( .A ( p_abuf15 ) , + .X ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( BUF_net_62 ) , + .X ( clb_O[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_103 ( .A ( BUF_net_66 ) , + .X ( clb_O[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( BUF_net_75 ) , .X ( p_abuf11 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( BUF_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_80 ) , + .X ( clb_O[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( BUF_net_77 ) , .X ( p_abuf12 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_107 ( .A ( BUF_net_79 ) , + .X ( p_abuf13 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_108 ( .A ( BUF_net_81 ) , + .X ( clb_O[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_110 ( .A ( p_abuf16 ) , + .X ( clb_O[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( BUF_net_63 ) , + .X ( clb_O[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( BUF_net_65 ) , + .X ( p_abuf5 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( BUF_net_67 ) , + .X ( clb_O[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( BUF_net_69 ) , + .X ( p_abuf8 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( BUF_net_71 ) , + .X ( p_abuf9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_32_ , - top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_0_ , - right_width_0_height_0__pin_1_ , right_width_0_height_0__pin_2_ , - right_width_0_height_0__pin_3_ , right_width_0_height_0__pin_4_ , - right_width_0_height_0__pin_5_ , right_width_0_height_0__pin_6_ , - right_width_0_height_0__pin_7_ , right_width_0_height_0__pin_8_ , - right_width_0_height_0__pin_9_ , right_width_0_height_0__pin_10_ , - right_width_0_height_0__pin_11_ , right_width_0_height_0__pin_12_ , - right_width_0_height_0__pin_13_ , right_width_0_height_0__pin_14_ , - right_width_0_height_0__pin_15_ , bottom_width_0_height_0__pin_16_ , - bottom_width_0_height_0__pin_17_ , bottom_width_0_height_0__pin_18_ , - bottom_width_0_height_0__pin_19_ , bottom_width_0_height_0__pin_20_ , - bottom_width_0_height_0__pin_21_ , bottom_width_0_height_0__pin_22_ , - bottom_width_0_height_0__pin_23_ , bottom_width_0_height_0__pin_24_ , - bottom_width_0_height_0__pin_25_ , bottom_width_0_height_0__pin_26_ , - bottom_width_0_height_0__pin_27_ , bottom_width_0_height_0__pin_28_ , - bottom_width_0_height_0__pin_29_ , bottom_width_0_height_0__pin_30_ , - bottom_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , - ccff_head , right_width_0_height_0__pin_34_upper , - right_width_0_height_0__pin_34_lower , - right_width_0_height_0__pin_35_upper , - right_width_0_height_0__pin_35_lower , - right_width_0_height_0__pin_36_upper , - right_width_0_height_0__pin_36_lower , - right_width_0_height_0__pin_37_upper , - right_width_0_height_0__pin_37_lower , - right_width_0_height_0__pin_38_upper , - right_width_0_height_0__pin_38_lower , - right_width_0_height_0__pin_39_upper , - right_width_0_height_0__pin_39_lower , - right_width_0_height_0__pin_40_upper , - right_width_0_height_0__pin_40_lower , - right_width_0_height_0__pin_41_upper , - right_width_0_height_0__pin_41_lower , - bottom_width_0_height_0__pin_42_upper , - bottom_width_0_height_0__pin_42_lower , - bottom_width_0_height_0__pin_43_upper , - bottom_width_0_height_0__pin_43_lower , - bottom_width_0_height_0__pin_44_upper , - bottom_width_0_height_0__pin_44_lower , - bottom_width_0_height_0__pin_45_upper , - bottom_width_0_height_0__pin_45_lower , - bottom_width_0_height_0__pin_46_upper , - bottom_width_0_height_0__pin_46_lower , - bottom_width_0_height_0__pin_47_upper , - bottom_width_0_height_0__pin_47_lower , - bottom_width_0_height_0__pin_48_upper , - bottom_width_0_height_0__pin_48_lower , - bottom_width_0_height_0__pin_49_upper , - bottom_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , - bottom_width_0_height_0__pin_51_ , ccff_tail , VDD , VSS ) ; +module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ , + top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ , + top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ , + top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ , + top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ , + top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_16_ , + right_width_0_height_0__pin_17_ , right_width_0_height_0__pin_18_ , + right_width_0_height_0__pin_19_ , right_width_0_height_0__pin_20_ , + right_width_0_height_0__pin_21_ , right_width_0_height_0__pin_22_ , + right_width_0_height_0__pin_23_ , right_width_0_height_0__pin_24_ , + right_width_0_height_0__pin_25_ , right_width_0_height_0__pin_26_ , + right_width_0_height_0__pin_27_ , right_width_0_height_0__pin_28_ , + right_width_0_height_0__pin_29_ , right_width_0_height_0__pin_30_ , + right_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , + ccff_head , top_width_0_height_0__pin_34_upper , + top_width_0_height_0__pin_34_lower , top_width_0_height_0__pin_35_upper , + top_width_0_height_0__pin_35_lower , top_width_0_height_0__pin_36_upper , + top_width_0_height_0__pin_36_lower , top_width_0_height_0__pin_37_upper , + top_width_0_height_0__pin_37_lower , top_width_0_height_0__pin_38_upper , + top_width_0_height_0__pin_38_lower , top_width_0_height_0__pin_39_upper , + top_width_0_height_0__pin_39_lower , top_width_0_height_0__pin_40_upper , + top_width_0_height_0__pin_40_lower , top_width_0_height_0__pin_41_upper , + top_width_0_height_0__pin_41_lower , + right_width_0_height_0__pin_42_upper , + right_width_0_height_0__pin_42_lower , + right_width_0_height_0__pin_43_upper , + right_width_0_height_0__pin_43_lower , + right_width_0_height_0__pin_44_upper , + right_width_0_height_0__pin_44_lower , + right_width_0_height_0__pin_45_upper , + right_width_0_height_0__pin_45_lower , + right_width_0_height_0__pin_46_upper , + right_width_0_height_0__pin_46_lower , + right_width_0_height_0__pin_47_upper , + right_width_0_height_0__pin_47_lower , + right_width_0_height_0__pin_48_upper , + right_width_0_height_0__pin_48_lower , + right_width_0_height_0__pin_49_upper , + right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , + bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_1_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_3_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_5_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_7_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_9_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_11_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_13_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_15_ ; input [0:0] top_width_0_height_0__pin_32_ ; input [0:0] top_width_0_height_0__pin_33_ ; -input [0:0] right_width_0_height_0__pin_0_ ; -input [0:0] right_width_0_height_0__pin_1_ ; -input [0:0] right_width_0_height_0__pin_2_ ; -input [0:0] right_width_0_height_0__pin_3_ ; -input [0:0] right_width_0_height_0__pin_4_ ; -input [0:0] right_width_0_height_0__pin_5_ ; -input [0:0] right_width_0_height_0__pin_6_ ; -input [0:0] right_width_0_height_0__pin_7_ ; -input [0:0] right_width_0_height_0__pin_8_ ; -input [0:0] right_width_0_height_0__pin_9_ ; -input [0:0] right_width_0_height_0__pin_10_ ; -input [0:0] right_width_0_height_0__pin_11_ ; -input [0:0] right_width_0_height_0__pin_12_ ; -input [0:0] right_width_0_height_0__pin_13_ ; -input [0:0] right_width_0_height_0__pin_14_ ; -input [0:0] right_width_0_height_0__pin_15_ ; -input [0:0] bottom_width_0_height_0__pin_16_ ; -input [0:0] bottom_width_0_height_0__pin_17_ ; -input [0:0] bottom_width_0_height_0__pin_18_ ; -input [0:0] bottom_width_0_height_0__pin_19_ ; -input [0:0] bottom_width_0_height_0__pin_20_ ; -input [0:0] bottom_width_0_height_0__pin_21_ ; -input [0:0] bottom_width_0_height_0__pin_22_ ; -input [0:0] bottom_width_0_height_0__pin_23_ ; -input [0:0] bottom_width_0_height_0__pin_24_ ; -input [0:0] bottom_width_0_height_0__pin_25_ ; -input [0:0] bottom_width_0_height_0__pin_26_ ; -input [0:0] bottom_width_0_height_0__pin_27_ ; -input [0:0] bottom_width_0_height_0__pin_28_ ; -input [0:0] bottom_width_0_height_0__pin_29_ ; -input [0:0] bottom_width_0_height_0__pin_30_ ; -input [0:0] bottom_width_0_height_0__pin_31_ ; +input [0:0] right_width_0_height_0__pin_16_ ; +input [0:0] right_width_0_height_0__pin_17_ ; +input [0:0] right_width_0_height_0__pin_18_ ; +input [0:0] right_width_0_height_0__pin_19_ ; +input [0:0] right_width_0_height_0__pin_20_ ; +input [0:0] right_width_0_height_0__pin_21_ ; +input [0:0] right_width_0_height_0__pin_22_ ; +input [0:0] right_width_0_height_0__pin_23_ ; +input [0:0] right_width_0_height_0__pin_24_ ; +input [0:0] right_width_0_height_0__pin_25_ ; +input [0:0] right_width_0_height_0__pin_26_ ; +input [0:0] right_width_0_height_0__pin_27_ ; +input [0:0] right_width_0_height_0__pin_28_ ; +input [0:0] right_width_0_height_0__pin_29_ ; +input [0:0] right_width_0_height_0__pin_30_ ; +input [0:0] right_width_0_height_0__pin_31_ ; input [0:0] left_width_0_height_0__pin_52_ ; input [0:0] ccff_head ; -output [0:0] right_width_0_height_0__pin_34_upper ; -output [0:0] right_width_0_height_0__pin_34_lower ; -output [0:0] right_width_0_height_0__pin_35_upper ; -output [0:0] right_width_0_height_0__pin_35_lower ; -output [0:0] right_width_0_height_0__pin_36_upper ; -output [0:0] right_width_0_height_0__pin_36_lower ; -output [0:0] right_width_0_height_0__pin_37_upper ; -output [0:0] right_width_0_height_0__pin_37_lower ; -output [0:0] right_width_0_height_0__pin_38_upper ; -output [0:0] right_width_0_height_0__pin_38_lower ; -output [0:0] right_width_0_height_0__pin_39_upper ; -output [0:0] right_width_0_height_0__pin_39_lower ; -output [0:0] right_width_0_height_0__pin_40_upper ; -output [0:0] right_width_0_height_0__pin_40_lower ; -output [0:0] right_width_0_height_0__pin_41_upper ; -output [0:0] right_width_0_height_0__pin_41_lower ; -output [0:0] bottom_width_0_height_0__pin_42_upper ; -output [0:0] bottom_width_0_height_0__pin_42_lower ; -output [0:0] bottom_width_0_height_0__pin_43_upper ; -output [0:0] bottom_width_0_height_0__pin_43_lower ; -output [0:0] bottom_width_0_height_0__pin_44_upper ; -output [0:0] bottom_width_0_height_0__pin_44_lower ; -output [0:0] bottom_width_0_height_0__pin_45_upper ; -output [0:0] bottom_width_0_height_0__pin_45_lower ; -output [0:0] bottom_width_0_height_0__pin_46_upper ; -output [0:0] bottom_width_0_height_0__pin_46_lower ; -output [0:0] bottom_width_0_height_0__pin_47_upper ; -output [0:0] bottom_width_0_height_0__pin_47_lower ; -output [0:0] bottom_width_0_height_0__pin_48_upper ; -output [0:0] bottom_width_0_height_0__pin_48_lower ; -output [0:0] bottom_width_0_height_0__pin_49_upper ; -output [0:0] bottom_width_0_height_0__pin_49_lower ; +output [0:0] top_width_0_height_0__pin_34_upper ; +output [0:0] top_width_0_height_0__pin_34_lower ; +output [0:0] top_width_0_height_0__pin_35_upper ; +output [0:0] top_width_0_height_0__pin_35_lower ; +output [0:0] top_width_0_height_0__pin_36_upper ; +output [0:0] top_width_0_height_0__pin_36_lower ; +output [0:0] top_width_0_height_0__pin_37_upper ; +output [0:0] top_width_0_height_0__pin_37_lower ; +output [0:0] top_width_0_height_0__pin_38_upper ; +output [0:0] top_width_0_height_0__pin_38_lower ; +output [0:0] top_width_0_height_0__pin_39_upper ; +output [0:0] top_width_0_height_0__pin_39_lower ; +output [0:0] top_width_0_height_0__pin_40_upper ; +output [0:0] top_width_0_height_0__pin_40_lower ; +output [0:0] top_width_0_height_0__pin_41_upper ; +output [0:0] top_width_0_height_0__pin_41_lower ; +output [0:0] right_width_0_height_0__pin_42_upper ; +output [0:0] right_width_0_height_0__pin_42_lower ; +output [0:0] right_width_0_height_0__pin_43_upper ; +output [0:0] right_width_0_height_0__pin_43_lower ; +output [0:0] right_width_0_height_0__pin_44_upper ; +output [0:0] right_width_0_height_0__pin_44_lower ; +output [0:0] right_width_0_height_0__pin_45_upper ; +output [0:0] right_width_0_height_0__pin_45_lower ; +output [0:0] right_width_0_height_0__pin_46_upper ; +output [0:0] right_width_0_height_0__pin_46_lower ; +output [0:0] right_width_0_height_0__pin_47_upper ; +output [0:0] right_width_0_height_0__pin_47_lower ; +output [0:0] right_width_0_height_0__pin_48_upper ; +output [0:0] right_width_0_height_0__pin_48_lower ; +output [0:0] right_width_0_height_0__pin_49_upper ; +output [0:0] right_width_0_height_0__pin_49_lower ; output [0:0] bottom_width_0_height_0__pin_50_ ; output [0:0] bottom_width_0_height_0__pin_51_ ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; input VDD ; input VSS ; -wire ropt_net_128 ; -wire ropt_net_134 ; -wire ropt_net_136 ; -wire ropt_net_147 ; -wire ropt_net_133 ; -wire ropt_net_144 ; -wire ropt_net_126 ; -wire ropt_net_130 ; -wire ropt_net_135 ; +wire p_abuf1 ; wire p_abuf14 ; +wire p_abuf2 ; +wire p_abuf5 ; +wire p_abuf4 ; +wire ropt_net_143 ; +wire ropt_net_148 ; +wire ropt_net_144 ; +wire p_abuf13 ; +wire p_abuf12 ; +wire ropt_net_131 ; +wire ropt_net_130 ; +wire ropt_net_133 ; supply1 VDD ; supply0 VSS ; +assign SC_IN_TOP = SC_IN_BOT ; + logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .clb_I0 ( { right_width_0_height_0__pin_0_[0] , - right_width_0_height_0__pin_1_[0] , - right_width_0_height_0__pin_2_[0] , - right_width_0_height_0__pin_3_[0] } ) , - .clb_I1 ( { right_width_0_height_0__pin_4_[0] , - right_width_0_height_0__pin_5_[0] , - right_width_0_height_0__pin_6_[0] , - right_width_0_height_0__pin_7_[0] } ) , - .clb_I2 ( { right_width_0_height_0__pin_8_[0] , - right_width_0_height_0__pin_9_[0] , - right_width_0_height_0__pin_10_[0] , - right_width_0_height_0__pin_11_[0] } ) , - .clb_I3 ( { right_width_0_height_0__pin_12_[0] , - right_width_0_height_0__pin_13_[0] , - right_width_0_height_0__pin_14_[0] , - right_width_0_height_0__pin_15_[0] } ) , - .clb_I4 ( { bottom_width_0_height_0__pin_16_[0] , - bottom_width_0_height_0__pin_17_[0] , - bottom_width_0_height_0__pin_18_[0] , - bottom_width_0_height_0__pin_19_[0] } ) , - .clb_I5 ( { bottom_width_0_height_0__pin_20_[0] , - bottom_width_0_height_0__pin_21_[0] , - bottom_width_0_height_0__pin_22_[0] , - bottom_width_0_height_0__pin_23_[0] } ) , - .clb_I6 ( { bottom_width_0_height_0__pin_24_[0] , - bottom_width_0_height_0__pin_25_[0] , - bottom_width_0_height_0__pin_26_[0] , - bottom_width_0_height_0__pin_27_[0] } ) , - .clb_I7 ( { bottom_width_0_height_0__pin_28_[0] , - bottom_width_0_height_0__pin_29_[0] , - bottom_width_0_height_0__pin_30_[0] , - bottom_width_0_height_0__pin_31_[0] } ) , - .clb_regin ( top_width_0_height_0__pin_32_ ) , - .clb_scin ( top_width_0_height_0__pin_33_ ) , + .clb_I0 ( { top_width_0_height_0__pin_0_[0] , + top_width_0_height_0__pin_1_[0] , top_width_0_height_0__pin_2_[0] } ) , + .clb_I0i ( top_width_0_height_0__pin_3_ ) , + .clb_I1 ( { top_width_0_height_0__pin_4_[0] , + top_width_0_height_0__pin_5_[0] , top_width_0_height_0__pin_6_[0] } ) , + .clb_I1i ( top_width_0_height_0__pin_7_ ) , + .clb_I2 ( { top_width_0_height_0__pin_8_[0] , + top_width_0_height_0__pin_9_[0] , top_width_0_height_0__pin_10_[0] } ) , + .clb_I2i ( top_width_0_height_0__pin_11_ ) , + .clb_I3 ( { top_width_0_height_0__pin_12_[0] , + top_width_0_height_0__pin_13_[0] , top_width_0_height_0__pin_14_[0] } ) , + .clb_I3i ( top_width_0_height_0__pin_15_ ) , + .clb_I4 ( { right_width_0_height_0__pin_16_[0] , + right_width_0_height_0__pin_17_[0] , + right_width_0_height_0__pin_18_[0] } ) , + .clb_I4i ( right_width_0_height_0__pin_19_ ) , + .clb_I5 ( { right_width_0_height_0__pin_20_[0] , + right_width_0_height_0__pin_21_[0] , + right_width_0_height_0__pin_22_[0] } ) , + .clb_I5i ( right_width_0_height_0__pin_23_ ) , + .clb_I6 ( { right_width_0_height_0__pin_24_[0] , + right_width_0_height_0__pin_25_[0] , + right_width_0_height_0__pin_26_[0] } ) , + .clb_I6i ( right_width_0_height_0__pin_27_ ) , + .clb_I7 ( { right_width_0_height_0__pin_28_[0] , + right_width_0_height_0__pin_29_[0] , + right_width_0_height_0__pin_30_[0] } ) , + .clb_I7i ( right_width_0_height_0__pin_31_ ) , + .clb_regin ( top_width_0_height_0__pin_32_ ) , + .clb_sc_in ( { SC_IN_BOT } ) , .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_129_ , aps_rename_130_ , aps_rename_132_ , - aps_rename_134_ , aps_rename_136_ , aps_rename_138_ , - aps_rename_140_ , aps_rename_141_ , aps_rename_143_ , - aps_rename_145_ , aps_rename_147_ , aps_rename_149_ , - aps_rename_151_ , aps_rename_153_ , aps_rename_155_ , - bottom_width_0_height_0__pin_49_upper[0] } ) , - .clb_regout ( bottom_width_0_height_0__pin_50_ ) , - .clb_scout ( bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( { ropt_net_124 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( right_width_0_height_0__pin_35_upper[0] ) , - .p_abuf1 ( right_width_0_height_0__pin_34_upper[0] ) , - .p_abuf2 ( ropt_net_134 ) , .p_abuf3 ( ropt_net_128 ) , - .p_abuf4 ( right_width_0_height_0__pin_39_upper[0] ) , - .p_abuf5 ( ropt_net_136 ) , .p_abuf6 ( ropt_net_133 ) , - .p_abuf7 ( ropt_net_147 ) , .p_abuf8 ( ropt_net_144 ) , - .p_abuf9 ( bottom_width_0_height_0__pin_42_upper[0] ) , - .p_abuf10 ( ropt_net_126 ) , - .p_abuf11 ( bottom_width_0_height_0__pin_44_upper[0] ) , - .p_abuf12 ( bottom_width_0_height_0__pin_47_upper[0] ) , - .p_abuf13 ( ropt_net_130 ) , .p_abuf14 ( p_abuf14 ) , - .p_abuf15 ( ropt_net_135 ) , .p0 ( optlc_net_118 ) , - .p1 ( optlc_net_119 ) , .p2 ( optlc_net_120 ) , .p3 ( optlc_net_121 ) , - .p4 ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2130 ( .VNB ( VSS ) , + .clb_O ( { ropt_net_145 , ropt_net_137 , aps_rename_132_ , + top_width_0_height_0__pin_37_upper[0] , + top_width_0_height_0__pin_38_upper[0] , ropt_net_141 , + aps_rename_137_ , aps_rename_139_ , aps_rename_141_ , + aps_rename_143_ , aps_rename_145_ , aps_rename_147_ , + right_width_0_height_0__pin_46_upper[0] , ropt_net_146 , + ropt_net_131 , ropt_net_130 } ) , + .clb_regout ( { ropt_net_134 } ) , + .clb_sc_out ( { aps_rename_153_ } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( ropt_net_133 ) , .p_abuf3 ( p_abuf1 ) , .p_abuf4 ( p_abuf2 ) , + .p_abuf5 ( top_width_0_height_0__pin_36_upper[0] ) , + .p_abuf6 ( p_abuf4 ) , .p_abuf7 ( p_abuf5 ) , + .p_abuf8 ( top_width_0_height_0__pin_41_upper[0] ) , + .p_abuf9 ( ropt_net_143 ) , .p_abuf10 ( ropt_net_148 ) , + .p_abuf11 ( right_width_0_height_0__pin_42_upper[0] ) , + .p_abuf12 ( right_width_0_height_0__pin_45_upper[0] ) , + .p_abuf13 ( ropt_net_144 ) , .p_abuf14 ( p_abuf12 ) , + .p_abuf15 ( p_abuf13 ) , .p_abuf16 ( p_abuf14 ) , .p0 ( optlc_net_125 ) , + .p1 ( optlc_net_126 ) , .p2 ( optlc_net_127 ) , .p3 ( optlc_net_128 ) , + .p4 ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1176 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2131 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1177 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2132 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1178 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2133 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1179 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2134 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1180 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2135 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1181 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2136 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1182 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2137 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1183 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2138 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1184 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2139 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1185 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2140 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1186 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2141 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1187 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2142 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1188 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2143 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1189 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2144 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1190 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2145 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1191 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2146 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1192 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2147 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1193 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2148 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1194 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2149 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1195 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2150 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1196 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2151 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1197 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2152 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1198 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2153 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1199 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2154 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1200 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2155 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1201 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2156 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1202 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2157 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1203 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2158 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1204 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2159 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1205 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2160 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1206 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2161 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1207 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2162 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1208 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2163 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1209 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2164 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1210 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2165 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1211 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2166 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1212 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2167 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1213 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2168 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1214 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2169 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1215 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2170 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1216 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!2171 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1217 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( aps_rename_129_ ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( aps_rename_130_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( p_abuf1 ) , + .X ( aps_rename_130_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( p_abuf14 ) , .X ( aps_rename_131_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( aps_rename_132_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( aps_rename_132_ ) , .X ( aps_rename_133_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( aps_rename_134_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( p_abuf2 ) , + .X ( aps_rename_134_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( p_abuf5 ) , .X ( aps_rename_135_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( aps_rename_136_ ) , - .X ( aps_rename_137_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( aps_rename_138_ ) , - .X ( aps_rename_139_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_140_ ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( aps_rename_141_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( p_abuf4 ) , + .X ( aps_rename_136_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_137_ ) , + .X ( aps_rename_138_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( aps_rename_139_ ) , + .X ( aps_rename_140_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( aps_rename_141_ ) , .X ( aps_rename_142_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( aps_rename_143_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( aps_rename_143_ ) , .X ( aps_rename_144_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( aps_rename_145_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( aps_rename_145_ ) , .X ( aps_rename_146_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( aps_rename_147_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( aps_rename_147_ ) , .X ( aps_rename_148_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( aps_rename_149_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( p_abuf13 ) , + .X ( aps_rename_149_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( p_abuf12 ) , .X ( aps_rename_150_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( aps_rename_151_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( ropt_net_131 ) , + .X ( aps_rename_151_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( ropt_net_130 ) , .X ( aps_rename_152_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( aps_rename_153_ ) , - .X ( aps_rename_154_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( aps_rename_155_ ) , - .X ( bottom_width_0_height_0__pin_48_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( p_abuf14 ) , - .X ( bottom_width_0_height_0__pin_49_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_89 ( .A ( aps_rename_131_ ) , - .X ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( aps_rename_133_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( aps_rename_153_ ) , .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( .A ( aps_rename_135_ ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( aps_rename_137_ ) , - .X ( right_width_0_height_0__pin_38_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( aps_rename_130_ ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( aps_rename_131_ ) , + .X ( top_width_0_height_0__pin_35_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( aps_rename_139_ ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( aps_rename_142_ ) , - .X ( right_width_0_height_0__pin_41_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( aps_rename_133_ ) , + .X ( top_width_0_height_0__pin_36_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( aps_rename_144_ ) , - .X ( bottom_width_0_height_0__pin_42_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_134_ ) , + .X ( top_width_0_height_0__pin_37_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( aps_rename_146_ ) , - .X ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( aps_rename_148_ ) , - .X ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( .A ( aps_rename_150_ ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_99 ( .A ( aps_rename_152_ ) , - .X ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_154_ ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_110 ( .A ( BUF_net_89 ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_111 ( .A ( BUF_net_96 ) , - .X ( bottom_width_0_height_0__pin_43_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( BUF_net_97 ) , - .X ( bottom_width_0_height_0__pin_44_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( BUF_net_99 ) , - .X ( bottom_width_0_height_0__pin_46_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( aps_rename_135_ ) , + .X ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( aps_rename_136_ ) , + .X ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( aps_rename_138_ ) , + .X ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( .A ( aps_rename_140_ ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_142_ ) , .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_879 ( .A ( ropt_net_125 ) , - .X ( right_width_0_height_0__pin_37_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_93 ( .A ( aps_rename_144_ ) , + .X ( right_width_0_height_0__pin_43_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_880 ( .A ( ropt_net_126 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_146_ ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( aps_rename_148_ ) , + .X ( right_width_0_height_0__pin_45_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( aps_rename_149_ ) , .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_881 ( .A ( ropt_net_127 ) , - .X ( bottom_width_0_height_0__pin_47_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_882 ( .A ( ropt_net_128 ) , - .X ( right_width_0_height_0__pin_36_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_884 ( .A ( ropt_net_129 ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_885 ( .A ( ropt_net_130 ) , - .X ( bottom_width_0_height_0__pin_46_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_886 ( .A ( ropt_net_131 ) , - .X ( right_width_0_height_0__pin_40_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_887 ( .A ( ropt_net_132 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( aps_rename_150_ ) , .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_888 ( .A ( ropt_net_133 ) , - .X ( right_width_0_height_0__pin_41_upper[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_98 ( .A ( aps_rename_151_ ) , + .X ( right_width_0_height_0__pin_48_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_890 ( .A ( ropt_net_134 ) , - .X ( right_width_0_height_0__pin_37_upper[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( aps_rename_152_ ) , + .X ( right_width_0_height_0__pin_49_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_892 ( .A ( ropt_net_135 ) , - .X ( bottom_width_0_height_0__pin_48_upper[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( BUF_net_119 ) , + .X ( top_width_0_height_0__pin_38_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_895 ( .A ( ropt_net_136 ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_898 ( .A ( ropt_net_137 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_909 ( .A ( ropt_net_138 ) , - .X ( bottom_width_0_height_0__pin_45_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( BUF_net_88 ) , + .X ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_120 ( .A ( BUF_net_89 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( BUF_net_122 ) , + .X ( top_width_0_height_0__pin_40_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_913 ( .A ( ropt_net_139 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_914 ( .A ( ropt_net_140 ) , - .X ( bottom_width_0_height_0__pin_45_upper[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_122 ( .A ( BUF_net_90 ) , + .X ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_884 ( .A ( ropt_net_130 ) , + .X ( right_width_0_height_0__pin_49_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_915 ( .A ( ropt_net_141 ) , - .X ( right_width_0_height_0__pin_39_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_885 ( .A ( ropt_net_131 ) , + .X ( right_width_0_height_0__pin_48_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_916 ( .A ( ropt_net_142 ) , - .X ( right_width_0_height_0__pin_36_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_886 ( .A ( ropt_net_132 ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_133 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_134 ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_889 ( .A ( ropt_net_135 ) , + .X ( top_width_0_height_0__pin_34_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_917 ( .A ( ropt_net_143 ) , - .X ( right_width_0_height_0__pin_34_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_890 ( .A ( ropt_net_136 ) , + .X ( top_width_0_height_0__pin_41_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_918 ( .A ( ropt_net_144 ) , - .X ( bottom_width_0_height_0__pin_43_upper[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_893 ( .A ( ropt_net_137 ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_896 ( .A ( ropt_net_138 ) , + .X ( right_width_0_height_0__pin_44_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_919 ( .A ( ropt_net_145 ) , - .X ( right_width_0_height_0__pin_38_upper[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_897 ( .A ( ropt_net_139 ) , + .X ( right_width_0_height_0__pin_42_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_920 ( .A ( ropt_net_146 ) , - .X ( right_width_0_height_0__pin_35_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_898 ( .A ( ropt_net_140 ) , + .X ( right_width_0_height_0__pin_46_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_921 ( .A ( ropt_net_147 ) , - .X ( right_width_0_height_0__pin_40_upper[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_899 ( .A ( ropt_net_141 ) , + .X ( top_width_0_height_0__pin_39_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_900 ( .A ( ropt_net_142 ) , + .X ( right_width_0_height_0__pin_47_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_901 ( .A ( ropt_net_143 ) , + .X ( top_width_0_height_0__pin_40_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_903 ( .A ( ropt_net_144 ) , + .X ( right_width_0_height_0__pin_44_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_906 ( .A ( ropt_net_145 ) , + .X ( top_width_0_height_0__pin_34_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_908 ( .A ( ropt_net_146 ) , + .X ( right_width_0_height_0__pin_47_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_910 ( .A ( ropt_net_147 ) , + .X ( top_width_0_height_0__pin_39_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_914 ( .A ( ropt_net_148 ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_915 ( .A ( ropt_net_150 ) , + .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_916 ( .A ( ropt_net_151 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_919 ( .A ( ropt_net_152 ) , + .X ( top_width_0_height_0__pin_35_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_920 ( .A ( ropt_net_153 ) , + .X ( right_width_0_height_0__pin_43_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_154 ) , + .X ( bottom_width_0_height_0__pin_50_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49656,14 +53186,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( @@ -49688,7 +53218,7 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49706,58 +53236,74 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y81600 ( @@ -49766,47 +53312,45 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x878600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x975200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49816,89 +53360,83 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x970600y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x938400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1058000y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1067200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49908,26 +53446,38 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x979800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y244800 ( @@ -49936,304 +53486,300 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x970600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1053400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_2!x667000y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1039600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1067200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x910800y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x929200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x961400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y380800 ( +sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_4!x1113200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y435200 ( 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) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1007400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1016600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x124200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1090200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y489600 ( @@ -50242,108 +53788,96 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x984400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x943000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1053400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1062600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1012000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1081000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y571200 ( @@ -50352,82 +53886,78 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x970600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x998200y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1090200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x989000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1007400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1067200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y625600 ( @@ -50438,109 +53968,83 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1016600y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1085600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -50552,85 +54056,99 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1007400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1016600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1058000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1090200y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x975200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -50638,96 +54156,100 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1085600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x906200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1016600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x970600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y870400 ( @@ -50736,98 +54258,98 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x970600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y952000 ( @@ -50836,72 +54358,46 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y979200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y979200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y979200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y979200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y979200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y979200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y1006400 ( @@ -50910,31 +54406,41 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y1033600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y1033600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y1033600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y1033600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y1033600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y1033600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y1033600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -50962,14 +54468,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1060800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y1060800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y1060800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y1060800 ( @@ -50994,7 +54500,7 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y1060800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -51011,351 +54517,370 @@ sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y1060800 ( endmodule -module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , ccff_head , - ccff_tail , VDD , VSS ) ; +module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + ccff_head , ccff_tail , sc_head , sc_tail , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; -output [0:7] gfpga_pad_GPIO_A ; -output [0:7] gfpga_pad_GPIO_IE ; -output [0:7] gfpga_pad_GPIO_OE ; -inout [0:7] gfpga_pad_GPIO_Y ; +input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] ccff_head ; output [0:0] ccff_tail ; +input sc_head ; +output sc_tail ; input VDD ; input VSS ; wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__0__0_ccff_tail ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ; wire [0:19] cbx_1__0__0_chanx_left_out ; wire [0:19] cbx_1__0__0_chanx_right_out ; -wire [0:0] cbx_1__0__0_top_grid_pin_16_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_17_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_18_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_19_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_20_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_21_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_22_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_23_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_24_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_25_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_26_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_27_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_28_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_29_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_30_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_31_ ; wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__0__1_ccff_tail ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ; wire [0:19] cbx_1__0__1_chanx_left_out ; wire [0:19] cbx_1__0__1_chanx_right_out ; -wire [0:0] cbx_1__0__1_top_grid_pin_16_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_17_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_18_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_19_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_20_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_21_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_22_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_23_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_24_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_25_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_26_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_27_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_28_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_29_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_30_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_31_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ; wire [0:0] cbx_1__1__0_ccff_tail ; wire [0:19] cbx_1__1__0_chanx_left_out ; wire [0:19] cbx_1__1__0_chanx_right_out ; -wire [0:0] cbx_1__1__0_top_grid_pin_16_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_17_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_18_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_19_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_20_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_21_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_22_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_23_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_24_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_25_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_26_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_27_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_28_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_29_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_30_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_31_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ; wire [0:0] cbx_1__1__1_ccff_tail ; wire [0:19] cbx_1__1__1_chanx_left_out ; wire [0:19] cbx_1__1__1_chanx_right_out ; -wire [0:0] cbx_1__1__1_top_grid_pin_16_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_17_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_18_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_19_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_20_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_21_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_22_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_23_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_24_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_25_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_26_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_27_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_28_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_29_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_30_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_31_ ; -wire [0:0] cbx_1__2__0_ccff_tail ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_9_ ; wire [0:19] cbx_1__2__0_chanx_left_out ; wire [0:19] cbx_1__2__0_chanx_right_out ; wire [0:0] cbx_1__2__0_top_grid_pin_0_ ; -wire [0:0] cbx_1__2__1_ccff_tail ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_9_ ; wire [0:19] cbx_1__2__1_chanx_left_out ; wire [0:19] cbx_1__2__1_chanx_right_out ; wire [0:0] cbx_1__2__1_top_grid_pin_0_ ; -wire [0:0] cby_0__1__0_ccff_tail ; wire [0:19] cby_0__1__0_chany_bottom_out ; wire [0:19] cby_0__1__0_chany_top_out ; wire [0:0] cby_0__1__0_left_grid_pin_0_ ; -wire [0:0] cby_0__1__0_right_grid_pin_52_ ; -wire [0:0] cby_0__1__1_ccff_tail ; wire [0:19] cby_0__1__1_chany_bottom_out ; wire [0:19] cby_0__1__1_chany_top_out ; wire [0:0] cby_0__1__1_left_grid_pin_0_ ; -wire [0:0] cby_0__1__1_right_grid_pin_52_ ; wire [0:0] cby_1__1__0_ccff_tail ; wire [0:19] cby_1__1__0_chany_bottom_out ; wire [0:19] cby_1__1__0_chany_top_out ; -wire [0:0] cby_1__1__0_left_grid_pin_0_ ; -wire [0:0] cby_1__1__0_left_grid_pin_10_ ; -wire [0:0] cby_1__1__0_left_grid_pin_11_ ; -wire [0:0] cby_1__1__0_left_grid_pin_12_ ; -wire [0:0] cby_1__1__0_left_grid_pin_13_ ; -wire [0:0] cby_1__1__0_left_grid_pin_14_ ; -wire [0:0] cby_1__1__0_left_grid_pin_15_ ; -wire [0:0] cby_1__1__0_left_grid_pin_1_ ; -wire [0:0] cby_1__1__0_left_grid_pin_2_ ; -wire [0:0] cby_1__1__0_left_grid_pin_3_ ; -wire [0:0] cby_1__1__0_left_grid_pin_4_ ; -wire [0:0] cby_1__1__0_left_grid_pin_5_ ; -wire [0:0] cby_1__1__0_left_grid_pin_6_ ; -wire [0:0] cby_1__1__0_left_grid_pin_7_ ; -wire [0:0] cby_1__1__0_left_grid_pin_8_ ; -wire [0:0] cby_1__1__0_left_grid_pin_9_ ; -wire [0:0] cby_1__1__0_right_grid_pin_52_ ; +wire [0:0] cby_1__1__0_left_grid_pin_16_ ; +wire [0:0] cby_1__1__0_left_grid_pin_17_ ; +wire [0:0] cby_1__1__0_left_grid_pin_18_ ; +wire [0:0] cby_1__1__0_left_grid_pin_19_ ; +wire [0:0] cby_1__1__0_left_grid_pin_20_ ; +wire [0:0] cby_1__1__0_left_grid_pin_21_ ; +wire [0:0] cby_1__1__0_left_grid_pin_22_ ; +wire [0:0] cby_1__1__0_left_grid_pin_23_ ; +wire [0:0] cby_1__1__0_left_grid_pin_24_ ; +wire [0:0] cby_1__1__0_left_grid_pin_25_ ; +wire [0:0] cby_1__1__0_left_grid_pin_26_ ; +wire [0:0] cby_1__1__0_left_grid_pin_27_ ; +wire [0:0] cby_1__1__0_left_grid_pin_28_ ; +wire [0:0] cby_1__1__0_left_grid_pin_29_ ; +wire [0:0] cby_1__1__0_left_grid_pin_30_ ; +wire [0:0] cby_1__1__0_left_grid_pin_31_ ; wire [0:0] cby_1__1__1_ccff_tail ; wire [0:19] cby_1__1__1_chany_bottom_out ; wire [0:19] cby_1__1__1_chany_top_out ; -wire [0:0] cby_1__1__1_left_grid_pin_0_ ; -wire [0:0] cby_1__1__1_left_grid_pin_10_ ; -wire [0:0] cby_1__1__1_left_grid_pin_11_ ; -wire [0:0] cby_1__1__1_left_grid_pin_12_ ; -wire [0:0] cby_1__1__1_left_grid_pin_13_ ; -wire [0:0] cby_1__1__1_left_grid_pin_14_ ; -wire [0:0] cby_1__1__1_left_grid_pin_15_ ; -wire [0:0] cby_1__1__1_left_grid_pin_1_ ; -wire [0:0] cby_1__1__1_left_grid_pin_2_ ; -wire [0:0] cby_1__1__1_left_grid_pin_3_ ; -wire [0:0] cby_1__1__1_left_grid_pin_4_ ; -wire [0:0] cby_1__1__1_left_grid_pin_5_ ; -wire [0:0] cby_1__1__1_left_grid_pin_6_ ; -wire [0:0] cby_1__1__1_left_grid_pin_7_ ; -wire [0:0] cby_1__1__1_left_grid_pin_8_ ; -wire [0:0] cby_1__1__1_left_grid_pin_9_ ; -wire [0:0] cby_1__1__1_right_grid_pin_52_ ; -wire [0:0] cby_1__1__2_ccff_tail ; -wire [0:19] cby_1__1__2_chany_bottom_out ; -wire [0:19] cby_1__1__2_chany_top_out ; -wire [0:0] cby_1__1__2_left_grid_pin_0_ ; -wire [0:0] cby_1__1__2_left_grid_pin_10_ ; -wire [0:0] cby_1__1__2_left_grid_pin_11_ ; -wire [0:0] cby_1__1__2_left_grid_pin_12_ ; -wire [0:0] cby_1__1__2_left_grid_pin_13_ ; -wire [0:0] cby_1__1__2_left_grid_pin_14_ ; -wire [0:0] cby_1__1__2_left_grid_pin_15_ ; -wire [0:0] cby_1__1__2_left_grid_pin_1_ ; -wire [0:0] cby_1__1__2_left_grid_pin_2_ ; -wire [0:0] cby_1__1__2_left_grid_pin_3_ ; -wire [0:0] cby_1__1__2_left_grid_pin_4_ ; -wire [0:0] cby_1__1__2_left_grid_pin_5_ ; -wire [0:0] cby_1__1__2_left_grid_pin_6_ ; -wire [0:0] cby_1__1__2_left_grid_pin_7_ ; -wire [0:0] cby_1__1__2_left_grid_pin_8_ ; -wire [0:0] cby_1__1__2_left_grid_pin_9_ ; -wire [0:0] cby_1__1__2_right_grid_pin_52_ ; -wire [0:0] cby_1__1__3_ccff_tail ; -wire [0:19] cby_1__1__3_chany_bottom_out ; -wire [0:19] cby_1__1__3_chany_top_out ; -wire [0:0] cby_1__1__3_left_grid_pin_0_ ; -wire [0:0] cby_1__1__3_left_grid_pin_10_ ; -wire [0:0] cby_1__1__3_left_grid_pin_11_ ; -wire [0:0] cby_1__1__3_left_grid_pin_12_ ; -wire [0:0] cby_1__1__3_left_grid_pin_13_ ; -wire [0:0] cby_1__1__3_left_grid_pin_14_ ; -wire [0:0] cby_1__1__3_left_grid_pin_15_ ; -wire [0:0] cby_1__1__3_left_grid_pin_1_ ; -wire [0:0] cby_1__1__3_left_grid_pin_2_ ; -wire [0:0] cby_1__1__3_left_grid_pin_3_ ; -wire [0:0] cby_1__1__3_left_grid_pin_4_ ; -wire [0:0] cby_1__1__3_left_grid_pin_5_ ; -wire [0:0] cby_1__1__3_left_grid_pin_6_ ; -wire [0:0] cby_1__1__3_left_grid_pin_7_ ; -wire [0:0] cby_1__1__3_left_grid_pin_8_ ; -wire [0:0] cby_1__1__3_left_grid_pin_9_ ; -wire [0:0] cby_1__1__3_right_grid_pin_52_ ; +wire [0:0] cby_1__1__1_left_grid_pin_16_ ; +wire [0:0] cby_1__1__1_left_grid_pin_17_ ; +wire [0:0] cby_1__1__1_left_grid_pin_18_ ; +wire [0:0] cby_1__1__1_left_grid_pin_19_ ; +wire [0:0] cby_1__1__1_left_grid_pin_20_ ; +wire [0:0] cby_1__1__1_left_grid_pin_21_ ; +wire [0:0] cby_1__1__1_left_grid_pin_22_ ; +wire [0:0] cby_1__1__1_left_grid_pin_23_ ; +wire [0:0] cby_1__1__1_left_grid_pin_24_ ; +wire [0:0] cby_1__1__1_left_grid_pin_25_ ; +wire [0:0] cby_1__1__1_left_grid_pin_26_ ; +wire [0:0] cby_1__1__1_left_grid_pin_27_ ; +wire [0:0] cby_1__1__1_left_grid_pin_28_ ; +wire [0:0] cby_1__1__1_left_grid_pin_29_ ; +wire [0:0] cby_1__1__1_left_grid_pin_30_ ; +wire [0:0] cby_1__1__1_left_grid_pin_31_ ; +wire [0:19] cby_2__1__0_chany_bottom_out ; +wire [0:19] cby_2__1__0_chany_top_out ; +wire [0:0] cby_2__1__0_left_grid_pin_16_ ; +wire [0:0] cby_2__1__0_left_grid_pin_17_ ; +wire [0:0] cby_2__1__0_left_grid_pin_18_ ; +wire [0:0] cby_2__1__0_left_grid_pin_19_ ; +wire [0:0] cby_2__1__0_left_grid_pin_20_ ; +wire [0:0] cby_2__1__0_left_grid_pin_21_ ; +wire [0:0] cby_2__1__0_left_grid_pin_22_ ; +wire [0:0] cby_2__1__0_left_grid_pin_23_ ; +wire [0:0] cby_2__1__0_left_grid_pin_24_ ; +wire [0:0] cby_2__1__0_left_grid_pin_25_ ; +wire [0:0] cby_2__1__0_left_grid_pin_26_ ; +wire [0:0] cby_2__1__0_left_grid_pin_27_ ; +wire [0:0] cby_2__1__0_left_grid_pin_28_ ; +wire [0:0] cby_2__1__0_left_grid_pin_29_ ; +wire [0:0] cby_2__1__0_left_grid_pin_30_ ; +wire [0:0] cby_2__1__0_left_grid_pin_31_ ; +wire [0:0] cby_2__1__0_right_grid_pin_0_ ; +wire [0:19] cby_2__1__1_chany_bottom_out ; +wire [0:19] cby_2__1__1_chany_top_out ; +wire [0:0] cby_2__1__1_left_grid_pin_16_ ; +wire [0:0] cby_2__1__1_left_grid_pin_17_ ; +wire [0:0] cby_2__1__1_left_grid_pin_18_ ; +wire [0:0] cby_2__1__1_left_grid_pin_19_ ; +wire [0:0] cby_2__1__1_left_grid_pin_20_ ; +wire [0:0] cby_2__1__1_left_grid_pin_21_ ; +wire [0:0] cby_2__1__1_left_grid_pin_22_ ; +wire [0:0] cby_2__1__1_left_grid_pin_23_ ; +wire [0:0] cby_2__1__1_left_grid_pin_24_ ; +wire [0:0] cby_2__1__1_left_grid_pin_25_ ; +wire [0:0] cby_2__1__1_left_grid_pin_26_ ; +wire [0:0] cby_2__1__1_left_grid_pin_27_ ; +wire [0:0] cby_2__1__1_left_grid_pin_28_ ; +wire [0:0] cby_2__1__1_left_grid_pin_29_ ; +wire [0:0] cby_2__1__1_left_grid_pin_30_ ; +wire [0:0] cby_2__1__1_left_grid_pin_31_ ; +wire [0:0] cby_2__1__1_right_grid_pin_0_ ; wire [0:0] direct_interc_0_out ; wire [0:0] direct_interc_1_out ; wire [0:0] direct_interc_2_out ; -wire [0:0] direct_interc_3_out ; -wire [0:0] direct_interc_4_out ; wire [0:0] direct_interc_5_out ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_upper ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_0_ccff_tail ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_upper ; wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_1_ccff_tail ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_2_ccff_tail ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_3_ccff_tail ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_io_bottom_0_ccff_tail ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ; wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ; wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ; wire [0:0] grid_io_bottom_1_ccff_tail ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ; wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ; wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ; wire [0:0] grid_io_left_0_ccff_tail ; wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ; wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ; @@ -51411,422 +54936,341 @@ supply0 VSS ; // grid_clb grid_clb_1__1_ ( - .prog_clk ( { ctsbuf_net_1722 } ) , + .prog_clk ( { ctsbuf_net_1113 } ) , .Test_en ( Test_en ) , .clk ( clk ) , - .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , - .top_width_0_height_0__pin_33_ ( direct_interc_3_out ) , - .right_width_0_height_0__pin_0_ ( cby_1__1__0_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_ ( cby_1__1__0_left_grid_pin_1_ ) , - .right_width_0_height_0__pin_2_ ( cby_1__1__0_left_grid_pin_2_ ) , - .right_width_0_height_0__pin_3_ ( cby_1__1__0_left_grid_pin_3_ ) , - .right_width_0_height_0__pin_4_ ( cby_1__1__0_left_grid_pin_4_ ) , - .right_width_0_height_0__pin_5_ ( cby_1__1__0_left_grid_pin_5_ ) , - .right_width_0_height_0__pin_6_ ( cby_1__1__0_left_grid_pin_6_ ) , - .right_width_0_height_0__pin_7_ ( cby_1__1__0_left_grid_pin_7_ ) , - .right_width_0_height_0__pin_8_ ( cby_1__1__0_left_grid_pin_8_ ) , - .right_width_0_height_0__pin_9_ ( cby_1__1__0_left_grid_pin_9_ ) , - .right_width_0_height_0__pin_10_ ( cby_1__1__0_left_grid_pin_10_ ) , - .right_width_0_height_0__pin_11_ ( cby_1__1__0_left_grid_pin_11_ ) , - .right_width_0_height_0__pin_12_ ( cby_1__1__0_left_grid_pin_12_ ) , - .right_width_0_height_0__pin_13_ ( cby_1__1__0_left_grid_pin_13_ ) , - .right_width_0_height_0__pin_14_ ( cby_1__1__0_left_grid_pin_14_ ) , - .right_width_0_height_0__pin_15_ ( cby_1__1__0_left_grid_pin_15_ ) , - .bottom_width_0_height_0__pin_16_ ( cbx_1__0__0_top_grid_pin_16_ ) , - .bottom_width_0_height_0__pin_17_ ( cbx_1__0__0_top_grid_pin_17_ ) , - .bottom_width_0_height_0__pin_18_ ( cbx_1__0__0_top_grid_pin_18_ ) , - .bottom_width_0_height_0__pin_19_ ( cbx_1__0__0_top_grid_pin_19_ ) , - .bottom_width_0_height_0__pin_20_ ( cbx_1__0__0_top_grid_pin_20_ ) , - .bottom_width_0_height_0__pin_21_ ( cbx_1__0__0_top_grid_pin_21_ ) , - .bottom_width_0_height_0__pin_22_ ( cbx_1__0__0_top_grid_pin_22_ ) , - .bottom_width_0_height_0__pin_23_ ( cbx_1__0__0_top_grid_pin_23_ ) , - .bottom_width_0_height_0__pin_24_ ( cbx_1__0__0_top_grid_pin_24_ ) , - .bottom_width_0_height_0__pin_25_ ( cbx_1__0__0_top_grid_pin_25_ ) , - .bottom_width_0_height_0__pin_26_ ( cbx_1__0__0_top_grid_pin_26_ ) , - .bottom_width_0_height_0__pin_27_ ( cbx_1__0__0_top_grid_pin_27_ ) , - .bottom_width_0_height_0__pin_28_ ( cbx_1__0__0_top_grid_pin_28_ ) , - .bottom_width_0_height_0__pin_29_ ( cbx_1__0__0_top_grid_pin_29_ ) , - .bottom_width_0_height_0__pin_30_ ( cbx_1__0__0_top_grid_pin_30_ ) , - .bottom_width_0_height_0__pin_31_ ( cbx_1__0__0_top_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( cby_0__1__0_right_grid_pin_52_ ) , - .ccff_head ( { ropt_net_31 } ) , - - .right_width_0_height_0__pin_34_upper ( grid_clb_0_right_width_0_height_0__pin_34_upper ) , - .right_width_0_height_0__pin_34_lower ( grid_clb_0_right_width_0_height_0__pin_34_lower ) , - .right_width_0_height_0__pin_35_upper ( grid_clb_0_right_width_0_height_0__pin_35_upper ) , - .right_width_0_height_0__pin_35_lower ( grid_clb_0_right_width_0_height_0__pin_35_lower ) , - .right_width_0_height_0__pin_36_upper ( grid_clb_0_right_width_0_height_0__pin_36_upper ) , - .right_width_0_height_0__pin_36_lower ( grid_clb_0_right_width_0_height_0__pin_36_lower ) , - .right_width_0_height_0__pin_37_upper ( grid_clb_0_right_width_0_height_0__pin_37_upper ) , - .right_width_0_height_0__pin_37_lower ( grid_clb_0_right_width_0_height_0__pin_37_lower ) , - .right_width_0_height_0__pin_38_upper ( grid_clb_0_right_width_0_height_0__pin_38_upper ) , - .right_width_0_height_0__pin_38_lower ( grid_clb_0_right_width_0_height_0__pin_38_lower ) , - .right_width_0_height_0__pin_39_upper ( grid_clb_0_right_width_0_height_0__pin_39_upper ) , - .right_width_0_height_0__pin_39_lower ( grid_clb_0_right_width_0_height_0__pin_39_lower ) , - .right_width_0_height_0__pin_40_upper ( grid_clb_0_right_width_0_height_0__pin_40_upper ) , - .right_width_0_height_0__pin_40_lower ( grid_clb_0_right_width_0_height_0__pin_40_lower ) , - .right_width_0_height_0__pin_41_upper ( grid_clb_0_right_width_0_height_0__pin_41_upper ) , - .right_width_0_height_0__pin_41_lower ( grid_clb_0_right_width_0_height_0__pin_41_lower ) , - .bottom_width_0_height_0__pin_42_upper ( grid_clb_0_bottom_width_0_height_0__pin_42_upper ) , - .bottom_width_0_height_0__pin_42_lower ( grid_clb_0_bottom_width_0_height_0__pin_42_lower ) , - .bottom_width_0_height_0__pin_43_upper ( grid_clb_0_bottom_width_0_height_0__pin_43_upper ) , - .bottom_width_0_height_0__pin_43_lower ( grid_clb_0_bottom_width_0_height_0__pin_43_lower ) , - .bottom_width_0_height_0__pin_44_upper ( grid_clb_0_bottom_width_0_height_0__pin_44_upper ) , - .bottom_width_0_height_0__pin_44_lower ( grid_clb_0_bottom_width_0_height_0__pin_44_lower ) , - .bottom_width_0_height_0__pin_45_upper ( grid_clb_0_bottom_width_0_height_0__pin_45_upper ) , - .bottom_width_0_height_0__pin_45_lower ( grid_clb_0_bottom_width_0_height_0__pin_45_lower ) , - .bottom_width_0_height_0__pin_46_upper ( grid_clb_0_bottom_width_0_height_0__pin_46_upper ) , - .bottom_width_0_height_0__pin_46_lower ( grid_clb_0_bottom_width_0_height_0__pin_46_lower ) , - .bottom_width_0_height_0__pin_47_upper ( grid_clb_0_bottom_width_0_height_0__pin_47_upper ) , - .bottom_width_0_height_0__pin_47_lower ( grid_clb_0_bottom_width_0_height_0__pin_47_lower ) , - .bottom_width_0_height_0__pin_48_upper ( grid_clb_0_bottom_width_0_height_0__pin_48_upper ) , - .bottom_width_0_height_0__pin_48_lower ( grid_clb_0_bottom_width_0_height_0__pin_48_lower ) , - .bottom_width_0_height_0__pin_49_upper ( grid_clb_0_bottom_width_0_height_0__pin_49_upper ) , - .bottom_width_0_height_0__pin_49_lower ( grid_clb_0_bottom_width_0_height_0__pin_49_lower ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , + .top_width_0_height_0__pin_33_ ( { sc_in_wires_0_ } ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ) , + .ccff_head ( grid_io_left_0_ccff_tail ) , + .top_width_0_height_0__pin_34_upper ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , + .top_width_0_height_0__pin_34_lower ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , + .top_width_0_height_0__pin_35_upper ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , + .top_width_0_height_0__pin_35_lower ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , + .right_width_0_height_0__pin_42_upper ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , + .right_width_0_height_0__pin_42_lower ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , + .right_width_0_height_0__pin_43_upper ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , + .right_width_0_height_0__pin_43_lower ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , .bottom_width_0_height_0__pin_51_ ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( grid_clb_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_3_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2 ) , .SC_OUT_BOT ( scff_Wires_5_ ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb grid_clb_1__2_ ( - .prog_clk ( { ctsbuf_net_1318 } ) , + .prog_clk ( { ctsbuf_net_1517 } ) , .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__2__0_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__2__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__2__0_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__2__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__2__0_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__2__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__2__0_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__2__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__2__0_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__2__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , .top_width_0_height_0__pin_33_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ) , - .right_width_0_height_0__pin_0_ ( cby_1__1__1_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_ ( cby_1__1__1_left_grid_pin_1_ ) , - .right_width_0_height_0__pin_2_ ( cby_1__1__1_left_grid_pin_2_ ) , - .right_width_0_height_0__pin_3_ ( cby_1__1__1_left_grid_pin_3_ ) , - .right_width_0_height_0__pin_4_ ( cby_1__1__1_left_grid_pin_4_ ) , - .right_width_0_height_0__pin_5_ ( cby_1__1__1_left_grid_pin_5_ ) , - .right_width_0_height_0__pin_6_ ( cby_1__1__1_left_grid_pin_6_ ) , - .right_width_0_height_0__pin_7_ ( cby_1__1__1_left_grid_pin_7_ ) , - .right_width_0_height_0__pin_8_ ( cby_1__1__1_left_grid_pin_8_ ) , - .right_width_0_height_0__pin_9_ ( cby_1__1__1_left_grid_pin_9_ ) , - .right_width_0_height_0__pin_10_ ( cby_1__1__1_left_grid_pin_10_ ) , - .right_width_0_height_0__pin_11_ ( cby_1__1__1_left_grid_pin_11_ ) , - .right_width_0_height_0__pin_12_ ( cby_1__1__1_left_grid_pin_12_ ) , - .right_width_0_height_0__pin_13_ ( cby_1__1__1_left_grid_pin_13_ ) , - .right_width_0_height_0__pin_14_ ( cby_1__1__1_left_grid_pin_14_ ) , - .right_width_0_height_0__pin_15_ ( cby_1__1__1_left_grid_pin_15_ ) , - .bottom_width_0_height_0__pin_16_ ( cbx_1__1__0_top_grid_pin_16_ ) , - .bottom_width_0_height_0__pin_17_ ( cbx_1__1__0_top_grid_pin_17_ ) , - .bottom_width_0_height_0__pin_18_ ( cbx_1__1__0_top_grid_pin_18_ ) , - .bottom_width_0_height_0__pin_19_ ( cbx_1__1__0_top_grid_pin_19_ ) , - .bottom_width_0_height_0__pin_20_ ( cbx_1__1__0_top_grid_pin_20_ ) , - .bottom_width_0_height_0__pin_21_ ( cbx_1__1__0_top_grid_pin_21_ ) , - .bottom_width_0_height_0__pin_22_ ( cbx_1__1__0_top_grid_pin_22_ ) , - .bottom_width_0_height_0__pin_23_ ( cbx_1__1__0_top_grid_pin_23_ ) , - .bottom_width_0_height_0__pin_24_ ( cbx_1__1__0_top_grid_pin_24_ ) , - .bottom_width_0_height_0__pin_25_ ( cbx_1__1__0_top_grid_pin_25_ ) , - .bottom_width_0_height_0__pin_26_ ( cbx_1__1__0_top_grid_pin_26_ ) , - .bottom_width_0_height_0__pin_27_ ( cbx_1__1__0_top_grid_pin_27_ ) , - .bottom_width_0_height_0__pin_28_ ( cbx_1__1__0_top_grid_pin_28_ ) , - .bottom_width_0_height_0__pin_29_ ( cbx_1__1__0_top_grid_pin_29_ ) , - .bottom_width_0_height_0__pin_30_ ( cbx_1__1__0_top_grid_pin_30_ ) , - .bottom_width_0_height_0__pin_31_ ( cbx_1__1__0_top_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( cby_0__1__1_right_grid_pin_52_ ) , - .ccff_head ( { ropt_net_27 } ) , - - .right_width_0_height_0__pin_34_upper ( grid_clb_1_right_width_0_height_0__pin_34_upper ) , - .right_width_0_height_0__pin_34_lower ( grid_clb_1_right_width_0_height_0__pin_34_lower ) , - .right_width_0_height_0__pin_35_upper ( grid_clb_1_right_width_0_height_0__pin_35_upper ) , - .right_width_0_height_0__pin_35_lower ( grid_clb_1_right_width_0_height_0__pin_35_lower ) , - .right_width_0_height_0__pin_36_upper ( grid_clb_1_right_width_0_height_0__pin_36_upper ) , - .right_width_0_height_0__pin_36_lower ( grid_clb_1_right_width_0_height_0__pin_36_lower ) , - .right_width_0_height_0__pin_37_upper ( grid_clb_1_right_width_0_height_0__pin_37_upper ) , - .right_width_0_height_0__pin_37_lower ( grid_clb_1_right_width_0_height_0__pin_37_lower ) , - .right_width_0_height_0__pin_38_upper ( grid_clb_1_right_width_0_height_0__pin_38_upper ) , - .right_width_0_height_0__pin_38_lower ( grid_clb_1_right_width_0_height_0__pin_38_lower ) , - .right_width_0_height_0__pin_39_upper ( grid_clb_1_right_width_0_height_0__pin_39_upper ) , - .right_width_0_height_0__pin_39_lower ( grid_clb_1_right_width_0_height_0__pin_39_lower ) , - .right_width_0_height_0__pin_40_upper ( grid_clb_1_right_width_0_height_0__pin_40_upper ) , - .right_width_0_height_0__pin_40_lower ( grid_clb_1_right_width_0_height_0__pin_40_lower ) , - .right_width_0_height_0__pin_41_upper ( grid_clb_1_right_width_0_height_0__pin_41_upper ) , - .right_width_0_height_0__pin_41_lower ( grid_clb_1_right_width_0_height_0__pin_41_lower ) , - .bottom_width_0_height_0__pin_42_upper ( grid_clb_1_bottom_width_0_height_0__pin_42_upper ) , - .bottom_width_0_height_0__pin_42_lower ( grid_clb_1_bottom_width_0_height_0__pin_42_lower ) , - .bottom_width_0_height_0__pin_43_upper ( grid_clb_1_bottom_width_0_height_0__pin_43_upper ) , - .bottom_width_0_height_0__pin_43_lower ( grid_clb_1_bottom_width_0_height_0__pin_43_lower ) , - .bottom_width_0_height_0__pin_44_upper ( grid_clb_1_bottom_width_0_height_0__pin_44_upper ) , - .bottom_width_0_height_0__pin_44_lower ( grid_clb_1_bottom_width_0_height_0__pin_44_lower ) , - .bottom_width_0_height_0__pin_45_upper ( grid_clb_1_bottom_width_0_height_0__pin_45_upper ) , - .bottom_width_0_height_0__pin_45_lower ( grid_clb_1_bottom_width_0_height_0__pin_45_lower ) , - .bottom_width_0_height_0__pin_46_upper ( grid_clb_1_bottom_width_0_height_0__pin_46_upper ) , - .bottom_width_0_height_0__pin_46_lower ( grid_clb_1_bottom_width_0_height_0__pin_46_lower ) , - .bottom_width_0_height_0__pin_47_upper ( grid_clb_1_bottom_width_0_height_0__pin_47_upper ) , - .bottom_width_0_height_0__pin_47_lower ( grid_clb_1_bottom_width_0_height_0__pin_47_lower ) , - .bottom_width_0_height_0__pin_48_upper ( grid_clb_1_bottom_width_0_height_0__pin_48_upper ) , - .bottom_width_0_height_0__pin_48_lower ( grid_clb_1_bottom_width_0_height_0__pin_48_lower ) , - .bottom_width_0_height_0__pin_49_upper ( grid_clb_1_bottom_width_0_height_0__pin_49_upper ) , - .bottom_width_0_height_0__pin_49_lower ( grid_clb_1_bottom_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( grid_clb_1_bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( grid_clb_1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ) , + .ccff_head ( grid_io_left_1_ccff_tail ) , + .top_width_0_height_0__pin_34_upper ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , + .top_width_0_height_0__pin_34_lower ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , + .top_width_0_height_0__pin_35_upper ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , + .top_width_0_height_0__pin_35_lower ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , + .right_width_0_height_0__pin_42_upper ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , + .right_width_0_height_0__pin_42_lower ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , + .right_width_0_height_0__pin_43_upper ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , + .right_width_0_height_0__pin_43_lower ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( { sc_out_wires_0_ } ) , + .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb grid_clb_2__1_ ( - .prog_clk ( { ctsbuf_net_1116 } ) , + .prog_clk ( { ctsbuf_net_57 } ) , .Test_en ( Test_en ) , .clk ( clk ) , - .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , - .top_width_0_height_0__pin_33_ ( direct_interc_4_out ) , - .right_width_0_height_0__pin_0_ ( cby_1__1__2_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_ ( cby_1__1__2_left_grid_pin_1_ ) , - .right_width_0_height_0__pin_2_ ( cby_1__1__2_left_grid_pin_2_ ) , - .right_width_0_height_0__pin_3_ ( cby_1__1__2_left_grid_pin_3_ ) , - .right_width_0_height_0__pin_4_ ( cby_1__1__2_left_grid_pin_4_ ) , - .right_width_0_height_0__pin_5_ ( cby_1__1__2_left_grid_pin_5_ ) , - .right_width_0_height_0__pin_6_ ( cby_1__1__2_left_grid_pin_6_ ) , - .right_width_0_height_0__pin_7_ ( cby_1__1__2_left_grid_pin_7_ ) , - .right_width_0_height_0__pin_8_ ( cby_1__1__2_left_grid_pin_8_ ) , - .right_width_0_height_0__pin_9_ ( cby_1__1__2_left_grid_pin_9_ ) , - .right_width_0_height_0__pin_10_ ( cby_1__1__2_left_grid_pin_10_ ) , - .right_width_0_height_0__pin_11_ ( cby_1__1__2_left_grid_pin_11_ ) , - .right_width_0_height_0__pin_12_ ( cby_1__1__2_left_grid_pin_12_ ) , - .right_width_0_height_0__pin_13_ ( cby_1__1__2_left_grid_pin_13_ ) , - .right_width_0_height_0__pin_14_ ( cby_1__1__2_left_grid_pin_14_ ) , - .right_width_0_height_0__pin_15_ ( cby_1__1__2_left_grid_pin_15_ ) , - .bottom_width_0_height_0__pin_16_ ( cbx_1__0__1_top_grid_pin_16_ ) , - .bottom_width_0_height_0__pin_17_ ( cbx_1__0__1_top_grid_pin_17_ ) , - .bottom_width_0_height_0__pin_18_ ( cbx_1__0__1_top_grid_pin_18_ ) , - .bottom_width_0_height_0__pin_19_ ( cbx_1__0__1_top_grid_pin_19_ ) , - .bottom_width_0_height_0__pin_20_ ( cbx_1__0__1_top_grid_pin_20_ ) , - .bottom_width_0_height_0__pin_21_ ( cbx_1__0__1_top_grid_pin_21_ ) , - .bottom_width_0_height_0__pin_22_ ( cbx_1__0__1_top_grid_pin_22_ ) , - .bottom_width_0_height_0__pin_23_ ( cbx_1__0__1_top_grid_pin_23_ ) , - .bottom_width_0_height_0__pin_24_ ( cbx_1__0__1_top_grid_pin_24_ ) , - .bottom_width_0_height_0__pin_25_ ( cbx_1__0__1_top_grid_pin_25_ ) , - .bottom_width_0_height_0__pin_26_ ( cbx_1__0__1_top_grid_pin_26_ ) , - .bottom_width_0_height_0__pin_27_ ( cbx_1__0__1_top_grid_pin_27_ ) , - .bottom_width_0_height_0__pin_28_ ( cbx_1__0__1_top_grid_pin_28_ ) , - .bottom_width_0_height_0__pin_29_ ( cbx_1__0__1_top_grid_pin_29_ ) , - .bottom_width_0_height_0__pin_30_ ( cbx_1__0__1_top_grid_pin_30_ ) , - .bottom_width_0_height_0__pin_31_ ( cbx_1__0__1_top_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( cby_1__1__0_right_grid_pin_52_ ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , + .top_width_0_height_0__pin_33_ ( { sc_in_wires_1_ } ) , + .right_width_0_height_0__pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_2__1__0_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_2__1__0_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_2__1__0_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_2__1__0_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_2__1__0_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_2__1__0_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_2__1__0_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_2__1__0_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_2__1__0_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_2__1__0_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_2__1__0_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_2__1__0_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_2__1__0_left_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ) , .ccff_head ( cby_1__1__0_ccff_tail ) , - .right_width_0_height_0__pin_34_upper ( grid_clb_2_right_width_0_height_0__pin_34_upper ) , - .right_width_0_height_0__pin_34_lower ( grid_clb_2_right_width_0_height_0__pin_34_lower ) , - .right_width_0_height_0__pin_35_upper ( grid_clb_2_right_width_0_height_0__pin_35_upper ) , - .right_width_0_height_0__pin_35_lower ( grid_clb_2_right_width_0_height_0__pin_35_lower ) , - .right_width_0_height_0__pin_36_upper ( grid_clb_2_right_width_0_height_0__pin_36_upper ) , - .right_width_0_height_0__pin_36_lower ( grid_clb_2_right_width_0_height_0__pin_36_lower ) , - .right_width_0_height_0__pin_37_upper ( grid_clb_2_right_width_0_height_0__pin_37_upper ) , - .right_width_0_height_0__pin_37_lower ( grid_clb_2_right_width_0_height_0__pin_37_lower ) , - .right_width_0_height_0__pin_38_upper ( grid_clb_2_right_width_0_height_0__pin_38_upper ) , - .right_width_0_height_0__pin_38_lower ( grid_clb_2_right_width_0_height_0__pin_38_lower ) , - .right_width_0_height_0__pin_39_upper ( grid_clb_2_right_width_0_height_0__pin_39_upper ) , - .right_width_0_height_0__pin_39_lower ( grid_clb_2_right_width_0_height_0__pin_39_lower ) , - .right_width_0_height_0__pin_40_upper ( grid_clb_2_right_width_0_height_0__pin_40_upper ) , - .right_width_0_height_0__pin_40_lower ( grid_clb_2_right_width_0_height_0__pin_40_lower ) , - .right_width_0_height_0__pin_41_upper ( grid_clb_2_right_width_0_height_0__pin_41_upper ) , - .right_width_0_height_0__pin_41_lower ( grid_clb_2_right_width_0_height_0__pin_41_lower ) , - .bottom_width_0_height_0__pin_42_upper ( grid_clb_2_bottom_width_0_height_0__pin_42_upper ) , - .bottom_width_0_height_0__pin_42_lower ( grid_clb_2_bottom_width_0_height_0__pin_42_lower ) , - .bottom_width_0_height_0__pin_43_upper ( grid_clb_2_bottom_width_0_height_0__pin_43_upper ) , - .bottom_width_0_height_0__pin_43_lower ( grid_clb_2_bottom_width_0_height_0__pin_43_lower ) , - .bottom_width_0_height_0__pin_44_upper ( grid_clb_2_bottom_width_0_height_0__pin_44_upper ) , - .bottom_width_0_height_0__pin_44_lower ( grid_clb_2_bottom_width_0_height_0__pin_44_lower ) , - .bottom_width_0_height_0__pin_45_upper ( grid_clb_2_bottom_width_0_height_0__pin_45_upper ) , - .bottom_width_0_height_0__pin_45_lower ( grid_clb_2_bottom_width_0_height_0__pin_45_lower ) , - .bottom_width_0_height_0__pin_46_upper ( grid_clb_2_bottom_width_0_height_0__pin_46_upper ) , - .bottom_width_0_height_0__pin_46_lower ( grid_clb_2_bottom_width_0_height_0__pin_46_lower ) , - .bottom_width_0_height_0__pin_47_upper ( grid_clb_2_bottom_width_0_height_0__pin_47_upper ) , - .bottom_width_0_height_0__pin_47_lower ( grid_clb_2_bottom_width_0_height_0__pin_47_lower ) , - .bottom_width_0_height_0__pin_48_upper ( grid_clb_2_bottom_width_0_height_0__pin_48_upper ) , - .bottom_width_0_height_0__pin_48_lower ( grid_clb_2_bottom_width_0_height_0__pin_48_lower ) , - .bottom_width_0_height_0__pin_49_upper ( grid_clb_2_bottom_width_0_height_0__pin_49_upper ) , - .bottom_width_0_height_0__pin_49_lower ( grid_clb_2_bottom_width_0_height_0__pin_49_lower ) , + .top_width_0_height_0__pin_34_upper ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , + .top_width_0_height_0__pin_34_lower ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , + .top_width_0_height_0__pin_35_upper ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , + .top_width_0_height_0__pin_35_lower ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , + .right_width_0_height_0__pin_42_upper ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , + .right_width_0_height_0__pin_42_lower ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , + .right_width_0_height_0__pin_43_upper ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , + .right_width_0_height_0__pin_43_lower ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , .bottom_width_0_height_0__pin_51_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( grid_clb_2_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( grid_clb_2_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_5 ) , .SC_IN_BOT ( scff_Wires_8_ ) , + .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb grid_clb_2__2_ ( - .prog_clk ( { ctsbuf_net_510 } ) , + .prog_clk ( { ctsbuf_net_911 } ) , .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__2__1_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__2__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__2__1_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__2__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__2__1_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__2__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__2__1_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__2__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__2__1_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__2__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , .top_width_0_height_0__pin_33_ ( direct_interc_5_out ) , - .right_width_0_height_0__pin_0_ ( cby_1__1__3_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_ ( cby_1__1__3_left_grid_pin_1_ ) , - .right_width_0_height_0__pin_2_ ( cby_1__1__3_left_grid_pin_2_ ) , - .right_width_0_height_0__pin_3_ ( cby_1__1__3_left_grid_pin_3_ ) , - .right_width_0_height_0__pin_4_ ( cby_1__1__3_left_grid_pin_4_ ) , - .right_width_0_height_0__pin_5_ ( cby_1__1__3_left_grid_pin_5_ ) , - .right_width_0_height_0__pin_6_ ( cby_1__1__3_left_grid_pin_6_ ) , - .right_width_0_height_0__pin_7_ ( cby_1__1__3_left_grid_pin_7_ ) , - .right_width_0_height_0__pin_8_ ( cby_1__1__3_left_grid_pin_8_ ) , - .right_width_0_height_0__pin_9_ ( cby_1__1__3_left_grid_pin_9_ ) , - .right_width_0_height_0__pin_10_ ( cby_1__1__3_left_grid_pin_10_ ) , - .right_width_0_height_0__pin_11_ ( cby_1__1__3_left_grid_pin_11_ ) , - .right_width_0_height_0__pin_12_ ( cby_1__1__3_left_grid_pin_12_ ) , - .right_width_0_height_0__pin_13_ ( cby_1__1__3_left_grid_pin_13_ ) , - .right_width_0_height_0__pin_14_ ( cby_1__1__3_left_grid_pin_14_ ) , - .right_width_0_height_0__pin_15_ ( cby_1__1__3_left_grid_pin_15_ ) , - .bottom_width_0_height_0__pin_16_ ( cbx_1__1__1_top_grid_pin_16_ ) , - .bottom_width_0_height_0__pin_17_ ( cbx_1__1__1_top_grid_pin_17_ ) , - .bottom_width_0_height_0__pin_18_ ( cbx_1__1__1_top_grid_pin_18_ ) , - .bottom_width_0_height_0__pin_19_ ( cbx_1__1__1_top_grid_pin_19_ ) , - .bottom_width_0_height_0__pin_20_ ( cbx_1__1__1_top_grid_pin_20_ ) , - .bottom_width_0_height_0__pin_21_ ( cbx_1__1__1_top_grid_pin_21_ ) , - .bottom_width_0_height_0__pin_22_ ( cbx_1__1__1_top_grid_pin_22_ ) , - .bottom_width_0_height_0__pin_23_ ( cbx_1__1__1_top_grid_pin_23_ ) , - .bottom_width_0_height_0__pin_24_ ( cbx_1__1__1_top_grid_pin_24_ ) , - .bottom_width_0_height_0__pin_25_ ( cbx_1__1__1_top_grid_pin_25_ ) , - .bottom_width_0_height_0__pin_26_ ( cbx_1__1__1_top_grid_pin_26_ ) , - .bottom_width_0_height_0__pin_27_ ( cbx_1__1__1_top_grid_pin_27_ ) , - .bottom_width_0_height_0__pin_28_ ( cbx_1__1__1_top_grid_pin_28_ ) , - .bottom_width_0_height_0__pin_29_ ( cbx_1__1__1_top_grid_pin_29_ ) , - .bottom_width_0_height_0__pin_30_ ( cbx_1__1__1_top_grid_pin_30_ ) , - .bottom_width_0_height_0__pin_31_ ( cbx_1__1__1_top_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( cby_1__1__1_right_grid_pin_52_ ) , + .right_width_0_height_0__pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_2__1__1_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_2__1__1_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_2__1__1_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_2__1__1_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_2__1__1_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_2__1__1_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_2__1__1_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_2__1__1_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_2__1__1_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_2__1__1_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_2__1__1_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_2__1__1_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_2__1__1_left_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ) , .ccff_head ( cby_1__1__1_ccff_tail ) , - .right_width_0_height_0__pin_34_upper ( grid_clb_3_right_width_0_height_0__pin_34_upper ) , - .right_width_0_height_0__pin_34_lower ( grid_clb_3_right_width_0_height_0__pin_34_lower ) , - .right_width_0_height_0__pin_35_upper ( grid_clb_3_right_width_0_height_0__pin_35_upper ) , - .right_width_0_height_0__pin_35_lower ( grid_clb_3_right_width_0_height_0__pin_35_lower ) , - .right_width_0_height_0__pin_36_upper ( grid_clb_3_right_width_0_height_0__pin_36_upper ) , - .right_width_0_height_0__pin_36_lower ( grid_clb_3_right_width_0_height_0__pin_36_lower ) , - .right_width_0_height_0__pin_37_upper ( grid_clb_3_right_width_0_height_0__pin_37_upper ) , - .right_width_0_height_0__pin_37_lower ( grid_clb_3_right_width_0_height_0__pin_37_lower ) , - .right_width_0_height_0__pin_38_upper ( grid_clb_3_right_width_0_height_0__pin_38_upper ) , - .right_width_0_height_0__pin_38_lower ( grid_clb_3_right_width_0_height_0__pin_38_lower ) , - .right_width_0_height_0__pin_39_upper ( grid_clb_3_right_width_0_height_0__pin_39_upper ) , - .right_width_0_height_0__pin_39_lower ( grid_clb_3_right_width_0_height_0__pin_39_lower ) , - .right_width_0_height_0__pin_40_upper ( grid_clb_3_right_width_0_height_0__pin_40_upper ) , - .right_width_0_height_0__pin_40_lower ( grid_clb_3_right_width_0_height_0__pin_40_lower ) , - .right_width_0_height_0__pin_41_upper ( grid_clb_3_right_width_0_height_0__pin_41_upper ) , - .right_width_0_height_0__pin_41_lower ( grid_clb_3_right_width_0_height_0__pin_41_lower ) , - .bottom_width_0_height_0__pin_42_upper ( grid_clb_3_bottom_width_0_height_0__pin_42_upper ) , - .bottom_width_0_height_0__pin_42_lower ( grid_clb_3_bottom_width_0_height_0__pin_42_lower ) , - .bottom_width_0_height_0__pin_43_upper ( grid_clb_3_bottom_width_0_height_0__pin_43_upper ) , - .bottom_width_0_height_0__pin_43_lower ( grid_clb_3_bottom_width_0_height_0__pin_43_lower ) , - .bottom_width_0_height_0__pin_44_upper ( grid_clb_3_bottom_width_0_height_0__pin_44_upper ) , - .bottom_width_0_height_0__pin_44_lower ( grid_clb_3_bottom_width_0_height_0__pin_44_lower ) , - .bottom_width_0_height_0__pin_45_upper ( grid_clb_3_bottom_width_0_height_0__pin_45_upper ) , - .bottom_width_0_height_0__pin_45_lower ( grid_clb_3_bottom_width_0_height_0__pin_45_lower ) , - .bottom_width_0_height_0__pin_46_upper ( grid_clb_3_bottom_width_0_height_0__pin_46_upper ) , - .bottom_width_0_height_0__pin_46_lower ( grid_clb_3_bottom_width_0_height_0__pin_46_lower ) , - .bottom_width_0_height_0__pin_47_upper ( grid_clb_3_bottom_width_0_height_0__pin_47_upper ) , - .bottom_width_0_height_0__pin_47_lower ( grid_clb_3_bottom_width_0_height_0__pin_47_lower ) , - .bottom_width_0_height_0__pin_48_upper ( grid_clb_3_bottom_width_0_height_0__pin_48_upper ) , - .bottom_width_0_height_0__pin_48_lower ( grid_clb_3_bottom_width_0_height_0__pin_48_lower ) , - .bottom_width_0_height_0__pin_49_upper ( grid_clb_3_bottom_width_0_height_0__pin_49_upper ) , - .bottom_width_0_height_0__pin_49_lower ( grid_clb_3_bottom_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( grid_clb_3_bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( grid_clb_3_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_io_top grid_io_top_1__3_ ( - .prog_clk ( { ctsbuf_net_914 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[0] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[0] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[0] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[0] ) , - .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , - .ccff_head ( cbx_1__2__0_ccff_tail ) , - .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , - .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_top_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_io_top grid_io_top_2__3_ ( - .prog_clk ( { ctsbuf_net_38 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[1] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[1] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[1] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[1] ) , - .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , - .ccff_head ( cbx_1__2__1_ccff_tail ) , - .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , - .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_top_1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_io_right grid_io_right_3__1_ ( - .prog_clk ( { ctsbuf_net_49 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[2] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[2] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[2] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[2] ) , - .left_width_0_height_0__pin_0_ ( cby_1__1__2_right_grid_pin_52_ ) , - .ccff_head ( cby_1__1__2_ccff_tail ) , - .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_right_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_io_right grid_io_right_3__2_ ( - .prog_clk ( { ctsbuf_net_16 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[3] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[3] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[3] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[3] ) , - .left_width_0_height_0__pin_0_ ( cby_1__1__3_right_grid_pin_52_ ) , - .ccff_head ( cby_1__1__3_ccff_tail ) , - .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_right_1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_io_bottom grid_io_bottom_1__0_ ( - .prog_clk ( { ctsbuf_net_611 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[4] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[4] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[4] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[4] ) , - .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , - .ccff_head ( cbx_1__0__0_ccff_tail ) , - .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , - .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_bottom_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_io_bottom grid_io_bottom_2__0_ ( - .prog_clk ( { ctsbuf_net_27 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[5] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[5] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[5] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[5] ) , - .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , - .ccff_head ( cbx_1__0__1_ccff_tail ) , - .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , - .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_bottom_1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_io_left grid_io_left_0__1_ ( - .prog_clk ( { ctsbuf_net_1520 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[6] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[6] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[6] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[6] ) , - .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , - .ccff_head ( cby_0__1__0_ccff_tail ) , - .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_left_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_io_left grid_io_left_0__2_ ( - .prog_clk ( { ctsbuf_net_1419 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[7] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[7] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[7] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[7] ) , - .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , - .ccff_head ( cby_0__1__1_ccff_tail ) , - .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_left_1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .top_width_0_height_0__pin_34_upper ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , + .top_width_0_height_0__pin_34_lower ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , + .top_width_0_height_0__pin_35_upper ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , + .top_width_0_height_0__pin_35_lower ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , + .right_width_0_height_0__pin_42_upper ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , + .right_width_0_height_0__pin_42_lower ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , + .right_width_0_height_0__pin_43_upper ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , + .right_width_0_height_0__pin_43_lower ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( { sc_out_wires_1_ } ) , + .ccff_tail ( grid_clb_3_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7 ) , .SC_IN_BOT ( scff_Wires_10_ ) , + .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0_ sb_0__0_ ( - .prog_clk ( { ctsbuf_net_1520 } ) , + .prog_clk ( { ctsbuf_net_1315 } ) , .chany_top_in ( cby_0__1__0_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , - .right_top_grid_pin_42_ ( grid_clb_0_bottom_width_0_height_0__pin_42_upper ) , - .right_top_grid_pin_43_ ( grid_clb_0_bottom_width_0_height_0__pin_43_upper ) , - .right_top_grid_pin_44_ ( grid_clb_0_bottom_width_0_height_0__pin_44_upper ) , - .right_top_grid_pin_45_ ( grid_clb_0_bottom_width_0_height_0__pin_45_upper ) , - .right_top_grid_pin_46_ ( grid_clb_0_bottom_width_0_height_0__pin_46_upper ) , - .right_top_grid_pin_47_ ( grid_clb_0_bottom_width_0_height_0__pin_47_upper ) , - .right_top_grid_pin_48_ ( grid_clb_0_bottom_width_0_height_0__pin_48_upper ) , - .right_top_grid_pin_49_ ( grid_clb_0_bottom_width_0_height_0__pin_49_upper ) , .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , .ccff_head ( grid_io_bottom_0_ccff_tail ) , .chany_top_out ( sb_0__0__0_chany_top_out ) , .chanx_right_out ( sb_0__0__0_chanx_right_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1_ sb_0__1_ ( - .prog_clk ( { p_abuf0 } ) , + .prog_clk ( { ctsbuf_net_1315 } ) , .chany_top_in ( cby_0__1__1_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , - .right_top_grid_pin_42_ ( grid_clb_1_bottom_width_0_height_0__pin_42_upper ) , - .right_top_grid_pin_43_ ( grid_clb_1_bottom_width_0_height_0__pin_43_upper ) , - .right_top_grid_pin_44_ ( grid_clb_1_bottom_width_0_height_0__pin_44_upper ) , - .right_top_grid_pin_45_ ( grid_clb_1_bottom_width_0_height_0__pin_45_upper ) , - .right_top_grid_pin_46_ ( grid_clb_1_bottom_width_0_height_0__pin_46_upper ) , - .right_top_grid_pin_47_ ( grid_clb_1_bottom_width_0_height_0__pin_47_upper ) , - .right_top_grid_pin_48_ ( grid_clb_1_bottom_width_0_height_0__pin_48_upper ) , - .right_top_grid_pin_49_ ( grid_clb_1_bottom_width_0_height_0__pin_49_upper ) , + .right_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , + .right_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , .chany_bottom_in ( cby_0__1__0_chany_top_out ) , .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , .ccff_head ( cbx_1__1__0_ccff_tail ) , @@ -51835,89 +55279,97 @@ sb_0__1_ sb_0__1_ ( .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , .ccff_tail ( sb_0__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2_ sb_0__2_ ( - .prog_clk ( { ctsbuf_net_1419 } ) , + .prog_clk ( { ctsbuf_net_1012 } ) , .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , + .right_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , .chany_bottom_in ( cby_0__1__1_chany_top_out ) , .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , .ccff_head ( grid_io_top_0_ccff_tail ) , .chanx_right_out ( sb_0__2__0_chanx_right_out ) , .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , - .ccff_tail ( sb_0__2__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( sb_0__2__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_9 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_10 ) , .SC_OUT_BOT ( scff_Wires_0_ ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0_ sb_1__0_ ( - .prog_clk ( { ctsbuf_net_813 } ) , + .prog_clk ( { ctsbuf_net_79 } ) , .chany_top_in ( cby_1__1__0_chany_bottom_out ) , - .top_left_grid_pin_34_ ( grid_clb_0_right_width_0_height_0__pin_34_lower ) , - .top_left_grid_pin_35_ ( grid_clb_0_right_width_0_height_0__pin_35_lower ) , - .top_left_grid_pin_36_ ( grid_clb_0_right_width_0_height_0__pin_36_lower ) , - .top_left_grid_pin_37_ ( grid_clb_0_right_width_0_height_0__pin_37_lower ) , - .top_left_grid_pin_38_ ( grid_clb_0_right_width_0_height_0__pin_38_lower ) , - .top_left_grid_pin_39_ ( grid_clb_0_right_width_0_height_0__pin_39_lower ) , - .top_left_grid_pin_40_ ( grid_clb_0_right_width_0_height_0__pin_40_lower ) , - .top_left_grid_pin_41_ ( grid_clb_0_right_width_0_height_0__pin_41_lower ) , + .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , + .top_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , + .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , - .right_top_grid_pin_42_ ( grid_clb_2_bottom_width_0_height_0__pin_42_upper ) , - .right_top_grid_pin_43_ ( grid_clb_2_bottom_width_0_height_0__pin_43_upper ) , - .right_top_grid_pin_44_ ( grid_clb_2_bottom_width_0_height_0__pin_44_upper ) , - .right_top_grid_pin_45_ ( grid_clb_2_bottom_width_0_height_0__pin_45_upper ) , - .right_top_grid_pin_46_ ( grid_clb_2_bottom_width_0_height_0__pin_46_upper ) , - .right_top_grid_pin_47_ ( grid_clb_2_bottom_width_0_height_0__pin_47_upper ) , - .right_top_grid_pin_48_ ( grid_clb_2_bottom_width_0_height_0__pin_48_upper ) , - .right_top_grid_pin_49_ ( grid_clb_2_bottom_width_0_height_0__pin_49_upper ) , .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , - .left_top_grid_pin_42_ ( grid_clb_0_bottom_width_0_height_0__pin_42_lower ) , - .left_top_grid_pin_43_ ( grid_clb_0_bottom_width_0_height_0__pin_43_lower ) , - .left_top_grid_pin_44_ ( grid_clb_0_bottom_width_0_height_0__pin_44_lower ) , - .left_top_grid_pin_45_ ( grid_clb_0_bottom_width_0_height_0__pin_45_lower ) , - .left_top_grid_pin_46_ ( grid_clb_0_bottom_width_0_height_0__pin_46_lower ) , - .left_top_grid_pin_47_ ( grid_clb_0_bottom_width_0_height_0__pin_47_lower ) , - .left_top_grid_pin_48_ ( grid_clb_0_bottom_width_0_height_0__pin_48_lower ) , - .left_top_grid_pin_49_ ( grid_clb_0_bottom_width_0_height_0__pin_49_lower ) , .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , .ccff_head ( grid_io_bottom_1_ccff_tail ) , .chany_top_out ( sb_1__0__0_chany_top_out ) , .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , - .ccff_tail ( sb_1__0__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_11 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_12 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1_ sb_1__1_ ( - .prog_clk ( { ctsbuf_net_1217 } ) , + .prog_clk ( { ctsbuf_net_1214 } ) , .chany_top_in ( cby_1__1__1_chany_bottom_out ) , - .top_left_grid_pin_34_ ( grid_clb_1_right_width_0_height_0__pin_34_lower ) , - .top_left_grid_pin_35_ ( grid_clb_1_right_width_0_height_0__pin_35_lower ) , - .top_left_grid_pin_36_ ( grid_clb_1_right_width_0_height_0__pin_36_lower ) , - .top_left_grid_pin_37_ ( grid_clb_1_right_width_0_height_0__pin_37_lower ) , - .top_left_grid_pin_38_ ( grid_clb_1_right_width_0_height_0__pin_38_lower ) , - .top_left_grid_pin_39_ ( grid_clb_1_right_width_0_height_0__pin_39_lower ) , - .top_left_grid_pin_40_ ( grid_clb_1_right_width_0_height_0__pin_40_lower ) , - .top_left_grid_pin_41_ ( grid_clb_1_right_width_0_height_0__pin_41_lower ) , + .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , + .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , + .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , - .right_top_grid_pin_42_ ( grid_clb_3_bottom_width_0_height_0__pin_42_upper ) , - .right_top_grid_pin_43_ ( grid_clb_3_bottom_width_0_height_0__pin_43_upper ) , - .right_top_grid_pin_44_ ( grid_clb_3_bottom_width_0_height_0__pin_44_upper ) , - .right_top_grid_pin_45_ ( grid_clb_3_bottom_width_0_height_0__pin_45_upper ) , - .right_top_grid_pin_46_ ( grid_clb_3_bottom_width_0_height_0__pin_46_upper ) , - .right_top_grid_pin_47_ ( grid_clb_3_bottom_width_0_height_0__pin_47_upper ) , - .right_top_grid_pin_48_ ( grid_clb_3_bottom_width_0_height_0__pin_48_upper ) , - .right_top_grid_pin_49_ ( grid_clb_3_bottom_width_0_height_0__pin_49_upper ) , + .right_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , + .right_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , .chany_bottom_in ( cby_1__1__0_chany_top_out ) , - .bottom_left_grid_pin_34_ ( grid_clb_0_right_width_0_height_0__pin_34_upper ) , - .bottom_left_grid_pin_35_ ( grid_clb_0_right_width_0_height_0__pin_35_upper ) , - .bottom_left_grid_pin_36_ ( grid_clb_0_right_width_0_height_0__pin_36_upper ) , - .bottom_left_grid_pin_37_ ( grid_clb_0_right_width_0_height_0__pin_37_upper ) , - .bottom_left_grid_pin_38_ ( grid_clb_0_right_width_0_height_0__pin_38_upper ) , - .bottom_left_grid_pin_39_ ( grid_clb_0_right_width_0_height_0__pin_39_upper ) , - .bottom_left_grid_pin_40_ ( grid_clb_0_right_width_0_height_0__pin_40_upper ) , - .bottom_left_grid_pin_41_ ( grid_clb_0_right_width_0_height_0__pin_41_upper ) , + .bottom_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , + .bottom_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , - .left_top_grid_pin_42_ ( grid_clb_1_bottom_width_0_height_0__pin_42_lower ) , - .left_top_grid_pin_43_ ( grid_clb_1_bottom_width_0_height_0__pin_43_lower ) , - .left_top_grid_pin_44_ ( grid_clb_1_bottom_width_0_height_0__pin_44_lower ) , - .left_top_grid_pin_45_ ( grid_clb_1_bottom_width_0_height_0__pin_45_lower ) , - .left_top_grid_pin_46_ ( grid_clb_1_bottom_width_0_height_0__pin_46_lower ) , - .left_top_grid_pin_47_ ( grid_clb_1_bottom_width_0_height_0__pin_47_lower ) , - .left_top_grid_pin_48_ ( grid_clb_1_bottom_width_0_height_0__pin_48_lower ) , - .left_top_grid_pin_49_ ( grid_clb_1_bottom_width_0_height_0__pin_49_lower ) , + .left_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , + .left_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , .ccff_head ( cbx_1__1__1_ccff_tail ) , .chany_top_out ( sb_1__1__0_chany_top_out ) , .chanx_right_out ( sb_1__1__0_chanx_right_out ) , @@ -51925,341 +55377,475 @@ sb_1__1_ sb_1__1_ ( .chanx_left_out ( sb_1__1__0_chanx_left_out ) , .ccff_tail ( sb_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2_ sb_1__2_ ( - .prog_clk ( { ctsbuf_net_712 } ) , + .prog_clk ( { ctsbuf_net_810 } ) , .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , + .right_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , .chany_bottom_in ( cby_1__1__1_chany_top_out ) , - .bottom_left_grid_pin_34_ ( grid_clb_1_right_width_0_height_0__pin_34_upper ) , - .bottom_left_grid_pin_35_ ( grid_clb_1_right_width_0_height_0__pin_35_upper ) , - .bottom_left_grid_pin_36_ ( grid_clb_1_right_width_0_height_0__pin_36_upper ) , - .bottom_left_grid_pin_37_ ( grid_clb_1_right_width_0_height_0__pin_37_upper ) , - .bottom_left_grid_pin_38_ ( grid_clb_1_right_width_0_height_0__pin_38_upper ) , - .bottom_left_grid_pin_39_ ( grid_clb_1_right_width_0_height_0__pin_39_upper ) , - .bottom_left_grid_pin_40_ ( grid_clb_1_right_width_0_height_0__pin_40_upper ) , - .bottom_left_grid_pin_41_ ( grid_clb_1_right_width_0_height_0__pin_41_upper ) , + .bottom_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , + .bottom_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , .chanx_left_in ( cbx_1__2__0_chanx_right_out ) , - .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .ccff_head ( { ropt_net_29 } ) , + .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , + .left_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , + .ccff_head ( grid_io_top_1_ccff_tail ) , .chanx_right_out ( sb_1__2__0_chanx_right_out ) , .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , .chanx_left_out ( sb_1__2__0_chanx_left_out ) , - .ccff_tail ( sb_1__2__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( sb_1__2__0_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_13 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_14 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_15 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_16 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0_ sb_2__0_ ( - .prog_clk ( { ctsbuf_net_27 } ) , - .chany_top_in ( cby_1__1__2_chany_bottom_out ) , - .top_left_grid_pin_34_ ( grid_clb_2_right_width_0_height_0__pin_34_lower ) , - .top_left_grid_pin_35_ ( grid_clb_2_right_width_0_height_0__pin_35_lower ) , - .top_left_grid_pin_36_ ( grid_clb_2_right_width_0_height_0__pin_36_lower ) , - .top_left_grid_pin_37_ ( grid_clb_2_right_width_0_height_0__pin_37_lower ) , - .top_left_grid_pin_38_ ( grid_clb_2_right_width_0_height_0__pin_38_lower ) , - .top_left_grid_pin_39_ ( grid_clb_2_right_width_0_height_0__pin_39_lower ) , - .top_left_grid_pin_40_ ( grid_clb_2_right_width_0_height_0__pin_40_lower ) , - .top_left_grid_pin_41_ ( grid_clb_2_right_width_0_height_0__pin_41_lower ) , + .prog_clk ( { ctsbuf_net_13 } ) , + .chany_top_in ( cby_2__1__0_chany_bottom_out ) , + .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , + .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , + .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , - .left_top_grid_pin_42_ ( grid_clb_2_bottom_width_0_height_0__pin_42_lower ) , - .left_top_grid_pin_43_ ( grid_clb_2_bottom_width_0_height_0__pin_43_lower ) , - .left_top_grid_pin_44_ ( grid_clb_2_bottom_width_0_height_0__pin_44_lower ) , - .left_top_grid_pin_45_ ( grid_clb_2_bottom_width_0_height_0__pin_45_lower ) , - .left_top_grid_pin_46_ ( grid_clb_2_bottom_width_0_height_0__pin_46_lower ) , - .left_top_grid_pin_47_ ( grid_clb_2_bottom_width_0_height_0__pin_47_lower ) , - .left_top_grid_pin_48_ ( grid_clb_2_bottom_width_0_height_0__pin_48_lower ) , - .left_top_grid_pin_49_ ( grid_clb_2_bottom_width_0_height_0__pin_49_lower ) , .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , .ccff_head ( grid_io_right_0_ccff_tail ) , .chany_top_out ( sb_2__0__0_chany_top_out ) , .chanx_left_out ( sb_2__0__0_chanx_left_out ) , .ccff_tail ( sb_2__0__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1_ sb_2__1_ ( - .prog_clk ( { ctsbuf_net_49 } ) , - .chany_top_in ( cby_1__1__3_chany_bottom_out ) , - .top_left_grid_pin_34_ ( grid_clb_3_right_width_0_height_0__pin_34_lower ) , - .top_left_grid_pin_35_ ( grid_clb_3_right_width_0_height_0__pin_35_lower ) , - .top_left_grid_pin_36_ ( grid_clb_3_right_width_0_height_0__pin_36_lower ) , - .top_left_grid_pin_37_ ( grid_clb_3_right_width_0_height_0__pin_37_lower ) , - .top_left_grid_pin_38_ ( grid_clb_3_right_width_0_height_0__pin_38_lower ) , - .top_left_grid_pin_39_ ( grid_clb_3_right_width_0_height_0__pin_39_lower ) , - .top_left_grid_pin_40_ ( grid_clb_3_right_width_0_height_0__pin_40_lower ) , - .top_left_grid_pin_41_ ( grid_clb_3_right_width_0_height_0__pin_41_lower ) , + .prog_clk ( { ctsbuf_net_68 } ) , + .chany_top_in ( cby_2__1__1_chany_bottom_out ) , + .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , + .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , + .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .chany_bottom_in ( cby_1__1__2_chany_top_out ) , + .chany_bottom_in ( cby_2__1__0_chany_top_out ) , .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .bottom_left_grid_pin_34_ ( grid_clb_2_right_width_0_height_0__pin_34_upper ) , - .bottom_left_grid_pin_35_ ( grid_clb_2_right_width_0_height_0__pin_35_upper ) , - .bottom_left_grid_pin_36_ ( grid_clb_2_right_width_0_height_0__pin_36_upper ) , - .bottom_left_grid_pin_37_ ( grid_clb_2_right_width_0_height_0__pin_37_upper ) , - .bottom_left_grid_pin_38_ ( grid_clb_2_right_width_0_height_0__pin_38_upper ) , - .bottom_left_grid_pin_39_ ( grid_clb_2_right_width_0_height_0__pin_39_upper ) , - .bottom_left_grid_pin_40_ ( grid_clb_2_right_width_0_height_0__pin_40_upper ) , - .bottom_left_grid_pin_41_ ( grid_clb_2_right_width_0_height_0__pin_41_upper ) , + .bottom_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , + .bottom_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , - .left_top_grid_pin_42_ ( grid_clb_3_bottom_width_0_height_0__pin_42_lower ) , - .left_top_grid_pin_43_ ( grid_clb_3_bottom_width_0_height_0__pin_43_lower ) , - .left_top_grid_pin_44_ ( grid_clb_3_bottom_width_0_height_0__pin_44_lower ) , - .left_top_grid_pin_45_ ( grid_clb_3_bottom_width_0_height_0__pin_45_lower ) , - .left_top_grid_pin_46_ ( grid_clb_3_bottom_width_0_height_0__pin_46_lower ) , - .left_top_grid_pin_47_ ( grid_clb_3_bottom_width_0_height_0__pin_47_lower ) , - .left_top_grid_pin_48_ ( grid_clb_3_bottom_width_0_height_0__pin_48_lower ) , - .left_top_grid_pin_49_ ( grid_clb_3_bottom_width_0_height_0__pin_49_lower ) , + .left_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , + .left_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , .ccff_head ( grid_io_right_1_ccff_tail ) , .chany_top_out ( sb_2__1__0_chany_top_out ) , .chany_bottom_out ( sb_2__1__0_chany_bottom_out ) , .chanx_left_out ( sb_2__1__0_chanx_left_out ) , .ccff_tail ( sb_2__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2_ sb_2__2_ ( - .prog_clk ( { ctsbuf_net_16 } ) , - .chany_bottom_in ( cby_1__1__3_chany_top_out ) , + .prog_clk ( { ctsbuf_net_24 } ) , + .chany_bottom_in ( cby_2__1__1_chany_top_out ) , .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .bottom_left_grid_pin_34_ ( grid_clb_3_right_width_0_height_0__pin_34_upper ) , - .bottom_left_grid_pin_35_ ( grid_clb_3_right_width_0_height_0__pin_35_upper ) , - .bottom_left_grid_pin_36_ ( grid_clb_3_right_width_0_height_0__pin_36_upper ) , - .bottom_left_grid_pin_37_ ( grid_clb_3_right_width_0_height_0__pin_37_upper ) , - .bottom_left_grid_pin_38_ ( grid_clb_3_right_width_0_height_0__pin_38_upper ) , - .bottom_left_grid_pin_39_ ( grid_clb_3_right_width_0_height_0__pin_39_upper ) , - .bottom_left_grid_pin_40_ ( grid_clb_3_right_width_0_height_0__pin_40_upper ) , - .bottom_left_grid_pin_41_ ( grid_clb_3_right_width_0_height_0__pin_41_upper ) , + .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , + .bottom_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , .chanx_left_in ( cbx_1__2__1_chanx_right_out ) , .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , + .left_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , .ccff_head ( ccff_head ) , .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , .chanx_left_out ( sb_2__2__0_chanx_left_out ) , - .ccff_tail ( sb_2__2__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( sb_2__2__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_17 ) , .SC_OUT_TOP ( sc_tail ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_18 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0_ cbx_1__0_ ( - .prog_clk ( { ctsbuf_net_611 } ) , + .prog_clk ( { ctsbuf_net_79 } ) , .chanx_left_in ( sb_0__0__0_chanx_right_out ) , .chanx_right_in ( sb_1__0__0_chanx_left_out ) , .ccff_head ( sb_1__0__0_ccff_tail ) , .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , - .top_grid_pin_16_ ( cbx_1__0__0_top_grid_pin_16_ ) , - .top_grid_pin_17_ ( cbx_1__0__0_top_grid_pin_17_ ) , - .top_grid_pin_18_ ( cbx_1__0__0_top_grid_pin_18_ ) , - .top_grid_pin_19_ ( cbx_1__0__0_top_grid_pin_19_ ) , - .top_grid_pin_20_ ( cbx_1__0__0_top_grid_pin_20_ ) , - .top_grid_pin_21_ ( cbx_1__0__0_top_grid_pin_21_ ) , - .top_grid_pin_22_ ( cbx_1__0__0_top_grid_pin_22_ ) , - .top_grid_pin_23_ ( cbx_1__0__0_top_grid_pin_23_ ) , - .top_grid_pin_24_ ( cbx_1__0__0_top_grid_pin_24_ ) , - .top_grid_pin_25_ ( cbx_1__0__0_top_grid_pin_25_ ) , - .top_grid_pin_26_ ( cbx_1__0__0_top_grid_pin_26_ ) , - .top_grid_pin_27_ ( cbx_1__0__0_top_grid_pin_27_ ) , - .top_grid_pin_28_ ( cbx_1__0__0_top_grid_pin_28_ ) , - .top_grid_pin_29_ ( cbx_1__0__0_top_grid_pin_29_ ) , - .top_grid_pin_30_ ( cbx_1__0__0_top_grid_pin_30_ ) , - .top_grid_pin_31_ ( cbx_1__0__0_top_grid_pin_31_ ) , .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , - .ccff_tail ( cbx_1__0__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , + .ccff_tail ( grid_io_bottom_0_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4:9] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4:9] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4:9] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , + .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_19 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_20 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0_ cbx_2__0_ ( - .prog_clk ( { ctsbuf_net_27 } ) , + .prog_clk ( { ctsbuf_net_35 } ) , .chanx_left_in ( sb_1__0__0_chanx_right_out ) , .chanx_right_in ( sb_2__0__0_chanx_left_out ) , .ccff_head ( sb_2__0__0_ccff_tail ) , .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , - .top_grid_pin_16_ ( cbx_1__0__1_top_grid_pin_16_ ) , - .top_grid_pin_17_ ( cbx_1__0__1_top_grid_pin_17_ ) , - .top_grid_pin_18_ ( cbx_1__0__1_top_grid_pin_18_ ) , - .top_grid_pin_19_ ( cbx_1__0__1_top_grid_pin_19_ ) , - .top_grid_pin_20_ ( cbx_1__0__1_top_grid_pin_20_ ) , - .top_grid_pin_21_ ( cbx_1__0__1_top_grid_pin_21_ ) , - .top_grid_pin_22_ ( cbx_1__0__1_top_grid_pin_22_ ) , - .top_grid_pin_23_ ( cbx_1__0__1_top_grid_pin_23_ ) , - .top_grid_pin_24_ ( cbx_1__0__1_top_grid_pin_24_ ) , - .top_grid_pin_25_ ( cbx_1__0__1_top_grid_pin_25_ ) , - .top_grid_pin_26_ ( cbx_1__0__1_top_grid_pin_26_ ) , - .top_grid_pin_27_ ( cbx_1__0__1_top_grid_pin_27_ ) , - .top_grid_pin_28_ ( cbx_1__0__1_top_grid_pin_28_ ) , - .top_grid_pin_29_ ( cbx_1__0__1_top_grid_pin_29_ ) , - .top_grid_pin_30_ ( cbx_1__0__1_top_grid_pin_30_ ) , - .top_grid_pin_31_ ( cbx_1__0__1_top_grid_pin_31_ ) , .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , - .ccff_tail ( cbx_1__0__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , + .ccff_tail ( grid_io_bottom_1_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[10:15] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[10:15] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[10:15] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , + .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_21 ) , + .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_22 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_1__1_ ( - .prog_clk ( { ctsbuf_net_1621 } ) , + .prog_clk ( { ctsbuf_net_1416 } ) , .chanx_left_in ( sb_0__1__0_chanx_right_out ) , .chanx_right_in ( sb_1__1__0_chanx_left_out ) , .ccff_head ( sb_1__1__0_ccff_tail ) , .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , - .top_grid_pin_16_ ( cbx_1__1__0_top_grid_pin_16_ ) , - .top_grid_pin_17_ ( cbx_1__1__0_top_grid_pin_17_ ) , - .top_grid_pin_18_ ( cbx_1__1__0_top_grid_pin_18_ ) , - .top_grid_pin_19_ ( cbx_1__1__0_top_grid_pin_19_ ) , - .top_grid_pin_20_ ( cbx_1__1__0_top_grid_pin_20_ ) , - .top_grid_pin_21_ ( cbx_1__1__0_top_grid_pin_21_ ) , - .top_grid_pin_22_ ( cbx_1__1__0_top_grid_pin_22_ ) , - .top_grid_pin_23_ ( cbx_1__1__0_top_grid_pin_23_ ) , - .top_grid_pin_24_ ( cbx_1__1__0_top_grid_pin_24_ ) , - .top_grid_pin_25_ ( cbx_1__1__0_top_grid_pin_25_ ) , - .top_grid_pin_26_ ( cbx_1__1__0_top_grid_pin_26_ ) , - .top_grid_pin_27_ ( cbx_1__1__0_top_grid_pin_27_ ) , - .top_grid_pin_28_ ( cbx_1__1__0_top_grid_pin_28_ ) , - .top_grid_pin_29_ ( cbx_1__1__0_top_grid_pin_29_ ) , - .top_grid_pin_30_ ( cbx_1__1__0_top_grid_pin_30_ ) , - .top_grid_pin_31_ ( cbx_1__1__0_top_grid_pin_31_ ) , - .ccff_tail ( cbx_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__0_ccff_tail ) , .CLB_SC_IN ( sc_out_wires_0_ ) , + .CLB_SC_OUT ( sc_in_wires_0_ ) , .SC_IN_TOP ( scff_Wires_2_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_23 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_24 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_2__1_ ( - .prog_clk ( { ctsbuf_net_1015 } ) , + .prog_clk ( { ctsbuf_net_68 } ) , .chanx_left_in ( sb_1__1__0_chanx_right_out ) , .chanx_right_in ( sb_2__1__0_chanx_left_out ) , .ccff_head ( sb_2__1__0_ccff_tail ) , .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , - .top_grid_pin_16_ ( cbx_1__1__1_top_grid_pin_16_ ) , - .top_grid_pin_17_ ( cbx_1__1__1_top_grid_pin_17_ ) , - .top_grid_pin_18_ ( cbx_1__1__1_top_grid_pin_18_ ) , - .top_grid_pin_19_ ( cbx_1__1__1_top_grid_pin_19_ ) , - .top_grid_pin_20_ ( cbx_1__1__1_top_grid_pin_20_ ) , - .top_grid_pin_21_ ( cbx_1__1__1_top_grid_pin_21_ ) , - .top_grid_pin_22_ ( cbx_1__1__1_top_grid_pin_22_ ) , - .top_grid_pin_23_ ( cbx_1__1__1_top_grid_pin_23_ ) , - .top_grid_pin_24_ ( cbx_1__1__1_top_grid_pin_24_ ) , - .top_grid_pin_25_ ( cbx_1__1__1_top_grid_pin_25_ ) , - .top_grid_pin_26_ ( cbx_1__1__1_top_grid_pin_26_ ) , - .top_grid_pin_27_ ( cbx_1__1__1_top_grid_pin_27_ ) , - .top_grid_pin_28_ ( cbx_1__1__1_top_grid_pin_28_ ) , - .top_grid_pin_29_ ( cbx_1__1__1_top_grid_pin_29_ ) , - .top_grid_pin_30_ ( cbx_1__1__1_top_grid_pin_30_ ) , - .top_grid_pin_31_ ( cbx_1__1__1_top_grid_pin_31_ ) , - .ccff_tail ( cbx_1__1__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__1_ccff_tail ) , .CLB_SC_IN ( sc_out_wires_1_ ) , + .CLB_SC_OUT ( sc_in_wires_1_ ) , .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_25 ) , + .SC_IN_BOT ( scff_Wires_9_ ) , .SC_OUT_TOP ( scff_Wires_10_ ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_26 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2_ cbx_1__2_ ( - .prog_clk ( { ctsbuf_net_914 } ) , + .prog_clk ( { ctsbuf_net_1012 } ) , .chanx_left_in ( sb_0__2__0_chanx_right_out ) , .chanx_right_in ( sb_1__2__0_chanx_left_out ) , .ccff_head ( sb_1__2__0_ccff_tail ) , .chanx_left_out ( cbx_1__2__0_chanx_left_out ) , .chanx_right_out ( cbx_1__2__0_chanx_right_out ) , .top_grid_pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , - .ccff_tail ( cbx_1__2__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .bottom_grid_pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__2__0_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__2__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__2__0_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__2__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__2__0_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__2__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__2__0_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__2__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__2__0_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__2__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_0_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_27 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_28 ) , .SC_OUT_BOT ( scff_Wires_1_ ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2_ cbx_2__2_ ( - .prog_clk ( { ctsbuf_net_16 } ) , + .prog_clk ( { ctsbuf_net_24 } ) , .chanx_left_in ( sb_1__2__0_chanx_right_out ) , .chanx_right_in ( sb_2__2__0_chanx_left_out ) , .ccff_head ( sb_2__2__0_ccff_tail ) , .chanx_left_out ( cbx_1__2__1_chanx_left_out ) , .chanx_right_out ( cbx_1__2__1_chanx_right_out ) , .top_grid_pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , - .ccff_tail ( cbx_1__2__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .bottom_grid_pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__2__1_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__2__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__2__1_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__2__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__2__1_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__2__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__2__1_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__2__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__2__1_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__2__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_1_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_29 ) , .SC_IN_BOT ( scff_Wires_11_ ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_30 ) , .SC_OUT_BOT ( scff_Wires_12_ ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_0__1_ cby_0__1_ ( - .prog_clk ( { ctsbuf_net_1520 } ) , + .prog_clk ( { ctsbuf_net_1315 } ) , .chany_bottom_in ( sb_0__0__0_chany_top_out ) , .chany_top_in ( sb_0__1__0_chany_bottom_out ) , .ccff_head ( sb_0__1__0_ccff_tail ) , .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , .chany_top_out ( cby_0__1__0_chany_top_out ) , - .right_grid_pin_52_ ( cby_0__1__0_right_grid_pin_52_ ) , .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , - .ccff_tail ( cby_0__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( grid_io_left_0_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[16] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[16] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[16] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_0__1_ cby_0__2_ ( - .prog_clk ( { ctsbuf_net_1419 } ) , + .prog_clk ( { ctsbuf_net_1315 } ) , .chany_bottom_in ( sb_0__1__0_chany_top_out ) , .chany_top_in ( sb_0__2__0_chany_bottom_out ) , .ccff_head ( sb_0__2__0_ccff_tail ) , .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , .chany_top_out ( cby_0__1__1_chany_top_out ) , - .right_grid_pin_52_ ( cby_0__1__1_right_grid_pin_52_ ) , .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , - .ccff_tail ( cby_0__1__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( grid_io_left_1_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[17] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[17] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[17] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__1_ ( - .prog_clk ( { ctsbuf_net_1217 } ) , + .prog_clk ( { ctsbuf_net_79 } ) , .chany_bottom_in ( sb_1__0__0_chany_top_out ) , .chany_top_in ( sb_1__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_0_ccff_tail ) , .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , .chany_top_out ( cby_1__1__0_chany_top_out ) , - .right_grid_pin_52_ ( cby_1__1__0_right_grid_pin_52_ ) , - .left_grid_pin_0_ ( cby_1__1__0_left_grid_pin_0_ ) , - .left_grid_pin_1_ ( cby_1__1__0_left_grid_pin_1_ ) , - .left_grid_pin_2_ ( cby_1__1__0_left_grid_pin_2_ ) , - .left_grid_pin_3_ ( cby_1__1__0_left_grid_pin_3_ ) , - .left_grid_pin_4_ ( cby_1__1__0_left_grid_pin_4_ ) , - .left_grid_pin_5_ ( cby_1__1__0_left_grid_pin_5_ ) , - .left_grid_pin_6_ ( cby_1__1__0_left_grid_pin_6_ ) , - .left_grid_pin_7_ ( cby_1__1__0_left_grid_pin_7_ ) , - .left_grid_pin_8_ ( cby_1__1__0_left_grid_pin_8_ ) , - .left_grid_pin_9_ ( cby_1__1__0_left_grid_pin_9_ ) , - .left_grid_pin_10_ ( cby_1__1__0_left_grid_pin_10_ ) , - .left_grid_pin_11_ ( cby_1__1__0_left_grid_pin_11_ ) , - .left_grid_pin_12_ ( cby_1__1__0_left_grid_pin_12_ ) , - .left_grid_pin_13_ ( cby_1__1__0_left_grid_pin_13_ ) , - .left_grid_pin_14_ ( cby_1__1__0_left_grid_pin_14_ ) , - .left_grid_pin_15_ ( cby_1__1__0_left_grid_pin_15_ ) , + .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__2_ ( - .prog_clk ( { ctsbuf_net_712 } ) , + .prog_clk ( { ctsbuf_net_810 } ) , .chany_bottom_in ( sb_1__1__0_chany_top_out ) , .chany_top_in ( sb_1__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_1_ccff_tail ) , .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , .chany_top_out ( cby_1__1__1_chany_top_out ) , - .right_grid_pin_52_ ( cby_1__1__1_right_grid_pin_52_ ) , - .left_grid_pin_0_ ( cby_1__1__1_left_grid_pin_0_ ) , - .left_grid_pin_1_ ( cby_1__1__1_left_grid_pin_1_ ) , - .left_grid_pin_2_ ( cby_1__1__1_left_grid_pin_2_ ) , - .left_grid_pin_3_ ( cby_1__1__1_left_grid_pin_3_ ) , - .left_grid_pin_4_ ( cby_1__1__1_left_grid_pin_4_ ) , - .left_grid_pin_5_ ( cby_1__1__1_left_grid_pin_5_ ) , - .left_grid_pin_6_ ( cby_1__1__1_left_grid_pin_6_ ) , - .left_grid_pin_7_ ( cby_1__1__1_left_grid_pin_7_ ) , - .left_grid_pin_8_ ( cby_1__1__1_left_grid_pin_8_ ) , - .left_grid_pin_9_ ( cby_1__1__1_left_grid_pin_9_ ) , - .left_grid_pin_10_ ( cby_1__1__1_left_grid_pin_10_ ) , - .left_grid_pin_11_ ( cby_1__1__1_left_grid_pin_11_ ) , - .left_grid_pin_12_ ( cby_1__1__1_left_grid_pin_12_ ) , - .left_grid_pin_13_ ( cby_1__1__1_left_grid_pin_13_ ) , - .left_grid_pin_14_ ( cby_1__1__1_left_grid_pin_14_ ) , - .left_grid_pin_15_ ( cby_1__1__1_left_grid_pin_15_ ) , + .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1_ cby_2__1_ ( - .prog_clk ( { ctsbuf_net_49 } ) , +cby_2__1_ cby_2__1_ ( + .prog_clk ( { ctsbuf_net_13 } ) , .chany_bottom_in ( sb_2__0__0_chany_top_out ) , .chany_top_in ( sb_2__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_2_ccff_tail ) , - .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) , - .chany_top_out ( cby_1__1__2_chany_top_out ) , - .right_grid_pin_52_ ( cby_1__1__2_right_grid_pin_52_ ) , - .left_grid_pin_0_ ( cby_1__1__2_left_grid_pin_0_ ) , - .left_grid_pin_1_ ( cby_1__1__2_left_grid_pin_1_ ) , - .left_grid_pin_2_ ( cby_1__1__2_left_grid_pin_2_ ) , - .left_grid_pin_3_ ( cby_1__1__2_left_grid_pin_3_ ) , - .left_grid_pin_4_ ( cby_1__1__2_left_grid_pin_4_ ) , - .left_grid_pin_5_ ( cby_1__1__2_left_grid_pin_5_ ) , - .left_grid_pin_6_ ( cby_1__1__2_left_grid_pin_6_ ) , - .left_grid_pin_7_ ( cby_1__1__2_left_grid_pin_7_ ) , - .left_grid_pin_8_ ( cby_1__1__2_left_grid_pin_8_ ) , - .left_grid_pin_9_ ( cby_1__1__2_left_grid_pin_9_ ) , - .left_grid_pin_10_ ( cby_1__1__2_left_grid_pin_10_ ) , - .left_grid_pin_11_ ( cby_1__1__2_left_grid_pin_11_ ) , - .left_grid_pin_12_ ( cby_1__1__2_left_grid_pin_12_ ) , - .left_grid_pin_13_ ( cby_1__1__2_left_grid_pin_13_ ) , - .left_grid_pin_14_ ( cby_1__1__2_left_grid_pin_14_ ) , - .left_grid_pin_15_ ( cby_1__1__2_left_grid_pin_15_ ) , - .ccff_tail ( cby_1__1__2_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1_ cby_2__2_ ( - .prog_clk ( { ctsbuf_net_16 } ) , + .chany_bottom_out ( cby_2__1__0_chany_bottom_out ) , + .chany_top_out ( cby_2__1__0_chany_top_out ) , + .right_grid_pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_2__1__0_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_2__1__0_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_2__1__0_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_2__1__0_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_2__1__0_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_2__1__0_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_2__1__0_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_2__1__0_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_2__1__0_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_2__1__0_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_2__1__0_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_2__1__0_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_2__1__0_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_0_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .left_width_0_height_0__pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1_ cby_2__2_ ( + .prog_clk ( { ctsbuf_net_46 } ) , .chany_bottom_in ( sb_2__1__0_chany_top_out ) , .chany_top_in ( sb_2__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_3_ccff_tail ) , - .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) , - .chany_top_out ( cby_1__1__3_chany_top_out ) , - .right_grid_pin_52_ ( cby_1__1__3_right_grid_pin_52_ ) , - .left_grid_pin_0_ ( cby_1__1__3_left_grid_pin_0_ ) , - .left_grid_pin_1_ ( cby_1__1__3_left_grid_pin_1_ ) , - .left_grid_pin_2_ ( cby_1__1__3_left_grid_pin_2_ ) , - .left_grid_pin_3_ ( cby_1__1__3_left_grid_pin_3_ ) , - .left_grid_pin_4_ ( cby_1__1__3_left_grid_pin_4_ ) , - .left_grid_pin_5_ ( cby_1__1__3_left_grid_pin_5_ ) , - .left_grid_pin_6_ ( cby_1__1__3_left_grid_pin_6_ ) , - .left_grid_pin_7_ ( cby_1__1__3_left_grid_pin_7_ ) , - .left_grid_pin_8_ ( cby_1__1__3_left_grid_pin_8_ ) , - .left_grid_pin_9_ ( cby_1__1__3_left_grid_pin_9_ ) , - .left_grid_pin_10_ ( cby_1__1__3_left_grid_pin_10_ ) , - .left_grid_pin_11_ ( cby_1__1__3_left_grid_pin_11_ ) , - .left_grid_pin_12_ ( cby_1__1__3_left_grid_pin_12_ ) , - .left_grid_pin_13_ ( cby_1__1__3_left_grid_pin_13_ ) , - .left_grid_pin_14_ ( cby_1__1__3_left_grid_pin_14_ ) , - .left_grid_pin_15_ ( cby_1__1__3_left_grid_pin_15_ ) , - .ccff_tail ( cby_1__1__3_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .chany_bottom_out ( cby_2__1__1_chany_bottom_out ) , + .chany_top_out ( cby_2__1__1_chany_top_out ) , + .right_grid_pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_2__1__1_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_2__1__1_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_2__1__1_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_2__1__1_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_2__1__1_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_2__1__1_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_2__1__1_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_2__1__1_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_2__1__1_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_2__1__1_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_2__1__1_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_2__1__1_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_2__1__1_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_1_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .left_width_0_height_0__pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; direct_interc_0 direct_interc_0_ ( .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -52269,18 +55855,9 @@ direct_interc_1 direct_interc_1_ ( direct_interc_2 direct_interc_2_ ( .in ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc_3 direct_interc_3_ ( - .in ( grid_clb_1_bottom_width_0_height_0__pin_51_ ) , - .out ( direct_interc_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc_4 direct_interc_4_ ( - .in ( grid_clb_3_bottom_width_0_height_0__pin_51_ ) , - .out ( direct_interc_4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; direct_interc_5 direct_interc_5_ ( .in ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , - .out ( direct_interc_5_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7301 ( - .A ( grid_io_left_1_ccff_tail[0] ) , .X ( ropt_net_25 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .out ( direct_interc_5_out ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_0 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1 ( .VNB ( VSS ) , @@ -54631,1970 +58208,46 @@ sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1173 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1174 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1175 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1176 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1177 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1178 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1179 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1180 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1181 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1182 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1183 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1184 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1185 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1186 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1187 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1188 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1189 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1190 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1191 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1192 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1193 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1194 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1195 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1196 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1197 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1198 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1199 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1200 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1201 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1202 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1203 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1204 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1205 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1206 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1207 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1208 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1209 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1210 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1211 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1212 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1213 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1214 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1215 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1216 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1217 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1218 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1219 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1220 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1221 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1222 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1223 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1224 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1225 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1226 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1227 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1228 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1229 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1230 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1231 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1232 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1233 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1234 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1235 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1236 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1237 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1238 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1239 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1240 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1241 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1242 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1243 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1244 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1245 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1246 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1247 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1248 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1249 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1250 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1251 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1252 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1253 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1254 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1255 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1256 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1257 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1258 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1259 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1260 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1261 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1262 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1263 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1264 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1265 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1266 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1267 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1268 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1269 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1270 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1271 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1272 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1273 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1274 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1275 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1276 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1277 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1278 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1279 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1280 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1281 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1282 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1283 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1284 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1285 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1286 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1287 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1288 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1289 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1290 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1291 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1292 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1293 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1294 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1295 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1296 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1297 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1298 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1299 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1300 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1301 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1302 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1303 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1304 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1305 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1306 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1307 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1308 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1309 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1310 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1311 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1312 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1313 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1314 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1315 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1316 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1317 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1318 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1319 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1320 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1321 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1322 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1323 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1324 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1325 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1326 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1327 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1328 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1329 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1330 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1331 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1332 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1333 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1334 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1335 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1336 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1337 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1338 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1339 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1340 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1341 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1342 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1343 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1344 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1345 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1346 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1347 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1348 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1349 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1350 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1351 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1352 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1353 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1354 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1355 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1356 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1357 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1358 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1359 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1360 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1361 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1362 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1363 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1364 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1365 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1366 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1367 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1368 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1369 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1370 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1371 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1372 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1373 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1374 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1375 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1376 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1377 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1378 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1379 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1380 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1381 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1382 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1383 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1384 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1385 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1386 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1387 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1388 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1389 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1390 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1391 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1392 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1393 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1394 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1395 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1396 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1397 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1398 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1399 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1400 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1401 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1402 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1403 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1404 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1405 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1406 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1407 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1408 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1409 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1410 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1411 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1412 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1413 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1414 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1415 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1416 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1417 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1418 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1419 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1420 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1421 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1422 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1423 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1424 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1425 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1426 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1427 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1428 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1429 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1430 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1431 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1432 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1433 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1434 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1435 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1436 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1437 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1438 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1439 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1440 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1441 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1442 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1443 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1444 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1445 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1446 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1447 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1448 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1449 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1450 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1451 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1452 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1453 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1454 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1455 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1456 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1457 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1458 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1459 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1460 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1461 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1462 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1463 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1464 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1465 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1466 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1467 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1468 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1469 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1470 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1471 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1472 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1473 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1474 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1475 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1476 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1477 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1478 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1479 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1480 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1481 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1482 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1483 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1484 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1485 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1486 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1487 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1488 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1489 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1490 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1491 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1492 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1493 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1494 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1495 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1496 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1497 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1498 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1499 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1500 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1501 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1502 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1503 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1504 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1505 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1506 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1507 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1508 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1509 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1510 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1511 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1512 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1513 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1514 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1515 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1516 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1517 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1518 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1519 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1520 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1521 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1522 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1523 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1524 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1525 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1526 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1527 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1528 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1529 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1530 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1531 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1532 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1533 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1534 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1535 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1536 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1537 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1538 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1539 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1540 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1541 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1542 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1543 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1544 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1545 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1546 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1547 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1548 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1549 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1550 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1551 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1552 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1553 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1554 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1555 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1556 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1557 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1558 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1559 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1560 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1561 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1562 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1563 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1564 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1565 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1566 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1567 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1568 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1569 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1570 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1571 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1572 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1573 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1574 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1575 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1576 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1577 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1578 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1579 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1580 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1581 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1582 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1583 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1584 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1585 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1586 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1587 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1588 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1589 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1590 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1591 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1592 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1593 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1594 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1595 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1596 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1597 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1598 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1599 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1600 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1601 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1602 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1603 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1604 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1605 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1606 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1607 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1608 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1609 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1610 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1611 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1612 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1613 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1614 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1615 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1616 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1617 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1618 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1619 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1620 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1621 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1622 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1623 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1624 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1625 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1626 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1627 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1628 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1629 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1630 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1631 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1632 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1633 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1634 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1635 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1636 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1637 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1638 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1639 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1640 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1641 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1642 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1643 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1644 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1645 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1646 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1647 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1648 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1649 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1650 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1651 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1652 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1653 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1654 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1655 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1656 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1657 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1658 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1659 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1660 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1661 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1662 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1663 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1664 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1665 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1666 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1667 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1668 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1669 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1670 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1671 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1672 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1673 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1674 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1675 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1676 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1677 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1678 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1679 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1680 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1681 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1682 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1683 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1684 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1685 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1686 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1687 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1688 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1689 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1690 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1691 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1692 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1693 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1694 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1695 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1696 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1697 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1698 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1699 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1700 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1701 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1702 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1703 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1704 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1705 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1706 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1707 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1708 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1709 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1710 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1711 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1712 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1713 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1714 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1715 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1716 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1717 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1718 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1719 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1720 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1721 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1722 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1723 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1724 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1725 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1726 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1727 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1728 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1729 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1730 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1731 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1732 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1733 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1734 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1735 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1736 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1737 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1738 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1739 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1740 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1741 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1742 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1743 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1744 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1745 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1746 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1747 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1748 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1749 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1750 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1751 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1752 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1753 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1754 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1755 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1756 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1757 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1758 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1759 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1760 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1761 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1762 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1763 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1764 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1765 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1766 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1767 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1768 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1769 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1770 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1771 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1772 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1773 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1774 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1775 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1776 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1777 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1778 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1779 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1780 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1781 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1782 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1783 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1784 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1785 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1786 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1787 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1788 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1789 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1790 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1791 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1792 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1793 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1794 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1795 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1796 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1797 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1798 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1799 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1800 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1801 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1802 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1803 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1804 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1805 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1806 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1807 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1808 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1809 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1810 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1811 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1812 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1813 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1814 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1815 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1816 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1817 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1818 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1819 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1820 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1821 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1822 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1823 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1824 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1825 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1826 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1827 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1828 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1829 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1830 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1831 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1832 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1833 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1834 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1835 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1836 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1837 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1838 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1839 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1840 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1841 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1842 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1843 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1844 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1845 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1846 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1847 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1848 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1849 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1850 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1851 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1852 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1853 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1854 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1855 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1856 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1857 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1858 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1859 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1860 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1861 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1862 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1863 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1864 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1865 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1866 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1867 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1868 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1869 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1870 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1871 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1872 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1873 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1874 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1875 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1876 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1877 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1878 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1879 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1880 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1881 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1882 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1883 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1884 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1885 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1886 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1887 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1888 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1889 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1890 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1891 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1892 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1893 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1894 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1895 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1896 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1897 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1898 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1899 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1900 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1901 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1902 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1903 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1904 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1905 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1906 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1907 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1908 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1909 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1910 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1911 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1912 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1913 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1914 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1915 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1916 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1917 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1918 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1919 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1920 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1921 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1922 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1923 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1924 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1925 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1926 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1927 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1928 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1929 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1930 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1931 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1932 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1933 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1934 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1935 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1936 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1937 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1938 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1939 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1940 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1941 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1942 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1943 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1944 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1945 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1946 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1947 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1948 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1949 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1950 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1951 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1952 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1953 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1954 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1955 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1956 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1957 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1958 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1959 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1960 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1961 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1962 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1963 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1964 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1965 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1966 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1967 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1968 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1969 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1970 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1971 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1972 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1973 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1974 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1975 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1976 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1977 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1978 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1979 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1980 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1981 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1982 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1983 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1984 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1985 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1986 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1987 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1988 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1989 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1990 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1991 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1992 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1993 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1994 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1995 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1996 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1997 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1998 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1999 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2000 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2001 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2002 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2003 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2004 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2005 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2006 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2007 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2008 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2009 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2010 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2011 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2012 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2013 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2014 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2015 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2016 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2017 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2018 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2019 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2020 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2021 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2022 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2023 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2024 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2025 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2026 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2027 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2028 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2029 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2030 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2031 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2032 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2033 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2034 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2035 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2036 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2037 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2038 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2039 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2040 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2041 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2042 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2043 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2044 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2045 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2046 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2047 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2048 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2049 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2050 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2051 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2052 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2053 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2054 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2055 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2056 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2057 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2058 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2059 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2060 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2061 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2062 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2063 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2064 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2065 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2066 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2067 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2068 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2069 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2070 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2071 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2072 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2073 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2074 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2075 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2076 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2077 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2078 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2079 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2080 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2081 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2082 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2083 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2084 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2085 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2086 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2087 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2088 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2089 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2090 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2091 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2092 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2093 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2094 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2095 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2096 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2097 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2098 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2099 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2100 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2101 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2102 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2103 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2104 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2105 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2106 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2107 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2108 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2109 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2110 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2111 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2112 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2113 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2114 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2115 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2116 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2117 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2118 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2119 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2120 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2121 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2122 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2123 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2124 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2125 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2126 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2127 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2128 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69097180 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_16 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69107181 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_27 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69117182 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_38 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69127183 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69137184 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_510 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69147185 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_611 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69157186 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_712 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69167187 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_813 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69177188 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_914 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7302 ( .A ( ropt_net_25 ) , - .X ( ropt_net_26 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69197190 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_1116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69207191 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_1217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69217192 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_1318 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69227193 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_1419 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69237194 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_1520 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7303 ( .A ( ropt_net_26 ) , - .X ( ropt_net_27 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69257196 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_1722 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufinv_8 cts_inv_69247195_69267197 ( - .A ( SYNOPSYS_UNCONNECTED_1 ) , .Y ( SYNOPSYS_UNCONNECTED_2 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_69187189_69277198 ( - .A ( SYNOPSYS_UNCONNECTED_3 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69397210 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_1823 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69407211 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_1924 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7304 ( - .A ( grid_io_top_1_ccff_tail[0] ) , .X ( ropt_net_28 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_7305 ( .A ( ropt_net_28 ) , - .X ( ropt_net_29 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7306 ( - .A ( grid_io_left_0_ccff_tail[0] ) , .X ( ropt_net_30 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_7307 ( .A ( ropt_net_30 ) , - .X ( ropt_net_31 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78798147 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_13 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78808148 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_24 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78838151 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78848152 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78858153 ( .A ( ctsbuf_net_1719 ) , + .Y ( ctsbuf_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78868154 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_810 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78878155 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_911 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78888156 ( .A ( ctsbuf_net_1719 ) , + .Y ( ctsbuf_net_1012 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78898157 ( .A ( ctsbuf_net_1719 ) , + .Y ( ctsbuf_net_1113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78918159 ( .A ( ctsbuf_net_1719 ) , + .Y ( ctsbuf_net_1315 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78938161 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_1517 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 cts_inv_78828150_78948162 ( + .A ( SYNOPSYS_UNCONNECTED_31 ) , .Y ( SYNOPSYS_UNCONNECTED_32 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 cts_inv_78818149_78958163 ( + .A ( SYNOPSYS_UNCONNECTED_33 ) , .Y ( SYNOPSYS_UNCONNECTED_34 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_78908158_78968164 ( + .A ( SYNOPSYS_UNCONNECTED_35 ) , .Y ( SYNOPSYS_UNCONNECTED_36 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufinv_8 cts_inv_78928160_78978165 ( + .A ( SYNOPSYS_UNCONNECTED_37 ) , .Y ( SYNOPSYS_UNCONNECTED_38 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_79058173 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_1618 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_79068174 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_1719 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( @@ -56615,14 +58268,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( @@ -56673,9 +58326,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1439800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -56727,9 +58380,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -56781,9 +58434,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -56835,9 +58488,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -56889,9 +58542,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -56943,9 +58596,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -56971,185 +58624,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -57173,14 +58660,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y27200 ( @@ -57283,11 +58770,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -57391,11 +58878,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -57499,11 +58986,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -57539,175 +59026,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -57785,12 +59108,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y54400 ( @@ -57893,11 +59216,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -58001,11 +59324,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -58083,189 +59406,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -58289,14 +59444,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y81600 ( @@ -58399,11 +59554,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -58507,11 +59662,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -58615,11 +59770,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -58655,175 +59810,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -58901,12 +59892,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y108800 ( @@ -59009,11 +60000,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59071,57 +60062,55 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4439000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4457400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59199,189 +60188,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59405,14 +60226,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y136000 ( @@ -59515,11 +60336,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59623,11 +60444,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59731,11 +60552,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59771,175 +60592,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60017,12 +60674,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y163200 ( @@ -60125,11 +60782,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60233,11 +60890,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60315,189 +60972,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60521,14 +61010,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y190400 ( @@ -60631,11 +61120,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60739,11 +61228,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60847,11 +61336,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60887,175 +61376,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61133,12 +61458,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y217600 ( @@ -61241,11 +61566,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61349,11 +61674,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61431,189 +61756,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61637,14 +61794,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y244800 ( @@ -61747,11 +61904,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61855,11 +62012,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61963,11 +62120,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62003,175 +62160,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62249,12 +62242,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y272000 ( @@ -62357,11 +62350,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62465,11 +62458,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62547,189 +62540,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62753,14 +62578,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y299200 ( @@ -62863,11 +62688,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62971,11 +62796,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63079,11 +62904,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63119,175 +62944,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63365,12 +63026,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y326400 ( @@ -63473,11 +63134,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63581,11 +63242,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63663,189 +63324,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63869,14 +63362,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( @@ -63979,11 +63472,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64087,11 +63580,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64195,11 +63688,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64235,175 +63728,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64481,12 +63810,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y380800 ( @@ -64589,11 +63918,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64697,11 +64026,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64779,189 +64108,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64985,14 +64146,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y408000 ( @@ -65095,11 +64256,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65203,11 +64364,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65311,11 +64472,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65351,175 +64512,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65551,58 +64548,52 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1117800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1154600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1228200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1265000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1301800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1338600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1375400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y435200 ( @@ -65705,11 +64696,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65813,11 +64804,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65895,189 +64886,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66101,14 +64924,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y462400 ( @@ -66211,11 +65034,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66319,11 +65142,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66427,11 +65250,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66467,175 +65290,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66713,12 +65372,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y489600 ( @@ -66821,11 +65480,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66929,11 +65588,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67011,189 +65670,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67217,14 +65708,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y516800 ( @@ -67327,11 +65818,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67435,11 +65926,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67543,11 +66034,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67583,175 +66074,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67829,12 +66156,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y544000 ( @@ -67937,11 +66264,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68045,11 +66372,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68127,189 +66454,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68333,14 +66492,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( @@ -68443,11 +66602,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68551,11 +66710,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68659,11 +66818,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68699,175 +66858,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68945,12 +66940,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y598400 ( @@ -69053,11 +67048,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69161,11 +67156,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69243,189 +67238,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69449,14 +67276,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( @@ -69559,11 +67386,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69667,11 +67494,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69775,11 +67602,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69815,175 +67642,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70061,12 +67724,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y652800 ( @@ -70169,11 +67832,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70277,11 +67940,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70359,189 +68022,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70565,14 +68060,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y680000 ( @@ -70675,11 +68170,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70783,11 +68278,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70891,11 +68386,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70931,175 +68426,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71177,12 +68508,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y707200 ( @@ -71285,11 +68616,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71393,11 +68724,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71475,189 +68806,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71681,14 +68844,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y734400 ( @@ -71791,11 +68954,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71899,11 +69062,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72007,11 +69170,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72047,175 +69210,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72293,12 +69292,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y761600 ( @@ -72401,11 +69400,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72509,11 +69508,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72591,189 +69590,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72797,14 +69628,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( @@ -72907,11 +69738,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73015,11 +69846,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73123,11 +69954,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73163,175 +69994,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73409,12 +70076,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y816000 ( @@ -73517,11 +70184,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73625,11 +70292,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73707,189 +70374,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73913,14 +70412,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y843200 ( @@ -74023,11 +70522,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74131,11 +70630,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74239,11 +70738,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74279,175 +70778,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74525,12 +70860,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y870400 ( @@ -74633,11 +70968,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74741,11 +71076,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74823,189 +71158,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75029,14 +71196,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y897600 ( @@ -75139,11 +71306,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75247,11 +71414,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75355,11 +71522,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75395,175 +71562,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75641,12 +71644,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y924800 ( @@ -75749,11 +71752,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75857,11 +71860,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75939,189 +71942,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76145,14 +71980,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y952000 ( @@ -76255,11 +72090,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76363,11 +72198,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76471,11 +72306,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76511,175 +72346,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76757,12 +72428,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y979200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y979200 ( @@ -76865,11 +72536,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76973,11 +72644,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77055,189 +72726,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y979200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77261,14 +72764,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1006400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1006400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1006400 ( @@ -77371,11 +72874,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1006400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77479,11 +72982,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1006400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77587,11 +73090,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1006400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77627,175 +73130,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1006400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1006400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77873,12 +73212,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1033600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1033600 ( @@ -77981,11 +73320,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78089,11 +73428,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78171,189 +73510,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1033600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78377,14 +73548,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1060800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1060800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1060800 ( @@ -78487,11 +73658,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1060800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78595,11 +73766,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1060800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78703,11 +73874,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1060800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78743,175 +73914,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1060800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1060800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78989,12 +73996,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1088000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y1088000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1088000 ( @@ -79097,11 +74104,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79205,11 +74212,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79287,187 +74294,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7419800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1088000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1088000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79491,14 +74332,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1115200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1115200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1115200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1115200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1115200 ( @@ -79549,63 +74390,63 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1115200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1115200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79657,63 +74498,63 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1115200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1115200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79765,63 +74606,63 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1115200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1115200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79857,175 +74698,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1115200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1115200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1115200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1115200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -80077,513 +74754,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1142400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1142400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1142400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1142400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1142400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1142400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1142400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1142400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1142400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1142400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1142400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1142400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1142400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1142400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -80607,14 +74902,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1169600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1169600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1169600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1169600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1169600 ( @@ -80649,295 +74944,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1169600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1169600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1169600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -80973,175 +75034,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1169600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1169600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1169600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1169600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -81193,513 +75090,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1196800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1196800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1196800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1196800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1196800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1196800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1196800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1196800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1196800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1196800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1196800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1196800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1196800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1196800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -81723,14 +75238,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1224000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1224000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1224000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1224000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1224000 ( @@ -81765,295 +75280,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1224000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1224000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1224000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -82089,175 +75370,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1224000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1224000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1224000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1224000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -82309,513 +75426,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1251200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1251200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1251200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1251200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1251200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1251200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1251200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1251200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1251200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1251200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1251200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1251200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1251200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1251200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -82839,14 +75574,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1278400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1278400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1278400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1278400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1278400 ( @@ -82881,295 +75616,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1278400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1278400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1278400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1278400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1278400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -83205,175 +75706,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1278400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1278400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1278400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1278400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -83425,513 +75762,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1305600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1305600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1305600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1305600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1305600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1305600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1305600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1305600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1305600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1305600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1305600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1305600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1305600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1305600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1305600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1305600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1305600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1305600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1305600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1305600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -83955,14 +75910,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1332800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1332800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1332800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1332800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1332800 ( @@ -83997,295 +75952,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1332800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1332800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1332800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1332800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1332800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -84321,175 +76042,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1332800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1332800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1332800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1332800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -84541,513 +76098,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1360000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1360000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1360000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1360000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1360000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1360000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1360000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1360000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1360000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1360000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1360000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1360000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1360000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1360000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1360000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1360000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1360000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1360000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1360000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1360000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -85071,14 +76246,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1387200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1387200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1387200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1387200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1387200 ( @@ -85113,295 +76288,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1387200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1387200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1387200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1387200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1387200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -85437,175 +76378,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1387200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1387200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1387200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1387200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -85657,513 +76434,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1414400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1414400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1414400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1414400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1414400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1414400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1414400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1414400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1414400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1414400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1414400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1414400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1414400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1414400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1414400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1414400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1414400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1414400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1414400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1414400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -86187,14 +76582,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1441600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1441600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1441600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1441600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1441600 ( @@ -86229,295 +76624,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1441600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1441600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1441600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1441600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1441600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -86553,175 +76714,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1441600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1441600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1441600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1441600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -86773,513 +76770,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1468800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1468800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1468800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1468800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1468800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1468800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1468800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1468800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1468800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1468800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1468800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1468800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1468800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1468800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1468800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1468800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1468800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1468800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1468800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1468800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -87303,14 +76918,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1496000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1496000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1496000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1496000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1496000 ( @@ -87345,295 +76960,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1496000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1496000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1496000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1496000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1496000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -87669,175 +77050,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1496000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1496000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1496000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1496000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -87889,513 +77106,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1523200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1523200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1523200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1523200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1523200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1523200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1523200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1523200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1523200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1523200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1523200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1523200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1523200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1523200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1523200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1523200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1523200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1523200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1523200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1523200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -88419,14 +77254,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1550400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1550400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1550400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1550400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1550400 ( @@ -88461,295 +77296,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1550400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1550400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1550400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1550400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1550400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -88785,175 +77386,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1550400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1550400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1550400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1550400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -89005,513 +77442,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1577600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1577600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1577600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1577600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1577600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1577600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1577600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1577600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1577600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1577600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1577600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1577600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1577600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1577600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1577600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1577600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1577600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1577600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1577600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1577600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -89535,14 +77590,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1604800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1604800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1604800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1604800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1604800 ( @@ -89577,295 +77632,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1604800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1604800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1604800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1604800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1604800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -89901,175 +77722,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1604800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1604800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1604800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1604800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -90121,513 +77778,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1632000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1632000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1632000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1632000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1632000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1632000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1632000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1632000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1632000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1632000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1632000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1632000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1632000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1632000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1632000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1632000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1632000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1632000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1632000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1632000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -90651,14 +77926,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1659200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1659200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1659200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1659200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1659200 ( @@ -90693,295 +77968,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1659200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1659200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1659200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1659200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1659200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -91017,175 +78058,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1659200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1659200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1659200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1659200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -91237,513 +78114,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1686400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1686400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1686400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1686400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1686400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1686400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1686400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1686400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1686400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1686400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1686400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1686400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1686400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1686400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1686400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1686400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1686400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1686400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1686400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1686400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -91767,14 +78262,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1713600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1713600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1713600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1713600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1713600 ( @@ -91809,295 +78304,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1713600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1713600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1713600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1713600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1713600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -92133,175 +78394,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1713600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1713600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1713600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1713600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -92353,513 +78450,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1740800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1740800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1740800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1740800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1740800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1740800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1740800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1740800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1740800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1740800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1740800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1740800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1740800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1740800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1740800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1740800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1740800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1740800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1740800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1740800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -92883,14 +78598,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1768000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1768000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1768000 ( @@ -92925,295 +78640,65 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1768000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1768000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1768000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1768000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -93249,175 +78734,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1768000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1768000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -93469,513 +78790,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1795200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1795200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y1795200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2313800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2350600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y1795200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1795200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y1795200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y1795200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1795200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1795200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1795200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -93999,14 +79058,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1822400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1822400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1822400 ( @@ -94041,79 +79100,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1822400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1822400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y1822400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -94149,79 +79174,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1822400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y1822400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y1822400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -94257,79 +79248,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1822400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y1822400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1822400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -94365,175 +79322,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1822400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1822400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -94585,513 +79378,261 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1849600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1849600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y1849600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2277000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2295400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2304600y1849600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2327600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2364400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2401200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2438000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2474800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2622000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2658800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2695600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2769200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2806000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2842800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1849600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y1849600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y1849600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4337800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4374600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4411400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4448200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4485000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4521800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4558600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4595400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4632200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4669000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4705800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4742600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4779400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4816200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y1849600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1849600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1849600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -95115,14 +79656,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1876800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1876800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1876800 ( @@ -95157,187 +79698,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1876800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1876800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1876800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y1876800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2433400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1876800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2442600y1876800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4305600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4324000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1876800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y1876800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -95373,79 +79850,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1876800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y1876800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1876800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1876800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -95481,175 +79924,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1876800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1876800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -95701,513 +79980,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1904000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1904000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1904000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1904000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1904000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1904000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1904000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1904000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1904000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1904000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1904000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1904000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1904000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1904000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1904000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1904000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1904000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1904000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1904000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1904000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1904000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -96231,14 +80120,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1931200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1931200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1931200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1931200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1931200 ( @@ -96263,305 +80152,81 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1931200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1931200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1931200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1931200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1931200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1931200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1931200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1931200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1931200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1931200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1931200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1931200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1931200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1931200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1931200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -96597,175 +80262,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1931200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1931200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1931200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1931200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -96843,12 +80344,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1958400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y1958400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y1958400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1958400 ( @@ -96871,91 +80372,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1958400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y1958400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y1958400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y1958400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -96979,91 +80420,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1958400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y1958400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y1958400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y1958400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -97141,189 +80522,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1958400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1958400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -97347,14 +80560,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1985600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1985600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y1985600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1985600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1985600 ( @@ -97429,255 +80642,129 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1985600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1844600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1985600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y1985600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3339600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3376400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3413200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3450000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3523600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3560400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3597200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3634000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3670800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3707600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5326800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5363600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5400400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5474000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5510800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5547600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5584400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5621200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5658000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y1985600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1985600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -97713,175 +80800,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y1985600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y1985600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y1985600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1985600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -97959,12 +80882,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2012800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2012800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y2012800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2012800 ( @@ -97987,91 +80910,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2012800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y2012800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2012800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2012800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -98095,91 +80958,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y2012800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2012800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y2012800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y2012800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -98257,189 +81060,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2012800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2012800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -98463,14 +81098,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2040000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2040000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2040000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2040000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2040000 ( @@ -98521,279 +81156,159 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2040000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2040000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y2040000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2040000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2040000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2040000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2040000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2040000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2040000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2040000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y2040000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y2040000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5727000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y2040000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -98829,175 +81344,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y2040000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y2040000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2040000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2040000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -99049,513 +81400,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2067200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2067200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2067200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2067200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2067200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2067200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2067200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2067200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -99579,14 +81540,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2094400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2094400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2094400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2094400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2094400 ( @@ -99621,295 +81582,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2094400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2094400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2094400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y2094400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2094400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -99945,175 +81672,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y2094400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y2094400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2094400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2094400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -100165,513 +81728,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2121600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2121600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2121600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2121600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2121600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2121600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2121600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2121600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -100695,14 +81868,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2148800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2148800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2148800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2148800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2148800 ( @@ -100737,295 +81910,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2148800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2148800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2148800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y2148800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2148800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -101061,175 +82000,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y2148800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y2148800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2148800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2148800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -101281,513 +82056,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2176000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2176000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2176000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2176000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2176000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2176000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2176000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2176000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -101811,14 +82196,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2203200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2203200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2203200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2203200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2203200 ( @@ -101853,295 +82238,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2203200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2203200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2203200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y2203200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2203200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -102177,175 +82328,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y2203200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y2203200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2203200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2203200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -102397,513 +82384,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2230400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2230400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2230400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2230400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2230400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2230400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2230400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2230400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -102927,14 +82524,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2257600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2257600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2257600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2257600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2257600 ( @@ -102969,295 +82566,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2257600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2257600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2257600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y2257600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2257600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -103293,175 +82656,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y2257600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y2257600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2257600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2257600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -103513,513 +82712,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2284800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2284800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2284800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2284800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2284800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2284800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2284800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2284800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -104043,14 +82852,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2312000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2312000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2312000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2312000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2312000 ( @@ -104085,295 +82894,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2312000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2312000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2312000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y2312000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2312000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -104409,175 +82984,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y2312000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y2312000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2312000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2312000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -104629,441 +83040,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2339200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2339200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3519000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y2339200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2339200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4397600y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4434400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4471200y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y2339200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2339200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5469400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y2339200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6384800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6421600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y2339200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2339200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2339200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -105087,14 +83180,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2366400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2366400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2366400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2366400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2366400 ( @@ -105129,220 +83222,62 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2366400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y2366400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2366400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2366400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y2366400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y2366400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2366400 ( @@ -105377,175 +83312,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y2366400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y2366400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2366400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2366400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -105597,441 +83368,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2393600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2393600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3519000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y2393600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2393600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4397600y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4434400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4471200y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y2393600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2393600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5469400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y2393600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6384800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6421600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y2393600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2393600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2393600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -106055,14 +83508,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2420800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2420800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2420800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2420800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2420800 ( @@ -106097,220 +83550,62 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2420800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y2420800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2420800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2420800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y2420800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y2420800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2420800 ( @@ -106345,175 +83640,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y2420800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y2420800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2420800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2420800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -106565,441 +83696,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2448000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2448000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3519000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y2448000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2448000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4397600y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4434400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4471200y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y2448000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2448000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5469400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y2448000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6384800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6421600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y2448000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2448000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2448000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107023,14 +83836,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2475200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2475200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2475200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2475200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2475200 ( @@ -107065,220 +83878,62 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2475200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y2475200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2475200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2475200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y2475200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y2475200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2475200 ( @@ -107313,175 +83968,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y2475200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y2475200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2475200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2475200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107533,441 +84024,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2502400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2502400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3519000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y2502400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2502400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4397600y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4434400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4471200y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y2502400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2502400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5469400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y2502400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6384800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6421600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y2502400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2502400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2502400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107991,14 +84164,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2529600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2529600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2529600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2529600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2529600 ( @@ -108033,220 +84206,62 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2529600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y2529600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2529600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2529600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y2529600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y2529600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2529600 ( @@ -108281,175 +84296,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y2529600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y2529600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2529600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2529600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108501,513 +84352,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2556800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2556800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2556800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2556800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2556800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2556800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2556800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2556800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109031,14 +84492,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2584000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2584000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2584000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2584000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2584000 ( @@ -109073,295 +84534,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2584000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2584000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2584000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y2584000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2584000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109397,175 +84624,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y2584000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y2584000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2584000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2584000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109617,513 +84680,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2611200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2611200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2611200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2611200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2611200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2611200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2611200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2611200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110147,14 +84820,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2638400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2638400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2638400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2638400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2638400 ( @@ -110189,295 +84862,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2638400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2638400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2638400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y2638400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2638400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110513,175 +84952,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y2638400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y2638400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2638400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2638400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110733,287 +85008,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2665600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2665600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2665600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2665600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2665600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2665600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2665600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111037,14 +85148,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2692800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2692800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2692800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2692800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2692800 ( @@ -111079,279 +85190,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2692800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2692800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2692800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2692800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y2692800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y2692800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y2692800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y2692800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y2692800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y2692800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2692800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2692800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111403,287 +85336,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2720000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2720000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2720000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y2720000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y2720000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y2720000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y2720000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y2720000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2720000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2720000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2720000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y2720000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2720000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2720000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2720000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111707,14 +85476,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2747200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2747200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2747200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2747200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2747200 ( @@ -111749,279 +85518,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2747200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2747200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2747200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2747200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y2747200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y2747200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y2747200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y2747200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y2747200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y2747200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2747200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2747200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112073,287 +85664,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2774400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2774400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2774400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2774400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2774400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2774400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2774400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112377,14 +85804,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2801600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2801600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2801600 ( @@ -112409,289 +85836,121 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2801600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2801600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2801600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y2801600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y2801600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y2801600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y2801600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2801600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2801600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112769,12 +86028,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2828800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2828800 ( @@ -112797,233 +86056,169 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y2828800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2828800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4958800y2828800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5018600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5055400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5092200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5129000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5165800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5202600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5239400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5276200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2828800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2828800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113047,14 +86242,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2856000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2856000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2856000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2856000 ( @@ -113129,239 +86324,169 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2856000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1844600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2856000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3339600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3376400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3413200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3450000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3523600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3560400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3597200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3634000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3670800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3707600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5326800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5363600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5400400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5474000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5510800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5547600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5584400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5621200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5658000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y2856000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y2856000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y2856000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y2856000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y2856000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y2856000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2856000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113439,261 +86564,201 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2883200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y2883200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1458200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1485800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1522600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1559400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1596200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1633000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1669800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1706600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1743400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1780200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1817000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1853800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2883200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y2883200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y2883200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2883200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2883200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2883200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2883200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y2883200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2883200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2883200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113717,14 +86782,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2910400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2910400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2910400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2910400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2910400 ( @@ -113775,263 +86840,199 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2910400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2910400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y2910400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2910400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2910400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y2910400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y2910400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y2910400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y2910400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2910400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2910400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2910400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2910400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114083,287 +87084,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2937600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2937600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2937600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2937600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2937600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2937600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2937600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114387,14 +87224,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2964800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y2964800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y2964800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2964800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2964800 ( @@ -114429,279 +87266,109 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2964800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2964800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2964800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y2964800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2964800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y2964800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2964800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y2964800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y2964800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y2964800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y2964800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y2964800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y2964800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2964800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2964800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114753,287 +87420,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y2992000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2992000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y2992000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2992000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y2992000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y2992000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y2992000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2313800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2350600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y2992000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y2992000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y2992000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y2992000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y2992000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y2992000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y2992000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y2992000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y2992000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2992000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2992000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115057,14 +87688,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3019200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3019200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3019200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3019200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3019200 ( @@ -115099,79 +87730,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3019200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3019200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3019200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y3019200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y3019200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115183,195 +87780,183 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3019200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y3019200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3019200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3019200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y3019200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y3019200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y3019200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3019200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3019200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3019200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115423,287 +88008,255 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3046400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3046400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3046400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3046400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y3046400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3046400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y3046400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2313800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2350600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2387400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2424200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2461000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2497800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2534600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2571400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2608200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2645000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2681800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2718600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2755400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2792200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2829000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2865800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y3046400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3046400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y3046400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y3046400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y3046400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4337800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4374600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4411400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4448200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4485000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4521800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4558600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4595400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4632200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4669000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4705800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4742600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4779400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4816200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3046400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3046400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3046400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3046400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3046400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3046400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115727,14 +88280,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3073600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3073600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3073600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3073600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3073600 ( @@ -115769,79 +88322,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3073600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3073600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3073600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y3073600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y3073600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115853,195 +88372,183 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3073600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y3073600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3073600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3073600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y3073600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y3073600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y3073600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3073600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3073600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3073600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116093,287 +88600,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3100800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3100800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3100800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3100800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y3100800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3100800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3100800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y3100800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3100800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y3100800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y3100800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3100800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y3100800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3100800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y3100800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y3100800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3100800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y3100800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3100800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3100800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116397,14 +88748,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3128000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3128000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3128000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3128000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3128000 ( @@ -116439,279 +88790,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3128000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3128000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3128000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3128000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y3128000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y3128000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y3128000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y3128000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y3128000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3128000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3128000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3128000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116763,287 +88936,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3155200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3155200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3155200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3155200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y3155200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3155200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3155200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y3155200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3155200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y3155200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y3155200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3155200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y3155200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3155200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y3155200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y3155200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3155200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y3155200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3155200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3155200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117067,14 +89084,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3182400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3182400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3182400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3182400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3182400 ( @@ -117109,279 +89126,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3182400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3182400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3182400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3182400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y3182400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y3182400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y3182400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y3182400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y3182400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3182400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3182400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3182400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117433,287 +89272,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3209600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3209600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3209600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3209600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y3209600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3209600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3209600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y3209600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3209600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y3209600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y3209600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3209600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y3209600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3209600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y3209600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y3209600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3209600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y3209600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3209600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3209600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117737,14 +89420,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3236800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3236800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3236800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3236800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3236800 ( @@ -117779,279 +89462,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3236800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3236800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3236800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3236800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y3236800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y3236800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y3236800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y3236800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y3236800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3236800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3236800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3236800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118103,287 +89608,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3264000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3264000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1007400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3264000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1016600y3264000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3264000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3264000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y3264000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3264000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y3264000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3264000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y3264000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3264000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y3264000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3264000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3264000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3264000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118407,14 +89756,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3291200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3291200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3291200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3291200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3291200 ( @@ -118449,283 +89798,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3291200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3291200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3291200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3291200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y3291200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y3291200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y3291200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y3291200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y3291200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3291200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3291200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3291200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118777,423 +89944,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3318400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3318400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3318400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3367200y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3385600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3394800y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3666200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3684600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3693800y3318400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y3318400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4563200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y3318400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6499800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y3318400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3318400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3318400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y3318400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3318400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119217,14 +90092,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3345600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3345600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3345600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3345600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3345600 ( @@ -119259,232 +90134,62 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3345600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3345600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3345600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3698400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3808800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3845600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3882400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3919200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3956000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3992800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4103200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4140000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4176800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4213600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4250400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4287200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y3345600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3345600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4567800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4577000y3345600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5391200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5501600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5538400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5575200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5612000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5648800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5685600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5722400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5759200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5796000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5832800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5869600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5906400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5943200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5980000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6016800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6053600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6090400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6127200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6164000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6200800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6237600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y3345600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3345600 ( @@ -119495,167 +90200,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y3345600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y3345600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y3345600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3345600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3345600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3345600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119707,421 +90280,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3372800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3372800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3372800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3367200y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3385600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3394800y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4337800y3372800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y3372800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4563200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y3372800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6499800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y3372800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3372800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3372800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y3372800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3372800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120145,14 +90428,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3400000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3400000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3400000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3400000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3400000 ( @@ -120187,233 +90470,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3400000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3400000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3400000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3367200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3385600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3394800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3400000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4567800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4577000y3400000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y3400000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120425,167 +90536,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y3400000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y3400000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y3400000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3400000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3400000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3400000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120637,291 +90616,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3427200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3427200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3427200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3427200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3427200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3427200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3427200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y3427200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3427200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y3427200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y3427200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3427200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y3427200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3427200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y3427200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y3427200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3427200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y3427200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3427200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3427200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120945,14 +90764,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3454400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3454400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3454400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3454400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3454400 ( @@ -120987,275 +90806,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3454400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y3454400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3454400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3454400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3454400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3454400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3454400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3454400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3454400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121307,214 +90952,120 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3481600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2893400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3068200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3105000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3141800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3178600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3215400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3252200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3289000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3325800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y3481600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y3481600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4839200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4857600y3481600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5018600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5055400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5092200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5129000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5165800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5202600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5239400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5276200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5313000y3481600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y3481600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6789600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6808000y3481600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3481600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3481600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3481600 ( @@ -121523,175 +91074,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y3481600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3481600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121715,14 +91100,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3508800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3508800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3508800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3508800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3508800 ( @@ -121757,375 +91142,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3508800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y3508800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3508800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6789600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6808000y3508800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3508800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7300200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7337000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7373800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7410600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7447400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7484200y3508800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7521000y3508800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7557800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7594600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7631400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7668200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7705000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7741800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7778600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7815400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7852200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7889000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7925800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7962600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7999400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8036200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8073000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8109800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8146600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8183400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8220200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8257000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3508800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3508800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122177,393 +91288,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3536000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2893400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3068200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3105000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3141800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3178600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3215400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3252200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3289000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3325800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y3536000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y3536000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4839200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4857600y3536000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5018600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5055400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5092200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5129000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5165800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5202600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5239400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5276200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5313000y3536000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y3536000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3536000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y3536000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3536000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y3536000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y3536000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3536000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y3536000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3536000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122587,14 +91436,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3563200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3563200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3563200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3563200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3563200 ( @@ -122629,375 +91478,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3563200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y3563200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3563200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5299200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6789600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6808000y3563200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3563200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7300200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7337000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7373800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7410600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7447400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7484200y3563200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7521000y3563200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7557800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7594600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7631400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7668200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7705000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7741800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7778600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7815400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7852200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7889000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7925800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7962600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7999400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8036200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8073000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8109800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8146600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8183400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8220200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8257000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3563200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3563200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123049,273 +91624,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3590400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3590400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y3590400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3590400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y3590400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3590400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y3590400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y3590400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3590400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y3590400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y3590400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3590400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y3590400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3590400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123339,14 +91772,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3617600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3617600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3617600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3617600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3617600 ( @@ -123381,247 +91814,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3617600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3617600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3617600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3617600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3617600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3617600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3617600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3617600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3617600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123673,275 +91960,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3644800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3644800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y3644800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3644800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y3644800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3644800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y3644800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y3644800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3644800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y3644800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y3644800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3644800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y3644800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3644800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123965,14 +92108,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3672000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3672000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3672000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3672000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3672000 ( @@ -124007,247 +92150,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3672000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3672000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3672000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3672000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3672000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3672000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3672000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3672000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3672000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124299,275 +92296,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3699200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3699200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y3699200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3699200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y3699200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3699200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y3699200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y3699200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3699200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y3699200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y3699200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3699200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y3699200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3699200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124591,14 +92444,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3726400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3726400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3726400 ( @@ -124633,247 +92486,105 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3726400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3726400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3726400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3726400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3726400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3726400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124925,69 +92636,39 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3753600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3753600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y3753600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2019400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125003,197 +92684,209 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y3753600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3969800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3979000y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3753600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y3753600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3753600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3753600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125217,14 +92910,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3780800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3780800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3780800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3780800 ( @@ -125259,247 +92952,233 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3780800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3780800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3780800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3780800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3780800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3780800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3780800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y3780800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3780800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3780800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125551,275 +93230,255 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3808000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3808000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y3808000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3808000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2313800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2350600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2387400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2424200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2461000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2497800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2534600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2571400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2608200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2645000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2681800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2718600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2755400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2792200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2829000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2865800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3808000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y3808000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4337800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4374600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4411400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4448200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4485000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4521800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4558600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4595400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4632200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4669000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4705800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4742600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4779400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4816200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y3808000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3808000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y3808000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y3808000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3808000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125843,14 +93502,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3835200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3835200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3835200 ( @@ -125885,247 +93544,233 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3835200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3835200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3835200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y3835200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3835200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3835200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3937600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3956000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3835200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y3835200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3835200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3835200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3835200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -126177,275 +93822,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3862400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3862400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3862400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y3862400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y3862400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3862400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3862400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y3862400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y3862400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3862400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3862400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y3862400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y3862400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3862400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y3862400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y3862400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y3862400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y3862400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3862400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -126469,14 +93962,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3889600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3889600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3889600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3889600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3889600 ( @@ -126501,257 +93994,121 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3889600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3889600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3889600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3889600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3889600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3889600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3889600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y3889600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3889600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y3889600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y3889600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3889600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y3889600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3889600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3889600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3889600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3889600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3889600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3889600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -126829,12 +94186,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3916800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3916800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y3916800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3916800 ( @@ -126857,221 +94214,171 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3916800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y3916800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y3916800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y3916800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y3916800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3916800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y3916800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y3916800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y3916800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y3916800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y3916800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3916800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3916800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -127095,14 +94402,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3944000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3944000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3944000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3944000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3944000 ( @@ -127177,207 +94484,169 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3944000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1844600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3944000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y3944000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3339600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3376400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3413200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3450000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3523600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3560400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3597200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3634000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3670800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3707600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5326800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5363600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5400400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5474000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5510800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5547600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5584400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5621200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5658000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3944000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3944000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3944000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3944000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3944000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -127455,12 +94724,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3971200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y3971200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y3971200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3971200 ( @@ -127483,221 +94752,171 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3971200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y3971200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y3971200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y3971200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3703000y3971200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3726000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y3971200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y3971200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y3971200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y3971200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y3971200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y3971200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3971200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3971200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -127721,14 +94940,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3998400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y3998400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y3998400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3998400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3998400 ( @@ -127779,231 +94998,199 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3998400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y3998400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y3998400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3998400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y3998400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y3998400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y3998400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y3998400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y3998400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y3998400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y3998400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3998400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -128055,275 +95242,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4025600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4025600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y4025600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4025600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4025600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4025600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y4025600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y4025600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4025600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4025600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -128347,14 +95382,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4052800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4052800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4052800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4052800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4052800 ( @@ -128389,247 +95424,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4052800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y4052800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4052800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4052800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4052800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4052800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4052800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4052800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4052800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -128681,275 +95570,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4080000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4080000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y4080000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4080000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2530000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2566800y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2603600y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4080000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4080000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y4080000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y4080000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4080000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4080000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -128973,14 +95710,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4107200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4107200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4107200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4107200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4107200 ( @@ -129015,247 +95752,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4107200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y4107200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4107200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4107200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4107200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4107200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4107200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4107200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4107200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -129307,275 +95898,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4134400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4134400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y4134400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4134400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4134400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4134400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y4134400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y4134400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4134400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4134400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -129599,14 +96038,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4161600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4161600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4161600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4161600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4161600 ( @@ -129641,247 +96080,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4161600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y4161600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4161600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4161600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4161600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4161600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4161600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4161600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4161600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -129933,275 +96226,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4188800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4188800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y4188800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4188800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4188800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4188800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y4188800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y4188800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4188800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4188800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -130225,14 +96366,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4216000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4216000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4216000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4216000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4216000 ( @@ -130267,247 +96408,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4216000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y4216000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4216000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4216000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4216000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4216000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4216000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4216000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4216000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -130559,275 +96554,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4243200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4243200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y4243200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4243200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4243200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4243200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y4243200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y4243200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4243200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4243200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -130851,14 +96694,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4270400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4270400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4270400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4270400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4270400 ( @@ -130893,247 +96736,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4270400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y4270400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4270400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4270400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4270400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4270400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4270400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4270400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4270400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -131185,275 +96882,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4297600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4297600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y4297600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4297600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4297600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4297600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y4297600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y4297600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4297600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4297600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -131477,14 +97022,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4324800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4324800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4324800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4324800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4324800 ( @@ -131519,253 +97064,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4324800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y4324800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4324800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y4324800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4324800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4324800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4324800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4324800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4324800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -131817,216 +97210,112 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4352000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4352000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2507000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2622000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2658800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2695600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2769200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2806000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2842800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2879600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2898000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2907200y4352000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4352000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3068200y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3105000y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3141800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3178600y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3215400y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3252200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3289000y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3325800y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4352000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4839200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4857600y4352000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5018600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5055400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5092200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5129000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5165800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5202600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5239400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5276200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5313000y4352000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6789600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6808000y4352000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4352000 ( @@ -132035,175 +97324,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4352000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4352000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -132227,14 +97350,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4379200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4379200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4379200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4379200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4379200 ( @@ -132269,375 +97392,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4379200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y4379200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4379200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6789600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6808000y4379200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4379200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7300200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7337000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7373800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7410600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7447400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7484200y4379200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7521000y4379200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7557800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7594600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7631400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7668200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7705000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7741800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7778600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7815400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7852200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7889000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7925800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7962600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7999400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8036200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8073000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8109800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8146600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8183400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8220200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8257000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4379200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4379200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -132689,211 +97538,109 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4406400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4406400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2893400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3068200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3105000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3141800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3178600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3215400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3252200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3289000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3325800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y4406400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4406400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4839200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4857600y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4406400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5018600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5055400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5092200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5129000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5165800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5202600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5239400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5276200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5313000y4406400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6679200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6688400y4406400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6711400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6748200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -132905,175 +97652,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4406400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4406400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -133097,14 +97678,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4433600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4433600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4433600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4433600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4433600 ( @@ -133139,375 +97720,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4433600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y4433600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4433600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6679200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6688400y4433600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4433600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6711400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6748200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6785000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6803400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7300200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7337000y4433600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7373800y4433600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7410600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7447400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7484200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7521000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7557800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7594600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7631400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7668200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7705000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7741800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7778600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7815400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7852200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7889000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7925800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7962600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7999400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8036200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8073000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8109800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8146600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8183400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8220200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8257000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4433600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4433600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -133559,291 +97866,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4460800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4460800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4460800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4460800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4460800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4460800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4460800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4460800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -133867,14 +98006,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4488000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4488000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4488000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4488000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4488000 ( @@ -133909,275 +98048,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4488000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4488000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4488000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4488000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4488000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4488000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4488000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4488000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4488000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -134229,423 +98194,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4515200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4515200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4515200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4515200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3367200y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3385600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3394800y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4515200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3887000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3914600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3951400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3988200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4025000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4061800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4098600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4135400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4172200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4209000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4245800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4282600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4319400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4356200y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4567800y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4577000y4515200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y4515200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y4515200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4515200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4515200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4515200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -134669,14 +98334,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4542400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4542400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4542400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4542400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4542400 ( @@ -134711,232 +98376,62 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4542400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4542400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4542400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3698400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3808800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3845600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3882400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3919200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3956000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3992800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4103200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4140000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4176800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4213600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4250400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4287200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y4542400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4542400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4567800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4577000y4542400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5391200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5501600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5538400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5575200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5612000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5648800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5685600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5722400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5759200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5796000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5832800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5869600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5906400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5943200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5980000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6016800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6053600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6090400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6127200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6164000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6200800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6237600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y4542400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4542400 ( @@ -134947,167 +98442,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y4542400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y4542400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y4542400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4542400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4542400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4542400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -135159,423 +98522,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4569600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4569600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4569600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4569600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3367200y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3385600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3394800y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4569600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4549400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4567800y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4577000y4569600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y4569600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6499800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y4569600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4569600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4569600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4569600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -135599,14 +98662,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4596800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4596800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4596800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4596800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4596800 ( @@ -135641,235 +98704,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4596800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4596800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4596800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3367200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3385600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3394800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4596800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4457400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4466600y4596800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4563200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y4596800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -135881,167 +98770,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y4596800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y4596800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y4596800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4596800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4596800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4596800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -136093,287 +98850,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4624000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4624000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4624000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4624000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4624000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4624000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4624000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -136397,14 +98990,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4651200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4651200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4651200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4651200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4651200 ( @@ -136439,279 +99032,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4651200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4651200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4651200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4651200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y4651200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y4651200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y4651200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y4651200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y4651200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4651200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4651200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4651200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -136763,287 +99178,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4678400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4678400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4678400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y4678400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y4678400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y4678400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y4678400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y4678400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4678400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4678400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4678400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4678400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y4678400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y4678400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4678400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -137067,14 +99318,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4705600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4705600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4705600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4705600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4705600 ( @@ -137109,279 +99360,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4705600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4705600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4705600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4705600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y4705600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y4705600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y4705600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y4705600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y4705600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4705600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4705600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4705600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -137433,287 +99506,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4732800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4732800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4732800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4732800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4732800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4732800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4732800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -137737,14 +99646,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4760000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4760000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4760000 ( @@ -137769,289 +99678,121 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4760000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4760000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4760000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y4760000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y4760000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y4760000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4760000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4760000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4760000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -138129,12 +99870,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4787200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4787200 ( @@ -138157,233 +99898,171 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y4787200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3703000y4787200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3726000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y4787200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y4787200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y4787200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4787200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4787200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -138407,14 +100086,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4814400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4814400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4814400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4814400 ( @@ -138489,239 +100168,169 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4814400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1844600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4814400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3339600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3376400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3413200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3450000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3523600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3560400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3597200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3634000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3670800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3707600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5326800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5363600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5400400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5474000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5510800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5547600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5584400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5621200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5658000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y4814400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y4814400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4814400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -138799,12 +100408,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4841600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4841600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y4841600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4841600 ( @@ -138827,233 +100436,171 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4841600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y4841600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4841600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y4841600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y4841600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y4841600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y4841600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y4841600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4841600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4841600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -139077,14 +100624,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4868800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4868800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4868800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4868800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4868800 ( @@ -139135,263 +100682,199 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4868800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4868800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y4868800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y4868800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y4868800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y4868800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y4868800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y4868800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4868800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4868800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4868800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4868800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4868800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -139443,287 +100926,123 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y4896000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4896000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4896000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4896000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4896000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4896000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4896000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -139747,14 +101066,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4923200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4923200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4923200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4923200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4923200 ( @@ -139789,605 +101108,405 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4923200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4923200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4923200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y4923200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4923200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y4923200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4923200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4923200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4923200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y4923200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4923200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1927400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1964200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2001000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2037800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2074600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2111400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2148200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2185000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2221800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2258600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2295400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2332200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4923200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2369000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4923200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4923200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x0y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x23000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x96600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y4950400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1421400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1439800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2451800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2470200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2479400y4950400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2594400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y4950400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y4950400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y4950400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y4950400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y4950400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4950400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -140411,14 +101530,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4977600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y4977600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y4977600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4977600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4977600 ( @@ -140453,79 +101572,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4977600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4977600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4977600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y4977600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y4977600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -140537,195 +101622,183 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y4977600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y4977600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y4977600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4977600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y4977600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y4977600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y4977600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y4977600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y4977600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4977600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -140777,287 +101850,255 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5004800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5004800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5004800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5004800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y5004800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5004800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y5004800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2313800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2350600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2387400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2424200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2461000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2497800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2534600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2571400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2608200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2645000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2681800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2718600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2755400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2792200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2829000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2865800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y5004800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y5004800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y5004800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y5004800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y5004800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4337800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4374600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4411400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4448200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4485000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4521800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4558600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4595400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4632200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4669000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4705800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4742600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4779400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4816200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5004800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y5004800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5004800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5004800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5004800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5004800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -141081,14 +102122,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5032000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5032000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5032000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5032000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5032000 ( @@ -141123,79 +102164,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5032000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5032000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5032000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y5032000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y5032000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -141207,195 +102214,183 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y5032000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y5032000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y5032000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5032000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y5032000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y5032000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y5032000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5032000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5032000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5032000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -141447,287 +102442,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5059200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5059200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5059200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5059200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y5059200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5059200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5059200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y5059200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5059200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y5059200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y5059200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5059200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y5059200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5059200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y5059200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y5059200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5059200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y5059200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5059200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5059200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -141751,14 +102590,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5086400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5086400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5086400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5086400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5086400 ( @@ -141793,279 +102632,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5086400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5086400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5086400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5086400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y5086400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y5086400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y5086400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y5086400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y5086400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5086400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5086400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5086400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -142117,287 +102778,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5113600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5113600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5113600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5113600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y5113600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5113600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5113600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y5113600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5113600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y5113600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y5113600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5113600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y5113600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5113600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y5113600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y5113600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5113600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y5113600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5113600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5113600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -142421,14 +102926,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5140800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5140800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5140800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5140800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5140800 ( @@ -142463,279 +102968,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5140800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5140800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5140800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5140800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y5140800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y5140800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y5140800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y5140800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y5140800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5140800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5140800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5140800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -142787,287 +103114,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5168000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5168000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5168000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5168000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y5168000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5168000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5168000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y5168000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5168000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y5168000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y5168000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5168000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y5168000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5168000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y5168000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y5168000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5168000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y5168000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5168000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5168000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -143091,14 +103262,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5195200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5195200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5195200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5195200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5195200 ( @@ -143133,279 +103304,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5195200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5195200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5195200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5195200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y5195200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y5195200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y5195200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y5195200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y5195200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5195200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5195200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5195200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -143457,287 +103450,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5222400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5222400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5222400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5222400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y5222400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5222400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5222400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y5222400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5222400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y5222400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y5222400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5222400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y5222400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5222400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y5222400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y5222400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5222400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y5222400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5222400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5222400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -143761,14 +103598,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5249600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5249600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5249600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5249600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5249600 ( @@ -143803,283 +103640,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5249600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5249600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5249600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5249600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y5249600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y5249600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y5249600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y5249600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y5249600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5249600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5249600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5249600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -144131,419 +103786,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5276800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2488600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2516200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2553000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2589800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5276800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y5276800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3367200y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3385600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3394800y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4549400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4567800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4577000y5276800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5276800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y5276800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5276800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5276800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y5276800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5276800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -144567,14 +103934,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5304000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5304000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5304000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5304000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5304000 ( @@ -144609,232 +103976,62 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5304000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5304000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5304000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3698400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3808800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3845600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3882400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3919200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3956000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3992800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4103200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4140000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4176800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4213600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4250400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4287200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y5304000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5304000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4567800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4577000y5304000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5391200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5501600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5538400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5575200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5612000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5648800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5685600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5722400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5759200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5796000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5832800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5869600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5906400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5943200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5980000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6016800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6053600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6090400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6127200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6164000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6200800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6237600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y5304000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5304000 ( @@ -144845,167 +104042,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y5304000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y5304000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y5304000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5304000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5304000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5304000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -145057,417 +104122,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5331200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5331200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3293600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4337800y5331200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y5331200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4563200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y5331200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6288200y5331200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5331200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6513600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5331200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y5331200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5331200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -145491,14 +104270,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5358400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5358400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5358400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5358400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5358400 ( @@ -145533,231 +104312,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5358400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5358400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5358400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3367200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3385600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3394800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5358400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4567800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4577000y5358400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y5358400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -145769,167 +104378,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y5358400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y5358400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y5358400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5358400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5358400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5358400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -145981,291 +104458,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5385600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5385600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5385600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5385600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y5385600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5385600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5385600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y5385600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5385600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y5385600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y5385600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5385600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y5385600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5385600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y5385600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y5385600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5385600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y5385600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5385600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5385600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -146289,14 +104606,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5412800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5412800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5412800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5412800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5412800 ( @@ -146331,275 +104648,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5412800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y5412800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5412800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5412800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5412800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5412800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5412800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5412800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5412800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -146651,214 +104794,120 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5440000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2893400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3068200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3105000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3141800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3178600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3215400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3252200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3289000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3325800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y5440000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5440000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4839200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4857600y5440000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5018600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5055400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5092200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5129000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5165800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5202600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5239400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5276200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5313000y5440000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y5440000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6789600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6808000y5440000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5440000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5440000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5440000 ( @@ -146867,175 +104916,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y5440000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5440000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -147059,14 +104942,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5467200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5467200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5467200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5467200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5467200 ( @@ -147101,375 +104984,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5467200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y5467200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5467200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6789600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6808000y5467200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5467200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7300200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7337000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7373800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7410600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7447400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7484200y5467200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7521000y5467200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7557800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7594600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7631400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7668200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7705000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7741800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7778600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7815400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7852200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7889000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7925800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7962600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7999400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8036200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8073000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8109800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8146600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8183400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8220200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8257000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5467200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5467200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -147521,393 +105130,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5494400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2893400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3068200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3105000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3141800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3178600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3215400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3252200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3289000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3325800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y5494400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5494400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4839200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4857600y5494400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5018600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5055400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5092200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5129000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5165800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5202600y5494400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y5494400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5299200y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5494400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y5494400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5494400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y5494400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y5494400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5494400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y5494400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5494400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -147931,14 +105278,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5521600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5521600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5521600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5521600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5521600 ( @@ -147973,375 +105320,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5521600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y5521600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5521600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6789600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6808000y5521600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5521600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7300200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7337000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7373800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7410600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7447400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7484200y5521600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7521000y5521600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7557800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7594600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7631400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7668200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7705000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7741800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7778600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7815400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7852200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7889000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7925800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7962600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7999400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8036200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8073000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8109800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8146600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8183400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8220200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8257000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5521600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5521600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -148393,273 +105466,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5548800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5548800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y5548800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5548800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y5548800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5548800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y5548800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y5548800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5548800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y5548800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y5548800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5548800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y5548800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5548800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -148683,14 +105614,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5576000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5576000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5576000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5576000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5576000 ( @@ -148725,247 +105656,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5576000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5576000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5576000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5576000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5576000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5576000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5576000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5576000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5576000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -149017,275 +105802,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5603200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5603200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y5603200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5603200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y5603200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5603200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y5603200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y5603200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5603200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y5603200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y5603200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5603200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y5603200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5603200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -149309,14 +105950,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5630400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5630400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5630400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5630400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5630400 ( @@ -149351,247 +105992,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5630400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5630400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5630400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5630400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5630400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5630400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5630400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5630400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5630400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -149643,275 +106138,131 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5657600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5657600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y5657600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5657600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y5657600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5657600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y5657600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y5657600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5657600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y5657600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y5657600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5657600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y5657600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5657600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -149935,14 +106286,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5684800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5684800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5684800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5684800 ( @@ -149967,257 +106318,129 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5684800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5684800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5684800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5684800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5684800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5684800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5684800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5684800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5684800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5684800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5684800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5684800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5684800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5684800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5684800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5684800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5684800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5684800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -150295,12 +106518,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5712000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5712000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y5712000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5712000 ( @@ -150347,197 +106570,267 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5712000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y5712000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5712000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y5712000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y5712000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y5712000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y5712000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3739800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y5712000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4494200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5712000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5712000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -150561,14 +106854,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5739200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5739200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5739200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5739200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5739200 ( @@ -150647,203 +106940,291 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5739200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5739200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5739200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5739200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5739200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5739200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5739200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -150921,12 +107302,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5766400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5766400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y5766400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5766400 ( @@ -150973,197 +107354,267 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5766400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5766400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y5766400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5766400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y5766400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y5766400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5766400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5766400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5766400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -151187,14 +107638,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5793600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5793600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5793600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5793600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5793600 ( @@ -151273,203 +107724,291 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4457400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4498800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4535600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4572400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4609200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4646000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4682800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4719600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4756400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4830000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4866800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4903600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4940400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4977200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5014000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5050800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5087600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6265200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5793600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5793600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5793600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5793600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5793600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5793600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -151547,12 +108086,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5820800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5820800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y5820800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5820800 ( @@ -151599,197 +108138,267 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5820800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5820800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y5820800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5820800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y5820800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y5820800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5820800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5820800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5820800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -151813,14 +108422,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5848000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5848000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5848000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5848000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5848000 ( @@ -151899,203 +108508,291 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5848000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5848000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5848000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5848000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2801400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5848000 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x7838400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5848000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3574200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5848000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5848000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4126200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5848000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y5848000 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x9131000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5848000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -152173,12 +108870,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5875200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5875200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y5875200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5875200 ( @@ -152225,197 +108922,267 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5875200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5875200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y5875200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5875200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x7870600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y5875200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3813400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y5875200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4586200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5875200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5322200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5875200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -152439,14 +109206,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5902400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5902400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5902400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5902400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5902400 ( @@ -152525,203 +109292,291 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5902400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5902400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5902400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y5902400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5902400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5902400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5902400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -152799,12 +109654,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5929600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5929600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y5929600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5929600 ( @@ -152851,197 +109706,267 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5929600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y5929600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y5929600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5929600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y5929600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y5929600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5929600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5929600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5929600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -153065,14 +109990,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5956800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y5956800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y5956800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5956800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5956800 ( @@ -153151,203 +110076,291 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5956800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5956800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5956800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y5956800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x8431800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y5956800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y5956800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5956800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -153425,12 +110438,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5984000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y5984000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y5984000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5984000 ( @@ -153477,197 +110490,267 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y5984000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y5984000 ( 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xofiller_sky130_fd_sc_hd__fill_2_x3353400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y5984000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y5984000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3887000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5984000 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x8717000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y5984000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4659800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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+sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y5984000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y5984000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5984000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -153691,14 +110774,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6011200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6011200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6011200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6011200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6011200 ( @@ -153777,203 +110860,291 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y6011200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6011200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6011200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6011200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6011200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6011200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6011200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -154051,12 +111222,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6038400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6038400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6038400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6038400 ( @@ -154103,197 +111274,267 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y6038400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6038400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y6038400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6038400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y6038400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y6038400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6038400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6038400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6038400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -154317,14 +111558,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6065600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6065600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6065600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6065600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6065600 ( @@ -154403,203 +111644,291 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y6065600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6065600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6065600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6065600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6065600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6065600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6065600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -154677,12 +112006,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6092800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6092800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6092800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6092800 ( @@ -154729,197 +112058,267 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y6092800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y6092800 ( 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xofiller_sky130_fd_sc_hd__fill_2_x7309400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y6092800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6092800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y6092800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y6092800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y6092800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4144600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y6092800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4917400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6092800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6092800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6092800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -154943,14 +112342,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6120000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6120000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6120000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6120000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6120000 ( @@ -155029,203 +112428,291 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y6120000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6120000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6120000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6120000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6120000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6120000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6120000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -155303,12 +112790,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6147200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6147200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6147200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6147200 ( @@ -155355,197 +112842,267 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y6147200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6147200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y6147200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6147200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y6147200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y6147200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6147200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6147200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6147200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -155569,14 +113126,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6174400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6174400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6174400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6174400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6174400 ( @@ -155655,203 +113212,291 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y6174400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6174400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6174400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6174400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6174400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6174400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6174400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -155929,12 +113574,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6201600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6201600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6201600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6201600 ( @@ -155981,197 +113626,267 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y6201600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6201600 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x5322200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6201600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -156195,14 +113910,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6228800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6228800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6228800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6228800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6228800 ( @@ -156281,203 +113996,291 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y6228800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6228800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6228800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2612800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8243200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6228800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6228800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6228800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6228800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -156555,12 +114358,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6256000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6256000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6256000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6256000 ( @@ -156607,197 +114410,267 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2304600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y6256000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6256000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7309400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7318600y6256000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6256000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y6256000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y6256000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8275400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8312200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8349000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8385800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8422600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8459400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8496200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8533000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8569800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8606600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8643400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8680200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8717000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8753800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8790600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8827400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8864200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8901000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8937800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8974600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9011400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9048200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9085000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9121800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9158600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9195400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9232200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6256000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6256000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6256000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -156821,14 +114694,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6283200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6283200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6283200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6283200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6283200 ( @@ -156907,209 +114780,291 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1918200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2313800y6283200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y6283200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y6283200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2622000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7304800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7764800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7783200y6283200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7797000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7833800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7870600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7907400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7944200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7981000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8017800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8054600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8091400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8128200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8165000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8201800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8238600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6283200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6283200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6283200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -157187,12 +115142,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6310400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6310400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6310400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6310400 ( @@ -157245,130 +115200,250 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3068200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3105000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3141800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3178600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3215400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3252200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3289000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3325800y6310400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y6310400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y6310400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4839200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4857600y6310400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5018600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5055400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5092200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5129000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5165800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5202600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5239400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5276200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5313000y6310400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6789600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6808000y6310400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6310400 ( @@ -157377,175 +115452,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y6310400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6310400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6310400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -157569,14 +115478,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6337600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6337600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6337600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6337600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6337600 ( @@ -157679,303 +115588,267 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6337600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6337600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2507000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2589800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2626600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2663400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2700200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2737000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2773800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2810600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2847400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3068200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3105000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3141800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3178600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3215400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3252200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3289000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3325800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y6337600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y6337600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y6337600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6789600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6808000y6337600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7300200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7337000y6337600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5156600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7557800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7594600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7631400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7668200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7705000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7741800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7778600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7815400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7852200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7889000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7925800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7962600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7999400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8036200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8073000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8109800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8146600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8183400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8220200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8257000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6337600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6337600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6337600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6337600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6337600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6337600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -158053,12 +115926,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6364800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6364800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6364800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6364800 ( @@ -158117,303 +115990,255 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2525400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2571400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2608200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2645000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2681800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2718600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2755400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2792200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2829000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2865800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2902600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3068200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3105000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3141800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3178600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3215400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3252200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3289000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3325800y6364800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y6364800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y6364800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4839200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4857600y6364800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5018600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5055400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5092200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5129000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5165800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5202600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5239400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5276200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5313000y6364800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6364800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y6364800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y6364800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y6364800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6364800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6364800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6364800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -158437,14 +116262,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6392000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6392000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6392000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6392000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6392000 ( @@ -158547,11 +116372,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6392000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6392000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -158603,251 +116428,211 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3362600y6392000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y6392000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y6392000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6789600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6808000y6392000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6969000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7005800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7042600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7079400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7116200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7153000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7189800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7226600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7263400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7300200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7337000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7373800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7410600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7447400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7484200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7521000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7557800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7594600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7631400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7668200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7705000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7741800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7778600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7815400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7852200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7889000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7925800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7962600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7999400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8036200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8073000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8109800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8146600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8183400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8220200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8257000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6392000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6392000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6392000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6392000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6392000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6392000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -158879,58 +116664,60 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6419200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6419200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y6419200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1159200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1232800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1269600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1306400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1343200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1380000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6419200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6419200 ( @@ -158993,197 +116780,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6419200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6504400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6522800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6419200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y6419200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y6419200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6419200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6419200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6419200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -159207,14 +117048,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6446400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6446400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6446400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6446400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6446400 ( @@ -159317,11 +117158,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6446400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6446400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -159333,191 +117174,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6446400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3358000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4517200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4554000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4572400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5308400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y6446400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3169400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y6446400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3942200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6446400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6446400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6446400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6446400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5046200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6446400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -159595,12 +117496,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6473600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6473600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6473600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6473600 ( @@ -159663,22 +117564,52 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6473600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3367200y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3385600y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3394800y6473600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6473600 ( @@ -159725,38 +117656,68 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4255000y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4282600y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4319400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4356200y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4457400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4466600y6473600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4563200y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y6473600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6473600 ( @@ -159809,183 +117770,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y6473600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6473600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y6473600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y6473600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6473600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6473600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -160009,14 +117832,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6500800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6500800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6500800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6500800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6500800 ( @@ -160119,11 +117942,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6500800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6500800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -160135,72 +117958,104 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6500800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3698400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3808800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3845600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3882400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3919200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3956000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3992800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4103200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4140000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4176800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4213600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4250400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4287200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y6500800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6500800 ( @@ -160211,72 +118066,104 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4567800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4577000y6500800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5391200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5501600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5538400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5575200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5612000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5648800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5685600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5722400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5759200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5796000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5832800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5869600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5906400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5943200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5980000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6016800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6053600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6090400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6127200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6164000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6200800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6237600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y6500800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6500800 ( @@ -160287,167 +118174,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y6500800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y6500800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y6500800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6500800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6500800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6500800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -160525,12 +118280,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6528000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6528000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6528000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6528000 ( @@ -160593,22 +118348,52 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6528000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3367200y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3385600y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3394800y6528000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6528000 ( @@ -160671,22 +118456,52 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4549400y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4567800y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4577000y6528000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y6528000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6528000 ( @@ -160749,173 +118564,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6499800y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y6528000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6528000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y6528000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y6528000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6528000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6528000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -160939,14 +118616,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6555200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6555200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6555200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6555200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6555200 ( @@ -161049,11 +118726,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6555200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6555200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -161065,73 +118742,103 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6555200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3367200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3385600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3394800y6555200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -161143,73 +118850,103 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4567800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4577000y6555200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y6555200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -161221,167 +118958,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6518200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6527400y6555200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y6555200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y6555200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6555200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6555200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6555200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -161459,12 +119064,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6582400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6582400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6582400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6582400 ( @@ -161527,191 +119132,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6582400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3486800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6582400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x7383000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6582400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y6582400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y6582400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3555800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6582400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4328600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y6582400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5101400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6582400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6582400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6582400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -161735,14 +119400,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6609600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6609600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6609600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6609600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6609600 ( @@ -161845,11 +119510,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6609600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6609600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -161861,195 +119526,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6609600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y6609600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y6609600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y6609600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y6609600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6609600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6609600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6609600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6609600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -162127,12 +119848,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6636800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6636800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6636800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6636800 ( @@ -162195,193 +119916,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6636800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6636800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y6636800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6636800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6636800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6636800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6636800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -162405,14 +120184,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6664000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6664000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6664000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6664000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6664000 ( @@ -162515,11 +120294,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6664000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6664000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -162531,195 +120310,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6664000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y6664000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y6664000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y6664000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y6664000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y6664000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3831800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6664000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6664000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6664000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6664000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4935800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6664000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -162797,12 +120632,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6691200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6691200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6691200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6691200 ( @@ -162865,193 +120700,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6691200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6691200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y6691200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6691200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6691200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6691200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6691200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -163075,14 +120968,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6718400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6718400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6718400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6718400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6718400 ( @@ -163185,11 +121078,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6718400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6718400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -163201,195 +121094,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6718400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y6718400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y6718400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y6718400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y6718400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6718400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6718400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6718400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6718400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -163467,12 +121416,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6745600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6745600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6745600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6745600 ( @@ -163535,193 +121484,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6745600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6745600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y6745600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6745600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3519000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6745600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5064600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6745600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6745600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6745600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -163745,14 +121752,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6772800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6772800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6772800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6772800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6772800 ( @@ -163855,11 +121862,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6772800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6772800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -163871,195 +121878,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6772800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y6772800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y6772800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y6772800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y6772800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6772800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6772800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6772800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6772800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -164137,12 +122200,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6800000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6800000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6800000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6800000 ( @@ -164205,193 +122268,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6800000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6800000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y6800000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6800000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6800000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6800000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6800000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -164415,14 +122536,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6827200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6827200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6827200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6827200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6827200 ( @@ -164525,11 +122646,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6827200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6827200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -164541,195 +122662,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6827200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y6827200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y6827200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y6827200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y6827200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6827200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6827200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6827200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6827200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -164807,12 +122984,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6854400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6854400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6854400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6854400 ( @@ -164875,193 +123052,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6854400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6854400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y6854400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6854400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6854400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6854400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6854400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -165085,14 +123320,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6881600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6881600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6881600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6881600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6881600 ( @@ -165195,11 +123430,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6881600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6881600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -165211,195 +123446,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6881600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y6881600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y6881600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y6881600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y6881600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6881600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6881600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6881600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6881600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -165477,12 +123768,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6908800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6908800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6908800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6908800 ( @@ -165545,193 +123836,251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6908800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6908800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x7456600y6908800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6908800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y6908800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3666200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6908800 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x8229400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y6908800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4439000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6908800 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x9002200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y6908800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5211800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6908800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6908800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6908800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -165755,14 +124104,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6936000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6936000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6936000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6936000 ( @@ -165813,63 +124162,63 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6936000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6936000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -165881,58753 +124230,249 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6936000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y6936000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y6936000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y6936000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y6936000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y6936000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3482200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6936000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x8431800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6936000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6936000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4604600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6936000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5359000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6936000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6963200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6963200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6963200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y6963200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6963200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y6963200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y6963200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6963200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y6990400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y6990400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y6990400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y6990400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y6990400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y6990400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y6990400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y6990400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y6990400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7017600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y7017600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y7017600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7017600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7017600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7044800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y7044800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y7044800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y7044800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y7044800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y7044800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y7044800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7044800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7044800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7072000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y7072000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y7072000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7072000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7072000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7099200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y7099200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y7099200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y7099200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y7099200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y7099200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y7099200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7099200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7099200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7126400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y7126400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y7126400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7126400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7126400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7153600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y7153600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y7153600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y7153600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y7153600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y7153600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y7153600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7153600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7153600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7180800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2599000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y7180800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y7180800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7180800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7180800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7208000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2617400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2626600y7208000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3523600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3542000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y7208000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4383800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4393000y7208000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5474000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5492400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y7208000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6343400y7208000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8261600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x8270800y7208000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7208000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7208000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7235200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7235200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7235200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7262400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6292800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y7262400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7262400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7262400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7289600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7289600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7289600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7316800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7316800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7316800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7344000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3519000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y7344000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4397600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4434400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4471200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y7344000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5469400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y7344000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6384800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6421600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y7344000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7344000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7344000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7371200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y7371200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y7371200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y7371200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y7371200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7371200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7371200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7398400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3519000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y7398400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4397600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4434400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4471200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y7398400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5469400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y7398400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6384800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6421600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y7398400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7398400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7398400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7425600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y7425600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y7425600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y7425600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y7425600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7425600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7425600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7452800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3519000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y7452800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4397600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4434400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4471200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y7452800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5469400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y7452800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6384800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6421600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y7452800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7452800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7452800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7480000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y7480000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y7480000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y7480000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y7480000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7480000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7480000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7507200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3519000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y7507200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4397600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4434400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4471200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5317600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5336000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y7507200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5469400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y7507200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6384800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6421600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7268000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7286400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x7295600y7507200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7507200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7507200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7534400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3537400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3546600y7534400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4360800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4370000y7534400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5487800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5497000y7534400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6311200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6320400y7534400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7534400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7534400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7561600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7561600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7561600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7588800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7588800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7588800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7616000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7616000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7616000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7643200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7643200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7643200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7670400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7670400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7670400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7697600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7697600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7697600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7724800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7724800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7724800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7752000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7752000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7752000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7779200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7779200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7779200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7806400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7806400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7806400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7833600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7833600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7833600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7860800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7860800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7860800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7888000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7888000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7888000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7915200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7915200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7915200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7942400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7942400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7942400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y7969600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y7969600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7969600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y7996800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y7996800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y7996800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8024000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8024000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8024000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8051200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8051200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8051200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8078400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8078400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8078400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8105600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8105600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8105600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8132800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8132800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8132800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8160000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8160000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8160000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8187200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8187200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8187200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8214400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8214400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8214400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8241600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8241600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8241600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8268800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8268800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8268800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8296000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8296000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8296000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8323200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8323200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8323200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8350400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8350400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8350400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8377600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8377600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8377600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8404800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8404800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8404800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8432000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8432000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8432000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8459200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8459200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8459200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8486400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8486400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8486400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8513600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8513600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8513600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8540800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8540800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8540800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8568000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8568000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8568000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8595200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8595200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8595200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8622400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8622400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8622400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8649600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8649600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8649600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8676800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8676800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8676800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8704000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8704000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8704000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8731200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8731200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8731200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8758400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8758400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8758400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8785600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8785600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8785600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8812800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8812800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8812800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8840000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8840000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8840000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8867200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8867200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8867200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8894400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8894400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8894400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8921600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8921600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8921600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y8948800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y8948800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8948800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y8976000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y8976000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y8976000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9003200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9003200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9003200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9030400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9030400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9030400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9057600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9057600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9057600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9084800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9084800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9084800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9112000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9112000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9112000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9139200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9139200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9139200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9166400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9166400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9166400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9193600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9193600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9193600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9220800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9220800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9220800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9248000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9248000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9248000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9275200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9275200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9275200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9302400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9302400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9302400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9329600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9329600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9329600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9356800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9356800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9356800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9384000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9384000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9384000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9411200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9411200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9411200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9438400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9438400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9438400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9465600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9465600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9465600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9492800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9492800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9492800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9520000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9520000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9520000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9547200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9547200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9547200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9574400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9574400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9574400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9601600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9601600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9601600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9628800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9628800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9628800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9656000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9656000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9656000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9683200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9683200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9683200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9710400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9710400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9710400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9737600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9737600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9737600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9764800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9764800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9764800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9792000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9792000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9792000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9819200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9819200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9819200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9846400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9738200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9775000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9811800y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9848600y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9885400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9922200y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9959000y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9977400y9846400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9846400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9873600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2359800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2396600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4347000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6297400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7291000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7327800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7364600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7401400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7438200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7475000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7511800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7548600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7585400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7622200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7659000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7695800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7732600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7769400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7806200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7843000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7879800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7916600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7953400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7990200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8027000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8063800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8100600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8137400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8174200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8211000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8247800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9241400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9278200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9315000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9351800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9388600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9425400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9462200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9499000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9535800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9572600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9609400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9646200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9683000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9719800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9873600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9873600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1435200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1444400y9900800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3371800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6978200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7015000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7051800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7088600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7125400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7162200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7199000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7235800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7272600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8266200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8303000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8339800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8376600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8413400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8450200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8487000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8523800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8560600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8597400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8634200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8671000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8707800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8744600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8781400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8818200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8855000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8891800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8928600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8965400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9002200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9039000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9075800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9112600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9149400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9186200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9223000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9900800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9900800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y9928000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1439800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2415000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3390200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4365400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6315800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6959800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6996600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7033400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7070200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7107000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7143800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7180600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7217400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7254200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7291000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7309400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7346200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7383000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7419800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7456600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7493400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7530200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7567000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7603800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7640600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7677400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7714200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7751000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7787800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7824600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7861400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7898200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7935000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7971800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8008600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8045400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8082200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8119000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8155800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8192600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8229400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8266200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8284600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8321400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8358200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8395000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8431800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8468600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8505400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8542200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8579000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8615800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8652600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8689400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8726200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8763000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8799800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8836600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8873400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8910200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8947000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8983800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9020600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9057400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9094200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9131000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9167800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9204600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x9241400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9259800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9296600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9333400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9370200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9407000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9443800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9480600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9517400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9554200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9591000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9627800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9664600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9701400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9747400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9784200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9821000y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9857800y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9894600y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9931400y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9968200y9928000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x9986600y9928000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6936000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef index e097ee1..601e375 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3131804fb8ed47922814b798e9db52aa9c46ec3a266a0b7555237d0c1026e0fc -size 1321656 +oid sha256:cfb3d851a1114eb1d0e5257e314de9662bd4591be78d3e3b910ebd6f961ff42a +size 1319821 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v index 79e60b2..9861918 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v @@ -8,23 +8,7 @@ module direct_interc_5 ( in , out ) ; input [0:0] in ; output [0:0] out ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( in[0] ) , .X ( out[0] ) ) ; -endmodule - - -module direct_interc_4 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( in[0] ) , .X ( out[0] ) ) ; -endmodule - - -module direct_interc_3 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( in[0] ) , .X ( out[0] ) ) ; +assign out[0] = in[0] ; endmodule @@ -52,6 +36,1642 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) ) ; endmodule +module direct_interc_4 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +assign ccff_tail[0] = mem_out[0] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +endmodule + + +module EMBEDDED_IO_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; + +assign FPGA_IN = SOC_IN ; +assign SOC_OUT = FPGA_OUT ; +assign SOC_DIR = FPGA_DIR ; +endmodule + + +module logical_tile_io_mode_physical__iopad_7 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_0_en ; +wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ; + +EMBEDDED_IO_7 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_7 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ) ) ; +endmodule + + +module logical_tile_io_mode_io__7 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +direct_interc_4 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_4 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3_3 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2_3 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1_5 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_10 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6_3 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5_3 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4_3 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0_6 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4_5 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3_5 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2_5 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_18 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7_2 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6_4 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5_4 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1_5 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_6 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; + +assign chany_bottom_out[0] = chany_top_in[0] ; +assign chany_bottom_out[1] = chany_top_in[1] ; +assign chany_bottom_out[2] = chany_top_in[2] ; +assign chany_bottom_out[3] = chany_top_in[3] ; +assign chany_bottom_out[4] = chany_top_in[4] ; +assign chany_bottom_out[5] = chany_top_in[5] ; +assign chany_bottom_out[6] = chany_top_in[6] ; +assign chany_bottom_out[7] = chany_top_in[7] ; +assign chany_bottom_out[8] = chany_top_in[8] ; +assign chany_bottom_out[9] = chany_top_in[9] ; +assign chany_bottom_out[10] = chany_top_in[10] ; +assign chany_bottom_out[11] = chany_top_in[11] ; +assign chany_bottom_out[12] = chany_top_in[12] ; +assign chany_bottom_out[13] = chany_top_in[13] ; +assign chany_bottom_out[14] = chany_top_in[14] ; +assign chany_bottom_out[15] = chany_top_in[15] ; +assign chany_bottom_out[16] = chany_top_in[16] ; +assign chany_bottom_out[17] = chany_top_in[17] ; +assign chany_bottom_out[18] = chany_top_in[18] ; +assign chany_bottom_out[19] = chany_top_in[19] ; +assign chany_top_out[0] = chany_bottom_in[0] ; +assign chany_top_out[1] = chany_bottom_in[1] ; +assign chany_top_out[2] = chany_bottom_in[2] ; +assign chany_top_out[3] = chany_bottom_in[3] ; +assign chany_top_out[4] = chany_bottom_in[4] ; +assign chany_top_out[5] = chany_bottom_in[5] ; +assign chany_top_out[6] = chany_bottom_in[6] ; +assign chany_top_out[7] = chany_bottom_in[7] ; +assign chany_top_out[8] = chany_bottom_in[8] ; +assign chany_top_out[9] = chany_bottom_in[9] ; +assign chany_top_out[10] = chany_bottom_in[10] ; +assign chany_top_out[11] = chany_bottom_in[11] ; +assign chany_top_out[12] = chany_bottom_in[12] ; +assign chany_top_out[13] = chany_bottom_in[13] ; +assign chany_top_out[14] = chany_bottom_in[14] ; +assign chany_top_out[15] = chany_bottom_in[15] ; +assign chany_top_out[16] = chany_bottom_in[16] ; +assign chany_top_out[17] = chany_bottom_in[17] ; +assign chany_top_out[18] = chany_bottom_in[18] ; +assign chany_top_out[19] = chany_bottom_in[19] ; + +mux_tree_tapbuf_size10_0_6 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( right_grid_pin_0_ ) ) ; +mux_tree_tapbuf_size10_1_5 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_16_ ) ) ; +mux_tree_tapbuf_size10_5_4 mux_right_ipin_3 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_19_ ) ) ; +mux_tree_tapbuf_size10_6_4 mux_right_ipin_4 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_20_ ) ) ; +mux_tree_tapbuf_size10_7_2 mux_right_ipin_7 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_23_ ) ) ; +mux_tree_tapbuf_size10_18 mux_right_ipin_8 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_24_ ) ) ; +mux_tree_tapbuf_size10_2_5 mux_right_ipin_11 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_27_ ) ) ; +mux_tree_tapbuf_size10_3_5 mux_right_ipin_12 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_28_ ) ) ; +mux_tree_tapbuf_size10_4_5 mux_right_ipin_15 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( left_grid_pin_31_ ) ) ; +mux_tree_tapbuf_size10_mem_0_6 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1_5 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6_4 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7_2 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_18 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2_5 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3_5 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4_5 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_0_6 mux_right_ipin_1 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_17_ ) ) ; +mux_tree_tapbuf_size8_4_3 mux_right_ipin_2 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_18_ ) ) ; +mux_tree_tapbuf_size8_5_3 mux_right_ipin_5 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_21_ ) ) ; +mux_tree_tapbuf_size8_6_3 mux_right_ipin_6 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_22_ ) ) ; +mux_tree_tapbuf_size8_10 mux_right_ipin_9 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_25_ ) ) ; +mux_tree_tapbuf_size8_1_5 mux_right_ipin_10 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_26_ ) ) ; +mux_tree_tapbuf_size8_2_3 mux_right_ipin_13 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_29_ ) ) ; +mux_tree_tapbuf_size8_3_3 mux_right_ipin_14 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_30_ ) ) ; +mux_tree_tapbuf_size8_mem_0_6 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_4_3 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5_3 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6_3 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_10 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1_5 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2_3 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +logical_tile_io_mode_io__7 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_41 } ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_42 } ) ) ; +sky130_fd_sc_hd__buf_4 FTB_41__40 ( + .A ( left_width_0_height_0__pin_1_upper[0] ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_731 ( .A ( ropt_net_41 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_732 ( .A ( ropt_net_42 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size8_mem_3_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -68,14 +1688,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__56 ( .A ( mem_out[3] ) , - .X ( net_aps_56 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( net_aps_56 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_3 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_2_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -91,7 +1709,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -112,28 +1730,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -154,7 +1751,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -175,7 +1772,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -196,7 +1793,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -217,7 +1814,28 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -236,10 +1854,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -259,14 +1874,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_2_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -354,46 +1968,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size8_9 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -570,28 +2144,51 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module mux_tree_tapbuf_size8_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_3 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_3_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -608,11 +2205,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( net_net_70 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_90 ( .A ( net_net_70 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_16 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_2_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -628,12 +2227,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_1_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -649,7 +2248,28 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -670,7 +2290,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -691,12 +2311,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_3 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_4_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -712,28 +2332,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -754,12 +2353,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_4_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_3_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -811,7 +2410,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -863,7 +2462,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_16 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_1_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -915,7 +2514,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_17 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1071,59 +2670,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_1_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_4_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1228,35 +2775,34 @@ endmodule module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , - left_grid_pin_1_ , left_grid_pin_2_ , left_grid_pin_3_ , - left_grid_pin_4_ , left_grid_pin_5_ , left_grid_pin_6_ , - left_grid_pin_7_ , left_grid_pin_8_ , left_grid_pin_9_ , - left_grid_pin_10_ , left_grid_pin_11_ , left_grid_pin_12_ , - left_grid_pin_13_ , left_grid_pin_14_ , left_grid_pin_15_ , ccff_tail ) ; + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chany_top_out ; -output [0:0] right_grid_pin_52_ ; -output [0:0] left_grid_pin_0_ ; -output [0:0] left_grid_pin_1_ ; -output [0:0] left_grid_pin_2_ ; -output [0:0] left_grid_pin_3_ ; -output [0:0] left_grid_pin_4_ ; -output [0:0] left_grid_pin_5_ ; -output [0:0] left_grid_pin_6_ ; -output [0:0] left_grid_pin_7_ ; -output [0:0] left_grid_pin_8_ ; -output [0:0] left_grid_pin_9_ ; -output [0:0] left_grid_pin_10_ ; -output [0:0] left_grid_pin_11_ ; -output [0:0] left_grid_pin_12_ ; -output [0:0] left_grid_pin_13_ ; -output [0:0] left_grid_pin_14_ ; -output [0:0] left_grid_pin_15_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -1275,8 +2821,6 @@ wire [0:3] mux_tree_tapbuf_size10_6_sram ; wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1284,8 +2828,6 @@ wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; @@ -1309,421 +2851,458 @@ wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -mux_tree_tapbuf_size10_0_5 mux_left_ipin_0 ( +mux_tree_tapbuf_size10_0_5 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_52_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size10_1_3 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_2_3 mux_right_ipin_1 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_1_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_4_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_6_3 mux_right_ipin_5 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_5_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_7_2 mux_right_ipin_8 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_8_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_16 mux_right_ipin_9 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_9_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_3_3 mux_right_ipin_12 ( + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_4_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size10_6_3 mux_right_ipin_7 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_12_ ) , .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size10_4_3 mux_right_ipin_13 ( + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_98 ) ) ; +mux_tree_tapbuf_size10_17 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[14] , chany_top_in[14] , chany_bottom_in[18] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_13_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_mem_0_5 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_1_4 mux_right_ipin_11 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_2_4 mux_right_ipin_12 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_3_4 mux_right_ipin_15 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_mem_0_5 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_3 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_3 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem_5_3 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_3 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_6_3 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_3 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem_17 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7_2 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1_4 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_16 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem_2_4 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +mux_tree_tapbuf_size10_mem_3_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_3 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_4_2 mux_right_ipin_2 ( +mux_tree_tapbuf_size8_0_5 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_2_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size8_5_2 mux_right_ipin_3 ( + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size8_4_2 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[16] , chany_top_in[16] } ) , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_3_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_6_2 mux_right_ipin_6 ( + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size8_5_2 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_6_ ) , .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size8_9 mux_right_ipin_7 ( + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_98 ) ) ; +mux_tree_tapbuf_size8_6_2 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[12] , chany_top_in[12] } ) , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_7_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_0_4 mux_right_ipin_10 ( + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_9 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_10_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size8_1_4 mux_right_ipin_11 ( + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size8_1_4 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[16] , chany_top_in[16] } ) , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_11_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size8_2_3 mux_right_ipin_14 ( + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size8_2_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_14_ ) , .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size8_3_2 mux_right_ipin_15 ( + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_3_2 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[12] , chany_top_in[12] } ) , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_15_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_mem_4_2 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size8_mem_0_5 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5_2 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_4_2 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6_2 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size8_mem_5_2 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_9 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_6_2 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0_4 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , +mux_tree_tapbuf_size8_mem_9 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_4 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_1_4 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , +mux_tree_tapbuf_size8_mem_2_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3_2 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_3_2 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_113 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , + .X ( ropt_net_112 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( aps_rename_4_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( aps_rename_5_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chany_top_in[1] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_111 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_29__28 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__39 ( .A ( chany_top_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( + .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_bottom_in[19] ) , - .X ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_top_in[16] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_1_ ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( aps_rename_2_ ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( aps_rename_4_ ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_5_ ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_112 ) , .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_113 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_114 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_115 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , + .X ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_116 ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_117 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_98 ( .A ( BUF_net_68 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_71 ) , - .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( aps_rename_1_ ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_59 ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( net_net_76 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( net_net_76 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; +module direct_interc_3 ( in , out ) ; +input [0:0] in ; output [0:0] out ; -input p0 ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +assign out[0] = in[0] ; endmodule -module mux_tree_tapbuf_size10_0_4 ( in , sram , sram_inv , out , p0 ) ; +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module EMBEDDED_IO_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +wire aps_rename_2_ ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , + .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_6 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_6 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__6 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_3 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_3 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_16 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1776,538 +3355,367 @@ endmodule module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , - ccff_tail ) ; + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , + right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chany_top_out ; -output [0:0] right_grid_pin_52_ ; output [0:0] left_grid_pin_0_ ; output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +wire ropt_net_162 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -mux_tree_tapbuf_size10_0_4 mux_left_ipin_0 ( +mux_tree_tapbuf_size10_16 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_52_ ) , .p0 ( optlc_net_144 ) ) ; -mux_tree_tapbuf_size10_15 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_145 ) ) ; -mux_tree_tapbuf_size10_mem_0_4 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size10_mem_16 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_15 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_177 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_153 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_154 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_155 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_156 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_157 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_158 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_159 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , - .X ( chany_bottom_out[15] ) ) ; +logical_tile_io_mode_io__6 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_163 } ) , + .p_abuf0 ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , + .X ( ropt_net_227 ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , - .X ( chany_bottom_out[19] ) ) ; + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , + .X ( ropt_net_210 ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_164 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_166 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_167 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_168 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_169 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_172 ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_175 ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_176 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_180 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_45 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_182 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_183 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_184 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_185 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_186 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_188 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_189 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_190 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_191 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_192 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_193 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_194 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_65 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chany_top_in[9] ) , - .X ( BUF_net_66 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_196 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_197 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_198 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_200 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_111 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_115 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_117 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_131 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_66 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chany_top_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) , + .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chany_top_in[15] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) , .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module direct_interc_2 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( net_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_115 ( .A ( net_net_74 ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( net_aps_61 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; +module EMBEDDED_IO_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( p_abuf0 ) , .X ( FPGA_IN ) ) ; endmodule -module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_0_ , ccff_tail ) ; +module logical_tile_io_mode_physical__iopad_5 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_0_ ; +output [0:0] iopad_inpad ; output [0:0] ccff_tail ; +output p_abuf0 ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] EMBEDDED_IO_0_en ; -mux_tree_tapbuf_size10_14 mux_bottom_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_143 ) ) ; -mux_tree_tapbuf_size10_mem_14 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ropt_net_181 } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_144 ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_148 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_149 ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_152 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_155 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_167 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_172 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_44 ( .A ( chanx_left_in[8] ) , - .X ( BUF_net_44 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_197 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_198 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_199 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_200 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_203 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_204 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_207 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_209 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_214 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_216 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_103 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_104 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_116 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_44 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_132 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_155 ) ) ; +EMBEDDED_IO_5 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__5 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) ) ; +direct_interc_2 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf0 } ) ) ; +direct_interc_2 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; endmodule @@ -2327,14 +3735,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( net_net_72 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_2_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -2350,7 +3756,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2371,28 +3777,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2413,7 +3798,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2434,7 +3819,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2455,7 +3840,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2476,7 +3861,28 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2525,7 +3931,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2539,10 +3945,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -2562,10 +3965,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -2613,50 +4015,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size8_8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -2664,46 +4022,6 @@ input [0:3] sram_inv ; output [0:0] out ; input p0 ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -2741,6 +4059,46 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size8_6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size8_5_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -2829,7 +4187,47 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_3_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -2845,12 +4243,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_3_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -2866,12 +4264,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_13 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_2_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -2887,7 +4285,49 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2908,7 +4348,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2929,12 +4369,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_1_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -2950,12 +4390,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_0_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -2971,33 +4411,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_3_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_4_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3049,7 +4468,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3101,7 +4520,111 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_13 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3257,7 +4780,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_1_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3309,7 +4832,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_0_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3361,89 +4884,54 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , - top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , - top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , - top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , - top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , - top_grid_pin_30_ , top_grid_pin_31_ , ccff_tail ) ; +module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , + bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_16_ ; -output [0:0] top_grid_pin_17_ ; -output [0:0] top_grid_pin_18_ ; -output [0:0] top_grid_pin_19_ ; -output [0:0] top_grid_pin_20_ ; -output [0:0] top_grid_pin_21_ ; -output [0:0] top_grid_pin_22_ ; -output [0:0] top_grid_pin_23_ ; -output [0:0] top_grid_pin_24_ ; -output [0:0] top_grid_pin_25_ ; -output [0:0] top_grid_pin_26_ ; -output [0:0] top_grid_pin_27_ ; -output [0:0] top_grid_pin_28_ ; -output [0:0] top_grid_pin_29_ ; -output [0:0] top_grid_pin_30_ ; -output [0:0] top_grid_pin_31_ ; +output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +wire p_abuf0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -3460,6 +4948,8 @@ wire [0:3] mux_tree_tapbuf_size10_6_sram ; wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -3491,315 +4981,326 @@ wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -mux_tree_tapbuf_size10_0_3 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0_4 mux_bottom_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_16_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_1_2 mux_bottom_ipin_1 ( + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_1_3 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_4_2 mux_bottom_ipin_4 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_5_2 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_5_2 mux_bottom_ipin_5 ( + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_6_2 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( top_grid_pin_21_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_6_2 mux_bottom_ipin_8 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_7_1 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_13 mux_bottom_ipin_9 ( + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_15 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_2_2 mux_bottom_ipin_12 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_2_3 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_3_2 mux_bottom_ipin_13 ( + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_3_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_mem_0_3 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_4_3 mux_top_ipin_15 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_mem_0_4 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_2 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1_3 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_2 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , +mux_tree_tapbuf_size10_mem_5_2 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_2 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_6_2 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_2 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size10_mem_7_1 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_13 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , +mux_tree_tapbuf_size10_mem_15 mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , +mux_tree_tapbuf_size10_mem_2_3 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_2 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , +mux_tree_tapbuf_size10_mem_3_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size8_4_1 mux_bottom_ipin_2 ( +mux_tree_tapbuf_size10_mem_4_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_0_4 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_5_1 mux_bottom_ipin_3 ( + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_4_1 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_6_1 mux_bottom_ipin_6 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_5_1 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( top_grid_pin_22_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_8 mux_bottom_ipin_7 ( + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_6_1 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_0_3 mux_bottom_ipin_10 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size8_8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_1_3 mux_bottom_ipin_11 ( + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_1_3 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_2_2 mux_bottom_ipin_14 ( + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_2_1 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_3_1 mux_bottom_ipin_15 ( + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_3_1 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_mem_4_1 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size8_mem_0_4 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5_1 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size8_mem_4_1 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6_1 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , +mux_tree_tapbuf_size8_mem_5_1 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_8 mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size8_mem_6_1 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0_3 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , +mux_tree_tapbuf_size8_mem_8 mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_3 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , +mux_tree_tapbuf_size8_mem_1_3 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , +mux_tree_tapbuf_size8_mem_2_1 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3_1 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_3_1 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_97 } ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_105 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_673 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_106 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_107 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_675 ( .A ( ropt_net_97 ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_108 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_98 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , +logical_tile_io_mode_io__5 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_102 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_682 ( .A ( ropt_net_103 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_104 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_119 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , .X ( chanx_left_out[17] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_59 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chanx_left_in[9] ) , - .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( BUF_net_61 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( aps_rename_3_ ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_82 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_2_ ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( p_abuf0 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_right_in[5] ) , .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_2_ ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_3_ ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; endmodule @@ -3819,12 +5320,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -3840,7 +5341,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3861,28 +5362,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3903,7 +5383,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3924,7 +5404,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3945,7 +5425,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3966,7 +5446,28 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -4015,7 +5516,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4103,7 +5604,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_7 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4147,46 +5648,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -4315,7 +5776,51 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_12 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -4331,14 +5836,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( net_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( net_net_69 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_2_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -4354,12 +5857,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_1_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -4375,12 +5878,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_14 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -4396,7 +5899,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -4417,7 +5920,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -4438,12 +5941,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_4_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -4459,12 +5962,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_0_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -4480,33 +5983,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_12 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4558,7 +6040,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4610,7 +6092,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_1_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4662,7 +6144,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_14 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4818,6 +6300,1267 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size10_4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , CLB_SC_IN , CLB_SC_OUT , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input CLB_SC_IN ; +output CLB_SC_OUT ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; + +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0_3 mux_top_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_4_2 mux_top_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_5_1 mux_top_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_6_1 mux_top_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_14 mux_top_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_1_2 mux_top_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_2_2 mux_top_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_3_2 mux_top_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_mem_0_3 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4_2 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5_1 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6_1 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_14 mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3_2 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size8_0_3 mux_top_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_7 mux_top_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_1_2 mux_top_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_mem_0_3 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_7 mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1_2 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( ropt_net_105 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( aps_rename_6_ ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( ropt_net_106 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_107 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_108 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_109 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( aps_rename_4_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[19] ) , + .X ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chanx_right_in[12] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chanx_right_in[16] ) , + .X ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( aps_rename_6_ ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( BUF_net_65 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( BUF_net_69 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_71 ) , + .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( CLB_SC_IN ) , + .X ( CLB_SC_OUT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( aps_rename_4_ ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb15_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__70 ( .A ( mem_out[0] ) , + .X ( net_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_114 ( .A ( net_net_114 ) , + .X ( net_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_152 ( .A ( net_net_113 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb14_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( net_aps_67 ) ) ; +endmodule + + +module EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb11_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( net_aps_64 ) ) ; +endmodule + + +module EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__63 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb8_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) ) ; +endmodule + + +module EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_14__60 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_155 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb5_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( net_aps_58 ) ) ; +endmodule + + +module EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module direct_interc_1 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb2_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( net_aps_55 ) ) ; +endmodule + + +module EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size10_4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -4870,6 +7613,110 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size10_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size10_1_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -4938,10 +7785,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -4967,45 +7811,73 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , - top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , - top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , - top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , - top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , - top_grid_pin_30_ , top_grid_pin_31_ , bottom_grid_pin_0_ , ccff_tail ) ; + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , + top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , + top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , + top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , + top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , + top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , + top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_16_ ; -output [0:0] top_grid_pin_17_ ; -output [0:0] top_grid_pin_18_ ; -output [0:0] top_grid_pin_19_ ; -output [0:0] top_grid_pin_20_ ; -output [0:0] top_grid_pin_21_ ; -output [0:0] top_grid_pin_22_ ; -output [0:0] top_grid_pin_23_ ; -output [0:0] top_grid_pin_24_ ; -output [0:0] top_grid_pin_25_ ; -output [0:0] top_grid_pin_26_ ; -output [0:0] top_grid_pin_27_ ; -output [0:0] top_grid_pin_28_ ; -output [0:0] top_grid_pin_29_ ; -output [0:0] top_grid_pin_30_ ; -output [0:0] top_grid_pin_31_ ; output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; output [0:0] ccff_tail ; +input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +wire ropt_net_188 ; +wire ropt_net_186 ; +wire ropt_net_190 ; +wire ropt_net_184 ; +wire ropt_net_185 ; +wire ropt_net_183 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -5018,351 +7890,381 @@ wire [0:3] mux_tree_tapbuf_size10_4_sram ; wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -mux_tree_tapbuf_size10_0_2 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0_2 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_16_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_1_1 mux_bottom_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_177 ) ) ; +mux_tree_tapbuf_size10_1_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_4_1 mux_bottom_ipin_4 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_2_1 mux_top_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_3_1 mux_top_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_4_1 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_5_1 mux_bottom_ipin_5 ( + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_13 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( top_grid_pin_21_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_6_1 mux_bottom_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_7_1 mux_bottom_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_2_1 mux_bottom_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_3_1 mux_bottom_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_12 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_mem_0_2 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_177 ) ) ; +mux_tree_tapbuf_size10_mem_0_2 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_1 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , +mux_tree_tapbuf_size10_mem_2_1 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_1 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_3_1 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_1 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4_1 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7_1 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , +mux_tree_tapbuf_size10_mem_13 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_1 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_1 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_12 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( top_grid_pin_22_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_7 mux_bottom_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_0_2 mux_bottom_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_1_2 mux_bottom_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_2_1 mux_bottom_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_7 mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0_2 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_2 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2_1 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_92 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_672 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_673 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , +logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_12_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( ropt_net_188 ) ) ; +logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_206 } ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , + .p_abuf0 ( ropt_net_186 ) ) ; +logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_14_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , + .p_abuf0 ( ropt_net_190 ) ) ; +logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_15_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , + .p_abuf0 ( ropt_net_184 ) ) ; +logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_16_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , + .p_abuf0 ( ropt_net_185 ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_17_ } ) , + .ccff_tail ( { ropt_net_221 } ) , + .p_abuf0 ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_230 ) , .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_176 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_183 ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_184 ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_185 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_186 ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_187 ) , + .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_188 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_190 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( BUF_net_111 ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_110 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[12] ) , .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_231 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_194 ) , + .X ( ropt_net_247 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_232 ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( BUF_net_109 ) , + .X ( ropt_net_246 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_right_in[15] ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_1_ ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_76 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_77 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_78 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_82 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_233 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_197 ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_234 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_235 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_199 ) , + .X ( ropt_net_251 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_201 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_202 ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_236 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_237 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_238 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_205 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_43__42 ( .A ( aps_rename_14_ ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_44__43 ( .A ( aps_rename_15_ ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_206 ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_208 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_212 ) , + .X ( ropt_net_248 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_213 ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_214 ) , + .X ( ropt_net_243 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_239 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[14] ) , + .X ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_216 ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_242 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_right_in[9] ) , + .X ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( chanx_right_in[10] ) , + .X ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_243 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_244 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_245 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_246 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_218 ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( aps_rename_12_ ) , + .X ( BUF_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_110 ( .A ( aps_rename_13_ ) , + .X ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_111 ( .A ( aps_rename_16_ ) , + .X ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_219 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_220 ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_221 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_222 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_223 ) , + .X ( ropt_net_249 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_224 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_225 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_227 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_247 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_248 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_249 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_250 ) , .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_252 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_253 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_254 ) , .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_255 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_256 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_257 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_146 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_147 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_148 ( .A ( BUF_net_102 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_149 ( .A ( BUF_net_103 ) , + .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_158 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_159 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_161 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_162 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_163 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_164 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_92 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_167 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_173 ( .A ( aps_rename_17_ ) , + .X ( ropt_net_205 ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_15_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem_1_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5374,9 +8276,132 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__39 ( .A ( mem_out[1] ) , - .X ( net_net_59 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( net_net_59 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( net_net_48 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_48 ( .A ( net_net_48 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5393,12 +8418,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_16_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5410,12 +8435,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_14_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5427,12 +8452,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_13_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5444,12 +8469,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_12_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_18_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5461,12 +8486,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_11_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_17_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5478,12 +8503,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_10_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_16_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5495,12 +8520,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_15_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5512,12 +8537,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_8_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_14_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5529,12 +8554,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_7_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_13_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5546,7 +8571,92 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5563,12 +8673,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_5_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_5_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5580,12 +8690,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_4_5 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -5597,7 +8707,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5614,7 +8724,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5631,7 +8741,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5648,7 +8758,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5665,12 +8775,29 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_15_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_mem_9_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -5710,7 +8837,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_16_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -5730,7 +8857,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_14_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -5750,7 +8877,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_13_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -5770,7 +8897,167 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_12_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_18_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_17_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_16_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -5786,7 +9073,7 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -5806,7 +9093,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_10_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_7_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -5814,75 +9101,11 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -5906,7 +9129,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_5_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_5_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -5914,19 +9137,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_4_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_4_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -6026,42 +9245,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem_0_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_0_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; +module mux_tree_tapbuf_size2_9_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; @@ -6069,44 +9254,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( BUF_net_41 ) , - .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -6124,7 +9279,45 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -6143,7 +9336,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -6180,6 +9373,70 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module mux_tree_tapbuf_size5_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size5_0_4 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; @@ -6193,6 +9450,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -6207,12 +9466,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_87 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_10 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_11 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -6226,12 +9483,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0_6 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_2_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -6245,724 +9502,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_0_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , - bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , - bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , - bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , - bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , - left_top_grid_pin_1_ , ccff_head , chany_bottom_out , chanx_left_out , - ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; - -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; - -mux_tree_tapbuf_size6_0_6 mux_bottom_track_1 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size6_10 mux_bottom_track_5 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size6_mem_0_6 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_10 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0_4 mux_bottom_track_3 ( - .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_123 } ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size5_8 mux_bottom_track_7 ( - .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , - chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size5_mem_0_4 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_8 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_11 mux_bottom_track_9 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , - chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size3_0_6 mux_bottom_track_25 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size3_mem_11 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0_6 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_0_5 mux_bottom_track_11 ( - .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_1_5 mux_bottom_track_13 ( - .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_2_5 mux_bottom_track_15 ( - .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_3_5 mux_bottom_track_17 ( - .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_4_4 mux_bottom_track_19 ( - .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_5_4 mux_bottom_track_21 ( - .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_6_3 mux_bottom_track_23 ( - .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_7_2 mux_bottom_track_27 ( - .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_8_2 mux_bottom_track_29 ( - .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_9_2 mux_bottom_track_31 ( - .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( { ropt_net_120 } ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_10_2 mux_bottom_track_33 ( - .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_11_1 mux_bottom_track_35 ( - .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_12_1 mux_bottom_track_37 ( - .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_13_1 mux_bottom_track_39 ( - .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_14_1 mux_left_track_1 ( - .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_16_1 mux_left_track_5 ( - .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_22 mux_left_track_9 ( - .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_15_1 mux_left_track_25 ( - .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_mem_0_5 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_5 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_5 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_5 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6_3 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7_2 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8_2 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9_2 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11_1 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12_1 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13_1 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_22 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_128 } ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_113 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chany_bottom_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( - .A ( chany_bottom_in[16] ) , .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_120 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( - .A ( chany_bottom_in[17] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( chany_bottom_in[8] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( ropt_net_123 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( - .A ( chany_bottom_in[15] ) , .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_bottom_in[0] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( - .A ( chany_bottom_in[12] ) , .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( - .A ( chany_bottom_in[18] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_128 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_129 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chany_bottom_in[4] ) , - .X ( BUF_net_46 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[9] ) , - .X ( BUF_net_51 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chany_bottom_in[10] ) , - .X ( BUF_net_52 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_136 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chany_bottom_in[13] ) , - .X ( BUF_net_54 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[14] ) , - .X ( BUF_net_55 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_131 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_140 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_46 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_98 ( .A ( BUF_net_51 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_99 ( .A ( BUF_net_52 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_54 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_55 ) , - .X ( chanx_left_out[15] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , - .X ( net_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( net_net_80 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_2_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_1_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_0_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_2_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_1_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -6976,264 +9521,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_1_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_104 ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -7252,31 +9540,84 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module mux_tree_tapbuf_size6_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_1_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1_2 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -7348,7 +9689,1324 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; + +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size6_0_5 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size6_1_2 mux_bottom_track_5 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6_2_1 mux_left_track_1 ( + .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6_11 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6_mem_0_5 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_2_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_11 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_0_4 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size5_1_1 mux_bottom_track_7 ( + .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , + chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size5_2_1 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size5_8 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size5_mem_0_4 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_2_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_8 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_9_3 mux_bottom_track_9 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_0_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_1_5 mux_bottom_track_13 ( + .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_2_5 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_3_5 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_4_5 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_5_3 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( { ropt_net_83 } ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_6_3 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_7_3 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_8_3 mux_bottom_track_29 ( + .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_10_3 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_11_3 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size2_12_3 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_13_3 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_14_3 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_81 } ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_15_2 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size2_16_2 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_17_1 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_18_1 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_19 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_20 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_21 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_22 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_23 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_mem_9_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0_5 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_5 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_5 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_5 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4_5 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5_3 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6_3 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7_3 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_8_3 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_11_3 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16_2 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_17_1 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_18_1 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_23 mem_left_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( { ropt_net_84 } ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) ) ; +mux_tree_tapbuf_size3_0_6 mux_bottom_track_25 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size3_10 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size3_1_4 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size3_mem_0_6 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_10 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_87 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_92 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_93 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_88 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_82 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_94 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chanx_left_in[18] ) , + .X ( BUF_net_46 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( ropt_net_95 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_60 ( .A ( BUF_net_46 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_75 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_76 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_77 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_78 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_667 ( .A ( ropt_net_81 ) , + .X ( ropt_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( ropt_net_82 ) , + .X ( ropt_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_83 ) , + .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_84 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_672 ( .A ( ropt_net_86 ) , + .X ( ropt_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_87 ) , + .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_88 ) , + .X ( ropt_net_93 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( ropt_net_96 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_97 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_98 ) , + .X ( chany_bottom_out[16] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , + .X ( net_net_91 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_91 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -7384,7 +11042,79 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_4_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7398,12 +11128,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_3_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7417,7 +11147,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -7436,7 +11166,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -7455,7 +11185,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -7474,12 +11204,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_8 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7493,12 +11223,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_5_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_5_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7512,12 +11242,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_4_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -7557,7 +11287,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -7572,8 +11302,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -7594,6 +11322,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -7717,7 +11447,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_10 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -7757,7 +11487,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_5_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_5_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -7813,7 +11543,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -7834,7 +11564,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -7975,7 +11705,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_0_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -7991,7 +11721,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8012,7 +11742,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8033,12 +11763,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_0_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_0_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -8186,12 +11916,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_11 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem_12 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8207,7 +11937,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8230,8 +11960,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -8261,10 +11989,14 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_61 ) , + .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_11 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_12 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -8316,49 +12048,50 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , top_right_grid_pin_1_ , chany_bottom_in , - bottom_right_grid_pin_1_ , bottom_left_grid_pin_34_ , - bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , - bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , - bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , - bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , - left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , - left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , - left_top_grid_pin_49_ , ccff_head , chany_top_out , chany_bottom_out , +module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , + bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , chanx_left_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:0] top_right_grid_pin_1_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chany_bottom_out ; @@ -8377,6 +12110,23 @@ wire [0:3] mux_tree_tapbuf_size14_1_sram ; wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -8391,6 +12141,7 @@ wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; @@ -8446,23 +12197,24 @@ wire [0:3] mux_tree_tapbuf_size9_0_sram ; wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -mux_tree_tapbuf_size10_11 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , +mux_tree_tapbuf_size10_12 mux_top_track_0 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size10_0_1 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size10_mem_11 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_166 } ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size10_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , @@ -8473,27 +12225,27 @@ mux_tree_tapbuf_size10_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; mux_tree_tapbuf_size8_1_1 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size8_3 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size8_0_1 mux_bottom_track_9 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size8_0_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size8_mem_1_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -8504,31 +12256,31 @@ mux_tree_tapbuf_size8_mem_3 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_0_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; mux_tree_tapbuf_size14_1 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , - top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , - top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , + top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size14_0_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_40_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size14_mem_1 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -8539,61 +12291,62 @@ mux_tree_tapbuf_size14_mem_0_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_5_1 mux_top_track_16 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , +mux_tree_tapbuf_size7_5_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size7_8 mux_top_track_24 ( - .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size7_10 mux_top_track_24 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size7_0_4 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_38_[0] , chanx_left_in[5] , chanx_left_in[12] , + .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_1_4 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , - left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size7_2_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , - left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_3_1 mux_left_track_5 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size7_3_2 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , - left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_4_1 mux_left_track_7 ( + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( { ropt_net_158 } ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size7_4_2 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , - left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_mem_5_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size7_mem_5_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_8 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , @@ -8613,151 +12366,150 @@ mux_tree_tapbuf_size7_mem_2_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_3_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4_1 mem_left_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_4_2 mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size6_9 mux_top_track_32 ( - .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size6_10 mux_top_track_32 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size6_0_5 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_39_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size6_0_4 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size6_1_3 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[0] , chanx_left_in[7] , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size6_1_1 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size6_mem_9 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size6_mem_10 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_5 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem_0_4 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem_1_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size9_1 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[2] , chanx_left_in[9] , +mux_tree_tapbuf_size9_2 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size9_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size9_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_8 mux_left_track_9 ( +mux_tree_tapbuf_size4_9 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , - left_top_grid_pin_42_[0] } ) , + left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size4_0_3 mux_left_track_11 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size4_0_5 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , - left_top_grid_pin_43_[0] } ) , + left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_129 } ) , - .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size4_1_2 mux_left_track_13 ( + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size4_1_4 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , - left_top_grid_pin_44_[0] } ) , + left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size4_2_2 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size4_2_3 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , - left_top_grid_pin_45_[0] } ) , + left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size4_mem_8 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size4_mem_9 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_0_5 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1_2 mem_left_track_13 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_1_4 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_2_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; mux_tree_tapbuf_size3_0_5 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , - left_top_grid_pin_46_[0] } ) , + left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size3_1_4 mux_left_track_19 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size3_1_3 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , - left_top_grid_pin_47_[0] } ) , + left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size3_2_4 mux_left_track_21 ( + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size3_2_3 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , - left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3_3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , - left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size3_10 mux_left_track_25 ( + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size3_9 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , - left_top_grid_pin_42_[0] } ) , + left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_123 ) ) ; + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( { ropt_net_155 } ) , + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3_mem_0_5 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_1_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2_4 mem_left_track_21 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_2_3 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , @@ -8767,165 +12519,378 @@ mux_tree_tapbuf_size3_mem_3_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_10 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( { ropt_net_127 } ) , +mux_tree_tapbuf_size3_mem_9 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_155 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_156 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_126 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( ropt_net_127 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[1] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_129 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_157 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_top_in[4] ) , +mux_tree_tapbuf_size2_0_4 mux_left_track_29 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( { ropt_net_156 } ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_1_4 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_2_4 mux_left_track_33 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_3_4 mux_left_track_35 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_4_4 mux_left_track_37 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_21 mux_left_track_39 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size2_mem_0_4 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_4 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_4 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_4 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_21 mem_left_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( { ropt_net_154 } ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( - .A ( chany_bottom_in[13] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_136 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( left_top_grid_pin_43_[0] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_158 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_140 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_160 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_141 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_142 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_143 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_144 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_162 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_145 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_146 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_151 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_152 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_153 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_164 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_167 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_168 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_170 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_154 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_155 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_156 ) , .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( + .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_158 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_161 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_162 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chany_top_in[16] ) , + .X ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_165 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_168 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_169 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_170 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_179 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_180 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_80 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_89 ) , + .X ( chanx_left_out[13] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_7_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8937,11 +12902,60 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , - .X ( net_net_49 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_49 ( .A ( net_net_49 ) , - .X ( net_net_48 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( net_net_48 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__35 ( .A ( mem_out[1] ) , + .X ( net_net_71 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( net_net_71 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8958,1930 +12972,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_10_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_9_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_8_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_5_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_4_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_3_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_1_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_0_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_1_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_65 ( .A ( BUF_net_41 ) , - .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_1_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_1_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_0_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , top_right_grid_pin_1_ , chanx_left_in , - left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , - left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , - left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , - ccff_head , chany_top_out , chanx_left_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; - -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; - -mux_tree_tapbuf_size6_2_2 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size6_8 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size6_0_4 mux_left_track_1 ( - .in ( { chany_top_in[0] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size6_1_2 mux_left_track_5 ( - .in ( { chany_top_in[18] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size6_mem_2_2 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_8 mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_2_2 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_7 mux_top_track_6 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size5_0_3 mux_left_track_3 ( - .in ( { chany_top_in[19] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_1_2 mux_left_track_7 ( - .in ( { chany_top_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_mem_2_2 mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_7 mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1_2 mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_9 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( { ropt_net_89 } ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size3_2_3 mux_top_track_24 ( - .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size3_1_3 mux_left_track_9 ( - .in ( { chany_top_in[16] , left_top_grid_pin_42_[0] , - left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_0_4 mux_left_track_25 ( - .in ( { chany_top_in[8] , left_top_grid_pin_42_[0] , - left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size3_mem_9 mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2_3 mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_3 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_8_1 mux_top_track_10 ( - .in ( { top_left_grid_pin_35_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size2_9_1 mux_top_track_12 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size2_10_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_11 mux_top_track_16 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_12 mux_top_track_18 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_20 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_22 ( - .in ( { top_left_grid_pin_41_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_15 mux_top_track_26 ( - .in ( { top_left_grid_pin_35_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_16 mux_top_track_28 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_17 mux_top_track_30 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chany_top_out[15] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_32 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_19 mux_top_track_34 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chany_top_out[17] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_20 mux_top_track_36 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_21 mux_top_track_38 ( - .in ( { top_left_grid_pin_41_[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_0_4 mux_left_track_11 ( - .in ( { chany_top_in[15] , left_top_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_1_4 mux_left_track_13 ( - .in ( { chany_top_in[14] , left_top_grid_pin_44_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_2_4 mux_left_track_15 ( - .in ( { chany_top_in[13] , left_top_grid_pin_45_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_3_4 mux_left_track_17 ( - .in ( { chany_top_in[12] , left_top_grid_pin_46_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_4_3 mux_left_track_19 ( - .in ( { chany_top_in[11] , left_top_grid_pin_47_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_5_3 mux_left_track_21 ( - .in ( { chany_top_in[10] , left_top_grid_pin_48_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_6_2 mux_left_track_23 ( - .in ( { chany_top_in[9] , left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_7_1 mux_left_track_27 ( - .in ( { chany_top_in[7] , left_top_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_mem_8_1 mem_top_track_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9_1 mem_top_track_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_top_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_18 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_20 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_22 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_top_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_top_track_28 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_top_track_30 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_top_track_34 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_top_track_36 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_21 mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0_4 mem_left_track_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_4 mem_left_track_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_4 mem_left_track_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_3 mem_left_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6_2 mem_left_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7_1 mem_left_track_27 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( { ropt_net_88 } ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_676 ( .A ( ropt_net_91 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_79 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_678 ( .A ( ropt_net_93 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_679 ( .A ( ropt_net_94 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_95 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_93 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_84 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_63 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_85 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_85 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_67 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_672 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_88 ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_89 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_90 ) , - .X ( ropt_net_91 ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -10898,12 +12989,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_4_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10915,7 +13006,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -10932,7 +13023,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -10949,7 +13040,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -10966,7 +13057,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -10983,12 +13074,165 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_mem_11_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11008,6 +13252,82 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_9_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size2_5_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -11028,7 +13348,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_4_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11096,11 +13416,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -11114,445 +13438,197 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( +endmodule + + +module mux_tree_tapbuf_size2_11_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__52 ( .A ( mem_out[2] ) , - .X ( net_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_95 ( .A ( net_net_95 ) , - .X ( net_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_130 ( .A ( net_net_94 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_0_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size2_16_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_136 ( .A ( BUF_net_69 ) , - .X ( out[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size2_15_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_68 ) , - .X ( out[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_1_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size2_14_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_0_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size2_13_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_5_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_4 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -11564,92 +13640,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__44 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__43 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__42 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__41 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__39 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -11666,12 +13657,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_5_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3_0_4 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11695,6 +13686,971 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule +module mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , + chany_top_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; + +mux_tree_tapbuf_size6_0_3 mux_top_track_0 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_109 } ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size6_9 mux_top_track_4 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size6_mem_0_3 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_9 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0_3 mux_top_track_2 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size5_7 mux_top_track_6 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size5_mem_0_3 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_7 mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_8 mux_top_track_8 ( + .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size3_0_4 mux_top_track_24 ( + .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size3_mem_8 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0_4 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_12_2 mux_top_track_10 ( + .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_13_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_14_2 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_15_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_16_1 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_17 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_18 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_20 mux_top_track_26 ( + .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_11_2 mux_left_track_9 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_0_3 mux_left_track_11 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_1_3 mux_left_track_13 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_2_3 mux_left_track_15 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_3_3 mux_left_track_17 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_4_3 mux_left_track_19 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_5_2 mux_left_track_25 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_6_2 mux_left_track_27 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( { ropt_net_108 } ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_7_2 mux_left_track_29 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( { ropt_net_103 } ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_8_2 mux_left_track_31 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_9_2 mux_left_track_33 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size2_10_2 mux_left_track_35 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size2_mem_12_2 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14_2 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16_1 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_top_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_11_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_3 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6_2 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7_2 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_8_2 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10_2 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( { ropt_net_105 } ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; +mux_tree_tapbuf_size4_0_4 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_1_3 mux_left_track_3 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_2_2 mux_left_track_5 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size4_8 mux_left_track_7 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_mem_0_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_8 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_118 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_119 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_103 ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_left_in[4] ) , + .X ( BUF_net_56 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_left_in[5] ) , + .X ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_66 ( .A ( BUF_net_56 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_84 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( BUF_net_57 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_86 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_123 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_125 ) , + .X ( chanx_left_out[10] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( net_net_89 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size3_4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -11815,103 +14771,144 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size4_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module mux_tree_tapbuf_size4_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -module mux_tree_tapbuf_size5_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule @@ -11929,177 +14926,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__33 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__32 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__31 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; @@ -12132,8 +14963,160 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; +module mux_tree_tapbuf_size7_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -12144,9 +15127,704 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12155,19 +15833,31 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -12176,6 +15866,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -12185,116 +15878,30 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__30 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__29 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__28 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__27 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__26 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -12304,33 +15911,66 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_0_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size10_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -12340,9 +15980,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12353,164 +15997,96 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; endmodule module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - chany_bottom_in , bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , - bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , - bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , - bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , - left_top_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , - chanx_left_out , ccff_tail ) ; + right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -12523,62 +16099,26 @@ wire [0:1] mux_tree_tapbuf_size3_4_sram ; wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_5_sram ; -wire [0:2] mux_tree_tapbuf_size5_5_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_6_sram ; -wire [0:2] mux_tree_tapbuf_size5_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; @@ -12587,522 +16127,542 @@ wire [0:2] mux_tree_tapbuf_size7_2_sram ; wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; -mux_tree_tapbuf_size6_2_1 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[5] , +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_11 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_3_1 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[3] , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size10_mem_11 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size9 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size9_0 mux_left_track_1 ( + .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , + chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size9_1 mux_left_track_3 ( + .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[7] , chany_bottom_in[14] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; +mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; +mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) ) ; +mux_tree_tapbuf_size14 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_7 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[2] , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_2 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_0_3 mux_left_track_5 ( - .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size6_1_1 mux_left_track_9 ( + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size8_0_1 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size6_mem_2_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_3_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_7 mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; -mux_tree_tapbuf_size5_5 mux_right_track_2 ( - .in ( { chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_172 } ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size5_4 mux_right_track_16 ( - .in ( { chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , + chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_6_1 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , + chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size5_6 mux_right_track_24 ( - .in ( { chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size5_0_2 mux_left_track_1 ( - .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , - chany_bottom_in[13] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size5_3_1 mux_left_track_3 ( - .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[7] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size5_1_1 mux_left_track_17 ( - .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_5_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size5_2_1 mux_left_track_25 ( - .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , - chany_bottom_in[11] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_6_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size5_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_6 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_3_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_5_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_2_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_6_sram_inv ) ) ; -mux_tree_tapbuf_size3_8 mux_right_track_32 ( - .in ( { chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size3_0_3 mux_bottom_track_13 ( - .in ( { chanx_right_in[10] , bottom_left_grid_pin_36_[0] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size3_1_2 mux_bottom_track_15 ( - .in ( { chanx_right_in[12] , bottom_left_grid_pin_37_[0] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size3_2_2 mux_bottom_track_17 ( - .in ( { chanx_right_in[13] , bottom_left_grid_pin_38_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size3_3_2 mux_bottom_track_19 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_39_[0] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_4_1 mux_bottom_track_21 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_40_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_5_1 mux_bottom_track_23 ( - .in ( { chanx_right_in[17] , bottom_left_grid_pin_41_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_mem_8 mem_right_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0_3 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3_2 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4_1 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_5_1 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_0_3 mux_bottom_track_1 ( - .in ( { chanx_right_in[2] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( { ropt_net_175 } ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size7_1_3 mux_bottom_track_3 ( - .in ( { chanx_right_in[4] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_9 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , + chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_2_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[5] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_0_3 mux_bottom_track_1 ( + .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( { ropt_net_207 } ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_7 mux_bottom_track_7 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size7_1_3 mux_bottom_track_3 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_mem_0_3 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_175 } ) , + .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_3_1 mux_bottom_track_7 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_4_1 mux_left_track_17 ( + .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_5_1 mux_left_track_25 ( + .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , + chany_bottom_in[11] , chany_bottom_in[18] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( { ropt_net_165 } ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size7_mem_6_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1_3 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_9 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , +mux_tree_tapbuf_size7_mem_0_3 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_7 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_1_3 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size4_2_1 mux_bottom_track_9 ( - .in ( { chanx_right_in[8] , bottom_left_grid_pin_34_[0] , +mux_tree_tapbuf_size7_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_3_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_4_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_5_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; +mux_tree_tapbuf_size5_6 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size5_mem_6 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_7 mux_bottom_track_9 ( + .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size4_0_2 mux_bottom_track_11 ( - .in ( { chanx_right_in[9] , bottom_left_grid_pin_35_[0] , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size4_0_3 mux_bottom_track_11 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_176 } ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size4_1_1 mux_bottom_track_25 ( + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size4_1_2 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , - bottom_left_grid_pin_34_[0] , chanx_left_in[18] } ) , + bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size4_7 mux_left_track_33 ( - .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , - chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size4_mem_2_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size4_mem_7 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_2 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_0_3 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , +mux_tree_tapbuf_size4_mem_1_2 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_7 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_0_3 mux_bottom_track_27 ( - .in ( { chanx_right_in[15] , bottom_left_grid_pin_35_[0] } ) , +mux_tree_tapbuf_size3_0_3 mux_bottom_track_13 ( + .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_1_2 mux_bottom_track_15 ( + .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_2_2 mux_bottom_track_17 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_3_2 mux_bottom_track_19 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_4_1 mux_bottom_track_21 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size3_7 mux_bottom_track_23 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( { ropt_net_176 } ) , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size3_mem_0_3 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3_2 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4_1 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_7 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_19 mux_bottom_track_27 ( + .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size2_1_3 mux_bottom_track_29 ( - .in ( { chanx_right_in[11] , bottom_left_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size2_2_3 mux_bottom_track_31 ( - .in ( { chanx_right_in[7] , bottom_left_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_3_3 mux_bottom_track_33 ( - .in ( { chanx_right_in[3] , bottom_left_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_4_2 mux_bottom_track_35 ( - .in ( { chanx_right_in[1] , bottom_left_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_5_2 mux_bottom_track_37 ( - .in ( { chanx_right_in[0] , bottom_left_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size2_14 mux_bottom_track_39 ( - .in ( { bottom_left_grid_pin_41_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size2_mem_0_3 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_3 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_3 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_2 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_2 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_162 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_164 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_169 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_172 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_left_in[5] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_173 ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_175 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_176 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_197 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_198 ) , +mux_tree_tapbuf_size6_8 mux_left_track_33 ( + .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , + chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size6_mem_8 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_181 } ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_199 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( chanx_left_in[4] ) , - .X ( BUF_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_185 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_187 ) , +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_165 ) , .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , - .X ( BUF_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_188 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[10] ) , .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_190 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_191 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_192 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_204 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( BUF_net_83 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_115 ( .A ( aps_rename_2_ ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_116 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_205 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_206 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_166 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[12] ) , .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_92 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_170 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_172 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_175 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_176 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_200 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[14] ) , + .X ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[17] ) , + .X ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[9] ) , + .X ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_181 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_182 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_183 ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_184 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_186 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_187 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_188 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_189 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_190 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_205 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_206 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_207 ) , .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_208 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_212 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( BUF_net_77 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_79 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_184 ) ) ; endmodule @@ -13120,7 +16680,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_28__79 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__79 ( .A ( mem_out[2] ) , + .X ( net_net_87 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -13163,7 +16725,7 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__77 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_8 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13302,7 +16864,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -13400,7 +16962,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__73 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -13573,7 +17135,7 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__65 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14166,7 +17728,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -15147,6 +18709,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -15157,6 +18720,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -15188,9 +18753,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; endmodule @@ -15254,58 +18820,60 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , - right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , - right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , - right_top_grid_pin_49_ , chany_bottom_in , bottom_left_grid_pin_34_ , - bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , - bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , - bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , - bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , - left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , - left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , - left_top_grid_pin_49_ , ccff_head , chany_top_out , chanx_right_out , +module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , + right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , + bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; @@ -15398,77 +18966,77 @@ wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; mux_tree_tapbuf_size12_6 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size12 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , - right_top_grid_pin_42_[0] , right_top_grid_pin_44_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_48_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , - right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , - bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , - chany_bottom_in[12] , chany_bottom_in[19] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] } ) , + chany_bottom_in[12] , chany_bottom_in[19] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[4] , chany_bottom_in[13] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[4] , chany_bottom_in[13] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -15510,49 +19078,49 @@ mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; mux_tree_tapbuf_size16 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , - top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , - top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , + top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , - right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , - chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_40_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[5] , chanx_left_in[7] , + chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[5] , chany_bottom_in[14] , left_top_grid_pin_42_[0] , - left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[5] , chany_bottom_in[14] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -15573,103 +19141,103 @@ mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_1 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , +mux_tree_tapbuf_size10 mux_top_track_8 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_9 mux_top_track_16 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_10 mux_top_track_24 ( - .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , - right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , - right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , - chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_38_[0] , chanx_left_in[6] , chanx_left_in[11] , + chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_39_[0] , chanx_left_in[8] , chanx_left_in[15] , + chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[9] , chanx_left_in[18] , + chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , - chany_bottom_in[6] , chany_bottom_in[16] , left_top_grid_pin_42_[0] , - left_top_grid_pin_46_[0] } ) , + chany_bottom_in[6] , chany_bottom_in[16] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , - chany_bottom_in[8] , chany_bottom_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_47_[0] } ) , + chany_bottom_in[8] , chany_bottom_in[17] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , - chany_bottom_in[11] , chany_bottom_in[18] , left_top_grid_pin_44_[0] , - left_top_grid_pin_48_[0] } ) , + chany_bottom_in[11] , chany_bottom_in[18] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_147 ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , @@ -15729,35 +19297,35 @@ mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; -mux_tree_tapbuf_size7_6 mux_top_track_32 ( - .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size7_8 mux_top_track_32 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size7_2_1 mux_right_track_32 ( - .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_45_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[10] , - chany_bottom_in[19] , chanx_left_in[10] } ) , + .in ( { chany_top_in[10] , chany_top_in[15] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size7_0_2 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size7_1_2 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , - chany_bottom_in[10] , chany_bottom_in[15] , left_top_grid_pin_45_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[10] , chany_bottom_in[15] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_146 ) ) ; -mux_tree_tapbuf_size7_mem_6 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size7_mem_8 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , @@ -15773,157 +19341,142 @@ mux_tree_tapbuf_size7_mem_0_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; mux_tree_tapbuf_size7_mem_1_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( { ropt_net_130 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__2 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chany_top_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_top_in[16] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_148 ) , - .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[6] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , .X ( chanx_left_out[13] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_130 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_132 ) , + .X ( ropt_net_133 ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_152 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_153 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_155 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_42__41 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_158 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_41__40 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_159 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_44__43 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_87 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[6] ) , - .X ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_100 ( .A ( chany_top_in[6] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_105 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_106 ( .A ( BUF_net_90 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_115 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_121 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_123 ( .A ( aps_rename_3_ ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_112 ( .A ( aps_rename_1_ ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[6] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem_0_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; @@ -15931,17 +19484,36 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( net_net_105 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; +module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; @@ -15950,43 +19522,55 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; endmodule @@ -16004,12 +19588,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__58 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_6 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_7 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16023,7 +19607,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16040,10 +19624,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -16057,14 +19638,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16076,7 +19656,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -16091,59 +19670,112 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; +module mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; @@ -16151,9 +19783,6 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -16165,7 +19794,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -16174,245 +19803,34 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16424,80 +19842,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -16517,103 +19867,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_1_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -16626,7 +19879,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16643,7 +19896,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16660,7 +19913,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16677,7 +19930,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16694,7 +19947,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16711,7 +19964,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16728,35 +19981,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -16816,6 +20045,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -16824,8 +20055,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -16925,7 +20154,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_0_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16939,7 +20168,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16958,12 +20187,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_0_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_0_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -17019,25 +20248,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size7_mem_0_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -17052,26 +20262,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -17090,12 +20281,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_1_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -17109,26 +20300,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -17147,11 +20319,186 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size7_1_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; @@ -17192,7 +20539,47 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -17312,49 +20699,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_104 ( .A ( BUF_net_61 ) , - .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -17394,7 +20739,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -17434,27 +20779,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -17471,12 +20795,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -17492,7 +20816,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -17513,55 +20837,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -17606,7 +20886,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17694,77 +20974,61 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , - right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , - right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , - right_top_grid_pin_49_ , right_bottom_grid_pin_1_ , chanx_left_in , - left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , - left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , - left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , - ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail ) ; +module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , + left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , + left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , + left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -17779,8 +21043,6 @@ wire [0:1] mux_tree_tapbuf_size3_5_sram ; wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_6_sram ; wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_7_sram ; -wire [0:1] mux_tree_tapbuf_size3_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -17788,18 +21050,23 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; @@ -17814,6 +21081,10 @@ wire [0:2] mux_tree_tapbuf_size7_5_sram ; wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -17821,131 +21092,126 @@ wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; + +assign SC_IN_TOP = SC_IN_BOT ; mux_tree_tapbuf_size8 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size8_2 mux_right_track_8 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , - right_bottom_grid_pin_1_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size8_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_3 ( - .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[13] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size8_1 mux_left_track_9 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - chanx_right_in[6] , chanx_right_in[16] , left_top_grid_pin_42_[0] , - left_top_grid_pin_46_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_126 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , +mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_4 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size7_6 mux_top_track_2 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size7_5 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_7 mux_top_track_4 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_130 ) ) ; mux_tree_tapbuf_size7_2 mux_top_track_6 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_2 mux_right_track_16 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , - chanx_left_in[8] , chanx_left_in[17] } ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_3 mux_right_track_0 ( + .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_3 mux_right_track_24 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , - chanx_left_in[9] , chanx_left_in[18] } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size7_5 mux_right_track_8 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , + chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_0_1 mux_left_track_17 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_47_[0] } ) , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , + chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_1_1 mux_left_track_25 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - chanx_right_in[9] , chanx_right_in[18] , left_top_grid_pin_44_[0] , - left_top_grid_pin_48_[0] } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_1_1 mux_left_track_3 ( + .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[13] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_2 mux_left_track_9 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_0_1 mux_left_track_17 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , @@ -17955,96 +21221,100 @@ mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_right_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , +mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , +mux_tree_tapbuf_size7_mem_1_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) ) ; mux_tree_tapbuf_size4_6 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , chanx_right_in[8] , + .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_0_1 mux_top_track_10 ( - .in ( { top_left_grid_pin_35_[0] , chanx_right_in[9] , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size4_0_2 mux_top_track_10 ( + .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_127 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4_mem_6 mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_1 mem_top_track_10 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_0_2 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; mux_tree_tapbuf_size3_0_2 mux_top_track_12 ( - .in ( { top_left_grid_pin_36_[0] , chanx_right_in[10] , + .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_1_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_37_[0] , chanx_right_in[12] , + .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_2_1 mux_top_track_16 ( - .in ( { top_left_grid_pin_38_[0] , chanx_right_in[13] , + .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_3_1 mux_top_track_18 ( - .in ( { top_left_grid_pin_39_[0] , chanx_right_in[14] , + .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_4 mux_top_track_20 ( - .in ( { top_left_grid_pin_40_[0] , chanx_right_in[16] , + .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( { ropt_net_134 } ) , - .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_5 mux_top_track_22 ( - .in ( { top_left_grid_pin_41_[0] , chanx_right_in[17] , + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_6 mux_top_track_24 ( - .in ( { top_left_grid_pin_34_[0] , chanx_right_in[18] , + .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3_7 mux_top_track_38 ( - .in ( { top_left_grid_pin_41_[0] , chanx_right_in[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size3_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_7_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size3_mem_0_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -18080,290 +21350,230 @@ mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_7 mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_0_2 mux_top_track_28 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[19] } ) , +mux_tree_tapbuf_size2_18 mux_top_track_38 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_1_2 mux_top_track_30 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[15] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_2_2 mux_top_track_32 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_3_2 mux_top_track_34 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[17] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_36 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_mem_0_2 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size2_mem_18 mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_2 mem_top_track_30 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_2 mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_2 mem_top_track_34 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_36 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size9_0 mux_right_track_0 ( - .in ( { chany_top_in[6] , chany_top_in[13] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size9 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; -mux_tree_tapbuf_size14 mux_right_track_4 ( +mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , - right_bottom_grid_pin_1_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size14_0 mux_left_track_5 ( + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , + chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - chanx_right_in[5] , chanx_right_in[14] , left_top_grid_pin_42_[0] , - left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , - left_top_grid_pin_49_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_6 mux_right_track_32 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - right_top_grid_pin_45_[0] , right_top_grid_pin_49_[0] , - chanx_left_in[10] } ) , + chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) ) ; +mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_7 mux_right_track_24 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_129 } ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size6_0_2 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - chanx_right_in[10] , left_top_grid_pin_45_[0] , - left_top_grid_pin_49_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size6_0_2 mux_left_track_25 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_mem_6 mem_right_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size6_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_131 } ) , +mux_tree_tapbuf_size6_mem_0_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size10 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - chanx_right_in[2] , chanx_right_in[12] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5_5 mux_right_track_32 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size5_0_2 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size5_mem_5 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_35_[0] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[16] ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( { ropt_net_139 } ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_129 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_163 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[7] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_156 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_157 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_134 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_136 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_158 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_159 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_160 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_161 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_162 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_145 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_146 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_164 ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_147 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_148 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_149 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_150 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_168 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_169 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_170 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_171 ) , .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_172 ) , - .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , + .X ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( + .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_153 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_176 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_154 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_155 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_107 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_157 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_114 ( .A ( BUF_net_70 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , + .X ( ropt_net_164 ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_1_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18375,14 +21585,14 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__39 ( .A ( mem_out[1] ) , - .X ( net_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_71 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_59 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( net_net_59 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_3_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18394,12 +21604,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_2_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_2_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18411,12 +21621,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_0_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18428,12 +21638,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_5_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18445,12 +21655,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18462,7 +21672,160 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18479,7 +21842,1144 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_75 ( .A ( BUF_net_43 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; + +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size6_0_1 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size6_6 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size6_mem_0_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_6 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size5_4 mux_right_track_6 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size5_mem_0_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_4 mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_4 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size3_0_1 mux_right_track_24 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0_1 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_4_2 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_5_1 mux_right_track_12 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_6_1 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_7_1 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_8_1 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_9_1 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size2_10_1 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_11_1 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_12_1 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_13_1 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_14_1 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_15 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_16 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_17 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_0_2 mux_bottom_track_1 ( + .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_3_2 mux_bottom_track_9 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_1_2 mux_bottom_track_25 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_mem_4_2 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6_1 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_8_1 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9_1 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10_1 mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_11_1 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13_1 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_17 mem_right_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0_2 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_2 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( { ropt_net_106 } ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( ropt_net_98 ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[7] ) , + .X ( BUF_net_52 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_115 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_101 ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_102 ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_106 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_72 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_78 ( .A ( BUF_net_52 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_79 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_80 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , + .X ( ropt_net_114 ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18496,12 +22996,100 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_1_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -18561,6 +23149,26 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size2_0_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -18581,365 +23189,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , - chany_bottom_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; - -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; - -mux_tree_tapbuf_size2_4_1 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_6_1 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_12 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_5_1 mux_right_track_24 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_0_1 mux_bottom_track_1 ( - .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_2_1 mux_bottom_track_5 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_3_1 mux_bottom_track_9 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_1_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_mem_4_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_1 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_103 } ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_133 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_135 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_136 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_102 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_103 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[3] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_702 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chany_bottom_in[5] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_113 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_114 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_116 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_117 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_118 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_120 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_121 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_122 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( .A ( chanx_right_in[2] ) , - .X ( BUF_net_42 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_140 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_123 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_143 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_124 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_145 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_146 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_57 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_148 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_125 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_126 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_127 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_128 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_129 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( BUF_net_42 ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_83 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_91 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_92 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_126 ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18951,32 +23201,14 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , + .X ( net_net_82 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( net_net_82 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18988,26 +23220,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__57 ( .A ( mem_out[1] ) , - .X ( net_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( net_net_101 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19024,7 +23237,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19041,7 +23254,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19058,12 +23271,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_0_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -19087,7 +23300,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -19197,7 +23410,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19216,7 +23429,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19235,7 +23448,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19374,12 +23587,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19393,12 +23606,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_1_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19412,12 +23625,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_0_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19431,7 +23644,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19450,12 +23663,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19469,7 +23682,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19488,7 +23701,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19521,7 +23734,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -19549,7 +23762,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_1_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -19561,8 +23774,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -19574,10 +23785,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_0_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -19633,7 +23846,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -19703,12 +23916,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19722,7 +23935,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19741,7 +23954,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19760,12 +23973,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19779,7 +23992,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__38 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19816,7 +24029,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -19912,7 +24125,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -19958,7 +24171,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__37 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19977,12 +24190,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__36 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19996,7 +24209,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__35 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20015,12 +24228,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__34 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20034,7 +24247,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__33 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20053,7 +24266,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__32 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20072,7 +24285,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__31 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20149,7 +24362,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20221,7 +24434,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20330,23 +24543,24 @@ endmodule module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , - right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , - right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , - chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , - chanx_right_out , chany_bottom_out , ccff_tail ) ; + chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_left_grid_pin_1_ ; input [0:0] ccff_head ; @@ -20357,7 +24571,22 @@ output [0:0] ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -20444,44 +24673,44 @@ mux_tree_tapbuf_size6_4 mux_top_track_0 ( chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size6_1 mux_top_track_8 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size6_3 mux_right_track_0 ( - .in ( { chany_top_in[2] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , chany_bottom_in[2] } ) , + .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size6_0_1 mux_bottom_track_1 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_121 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_121 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -20492,7 +24721,7 @@ mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_top_track_8 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , @@ -20502,8 +24731,8 @@ mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , +mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; @@ -20517,37 +24746,37 @@ mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; -mux_tree_tapbuf_size5_1 mux_top_track_2 ( +mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size5_0_1 mux_bottom_track_17 ( + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_122 ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , @@ -20562,7 +24791,7 @@ mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0_1 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , @@ -20577,49 +24806,50 @@ mux_tree_tapbuf_size4_5 mux_top_track_24 ( chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size4 mux_top_track_32 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size4_3 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size4_4 mux_right_track_8 ( - .in ( { chany_top_in[7] , chany_top_in[8] , right_top_grid_pin_42_[0] , + .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size4_0 mux_right_track_10 ( - .in ( { chany_top_in[9] , chany_top_in[11] , right_top_grid_pin_43_[0] , - chany_bottom_in[9] } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size4_0_1 mux_right_track_10 ( + .in ( { chany_top_in[9] , chany_top_in[11] , + right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size4_1 mux_right_track_12 ( - .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_44_[0] , - chany_bottom_in[10] } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size4_1_1 mux_right_track_12 ( + .in ( { chany_top_in[10] , chany_top_in[15] , + right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size4_2 mux_right_track_14 ( - .in ( { chany_top_in[12] , chany_top_in[19] , right_top_grid_pin_45_[0] , - chany_bottom_in[12] } ) , + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( { ropt_net_130 } ) , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size4_2_1 mux_right_track_14 ( + .in ( { chany_top_in[12] , chany_top_in[19] , + right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size4_3 mux_right_track_24 ( - .in ( { chany_top_in[18] , right_top_grid_pin_42_[0] , + .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_3 mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , @@ -20629,17 +24859,17 @@ mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_0_1 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_1_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4_mem_2_1 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_5_sram ) , @@ -20650,26 +24880,26 @@ mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; mux_tree_tapbuf_size7_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[4] } ) , + .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size7_1 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , chany_bottom_in[5] } ) , + .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size7 mux_right_track_6 ( - .in ( { chany_top_in[3] , chany_top_in[6] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[6] } ) , + .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -20686,34 +24916,34 @@ mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; mux_tree_tapbuf_size3_1 mux_right_track_16 ( - .in ( { chany_top_in[13] , right_top_grid_pin_46_[0] , + .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size3_2 mux_right_track_18 ( - .in ( { chany_top_in[14] , right_top_grid_pin_47_[0] , + .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size3_3 mux_right_track_20 ( - .in ( { chany_top_in[16] , right_top_grid_pin_48_[0] , + .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3_4 mux_right_track_22 ( - .in ( { chany_top_in[17] , right_top_grid_pin_49_[0] , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size3 mux_right_track_22 ( + .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3_0_1 mux_bottom_track_33 ( + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -20729,248 +24959,180 @@ mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_right_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_127 } ) , + .ccff_tail ( { ropt_net_131 } ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_11 mux_right_track_26 ( - .in ( { right_top_grid_pin_43_[0] , chany_bottom_in[15] } ) , +mux_tree_tapbuf_size2_0_1 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_1_1 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_2_1 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_3_1 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_4_1 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size2_mem_0_1 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_123 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_127 ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_129 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[4] ) , +mux_tree_tapbuf_size2_mem_1_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_1 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4_1 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[2] ) , .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_140 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_142 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_143 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[17] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_152 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_153 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_155 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_144 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chany_bottom_in[13] ) , +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_157 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( BUF_net_69 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[2] ) , .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_158 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_139 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_161 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_162 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_bottom_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[4] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_148 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[14] ) , + .X ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_149 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_150 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_151 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_152 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_153 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( BUF_net_69 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( chany_top_in[8] ) , .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_75 ) , + .X ( ropt_net_153 ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20984,12 +25146,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__37 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21003,13 +25165,51 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__36 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -21019,135 +25219,25 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -21157,32 +25247,80 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21194,128 +25332,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__33 ( .A ( mem_out[1] ) , - .X ( net_aps_33 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( net_aps_33 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , + .X ( net_aps_35 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21332,41 +25351,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21383,11 +25368,292 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_83 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -21548,43 +25814,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_81 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21604,7 +25834,67 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21625,24 +25915,20 @@ endmodule module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , - right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , - right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , - right_bottom_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - ccff_tail ) ; + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , + chany_top_out , chanx_right_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; @@ -21654,6 +25940,14 @@ wire [0:1] mux_tree_tapbuf_size2_10_sram ; wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; @@ -21674,6 +25968,10 @@ wire [0:1] mux_tree_tapbuf_size2_9_sram ; wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; @@ -21683,92 +25981,106 @@ wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -mux_tree_tapbuf_size2_8 mux_top_track_0 ( +mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_10 mux_top_track_4 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_9 mux_top_track_24 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( { ropt_net_107 } ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_10 ( - .in ( { chany_top_in[4] , right_top_grid_pin_43_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_11 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_12 ( - .in ( { chany_top_in[5] , right_top_grid_pin_44_[0] } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_14 ( - .in ( { chany_top_in[6] , right_top_grid_pin_45_[0] } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_16 ( - .in ( { chany_top_in[7] , right_top_grid_pin_46_[0] } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_18 ( - .in ( { chany_top_in[8] , right_top_grid_pin_47_[0] } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_20 ( - .in ( { chany_top_in[9] , right_top_grid_pin_48_[0] } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_22 ( - .in ( { chany_top_in[10] , right_top_grid_pin_49_[0] } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_26 ( - .in ( { chany_top_in[12] , right_top_grid_pin_43_[0] } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_106 } ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , @@ -21778,780 +26090,208 @@ mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , +mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_105 } ) , +mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size6_0 mux_right_track_0 ( - .in ( { chany_top_in[19] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size6 mux_right_track_4 ( - .in ( { chany_top_in[1] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , +mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( { ropt_net_110 } ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( { ropt_net_118 } ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_right_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size5 mux_right_track_6 ( - .in ( { chany_top_in[2] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3 mux_right_track_8 ( - .in ( { chany_top_in[3] , right_top_grid_pin_42_[0] , - right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_0 mux_right_track_24 ( - .in ( { chany_top_in[11] , right_top_grid_pin_42_[0] , - right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_right_in[7] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_697 ( .A ( ropt_net_113 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_114 ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_44 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_47 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , - .X ( BUF_net_49 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_115 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_116 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[17] ) , .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_117 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , - .X ( BUF_net_56 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_132 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_69 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_76 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_77 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( aps_rename_2_ ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( BUF_net_49 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_right_in[8] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_56 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_125 ) , .X ( chany_top_out[11] ) ) ; -endmodule - - -module direct_interc_4 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module GPIO_3 ( A , IE , OE , Y , in , out , mem_out ) ; -output A ; -output IE ; -output OE ; -output Y ; -input in ; -output out ; -input mem_out ; - -wire aps_rename_1_ ; - -assign A = in ; -assign out = Y ; - -sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( IE ) , .Y ( OE ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__1 ( .A ( mem_out ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_3 ( .A ( aps_rename_1_ ) , .X ( IE ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_3 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , - ccff_head , iopad_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; - -wire [0:0] GPIO_0_en ; - -GPIO_3 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , - .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , - .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , - .mem_out ( GPIO_0_en[0] ) ) ; -GPIO_sky130_fd_sc_hd__dfxbp_1_mem_3 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -endmodule - - -module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , - ccff_head , io_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , - .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , - .ccff_tail ( ccff_tail ) ) ; -direct_interc_4 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_4 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module grid_io_left ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , - gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , right_width_0_height_0__pin_0_ , - ccff_head , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] right_width_0_height_0__pin_0_ ; -input [0:0] ccff_head ; -output [0:0] right_width_0_height_0__pin_1_upper ; -output [0:0] right_width_0_height_0__pin_1_lower ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_io__3 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , - .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , - .io_inpad ( right_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_9 } ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( - .A ( right_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_5 ( .A ( aps_rename_2_ ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_569 ( .A ( ropt_net_9 ) , - .X ( ropt_net_11 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_570 ( .A ( ropt_net_11 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module direct_interc_3 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , - .X ( net_net_8 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_13 ( .A ( net_net_8 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module GPIO_2 ( A , IE , OE , Y , in , out , mem_out ) ; -output A ; -output IE ; -output OE ; -output Y ; -input in ; -output out ; -input mem_out ; - -wire aps_rename_1_ ; - -assign A = in ; -assign out = Y ; - -sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__1 ( .A ( mem_out ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_5 ( .A ( aps_rename_1_ ) , .X ( IE ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , - ccff_head , iopad_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; - -wire [0:0] GPIO_0_en ; - -GPIO_2 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , - .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , - .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , - .mem_out ( GPIO_0_en[0] ) ) ; -GPIO_sky130_fd_sc_hd__dfxbp_1_mem_2 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -endmodule - - -module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , - ccff_head , io_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , - .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , - .ccff_tail ( ccff_tail ) ) ; -direct_interc_3 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_3 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module grid_io_bottom ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , - gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , top_width_0_height_0__pin_0_ , - ccff_head , top_width_0_height_0__pin_1_upper , - top_width_0_height_0__pin_1_lower , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] top_width_0_height_0__pin_0_ ; -input [0:0] ccff_head ; -output [0:0] top_width_0_height_0__pin_1_upper ; -output [0:0] top_width_0_height_0__pin_1_lower ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_io__2 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( { ropt_net_16 } ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , - .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , - .io_inpad ( top_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_17 } ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( - .A ( top_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_6 ( .A ( aps_rename_2_ ) , - .X ( BUF_net_6 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_574 ( .A ( BUF_net_6 ) , - .X ( ropt_net_18 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_577 ( .A ( ropt_net_18 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_575 ( .A ( ropt_net_16 ) , - .X ( ropt_net_19 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_576 ( .A ( ropt_net_17 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( ropt_net_19 ) , - .X ( gfpga_pad_GPIO_IE[0] ) ) ; -endmodule - - -module direct_interc_2 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , - .X ( net_net_7 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_9 ( .A ( net_net_7 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module GPIO_1 ( A , IE , OE , Y , in , out , mem_out ) ; -output A ; -output IE ; -output OE ; -output Y ; -input in ; -output out ; -input mem_out ; - -assign A = in ; -assign out = Y ; - -sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( IE ) , .Y ( OE ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_1__1 ( .A ( mem_out ) , .X ( IE ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_1 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , - ccff_head , iopad_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; - -wire [0:0] GPIO_0_en ; - -GPIO_1 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , - .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , - .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , - .mem_out ( GPIO_0_en[0] ) ) ; -GPIO_sky130_fd_sc_hd__dfxbp_1_mem_1 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -endmodule - - -module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , - ccff_head , io_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , - .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , - .ccff_tail ( ccff_tail ) ) ; -direct_interc_2 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_2 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module grid_io_right ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , - gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , left_width_0_height_0__pin_0_ , - ccff_head , left_width_0_height_0__pin_1_upper , - left_width_0_height_0__pin_1_lower , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] left_width_0_height_0__pin_0_ ; -input [0:0] ccff_head ; -output [0:0] left_width_0_height_0__pin_1_upper ; -output [0:0] left_width_0_height_0__pin_1_lower ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_io__1 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , - .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , - .io_inpad ( left_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_11 } ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( - .A ( left_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_572 ( .A ( ropt_net_12 ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_8 ( .A ( aps_rename_1_ ) , - .X ( ropt_net_10 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_570 ( .A ( ropt_net_10 ) , - .X ( ropt_net_12 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_571 ( .A ( ropt_net_11 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module direct_interc_1 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , - .X ( net_net_7 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_13 ( .A ( net_net_7 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module GPIO ( A , IE , OE , Y , in , out , mem_out ) ; -output A ; -output IE ; -output OE ; -output Y ; -input in ; -output out ; -input mem_out ; - -wire aps_rename_1_ ; - -assign A = in ; -assign out = Y ; - -sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__1 ( .A ( mem_out ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_12 ( .A ( aps_rename_1_ ) , .X ( IE ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , - ccff_head , iopad_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; - -wire [0:0] GPIO_0_en ; - -GPIO GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , - .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , - .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , - .mem_out ( GPIO_0_en[0] ) ) ; -GPIO_sky130_fd_sc_hd__dfxbp_1_mem GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -endmodule - - -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , - ccff_head , io_inpad , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , - .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , - .ccff_tail ( ccff_tail ) ) ; -direct_interc_1 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module grid_io_top ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , - gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , bottom_width_0_height_0__pin_0_ , - ccff_head , bottom_width_0_height_0__pin_1_upper , - bottom_width_0_height_0__pin_1_lower , ccff_tail ) ; -input [0:0] prog_clk ; -output [0:0] gfpga_pad_GPIO_A ; -output [0:0] gfpga_pad_GPIO_IE ; -output [0:0] gfpga_pad_GPIO_OE ; -inout [0:0] gfpga_pad_GPIO_Y ; -input [0:0] bottom_width_0_height_0__pin_0_ ; -input [0:0] ccff_head ; -output [0:0] bottom_width_0_height_0__pin_1_upper ; -output [0:0] bottom_width_0_height_0__pin_1_lower ; -output [0:0] ccff_tail ; - -logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , - .gfpga_pad_GPIO_IE ( { ropt_net_16 } ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , - .io_outpad ( bottom_width_0_height_0__pin_0_ ) , - .ccff_head ( ccff_head ) , - .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_15 } ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( - .A ( bottom_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_5 ( .A ( aps_rename_2_ ) , - .X ( BUF_net_5 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_574 ( .A ( BUF_net_5 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_576 ( .A ( ropt_net_16 ) , - .X ( gfpga_pad_GPIO_IE[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_575 ( .A ( ropt_net_15 ) , - .X ( ropt_net_17 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_577 ( .A ( ropt_net_17 ) , +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_127 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_110 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[4] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_78 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( BUF_net_58 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , + .X ( chanx_right_out[18] ) ) ; endmodule @@ -22567,9 +26307,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__55 ( .A ( mem_out[1] ) , - .X ( net_aps_55 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( .A ( net_aps_55 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__56 ( .A ( mem_out[1] ) , + .X ( net_aps_56 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_aps_56 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22586,7 +26326,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22603,7 +26343,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22624,52 +26364,64 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module mux_tree_size2_22 ( in , sram , sram_inv , out , p2 ) ; +module mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +output p_abuf0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_21 ( in , sram , sram_inv , out , p2 ) ; +module mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +output p_abuf0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , p_abuf2 ) ; + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , p_abuf0 , p_abuf1 , + p_abuf2 ) ; input [0:0] Test_en ; input [0:0] clk ; input [0:0] ff_D ; input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; +output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( p_abuf2 ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; + .Q ( p_abuf2 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( net_net_100 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_101 ( .A ( p_abuf2 ) , + .X ( net_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( .A ( p_abuf2 ) , .X ( p_abuf1 ) ) ; endmodule @@ -22682,9 +26434,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -22700,7 +26452,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22763,7 +26515,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb7_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__51 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__52 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23002,23 +26754,27 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , - p_abuf1 , p_abuf2 , p2 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , + p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p1 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; +output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; +output p_abuf4 ; +input p1 ; input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -23044,15 +26800,16 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .p2 ( p2 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_regout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .p_abuf0 ( fabric_regout[0] ) , .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) ) ; mux_tree_size2_21 mux_fabric_out_0 ( .in ( { @@ -23061,14 +26818,14 @@ mux_tree_size2_21 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf3 ) , .p1 ( p1 ) ) ; mux_tree_size2_22 mux_fabric_out_1 ( - .in ( { fabric_regout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf4 ) , .p1 ( p1 ) ) ; mux_tree_size2_23 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , @@ -23110,7 +26867,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -23125,50 +26882,52 @@ direct_interc direct_interc_9_ ( direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__256 ( .A ( fabric_regout[0] ) , - .X ( fabric_scout[0] ) ) ; endmodule module logical_tile_clb_mode_default__fle ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 , + p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +output p_abuf2 ; +input p1 ; input p2 ; logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , - .p2 ( p2 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p_abuf4 ( p_abuf4 ) , + .p1 ( p1 ) , .p2 ( p2 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; + .out ( { p_abuf3 } ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; + .out ( { p_abuf4 } ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf0 } ) ) ; + .out ( { p_abuf1 } ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf1 } ) ) ; + .out ( { p_abuf2 } ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -23186,7 +26945,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -23205,7 +26964,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23222,7 +26981,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23239,55 +26998,55 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_20 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_20 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_19 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_19 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_18 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_18 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -23301,9 +27060,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -23316,9 +27075,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -23334,23 +27093,23 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_30 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_30 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -23397,7 +27156,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb6_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__46 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__47 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23429,11 +27188,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , @@ -23523,11 +27282,11 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , @@ -23582,13 +27341,13 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p1 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -23612,7 +27371,7 @@ mux_tree_size2_30 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -23636,21 +27395,21 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p1 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p1 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -23665,24 +27424,24 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_18 mux_fabric_out_0 ( .in ( { @@ -23691,21 +27450,21 @@ mux_tree_size2_18 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; mux_tree_size2_19 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; mux_tree_size2_20 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -23722,10 +27481,10 @@ mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -23740,7 +27499,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -23759,29 +27518,29 @@ endmodule module logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p1 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p1 ; +input p2 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p1 ( p1 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p2 ( p2 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -23793,7 +27552,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -23811,7 +27570,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -23830,7 +27589,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__45 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23847,7 +27606,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23864,55 +27623,55 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_17 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_16 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_16 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_15 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_15 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -23926,9 +27685,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -23941,9 +27700,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -23959,23 +27718,23 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__42 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_29 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_29 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -24022,7 +27781,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb5_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__41 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__42 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24148,9 +27907,9 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; @@ -24207,13 +27966,13 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p1 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -24237,7 +27996,7 @@ mux_tree_size2_29 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p1 ( p1 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -24261,21 +28020,23 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p1 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 , + p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p1 ; +input p0 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -24290,24 +28051,24 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p1 ( p1 ) ) ; + .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_15 mux_fabric_out_0 ( .in ( { @@ -24316,21 +28077,21 @@ mux_tree_size2_15 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; mux_tree_size2_16 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; mux_tree_size2_17 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p1 ( p1 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -24347,10 +28108,10 @@ mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -24365,7 +28126,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -24384,29 +28145,30 @@ endmodule module logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p1 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p1 ; +input p0 ; +input p2 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p1 ( p1 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -24418,7 +28180,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -24436,7 +28198,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -24455,7 +28217,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24472,7 +28234,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__39 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24489,55 +28251,55 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_14 ( in , sram , sram_inv , out , p3 ) ; +module mux_tree_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_13 ( in , sram , sram_inv , out , p3 ) ; +module mux_tree_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_12 ( in , sram , sram_inv , out , p1 ) ; +module mux_tree_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -24551,9 +28313,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -24566,9 +28328,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -24584,23 +28346,23 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_28 ( in , sram , sram_inv , out , p3 ) ; +module mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -24647,7 +28409,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__36 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24688,13 +28450,13 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -24779,7 +28541,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , @@ -24832,13 +28594,13 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -24862,7 +28624,7 @@ mux_tree_size2_28 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -24886,23 +28648,21 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p1 , - p3 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p1 ; -input p3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -24917,24 +28677,24 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_12 mux_fabric_out_0 ( .in ( { @@ -24943,21 +28703,21 @@ mux_tree_size2_12 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p1 ( p1 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_13 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_14 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -24974,10 +28734,10 @@ mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -24992,7 +28752,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -25011,30 +28771,29 @@ endmodule module logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p1 , p3 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p1 ; -input p3 ; +input p0 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p1 ( p1 ) , .p3 ( p3 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -25046,7 +28805,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -25064,7 +28823,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -25083,7 +28842,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25100,7 +28859,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25117,55 +28876,55 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_11 ( in , sram , sram_inv , out , p3 ) ; +module mux_tree_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_10 ( in , sram , sram_inv , out , p3 ) ; +module mux_tree_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_9 ( in , sram , sram_inv , out , p3 ) ; +module mux_tree_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -25179,9 +28938,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -25194,9 +28953,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -25212,7 +28971,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25275,7 +29034,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25313,7 +29072,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( @@ -25514,23 +29273,21 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 , - p3 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input p0 ; -input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -25545,7 +29302,7 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , @@ -25555,14 +29312,14 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_9 mux_fabric_out_0 ( .in ( { @@ -25571,21 +29328,21 @@ mux_tree_size2_9 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_10 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_11 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p3 ( p3 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -25602,10 +29359,10 @@ mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -25620,7 +29377,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -25639,30 +29396,29 @@ endmodule module logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p0 , p3 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input p0 ; -input p3 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -25674,7 +29430,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -25692,7 +29448,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -25711,7 +29467,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25728,7 +29484,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25745,55 +29501,55 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_size2_8 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_size2_7 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_size2_6 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -25807,9 +29563,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -25822,9 +29578,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -25840,23 +29596,23 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_26 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_size2_26 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -25903,7 +29659,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb2_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__27 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25939,7 +29695,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , @@ -26088,13 +29844,13 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p0 ; +input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -26118,7 +29874,7 @@ mux_tree_size2_26 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; + .p1 ( p1 ) ) ; mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , @@ -26142,21 +29898,23 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p1 , + p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p0 ; +input p1 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -26171,24 +29929,24 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; + .p1 ( p1 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_6 mux_fabric_out_0 ( .in ( { @@ -26197,21 +29955,21 @@ mux_tree_size2_6 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p0 ( p0 ) ) ; + .p1 ( p1 ) ) ; mux_tree_size2_7 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p0 ( p0 ) ) ; + .p1 ( p1 ) ) ; mux_tree_size2_8 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; + .p3 ( p3 ) ) ; mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -26228,10 +29986,10 @@ mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -26246,7 +30004,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -26265,29 +30023,30 @@ endmodule module logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p0 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p1 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p0 ; +input p1 ; +input p3 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p1 ( p1 ) , .p3 ( p3 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -26299,7 +30058,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -26317,7 +30076,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -26336,7 +30095,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26353,7 +30112,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26370,39 +30129,39 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_size2_5 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_size2_4 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -26432,9 +30191,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -26447,9 +30206,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -26465,7 +30224,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26528,7 +30287,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb1_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__21 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26566,16 +30325,16 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -26654,13 +30413,13 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , @@ -26767,23 +30526,23 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 , - p1 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 , + p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input p0 ; -input p1 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -26798,7 +30557,7 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , @@ -26808,14 +30567,14 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_3 mux_fabric_out_0 ( .in ( { @@ -26826,19 +30585,19 @@ mux_tree_size2_3 mux_fabric_out_0 ( .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , .p0 ( p0 ) ) ; mux_tree_size2_4 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p0 ( p0 ) ) ; + .p3 ( p3 ) ) ; mux_tree_size2_5 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p1 ) ) ; + .p3 ( p3 ) ) ; mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -26855,10 +30614,10 @@ mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -26873,7 +30632,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -26892,30 +30651,30 @@ endmodule module logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p0 , p1 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p0 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input p0 ; -input p1 ; +input p3 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -26927,7 +30686,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -26945,7 +30704,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -26964,7 +30723,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__20 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26981,7 +30740,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__19 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26998,7 +30757,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27047,7 +30806,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( net_net_61 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( net_net_61 ) , + .X ( out[0] ) ) ; endmodule @@ -27060,9 +30822,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -27075,9 +30837,9 @@ input [0:0] ff_DI ; output [0:0] ff_Q ; input [0:0] ff_clk ; -sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .Q ( ff_Q[0] ) ) ; endmodule @@ -27101,7 +30863,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__17 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27164,7 +30926,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb0_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__16 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__17 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27198,9 +30960,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , @@ -27211,7 +30973,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -27290,11 +31052,11 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , @@ -27403,21 +31165,21 @@ endmodule module logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p1 ) ; + Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fabric_in ; input [0:0] fabric_regin ; -input [0:0] fabric_scin ; +input [0:0] fabric_sc_in ; input [0:0] fabric_clk ; input [0:0] ccff_head ; output [0:1] fabric_out ; output [0:0] fabric_regout ; -output [0:0] fabric_scout ; +output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p1 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -27432,24 +31194,24 @@ wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -assign fabric_regout[0] = fabric_scout[0] ; +assign fabric_regout[0] = fabric_sc_out[0] ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p1 ) ) ; + .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_scin ) , + .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_scout ) , + .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; mux_tree_size2_0 mux_fabric_out_0 ( .in ( { @@ -27458,21 +31220,21 @@ mux_tree_size2_0 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p0 ( p1 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_1 mux_fabric_out_1 ( - .in ( { fabric_scout[0] , + .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p0 ( p1 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_2 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p1 ) ) ; + .p0 ( p0 ) ) ; mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , @@ -27489,10 +31251,10 @@ mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_scout ) ) ; + .out ( fabric_sc_out ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; @@ -27507,7 +31269,7 @@ direct_interc direct_interc_5_ ( .out ( fabric_in[3] ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_scin ) ) ; + .out ( fabric_sc_in ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; @@ -27526,29 +31288,29 @@ endmodule module logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , - fle_regout , fle_scout , ccff_tail , p1 ) ; + fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; input [0:3] fle_in ; input [0:0] fle_regin ; -input [0:0] fle_scin ; +input [0:0] fle_sc_in ; input [0:0] fle_clk ; input [0:0] ccff_head ; output [0:1] fle_out ; output [0:0] fle_regout ; -output [0:0] fle_scout ; +output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p1 ; +input p0 ; logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , - .ccff_tail ( ccff_tail ) , .p1 ( p1 ) ) ; + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( fle_out[0] ) ) ; @@ -27560,7 +31322,7 @@ direct_interc direct_interc_2_ ( .out ( fle_regout ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_scout ) ) ; + .out ( fle_sc_out ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; @@ -27578,7 +31340,7 @@ direct_interc direct_interc_8_ ( .out ( fle_regin ) ) ; direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_scin ) ) ; + .out ( fle_sc_in ) ) ; direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; @@ -27586,33 +31348,41 @@ endmodule module logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , clb_I0 , - clb_I1 , clb_I2 , clb_I3 , clb_I4 , clb_I5 , clb_I6 , clb_I7 , clb_regin , - clb_scin , clb_clk , ccff_head , clb_O , clb_regout , clb_scout , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 , - p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , p_abuf12 , - p_abuf13 , p_abuf14 , p_abuf15 , p0 , p1 , p2 , p3 , p4 ) ; + clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , clb_I3i , + clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , clb_I7 , + clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , + clb_regout , clb_sc_out , ccff_tail , p_abuf0 , p_abuf3 , p_abuf4 , + p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , + p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p_abuf16 , p0 , p1 , p2 , p3 , + p4 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; -input [0:3] clb_I0 ; -input [0:3] clb_I1 ; -input [0:3] clb_I2 ; -input [0:3] clb_I3 ; -input [0:3] clb_I4 ; -input [0:3] clb_I5 ; -input [0:3] clb_I6 ; -input [0:3] clb_I7 ; +input [0:2] clb_I0 ; +input [0:0] clb_I0i ; +input [0:2] clb_I1 ; +input [0:0] clb_I1i ; +input [0:2] clb_I2 ; +input [0:0] clb_I2i ; +input [0:2] clb_I3 ; +input [0:0] clb_I3i ; +input [0:2] clb_I4 ; +input [0:0] clb_I4i ; +input [0:2] clb_I5 ; +input [0:0] clb_I5i ; +input [0:2] clb_I6 ; +input [0:0] clb_I6i ; +input [0:2] clb_I7 ; +input [0:0] clb_I7i ; input [0:0] clb_regin ; -input [0:0] clb_scin ; +input [0:0] clb_sc_in ; input [0:0] clb_clk ; input [0:0] ccff_head ; output [0:15] clb_O ; output [0:0] clb_regout ; -output [0:0] clb_scout ; +output [0:0] clb_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; output p_abuf3 ; output p_abuf4 ; output p_abuf5 ; @@ -27626,6 +31396,7 @@ output p_abuf12 ; output p_abuf13 ; output p_abuf14 ; output p_abuf15 ; +output p_abuf16 ; input p0 ; input p1 ; input p2 ; @@ -27633,149 +31404,146 @@ input p3 ; input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; -wire [1:1] logical_tile_clb_mode_default__fle_0_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; -wire [1:1] logical_tile_clb_mode_default__fle_1_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; wire [1:1] logical_tile_clb_mode_default__fle_4_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I0 ) , .fle_regin ( clb_regin ) , .fle_scin ( clb_scin ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I0[2] , clb_I0[1] , clb_I0[0] , clb_I0i[0] } ) , + .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , - .fle_out ( { clb_O[1] , logical_tile_clb_mode_default__fle_0_fle_out[1] } ) , + .fle_out ( { p_abuf16 , p_abuf3 } ) , .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_0_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .p1 ( p1 ) ) ; + .p0 ( p0 ) ) ; logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I1 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I1[2] , clb_I1[1] , clb_I1[0] , clb_I1i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_0_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .fle_out ( { clb_O[3] , logical_tile_clb_mode_default__fle_1_fle_out[1] } ) , + .fle_out ( { p_abuf4 , clb_O[2] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_1_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .p0 ( p0 ) , .p1 ( p1 ) ) ; + .p0 ( p0 ) , .p3 ( p4 ) ) ; logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I2 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I2[2] , clb_I2[1] , clb_I2[0] , clb_I2i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_1_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .fle_out ( { clb_O[5] , clb_O[4] } ) , + .fle_out ( { p_abuf6 , p_abuf7 } ) , .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_2_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p0 ( p0 ) ) ; + .p1 ( p2 ) , .p3 ( p4 ) ) ; logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I3 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I3[2] , clb_I3[1] , clb_I3[0] , clb_I3i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_2_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .fle_out ( logical_tile_clb_mode_default__fle_3_fle_out ) , + .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .fle_out ( { logical_tile_clb_mode_default__fle_3_fle_out[0] , clb_O[6] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_3_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .p0 ( p0 ) , .p3 ( p4 ) ) ; + .p0 ( p1 ) ) ; logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I4 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I4[2] , clb_I4[1] , clb_I4[0] , clb_I4i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_3_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , .fle_out ( { clb_O[9] , logical_tile_clb_mode_default__fle_4_fle_out[1] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_4_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p1 ( p2 ) , .p3 ( p4 ) ) ; + .p0 ( p1 ) ) ; logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I5 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I5[2] , clb_I5[1] , clb_I5[0] , clb_I5i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_4_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .fle_out ( { logical_tile_clb_mode_default__fle_5_fle_out[0] , clb_O[10] } ) , + .fle_out ( { clb_O[11] , clb_O[10] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_5_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p1 ( p2 ) ) ; + .p0 ( p1 ) , .p2 ( p3 ) ) ; logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I6 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I6[2] , clb_I6[1] , clb_I6[0] , clb_I6i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_5_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .fle_out ( { logical_tile_clb_mode_default__fle_6_fle_out[0] , clb_O[12] } ) , + .fle_out ( { p_abuf14 , p_abuf15 } ) , .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , - .fle_scout ( logical_tile_clb_mode_default__fle_6_fle_scout ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p1 ( p2 ) ) ; + .p2 ( p3 ) ) ; logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( clb_I7 ) , + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( { clb_I7[2] , clb_I7[1] , clb_I7[0] , clb_I7i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , - .fle_scin ( logical_tile_clb_mode_default__fle_6_fle_scout ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .fle_out ( { p_abuf14 , clb_O[14] } ) , - .fle_regout ( clb_regout ) , .fle_scout ( clb_scout ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf16 ) , .p_abuf1 ( p_abuf17 ) , - .p2 ( p3 ) ) ; + .fle_out ( { clb_O[15] , clb_O[14] } ) , + .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p1 ( p2 ) , .p2 ( p3 ) ) ; direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_out ) ) ; + .out ( { p_abuf3 } ) ) ; direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( clb_O[1] ) ) ; + .out ( { p_abuf16 } ) ) ; direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_out ) ) ; + .out ( clb_O[2] ) ) ; direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( clb_O[3] ) ) ; + .out ( { p_abuf4 } ) ) ; direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( clb_O[4] ) ) ; + .out ( { p_abuf7 } ) ) ; direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( clb_O[5] ) ) ; + .out ( { p_abuf6 } ) ) ; direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) ) ; + .out ( clb_O[6] ) ) ; direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) ) ; + .out ( logical_tile_clb_mode_default__fle_3_fle_out ) ) ; direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_out ) ) ; @@ -27787,924 +31555,947 @@ direct_interc direct_interc_10_ ( .out ( clb_O[10] ) ) ; direct_interc direct_interc_11_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_out ) ) ; + .out ( clb_O[11] ) ) ; direct_interc direct_interc_12_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( clb_O[12] ) ) ; + .out ( { p_abuf15 } ) ) ; direct_interc direct_interc_13_ ( .in ( { SYNOPSYS_UNCONNECTED_14 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_out ) ) ; + .out ( { p_abuf14 } ) ) ; direct_interc direct_interc_14_ ( .in ( { SYNOPSYS_UNCONNECTED_15 } ) , .out ( clb_O[14] ) ) ; direct_interc direct_interc_15_ ( .in ( { SYNOPSYS_UNCONNECTED_16 } ) , - .out ( { p_abuf14 } ) ) ; + .out ( clb_O[15] ) ) ; direct_interc direct_interc_16_ ( .in ( { SYNOPSYS_UNCONNECTED_17 } ) , - .out ( { p_abuf16 } ) ) ; + .out ( { p_abuf1 } ) ) ; direct_interc direct_interc_17_ ( .in ( { SYNOPSYS_UNCONNECTED_18 } ) , - .out ( { p_abuf17 } ) ) ; + .out ( { p_abuf2 } ) ) ; direct_interc direct_interc_18_ ( .in ( { SYNOPSYS_UNCONNECTED_19 } ) , - .out ( clb_I0[0] ) ) ; + .out ( clb_I0[2] ) ) ; direct_interc direct_interc_19_ ( .in ( { SYNOPSYS_UNCONNECTED_20 } ) , .out ( clb_I0[1] ) ) ; direct_interc direct_interc_20_ ( .in ( { SYNOPSYS_UNCONNECTED_21 } ) , - .out ( clb_I0[2] ) ) ; + .out ( clb_I0[0] ) ) ; direct_interc direct_interc_21_ ( .in ( { SYNOPSYS_UNCONNECTED_22 } ) , - .out ( clb_I0[3] ) ) ; + .out ( clb_I0i ) ) ; direct_interc direct_interc_22_ ( .in ( { SYNOPSYS_UNCONNECTED_23 } ) , .out ( clb_regin ) ) ; direct_interc direct_interc_23_ ( .in ( { SYNOPSYS_UNCONNECTED_24 } ) , - .out ( clb_scin ) ) ; + .out ( clb_sc_in ) ) ; direct_interc direct_interc_24_ ( .in ( { SYNOPSYS_UNCONNECTED_25 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_25_ ( .in ( { SYNOPSYS_UNCONNECTED_26 } ) , - .out ( clb_I1[0] ) ) ; + .out ( clb_I1[2] ) ) ; direct_interc direct_interc_26_ ( .in ( { SYNOPSYS_UNCONNECTED_27 } ) , .out ( clb_I1[1] ) ) ; direct_interc direct_interc_27_ ( .in ( { SYNOPSYS_UNCONNECTED_28 } ) , - .out ( clb_I1[2] ) ) ; + .out ( clb_I1[0] ) ) ; direct_interc direct_interc_28_ ( .in ( { SYNOPSYS_UNCONNECTED_29 } ) , - .out ( clb_I1[3] ) ) ; + .out ( clb_I1i ) ) ; direct_interc direct_interc_29_ ( .in ( { SYNOPSYS_UNCONNECTED_30 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; direct_interc direct_interc_30_ ( .in ( { SYNOPSYS_UNCONNECTED_31 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; direct_interc direct_interc_31_ ( .in ( { SYNOPSYS_UNCONNECTED_32 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_32_ ( .in ( { SYNOPSYS_UNCONNECTED_33 } ) , - .out ( clb_I2[0] ) ) ; + .out ( clb_I2[2] ) ) ; direct_interc direct_interc_33_ ( .in ( { SYNOPSYS_UNCONNECTED_34 } ) , .out ( clb_I2[1] ) ) ; direct_interc direct_interc_34_ ( .in ( { SYNOPSYS_UNCONNECTED_35 } ) , - .out ( clb_I2[2] ) ) ; + .out ( clb_I2[0] ) ) ; direct_interc direct_interc_35_ ( .in ( { SYNOPSYS_UNCONNECTED_36 } ) , - .out ( clb_I2[3] ) ) ; + .out ( clb_I2i ) ) ; direct_interc direct_interc_36_ ( .in ( { SYNOPSYS_UNCONNECTED_37 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; direct_interc direct_interc_37_ ( .in ( { SYNOPSYS_UNCONNECTED_38 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; direct_interc direct_interc_38_ ( .in ( { SYNOPSYS_UNCONNECTED_39 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_39_ ( .in ( { SYNOPSYS_UNCONNECTED_40 } ) , - .out ( clb_I3[0] ) ) ; + .out ( clb_I3[2] ) ) ; direct_interc direct_interc_40_ ( .in ( { SYNOPSYS_UNCONNECTED_41 } ) , .out ( clb_I3[1] ) ) ; direct_interc direct_interc_41_ ( .in ( { SYNOPSYS_UNCONNECTED_42 } ) , - .out ( clb_I3[2] ) ) ; + .out ( clb_I3[0] ) ) ; direct_interc direct_interc_42_ ( .in ( { SYNOPSYS_UNCONNECTED_43 } ) , - .out ( clb_I3[3] ) ) ; + .out ( clb_I3i ) ) ; direct_interc direct_interc_43_ ( .in ( { SYNOPSYS_UNCONNECTED_44 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; direct_interc direct_interc_44_ ( .in ( { SYNOPSYS_UNCONNECTED_45 } ) , - .out ( logical_tile_clb_mode_default__fle_2_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; direct_interc direct_interc_45_ ( .in ( { SYNOPSYS_UNCONNECTED_46 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_46_ ( .in ( { SYNOPSYS_UNCONNECTED_47 } ) , - .out ( clb_I4[0] ) ) ; + .out ( clb_I4[2] ) ) ; direct_interc direct_interc_47_ ( .in ( { SYNOPSYS_UNCONNECTED_48 } ) , .out ( clb_I4[1] ) ) ; direct_interc direct_interc_48_ ( .in ( { SYNOPSYS_UNCONNECTED_49 } ) , - .out ( clb_I4[2] ) ) ; + .out ( clb_I4[0] ) ) ; direct_interc direct_interc_49_ ( .in ( { SYNOPSYS_UNCONNECTED_50 } ) , - .out ( clb_I4[3] ) ) ; + .out ( clb_I4i ) ) ; direct_interc direct_interc_50_ ( .in ( { SYNOPSYS_UNCONNECTED_51 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; direct_interc direct_interc_51_ ( .in ( { SYNOPSYS_UNCONNECTED_52 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; direct_interc direct_interc_52_ ( .in ( { SYNOPSYS_UNCONNECTED_53 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_53_ ( .in ( { SYNOPSYS_UNCONNECTED_54 } ) , - .out ( clb_I5[0] ) ) ; + .out ( clb_I5[2] ) ) ; direct_interc direct_interc_54_ ( .in ( { SYNOPSYS_UNCONNECTED_55 } ) , .out ( clb_I5[1] ) ) ; direct_interc direct_interc_55_ ( .in ( { SYNOPSYS_UNCONNECTED_56 } ) , - .out ( clb_I5[2] ) ) ; + .out ( clb_I5[0] ) ) ; direct_interc direct_interc_56_ ( .in ( { SYNOPSYS_UNCONNECTED_57 } ) , - .out ( clb_I5[3] ) ) ; + .out ( clb_I5i ) ) ; direct_interc direct_interc_57_ ( .in ( { SYNOPSYS_UNCONNECTED_58 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; direct_interc direct_interc_58_ ( .in ( { SYNOPSYS_UNCONNECTED_59 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; direct_interc direct_interc_59_ ( .in ( { SYNOPSYS_UNCONNECTED_60 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_60_ ( .in ( { SYNOPSYS_UNCONNECTED_61 } ) , - .out ( clb_I6[0] ) ) ; + .out ( clb_I6[2] ) ) ; direct_interc direct_interc_61_ ( .in ( { SYNOPSYS_UNCONNECTED_62 } ) , .out ( clb_I6[1] ) ) ; direct_interc direct_interc_62_ ( .in ( { SYNOPSYS_UNCONNECTED_63 } ) , - .out ( clb_I6[2] ) ) ; + .out ( clb_I6[0] ) ) ; direct_interc direct_interc_63_ ( .in ( { SYNOPSYS_UNCONNECTED_64 } ) , - .out ( clb_I6[3] ) ) ; + .out ( clb_I6i ) ) ; direct_interc direct_interc_64_ ( .in ( { SYNOPSYS_UNCONNECTED_65 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; direct_interc direct_interc_65_ ( .in ( { SYNOPSYS_UNCONNECTED_66 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; direct_interc direct_interc_66_ ( .in ( { SYNOPSYS_UNCONNECTED_67 } ) , .out ( clb_clk ) ) ; direct_interc direct_interc_67_ ( .in ( { SYNOPSYS_UNCONNECTED_68 } ) , - .out ( clb_I7[0] ) ) ; + .out ( clb_I7[2] ) ) ; direct_interc direct_interc_68_ ( .in ( { SYNOPSYS_UNCONNECTED_69 } ) , .out ( clb_I7[1] ) ) ; direct_interc direct_interc_69_ ( .in ( { SYNOPSYS_UNCONNECTED_70 } ) , - .out ( clb_I7[2] ) ) ; + .out ( clb_I7[0] ) ) ; direct_interc direct_interc_70_ ( .in ( { SYNOPSYS_UNCONNECTED_71 } ) , - .out ( clb_I7[3] ) ) ; + .out ( clb_I7i ) ) ; direct_interc direct_interc_71_ ( .in ( { SYNOPSYS_UNCONNECTED_72 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; direct_interc direct_interc_72_ ( .in ( { SYNOPSYS_UNCONNECTED_73 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_scout ) ) ; + .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; direct_interc direct_interc_73_ ( .in ( { SYNOPSYS_UNCONNECTED_74 } ) , .out ( clb_clk ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( - .A ( logical_tile_clb_mode_default__fle_0_fle_out[1] ) , .X ( clb_O[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( clb_O[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( - .A ( logical_tile_clb_mode_default__fle_0_fle_out[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( - .A ( logical_tile_clb_mode_default__fle_1_fle_out[1] ) , .X ( clb_O[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( clb_O[3] ) , .X ( p_abuf2 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( - .A ( logical_tile_clb_mode_default__fle_1_fle_out[1] ) , .X ( p_abuf3 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( p_abuf3 ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( p_abuf4 ) , + .X ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( p_abuf6 ) , + .X ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( clb_O[2] ) , + .X ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( p_abuf7 ) , + .X ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , .X ( clb_O[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( clb_O[5] ) , .X ( p_abuf4 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( clb_O[4] ) , .X ( p_abuf5 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , .X ( p_abuf6 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) , .X ( clb_O[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) , .X ( p_abuf7 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( + .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , .X ( clb_O[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( clb_O[9] ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( - .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , - .X ( BUF_net_76 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( - .A ( logical_tile_clb_mode_default__fle_5_fle_out[0] ) , - .X ( clb_O[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( - .A ( logical_tile_clb_mode_default__fle_5_fle_out[0] ) , - .X ( BUF_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_81 ( - .A ( logical_tile_clb_mode_default__fle_6_fle_out[0] ) , - .X ( clb_O[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( clb_O[10] ) , - .X ( BUF_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( - .A ( logical_tile_clb_mode_default__fle_6_fle_out[0] ) , - .X ( BUF_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( p_abuf14 ) , - .X ( BUF_net_85 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( clb_O[12] ) , - .X ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( BUF_net_74 ) , - .X ( p_abuf8 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( clb_O[14] ) , - .X ( BUF_net_87 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( BUF_net_78 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( clb_O[6] ) , + .X ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( clb_O[9] ) , .X ( p_abuf10 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( BUF_net_85 ) , - .X ( clb_O[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_104 ( .A ( BUF_net_84 ) , - .X ( p_abuf13 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_87 ) , - .X ( p_abuf15 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( BUF_net_76 ) , - .X ( p_abuf9 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( + .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , + .X ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( p_abuf14 ) , + .X ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_77 ( .A ( clb_O[11] ) , + .X ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( clb_O[10] ) , + .X ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_81 ( .A ( p_abuf15 ) , + .X ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( BUF_net_62 ) , + .X ( clb_O[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_103 ( .A ( BUF_net_66 ) , + .X ( clb_O[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( BUF_net_75 ) , .X ( p_abuf11 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( BUF_net_82 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_80 ) , + .X ( clb_O[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( BUF_net_77 ) , .X ( p_abuf12 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_107 ( .A ( BUF_net_79 ) , + .X ( p_abuf13 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_108 ( .A ( BUF_net_81 ) , + .X ( clb_O[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_110 ( .A ( p_abuf16 ) , + .X ( clb_O[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( BUF_net_63 ) , + .X ( clb_O[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( BUF_net_65 ) , + .X ( p_abuf5 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( BUF_net_67 ) , + .X ( clb_O[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( BUF_net_69 ) , + .X ( p_abuf8 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( BUF_net_71 ) , + .X ( p_abuf9 ) ) ; endmodule -module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_32_ , - top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_0_ , - right_width_0_height_0__pin_1_ , right_width_0_height_0__pin_2_ , - right_width_0_height_0__pin_3_ , right_width_0_height_0__pin_4_ , - right_width_0_height_0__pin_5_ , right_width_0_height_0__pin_6_ , - right_width_0_height_0__pin_7_ , right_width_0_height_0__pin_8_ , - right_width_0_height_0__pin_9_ , right_width_0_height_0__pin_10_ , - right_width_0_height_0__pin_11_ , right_width_0_height_0__pin_12_ , - right_width_0_height_0__pin_13_ , right_width_0_height_0__pin_14_ , - right_width_0_height_0__pin_15_ , bottom_width_0_height_0__pin_16_ , - bottom_width_0_height_0__pin_17_ , bottom_width_0_height_0__pin_18_ , - bottom_width_0_height_0__pin_19_ , bottom_width_0_height_0__pin_20_ , - bottom_width_0_height_0__pin_21_ , bottom_width_0_height_0__pin_22_ , - bottom_width_0_height_0__pin_23_ , bottom_width_0_height_0__pin_24_ , - bottom_width_0_height_0__pin_25_ , bottom_width_0_height_0__pin_26_ , - bottom_width_0_height_0__pin_27_ , bottom_width_0_height_0__pin_28_ , - bottom_width_0_height_0__pin_29_ , bottom_width_0_height_0__pin_30_ , - bottom_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , - ccff_head , right_width_0_height_0__pin_34_upper , - right_width_0_height_0__pin_34_lower , - right_width_0_height_0__pin_35_upper , - right_width_0_height_0__pin_35_lower , - right_width_0_height_0__pin_36_upper , - right_width_0_height_0__pin_36_lower , - right_width_0_height_0__pin_37_upper , - right_width_0_height_0__pin_37_lower , - right_width_0_height_0__pin_38_upper , - right_width_0_height_0__pin_38_lower , - right_width_0_height_0__pin_39_upper , - right_width_0_height_0__pin_39_lower , - right_width_0_height_0__pin_40_upper , - right_width_0_height_0__pin_40_lower , - right_width_0_height_0__pin_41_upper , - right_width_0_height_0__pin_41_lower , - bottom_width_0_height_0__pin_42_upper , - bottom_width_0_height_0__pin_42_lower , - bottom_width_0_height_0__pin_43_upper , - bottom_width_0_height_0__pin_43_lower , - bottom_width_0_height_0__pin_44_upper , - bottom_width_0_height_0__pin_44_lower , - bottom_width_0_height_0__pin_45_upper , - bottom_width_0_height_0__pin_45_lower , - bottom_width_0_height_0__pin_46_upper , - bottom_width_0_height_0__pin_46_lower , - bottom_width_0_height_0__pin_47_upper , - bottom_width_0_height_0__pin_47_lower , - bottom_width_0_height_0__pin_48_upper , - bottom_width_0_height_0__pin_48_lower , - bottom_width_0_height_0__pin_49_upper , - bottom_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , - bottom_width_0_height_0__pin_51_ , ccff_tail ) ; +module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ , + top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ , + top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ , + top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ , + top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ , + top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_16_ , + right_width_0_height_0__pin_17_ , right_width_0_height_0__pin_18_ , + right_width_0_height_0__pin_19_ , right_width_0_height_0__pin_20_ , + right_width_0_height_0__pin_21_ , right_width_0_height_0__pin_22_ , + right_width_0_height_0__pin_23_ , right_width_0_height_0__pin_24_ , + right_width_0_height_0__pin_25_ , right_width_0_height_0__pin_26_ , + right_width_0_height_0__pin_27_ , right_width_0_height_0__pin_28_ , + right_width_0_height_0__pin_29_ , right_width_0_height_0__pin_30_ , + right_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , + ccff_head , top_width_0_height_0__pin_34_upper , + top_width_0_height_0__pin_34_lower , top_width_0_height_0__pin_35_upper , + top_width_0_height_0__pin_35_lower , top_width_0_height_0__pin_36_upper , + top_width_0_height_0__pin_36_lower , top_width_0_height_0__pin_37_upper , + top_width_0_height_0__pin_37_lower , top_width_0_height_0__pin_38_upper , + top_width_0_height_0__pin_38_lower , top_width_0_height_0__pin_39_upper , + top_width_0_height_0__pin_39_lower , top_width_0_height_0__pin_40_upper , + top_width_0_height_0__pin_40_lower , top_width_0_height_0__pin_41_upper , + top_width_0_height_0__pin_41_lower , + right_width_0_height_0__pin_42_upper , + right_width_0_height_0__pin_42_lower , + right_width_0_height_0__pin_43_upper , + right_width_0_height_0__pin_43_lower , + right_width_0_height_0__pin_44_upper , + right_width_0_height_0__pin_44_lower , + right_width_0_height_0__pin_45_upper , + right_width_0_height_0__pin_45_lower , + right_width_0_height_0__pin_46_upper , + right_width_0_height_0__pin_46_lower , + right_width_0_height_0__pin_47_upper , + right_width_0_height_0__pin_47_lower , + right_width_0_height_0__pin_48_upper , + right_width_0_height_0__pin_48_lower , + right_width_0_height_0__pin_49_upper , + right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , + bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_1_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_3_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_5_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_7_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_9_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_11_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_13_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_15_ ; input [0:0] top_width_0_height_0__pin_32_ ; input [0:0] top_width_0_height_0__pin_33_ ; -input [0:0] right_width_0_height_0__pin_0_ ; -input [0:0] right_width_0_height_0__pin_1_ ; -input [0:0] right_width_0_height_0__pin_2_ ; -input [0:0] right_width_0_height_0__pin_3_ ; -input [0:0] right_width_0_height_0__pin_4_ ; -input [0:0] right_width_0_height_0__pin_5_ ; -input [0:0] right_width_0_height_0__pin_6_ ; -input [0:0] right_width_0_height_0__pin_7_ ; -input [0:0] right_width_0_height_0__pin_8_ ; -input [0:0] right_width_0_height_0__pin_9_ ; -input [0:0] right_width_0_height_0__pin_10_ ; -input [0:0] right_width_0_height_0__pin_11_ ; -input [0:0] right_width_0_height_0__pin_12_ ; -input [0:0] right_width_0_height_0__pin_13_ ; -input [0:0] right_width_0_height_0__pin_14_ ; -input [0:0] right_width_0_height_0__pin_15_ ; -input [0:0] bottom_width_0_height_0__pin_16_ ; -input [0:0] bottom_width_0_height_0__pin_17_ ; -input [0:0] bottom_width_0_height_0__pin_18_ ; -input [0:0] bottom_width_0_height_0__pin_19_ ; -input [0:0] bottom_width_0_height_0__pin_20_ ; -input [0:0] bottom_width_0_height_0__pin_21_ ; -input [0:0] bottom_width_0_height_0__pin_22_ ; -input [0:0] bottom_width_0_height_0__pin_23_ ; -input [0:0] bottom_width_0_height_0__pin_24_ ; -input [0:0] bottom_width_0_height_0__pin_25_ ; -input [0:0] bottom_width_0_height_0__pin_26_ ; -input [0:0] bottom_width_0_height_0__pin_27_ ; -input [0:0] bottom_width_0_height_0__pin_28_ ; -input [0:0] bottom_width_0_height_0__pin_29_ ; -input [0:0] bottom_width_0_height_0__pin_30_ ; -input [0:0] bottom_width_0_height_0__pin_31_ ; +input [0:0] right_width_0_height_0__pin_16_ ; +input [0:0] right_width_0_height_0__pin_17_ ; +input [0:0] right_width_0_height_0__pin_18_ ; +input [0:0] right_width_0_height_0__pin_19_ ; +input [0:0] right_width_0_height_0__pin_20_ ; +input [0:0] right_width_0_height_0__pin_21_ ; +input [0:0] right_width_0_height_0__pin_22_ ; +input [0:0] right_width_0_height_0__pin_23_ ; +input [0:0] right_width_0_height_0__pin_24_ ; +input [0:0] right_width_0_height_0__pin_25_ ; +input [0:0] right_width_0_height_0__pin_26_ ; +input [0:0] right_width_0_height_0__pin_27_ ; +input [0:0] right_width_0_height_0__pin_28_ ; +input [0:0] right_width_0_height_0__pin_29_ ; +input [0:0] right_width_0_height_0__pin_30_ ; +input [0:0] right_width_0_height_0__pin_31_ ; input [0:0] left_width_0_height_0__pin_52_ ; input [0:0] ccff_head ; -output [0:0] right_width_0_height_0__pin_34_upper ; -output [0:0] right_width_0_height_0__pin_34_lower ; -output [0:0] right_width_0_height_0__pin_35_upper ; -output [0:0] right_width_0_height_0__pin_35_lower ; -output [0:0] right_width_0_height_0__pin_36_upper ; -output [0:0] right_width_0_height_0__pin_36_lower ; -output [0:0] right_width_0_height_0__pin_37_upper ; -output [0:0] right_width_0_height_0__pin_37_lower ; -output [0:0] right_width_0_height_0__pin_38_upper ; -output [0:0] right_width_0_height_0__pin_38_lower ; -output [0:0] right_width_0_height_0__pin_39_upper ; -output [0:0] right_width_0_height_0__pin_39_lower ; -output [0:0] right_width_0_height_0__pin_40_upper ; -output [0:0] right_width_0_height_0__pin_40_lower ; -output [0:0] right_width_0_height_0__pin_41_upper ; -output [0:0] right_width_0_height_0__pin_41_lower ; -output [0:0] bottom_width_0_height_0__pin_42_upper ; -output [0:0] bottom_width_0_height_0__pin_42_lower ; -output [0:0] bottom_width_0_height_0__pin_43_upper ; -output [0:0] bottom_width_0_height_0__pin_43_lower ; -output [0:0] bottom_width_0_height_0__pin_44_upper ; -output [0:0] bottom_width_0_height_0__pin_44_lower ; -output [0:0] bottom_width_0_height_0__pin_45_upper ; -output [0:0] bottom_width_0_height_0__pin_45_lower ; -output [0:0] bottom_width_0_height_0__pin_46_upper ; -output [0:0] bottom_width_0_height_0__pin_46_lower ; -output [0:0] bottom_width_0_height_0__pin_47_upper ; -output [0:0] bottom_width_0_height_0__pin_47_lower ; -output [0:0] bottom_width_0_height_0__pin_48_upper ; -output [0:0] bottom_width_0_height_0__pin_48_lower ; -output [0:0] bottom_width_0_height_0__pin_49_upper ; -output [0:0] bottom_width_0_height_0__pin_49_lower ; +output [0:0] top_width_0_height_0__pin_34_upper ; +output [0:0] top_width_0_height_0__pin_34_lower ; +output [0:0] top_width_0_height_0__pin_35_upper ; +output [0:0] top_width_0_height_0__pin_35_lower ; +output [0:0] top_width_0_height_0__pin_36_upper ; +output [0:0] top_width_0_height_0__pin_36_lower ; +output [0:0] top_width_0_height_0__pin_37_upper ; +output [0:0] top_width_0_height_0__pin_37_lower ; +output [0:0] top_width_0_height_0__pin_38_upper ; +output [0:0] top_width_0_height_0__pin_38_lower ; +output [0:0] top_width_0_height_0__pin_39_upper ; +output [0:0] top_width_0_height_0__pin_39_lower ; +output [0:0] top_width_0_height_0__pin_40_upper ; +output [0:0] top_width_0_height_0__pin_40_lower ; +output [0:0] top_width_0_height_0__pin_41_upper ; +output [0:0] top_width_0_height_0__pin_41_lower ; +output [0:0] right_width_0_height_0__pin_42_upper ; +output [0:0] right_width_0_height_0__pin_42_lower ; +output [0:0] right_width_0_height_0__pin_43_upper ; +output [0:0] right_width_0_height_0__pin_43_lower ; +output [0:0] right_width_0_height_0__pin_44_upper ; +output [0:0] right_width_0_height_0__pin_44_lower ; +output [0:0] right_width_0_height_0__pin_45_upper ; +output [0:0] right_width_0_height_0__pin_45_lower ; +output [0:0] right_width_0_height_0__pin_46_upper ; +output [0:0] right_width_0_height_0__pin_46_lower ; +output [0:0] right_width_0_height_0__pin_47_upper ; +output [0:0] right_width_0_height_0__pin_47_lower ; +output [0:0] right_width_0_height_0__pin_48_upper ; +output [0:0] right_width_0_height_0__pin_48_lower ; +output [0:0] right_width_0_height_0__pin_49_upper ; +output [0:0] right_width_0_height_0__pin_49_lower ; output [0:0] bottom_width_0_height_0__pin_50_ ; output [0:0] bottom_width_0_height_0__pin_51_ ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; -wire ropt_net_128 ; -wire ropt_net_134 ; -wire ropt_net_136 ; -wire ropt_net_147 ; -wire ropt_net_133 ; -wire ropt_net_144 ; -wire ropt_net_126 ; -wire ropt_net_130 ; -wire ropt_net_135 ; +wire p_abuf1 ; wire p_abuf14 ; +wire p_abuf2 ; +wire p_abuf5 ; +wire p_abuf4 ; +wire ropt_net_143 ; +wire ropt_net_148 ; +wire ropt_net_144 ; +wire p_abuf13 ; +wire p_abuf12 ; +wire ropt_net_131 ; +wire ropt_net_130 ; +wire ropt_net_133 ; + +assign SC_IN_TOP = SC_IN_BOT ; logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .clb_I0 ( { right_width_0_height_0__pin_0_[0] , - right_width_0_height_0__pin_1_[0] , - right_width_0_height_0__pin_2_[0] , - right_width_0_height_0__pin_3_[0] } ) , - .clb_I1 ( { right_width_0_height_0__pin_4_[0] , - right_width_0_height_0__pin_5_[0] , - right_width_0_height_0__pin_6_[0] , - right_width_0_height_0__pin_7_[0] } ) , - .clb_I2 ( { right_width_0_height_0__pin_8_[0] , - right_width_0_height_0__pin_9_[0] , - right_width_0_height_0__pin_10_[0] , - right_width_0_height_0__pin_11_[0] } ) , - .clb_I3 ( { right_width_0_height_0__pin_12_[0] , - right_width_0_height_0__pin_13_[0] , - right_width_0_height_0__pin_14_[0] , - right_width_0_height_0__pin_15_[0] } ) , - .clb_I4 ( { bottom_width_0_height_0__pin_16_[0] , - bottom_width_0_height_0__pin_17_[0] , - bottom_width_0_height_0__pin_18_[0] , - bottom_width_0_height_0__pin_19_[0] } ) , - .clb_I5 ( { bottom_width_0_height_0__pin_20_[0] , - bottom_width_0_height_0__pin_21_[0] , - bottom_width_0_height_0__pin_22_[0] , - bottom_width_0_height_0__pin_23_[0] } ) , - .clb_I6 ( { bottom_width_0_height_0__pin_24_[0] , - bottom_width_0_height_0__pin_25_[0] , - bottom_width_0_height_0__pin_26_[0] , - bottom_width_0_height_0__pin_27_[0] } ) , - .clb_I7 ( { bottom_width_0_height_0__pin_28_[0] , - bottom_width_0_height_0__pin_29_[0] , - bottom_width_0_height_0__pin_30_[0] , - bottom_width_0_height_0__pin_31_[0] } ) , - .clb_regin ( top_width_0_height_0__pin_32_ ) , - .clb_scin ( top_width_0_height_0__pin_33_ ) , + .clb_I0 ( { top_width_0_height_0__pin_0_[0] , + top_width_0_height_0__pin_1_[0] , top_width_0_height_0__pin_2_[0] } ) , + .clb_I0i ( top_width_0_height_0__pin_3_ ) , + .clb_I1 ( { top_width_0_height_0__pin_4_[0] , + top_width_0_height_0__pin_5_[0] , top_width_0_height_0__pin_6_[0] } ) , + .clb_I1i ( top_width_0_height_0__pin_7_ ) , + .clb_I2 ( { top_width_0_height_0__pin_8_[0] , + top_width_0_height_0__pin_9_[0] , top_width_0_height_0__pin_10_[0] } ) , + .clb_I2i ( top_width_0_height_0__pin_11_ ) , + .clb_I3 ( { top_width_0_height_0__pin_12_[0] , + top_width_0_height_0__pin_13_[0] , top_width_0_height_0__pin_14_[0] } ) , + .clb_I3i ( top_width_0_height_0__pin_15_ ) , + .clb_I4 ( { right_width_0_height_0__pin_16_[0] , + right_width_0_height_0__pin_17_[0] , + right_width_0_height_0__pin_18_[0] } ) , + .clb_I4i ( right_width_0_height_0__pin_19_ ) , + .clb_I5 ( { right_width_0_height_0__pin_20_[0] , + right_width_0_height_0__pin_21_[0] , + right_width_0_height_0__pin_22_[0] } ) , + .clb_I5i ( right_width_0_height_0__pin_23_ ) , + .clb_I6 ( { right_width_0_height_0__pin_24_[0] , + right_width_0_height_0__pin_25_[0] , + right_width_0_height_0__pin_26_[0] } ) , + .clb_I6i ( right_width_0_height_0__pin_27_ ) , + .clb_I7 ( { right_width_0_height_0__pin_28_[0] , + right_width_0_height_0__pin_29_[0] , + right_width_0_height_0__pin_30_[0] } ) , + .clb_I7i ( right_width_0_height_0__pin_31_ ) , + .clb_regin ( top_width_0_height_0__pin_32_ ) , + .clb_sc_in ( { SC_IN_BOT } ) , .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_129_ , aps_rename_130_ , aps_rename_132_ , - aps_rename_134_ , aps_rename_136_ , aps_rename_138_ , - aps_rename_140_ , aps_rename_141_ , aps_rename_143_ , - aps_rename_145_ , aps_rename_147_ , aps_rename_149_ , - aps_rename_151_ , aps_rename_153_ , aps_rename_155_ , - bottom_width_0_height_0__pin_49_upper[0] } ) , - .clb_regout ( bottom_width_0_height_0__pin_50_ ) , - .clb_scout ( bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( { ropt_net_124 } ) , - .p_abuf0 ( right_width_0_height_0__pin_35_upper[0] ) , - .p_abuf1 ( right_width_0_height_0__pin_34_upper[0] ) , - .p_abuf2 ( ropt_net_134 ) , .p_abuf3 ( ropt_net_128 ) , - .p_abuf4 ( right_width_0_height_0__pin_39_upper[0] ) , - .p_abuf5 ( ropt_net_136 ) , .p_abuf6 ( ropt_net_133 ) , - .p_abuf7 ( ropt_net_147 ) , .p_abuf8 ( ropt_net_144 ) , - .p_abuf9 ( bottom_width_0_height_0__pin_42_upper[0] ) , - .p_abuf10 ( ropt_net_126 ) , - .p_abuf11 ( bottom_width_0_height_0__pin_44_upper[0] ) , - .p_abuf12 ( bottom_width_0_height_0__pin_47_upper[0] ) , - .p_abuf13 ( ropt_net_130 ) , .p_abuf14 ( p_abuf14 ) , - .p_abuf15 ( ropt_net_135 ) , .p0 ( optlc_net_118 ) , - .p1 ( optlc_net_119 ) , .p2 ( optlc_net_120 ) , .p3 ( optlc_net_121 ) , - .p4 ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( aps_rename_129_ ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( aps_rename_130_ ) , + .clb_O ( { ropt_net_145 , ropt_net_137 , aps_rename_132_ , + top_width_0_height_0__pin_37_upper[0] , + top_width_0_height_0__pin_38_upper[0] , ropt_net_141 , + aps_rename_137_ , aps_rename_139_ , aps_rename_141_ , + aps_rename_143_ , aps_rename_145_ , aps_rename_147_ , + right_width_0_height_0__pin_46_upper[0] , ropt_net_146 , + ropt_net_131 , ropt_net_130 } ) , + .clb_regout ( { ropt_net_134 } ) , + .clb_sc_out ( { aps_rename_153_ } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_133 ) , + .p_abuf3 ( p_abuf1 ) , .p_abuf4 ( p_abuf2 ) , + .p_abuf5 ( top_width_0_height_0__pin_36_upper[0] ) , + .p_abuf6 ( p_abuf4 ) , .p_abuf7 ( p_abuf5 ) , + .p_abuf8 ( top_width_0_height_0__pin_41_upper[0] ) , + .p_abuf9 ( ropt_net_143 ) , .p_abuf10 ( ropt_net_148 ) , + .p_abuf11 ( right_width_0_height_0__pin_42_upper[0] ) , + .p_abuf12 ( right_width_0_height_0__pin_45_upper[0] ) , + .p_abuf13 ( ropt_net_144 ) , .p_abuf14 ( p_abuf12 ) , + .p_abuf15 ( p_abuf13 ) , .p_abuf16 ( p_abuf14 ) , .p0 ( optlc_net_125 ) , + .p1 ( optlc_net_126 ) , .p2 ( optlc_net_127 ) , .p3 ( optlc_net_128 ) , + .p4 ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( p_abuf1 ) , + .X ( aps_rename_130_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( p_abuf14 ) , .X ( aps_rename_131_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( aps_rename_132_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( aps_rename_132_ ) , .X ( aps_rename_133_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( aps_rename_134_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( p_abuf2 ) , + .X ( aps_rename_134_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( p_abuf5 ) , .X ( aps_rename_135_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( aps_rename_136_ ) , - .X ( aps_rename_137_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( aps_rename_138_ ) , - .X ( aps_rename_139_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_140_ ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( aps_rename_141_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( p_abuf4 ) , + .X ( aps_rename_136_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_137_ ) , + .X ( aps_rename_138_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( aps_rename_139_ ) , + .X ( aps_rename_140_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( aps_rename_141_ ) , .X ( aps_rename_142_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( aps_rename_143_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( aps_rename_143_ ) , .X ( aps_rename_144_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( aps_rename_145_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( aps_rename_145_ ) , .X ( aps_rename_146_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( aps_rename_147_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( aps_rename_147_ ) , .X ( aps_rename_148_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( aps_rename_149_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( p_abuf13 ) , + .X ( aps_rename_149_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( p_abuf12 ) , .X ( aps_rename_150_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( aps_rename_151_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( ropt_net_131 ) , + .X ( aps_rename_151_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( ropt_net_130 ) , .X ( aps_rename_152_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( aps_rename_153_ ) , - .X ( aps_rename_154_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( aps_rename_155_ ) , - .X ( bottom_width_0_height_0__pin_48_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( p_abuf14 ) , - .X ( bottom_width_0_height_0__pin_49_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_89 ( .A ( aps_rename_131_ ) , - .X ( BUF_net_89 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( aps_rename_133_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( aps_rename_153_ ) , .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( .A ( aps_rename_135_ ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( aps_rename_137_ ) , - .X ( right_width_0_height_0__pin_38_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( aps_rename_139_ ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( aps_rename_142_ ) , - .X ( right_width_0_height_0__pin_41_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( aps_rename_144_ ) , - .X ( bottom_width_0_height_0__pin_42_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( aps_rename_146_ ) , - .X ( BUF_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( aps_rename_148_ ) , - .X ( BUF_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( .A ( aps_rename_150_ ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_99 ( .A ( aps_rename_152_ ) , - .X ( BUF_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_154_ ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_110 ( .A ( BUF_net_89 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_111 ( .A ( BUF_net_96 ) , - .X ( bottom_width_0_height_0__pin_43_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( BUF_net_97 ) , - .X ( bottom_width_0_height_0__pin_44_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( BUF_net_99 ) , - .X ( bottom_width_0_height_0__pin_46_lower[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_118 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_119 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_120 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( aps_rename_130_ ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( aps_rename_131_ ) , + .X ( top_width_0_height_0__pin_35_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( aps_rename_133_ ) , + .X ( top_width_0_height_0__pin_36_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_134_ ) , + .X ( top_width_0_height_0__pin_37_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( aps_rename_135_ ) , + .X ( BUF_net_88 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( aps_rename_136_ ) , + .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( aps_rename_138_ ) , + .X ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( .A ( aps_rename_140_ ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_142_ ) , .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_879 ( .A ( ropt_net_125 ) , - .X ( right_width_0_height_0__pin_37_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_880 ( .A ( ropt_net_126 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_93 ( .A ( aps_rename_144_ ) , + .X ( right_width_0_height_0__pin_43_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_146_ ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( aps_rename_148_ ) , + .X ( right_width_0_height_0__pin_45_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( aps_rename_149_ ) , .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_881 ( .A ( ropt_net_127 ) , - .X ( bottom_width_0_height_0__pin_47_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_882 ( .A ( ropt_net_128 ) , - .X ( right_width_0_height_0__pin_36_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_884 ( .A ( ropt_net_129 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_885 ( .A ( ropt_net_130 ) , - .X ( bottom_width_0_height_0__pin_46_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_886 ( .A ( ropt_net_131 ) , - .X ( right_width_0_height_0__pin_40_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_887 ( .A ( ropt_net_132 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( aps_rename_150_ ) , .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_888 ( .A ( ropt_net_133 ) , - .X ( right_width_0_height_0__pin_41_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_890 ( .A ( ropt_net_134 ) , - .X ( right_width_0_height_0__pin_37_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_892 ( .A ( ropt_net_135 ) , - .X ( bottom_width_0_height_0__pin_48_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_895 ( .A ( ropt_net_136 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_898 ( .A ( ropt_net_137 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_909 ( .A ( ropt_net_138 ) , - .X ( bottom_width_0_height_0__pin_45_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_913 ( .A ( ropt_net_139 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_914 ( .A ( ropt_net_140 ) , - .X ( bottom_width_0_height_0__pin_45_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_915 ( .A ( ropt_net_141 ) , - .X ( right_width_0_height_0__pin_39_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_916 ( .A ( ropt_net_142 ) , - .X ( right_width_0_height_0__pin_36_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_917 ( .A ( ropt_net_143 ) , - .X ( right_width_0_height_0__pin_34_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_918 ( .A ( ropt_net_144 ) , - .X ( bottom_width_0_height_0__pin_43_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_919 ( .A ( ropt_net_145 ) , - .X ( right_width_0_height_0__pin_38_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_920 ( .A ( ropt_net_146 ) , - .X ( right_width_0_height_0__pin_35_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_921 ( .A ( ropt_net_147 ) , - .X ( right_width_0_height_0__pin_40_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_98 ( .A ( aps_rename_151_ ) , + .X ( right_width_0_height_0__pin_48_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( aps_rename_152_ ) , + .X ( right_width_0_height_0__pin_49_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( BUF_net_119 ) , + .X ( top_width_0_height_0__pin_38_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( BUF_net_88 ) , + .X ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_120 ( .A ( BUF_net_89 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( BUF_net_122 ) , + .X ( top_width_0_height_0__pin_40_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_122 ( .A ( BUF_net_90 ) , + .X ( BUF_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_884 ( .A ( ropt_net_130 ) , + .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_885 ( .A ( ropt_net_131 ) , + .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_886 ( .A ( ropt_net_132 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_133 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_134 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_889 ( .A ( ropt_net_135 ) , + .X ( top_width_0_height_0__pin_34_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_890 ( .A ( ropt_net_136 ) , + .X ( top_width_0_height_0__pin_41_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_893 ( .A ( ropt_net_137 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_896 ( .A ( ropt_net_138 ) , + .X ( right_width_0_height_0__pin_44_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_897 ( .A ( ropt_net_139 ) , + .X ( right_width_0_height_0__pin_42_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_898 ( .A ( ropt_net_140 ) , + .X ( right_width_0_height_0__pin_46_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_899 ( .A ( ropt_net_141 ) , + .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_900 ( .A ( ropt_net_142 ) , + .X ( right_width_0_height_0__pin_47_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_901 ( .A ( ropt_net_143 ) , + .X ( top_width_0_height_0__pin_40_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_903 ( .A ( ropt_net_144 ) , + .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_906 ( .A ( ropt_net_145 ) , + .X ( top_width_0_height_0__pin_34_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_908 ( .A ( ropt_net_146 ) , + .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_910 ( .A ( ropt_net_147 ) , + .X ( top_width_0_height_0__pin_39_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_914 ( .A ( ropt_net_148 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_915 ( .A ( ropt_net_150 ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_916 ( .A ( ropt_net_151 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_919 ( .A ( ropt_net_152 ) , + .X ( top_width_0_height_0__pin_35_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_920 ( .A ( ropt_net_153 ) , + .X ( right_width_0_height_0__pin_43_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_154 ) , + .X ( bottom_width_0_height_0__pin_50_[0] ) ) ; endmodule -module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_GPIO_A , - gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , ccff_head , - ccff_tail ) ; +module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + ccff_head , ccff_tail , sc_head , sc_tail ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; -output [0:7] gfpga_pad_GPIO_A ; -output [0:7] gfpga_pad_GPIO_IE ; -output [0:7] gfpga_pad_GPIO_OE ; -inout [0:7] gfpga_pad_GPIO_Y ; +input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] ccff_head ; output [0:0] ccff_tail ; +input sc_head ; +output sc_tail ; wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__0__0_ccff_tail ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ; wire [0:19] cbx_1__0__0_chanx_left_out ; wire [0:19] cbx_1__0__0_chanx_right_out ; -wire [0:0] cbx_1__0__0_top_grid_pin_16_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_17_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_18_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_19_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_20_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_21_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_22_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_23_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_24_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_25_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_26_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_27_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_28_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_29_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_30_ ; -wire [0:0] cbx_1__0__0_top_grid_pin_31_ ; wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__0__1_ccff_tail ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ; wire [0:19] cbx_1__0__1_chanx_left_out ; wire [0:19] cbx_1__0__1_chanx_right_out ; -wire [0:0] cbx_1__0__1_top_grid_pin_16_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_17_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_18_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_19_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_20_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_21_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_22_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_23_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_24_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_25_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_26_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_27_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_28_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_29_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_30_ ; -wire [0:0] cbx_1__0__1_top_grid_pin_31_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ; wire [0:0] cbx_1__1__0_ccff_tail ; wire [0:19] cbx_1__1__0_chanx_left_out ; wire [0:19] cbx_1__1__0_chanx_right_out ; -wire [0:0] cbx_1__1__0_top_grid_pin_16_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_17_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_18_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_19_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_20_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_21_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_22_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_23_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_24_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_25_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_26_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_27_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_28_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_29_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_30_ ; -wire [0:0] cbx_1__1__0_top_grid_pin_31_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ; wire [0:0] cbx_1__1__1_ccff_tail ; wire [0:19] cbx_1__1__1_chanx_left_out ; wire [0:19] cbx_1__1__1_chanx_right_out ; -wire [0:0] cbx_1__1__1_top_grid_pin_16_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_17_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_18_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_19_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_20_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_21_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_22_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_23_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_24_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_25_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_26_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_27_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_28_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_29_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_30_ ; -wire [0:0] cbx_1__1__1_top_grid_pin_31_ ; -wire [0:0] cbx_1__2__0_ccff_tail ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__2__0_bottom_grid_pin_9_ ; wire [0:19] cbx_1__2__0_chanx_left_out ; wire [0:19] cbx_1__2__0_chanx_right_out ; wire [0:0] cbx_1__2__0_top_grid_pin_0_ ; -wire [0:0] cbx_1__2__1_ccff_tail ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__2__1_bottom_grid_pin_9_ ; wire [0:19] cbx_1__2__1_chanx_left_out ; wire [0:19] cbx_1__2__1_chanx_right_out ; wire [0:0] cbx_1__2__1_top_grid_pin_0_ ; -wire [0:0] cby_0__1__0_ccff_tail ; wire [0:19] cby_0__1__0_chany_bottom_out ; wire [0:19] cby_0__1__0_chany_top_out ; wire [0:0] cby_0__1__0_left_grid_pin_0_ ; -wire [0:0] cby_0__1__0_right_grid_pin_52_ ; -wire [0:0] cby_0__1__1_ccff_tail ; wire [0:19] cby_0__1__1_chany_bottom_out ; wire [0:19] cby_0__1__1_chany_top_out ; wire [0:0] cby_0__1__1_left_grid_pin_0_ ; -wire [0:0] cby_0__1__1_right_grid_pin_52_ ; wire [0:0] cby_1__1__0_ccff_tail ; wire [0:19] cby_1__1__0_chany_bottom_out ; wire [0:19] cby_1__1__0_chany_top_out ; -wire [0:0] cby_1__1__0_left_grid_pin_0_ ; -wire [0:0] cby_1__1__0_left_grid_pin_10_ ; -wire [0:0] cby_1__1__0_left_grid_pin_11_ ; -wire [0:0] cby_1__1__0_left_grid_pin_12_ ; -wire [0:0] cby_1__1__0_left_grid_pin_13_ ; -wire [0:0] cby_1__1__0_left_grid_pin_14_ ; -wire [0:0] cby_1__1__0_left_grid_pin_15_ ; -wire [0:0] cby_1__1__0_left_grid_pin_1_ ; -wire [0:0] cby_1__1__0_left_grid_pin_2_ ; -wire [0:0] cby_1__1__0_left_grid_pin_3_ ; -wire [0:0] cby_1__1__0_left_grid_pin_4_ ; -wire [0:0] cby_1__1__0_left_grid_pin_5_ ; -wire [0:0] cby_1__1__0_left_grid_pin_6_ ; -wire [0:0] cby_1__1__0_left_grid_pin_7_ ; -wire [0:0] cby_1__1__0_left_grid_pin_8_ ; -wire [0:0] cby_1__1__0_left_grid_pin_9_ ; -wire [0:0] cby_1__1__0_right_grid_pin_52_ ; +wire [0:0] cby_1__1__0_left_grid_pin_16_ ; +wire [0:0] cby_1__1__0_left_grid_pin_17_ ; +wire [0:0] cby_1__1__0_left_grid_pin_18_ ; +wire [0:0] cby_1__1__0_left_grid_pin_19_ ; +wire [0:0] cby_1__1__0_left_grid_pin_20_ ; +wire [0:0] cby_1__1__0_left_grid_pin_21_ ; +wire [0:0] cby_1__1__0_left_grid_pin_22_ ; +wire [0:0] cby_1__1__0_left_grid_pin_23_ ; +wire [0:0] cby_1__1__0_left_grid_pin_24_ ; +wire [0:0] cby_1__1__0_left_grid_pin_25_ ; +wire [0:0] cby_1__1__0_left_grid_pin_26_ ; +wire [0:0] cby_1__1__0_left_grid_pin_27_ ; +wire [0:0] cby_1__1__0_left_grid_pin_28_ ; +wire [0:0] cby_1__1__0_left_grid_pin_29_ ; +wire [0:0] cby_1__1__0_left_grid_pin_30_ ; +wire [0:0] cby_1__1__0_left_grid_pin_31_ ; wire [0:0] cby_1__1__1_ccff_tail ; wire [0:19] cby_1__1__1_chany_bottom_out ; wire [0:19] cby_1__1__1_chany_top_out ; -wire [0:0] cby_1__1__1_left_grid_pin_0_ ; -wire [0:0] cby_1__1__1_left_grid_pin_10_ ; -wire [0:0] cby_1__1__1_left_grid_pin_11_ ; -wire [0:0] cby_1__1__1_left_grid_pin_12_ ; -wire [0:0] cby_1__1__1_left_grid_pin_13_ ; -wire [0:0] cby_1__1__1_left_grid_pin_14_ ; -wire [0:0] cby_1__1__1_left_grid_pin_15_ ; -wire [0:0] cby_1__1__1_left_grid_pin_1_ ; -wire [0:0] cby_1__1__1_left_grid_pin_2_ ; -wire [0:0] cby_1__1__1_left_grid_pin_3_ ; -wire [0:0] cby_1__1__1_left_grid_pin_4_ ; -wire [0:0] cby_1__1__1_left_grid_pin_5_ ; -wire [0:0] cby_1__1__1_left_grid_pin_6_ ; -wire [0:0] cby_1__1__1_left_grid_pin_7_ ; -wire [0:0] cby_1__1__1_left_grid_pin_8_ ; -wire [0:0] cby_1__1__1_left_grid_pin_9_ ; -wire [0:0] cby_1__1__1_right_grid_pin_52_ ; -wire [0:0] cby_1__1__2_ccff_tail ; -wire [0:19] cby_1__1__2_chany_bottom_out ; -wire [0:19] cby_1__1__2_chany_top_out ; -wire [0:0] cby_1__1__2_left_grid_pin_0_ ; -wire [0:0] cby_1__1__2_left_grid_pin_10_ ; -wire [0:0] cby_1__1__2_left_grid_pin_11_ ; -wire [0:0] cby_1__1__2_left_grid_pin_12_ ; -wire [0:0] cby_1__1__2_left_grid_pin_13_ ; -wire [0:0] cby_1__1__2_left_grid_pin_14_ ; -wire [0:0] cby_1__1__2_left_grid_pin_15_ ; -wire [0:0] cby_1__1__2_left_grid_pin_1_ ; -wire [0:0] cby_1__1__2_left_grid_pin_2_ ; -wire [0:0] cby_1__1__2_left_grid_pin_3_ ; -wire [0:0] cby_1__1__2_left_grid_pin_4_ ; -wire [0:0] cby_1__1__2_left_grid_pin_5_ ; -wire [0:0] cby_1__1__2_left_grid_pin_6_ ; -wire [0:0] cby_1__1__2_left_grid_pin_7_ ; -wire [0:0] cby_1__1__2_left_grid_pin_8_ ; -wire [0:0] cby_1__1__2_left_grid_pin_9_ ; -wire [0:0] cby_1__1__2_right_grid_pin_52_ ; -wire [0:0] cby_1__1__3_ccff_tail ; -wire [0:19] cby_1__1__3_chany_bottom_out ; -wire [0:19] cby_1__1__3_chany_top_out ; -wire [0:0] cby_1__1__3_left_grid_pin_0_ ; -wire [0:0] cby_1__1__3_left_grid_pin_10_ ; -wire [0:0] cby_1__1__3_left_grid_pin_11_ ; -wire [0:0] cby_1__1__3_left_grid_pin_12_ ; -wire [0:0] cby_1__1__3_left_grid_pin_13_ ; -wire [0:0] cby_1__1__3_left_grid_pin_14_ ; -wire [0:0] cby_1__1__3_left_grid_pin_15_ ; -wire [0:0] cby_1__1__3_left_grid_pin_1_ ; -wire [0:0] cby_1__1__3_left_grid_pin_2_ ; -wire [0:0] cby_1__1__3_left_grid_pin_3_ ; -wire [0:0] cby_1__1__3_left_grid_pin_4_ ; -wire [0:0] cby_1__1__3_left_grid_pin_5_ ; -wire [0:0] cby_1__1__3_left_grid_pin_6_ ; -wire [0:0] cby_1__1__3_left_grid_pin_7_ ; -wire [0:0] cby_1__1__3_left_grid_pin_8_ ; -wire [0:0] cby_1__1__3_left_grid_pin_9_ ; -wire [0:0] cby_1__1__3_right_grid_pin_52_ ; +wire [0:0] cby_1__1__1_left_grid_pin_16_ ; +wire [0:0] cby_1__1__1_left_grid_pin_17_ ; +wire [0:0] cby_1__1__1_left_grid_pin_18_ ; +wire [0:0] cby_1__1__1_left_grid_pin_19_ ; +wire [0:0] cby_1__1__1_left_grid_pin_20_ ; +wire [0:0] cby_1__1__1_left_grid_pin_21_ ; +wire [0:0] cby_1__1__1_left_grid_pin_22_ ; +wire [0:0] cby_1__1__1_left_grid_pin_23_ ; +wire [0:0] cby_1__1__1_left_grid_pin_24_ ; +wire [0:0] cby_1__1__1_left_grid_pin_25_ ; +wire [0:0] cby_1__1__1_left_grid_pin_26_ ; +wire [0:0] cby_1__1__1_left_grid_pin_27_ ; +wire [0:0] cby_1__1__1_left_grid_pin_28_ ; +wire [0:0] cby_1__1__1_left_grid_pin_29_ ; +wire [0:0] cby_1__1__1_left_grid_pin_30_ ; +wire [0:0] cby_1__1__1_left_grid_pin_31_ ; +wire [0:19] cby_2__1__0_chany_bottom_out ; +wire [0:19] cby_2__1__0_chany_top_out ; +wire [0:0] cby_2__1__0_left_grid_pin_16_ ; +wire [0:0] cby_2__1__0_left_grid_pin_17_ ; +wire [0:0] cby_2__1__0_left_grid_pin_18_ ; +wire [0:0] cby_2__1__0_left_grid_pin_19_ ; +wire [0:0] cby_2__1__0_left_grid_pin_20_ ; +wire [0:0] cby_2__1__0_left_grid_pin_21_ ; +wire [0:0] cby_2__1__0_left_grid_pin_22_ ; +wire [0:0] cby_2__1__0_left_grid_pin_23_ ; +wire [0:0] cby_2__1__0_left_grid_pin_24_ ; +wire [0:0] cby_2__1__0_left_grid_pin_25_ ; +wire [0:0] cby_2__1__0_left_grid_pin_26_ ; +wire [0:0] cby_2__1__0_left_grid_pin_27_ ; +wire [0:0] cby_2__1__0_left_grid_pin_28_ ; +wire [0:0] cby_2__1__0_left_grid_pin_29_ ; +wire [0:0] cby_2__1__0_left_grid_pin_30_ ; +wire [0:0] cby_2__1__0_left_grid_pin_31_ ; +wire [0:0] cby_2__1__0_right_grid_pin_0_ ; +wire [0:19] cby_2__1__1_chany_bottom_out ; +wire [0:19] cby_2__1__1_chany_top_out ; +wire [0:0] cby_2__1__1_left_grid_pin_16_ ; +wire [0:0] cby_2__1__1_left_grid_pin_17_ ; +wire [0:0] cby_2__1__1_left_grid_pin_18_ ; +wire [0:0] cby_2__1__1_left_grid_pin_19_ ; +wire [0:0] cby_2__1__1_left_grid_pin_20_ ; +wire [0:0] cby_2__1__1_left_grid_pin_21_ ; +wire [0:0] cby_2__1__1_left_grid_pin_22_ ; +wire [0:0] cby_2__1__1_left_grid_pin_23_ ; +wire [0:0] cby_2__1__1_left_grid_pin_24_ ; +wire [0:0] cby_2__1__1_left_grid_pin_25_ ; +wire [0:0] cby_2__1__1_left_grid_pin_26_ ; +wire [0:0] cby_2__1__1_left_grid_pin_27_ ; +wire [0:0] cby_2__1__1_left_grid_pin_28_ ; +wire [0:0] cby_2__1__1_left_grid_pin_29_ ; +wire [0:0] cby_2__1__1_left_grid_pin_30_ ; +wire [0:0] cby_2__1__1_left_grid_pin_31_ ; +wire [0:0] cby_2__1__1_right_grid_pin_0_ ; wire [0:0] direct_interc_0_out ; wire [0:0] direct_interc_1_out ; wire [0:0] direct_interc_2_out ; -wire [0:0] direct_interc_3_out ; -wire [0:0] direct_interc_4_out ; wire [0:0] direct_interc_5_out ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_upper ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_0_ccff_tail ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_upper ; wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_1_ccff_tail ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_2_ccff_tail ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_3_ccff_tail ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_io_bottom_0_ccff_tail ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ; wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ; wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ; wire [0:0] grid_io_bottom_1_ccff_tail ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ; wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ; wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ; wire [0:0] grid_io_left_0_ccff_tail ; wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ; wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ; @@ -28758,422 +32549,337 @@ wire [0:19] sb_2__2__0_chany_bottom_out ; // grid_clb grid_clb_1__1_ ( - .prog_clk ( { ctsbuf_net_1722 } ) , + .prog_clk ( { ctsbuf_net_1113 } ) , .Test_en ( Test_en ) , .clk ( clk ) , - .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , - .top_width_0_height_0__pin_33_ ( direct_interc_3_out ) , - .right_width_0_height_0__pin_0_ ( cby_1__1__0_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_ ( cby_1__1__0_left_grid_pin_1_ ) , - .right_width_0_height_0__pin_2_ ( cby_1__1__0_left_grid_pin_2_ ) , - .right_width_0_height_0__pin_3_ ( cby_1__1__0_left_grid_pin_3_ ) , - .right_width_0_height_0__pin_4_ ( cby_1__1__0_left_grid_pin_4_ ) , - .right_width_0_height_0__pin_5_ ( cby_1__1__0_left_grid_pin_5_ ) , - .right_width_0_height_0__pin_6_ ( cby_1__1__0_left_grid_pin_6_ ) , - .right_width_0_height_0__pin_7_ ( cby_1__1__0_left_grid_pin_7_ ) , - .right_width_0_height_0__pin_8_ ( cby_1__1__0_left_grid_pin_8_ ) , - .right_width_0_height_0__pin_9_ ( cby_1__1__0_left_grid_pin_9_ ) , - .right_width_0_height_0__pin_10_ ( cby_1__1__0_left_grid_pin_10_ ) , - .right_width_0_height_0__pin_11_ ( cby_1__1__0_left_grid_pin_11_ ) , - .right_width_0_height_0__pin_12_ ( cby_1__1__0_left_grid_pin_12_ ) , - .right_width_0_height_0__pin_13_ ( cby_1__1__0_left_grid_pin_13_ ) , - .right_width_0_height_0__pin_14_ ( cby_1__1__0_left_grid_pin_14_ ) , - .right_width_0_height_0__pin_15_ ( cby_1__1__0_left_grid_pin_15_ ) , - .bottom_width_0_height_0__pin_16_ ( cbx_1__0__0_top_grid_pin_16_ ) , - .bottom_width_0_height_0__pin_17_ ( cbx_1__0__0_top_grid_pin_17_ ) , - .bottom_width_0_height_0__pin_18_ ( cbx_1__0__0_top_grid_pin_18_ ) , - .bottom_width_0_height_0__pin_19_ ( cbx_1__0__0_top_grid_pin_19_ ) , - .bottom_width_0_height_0__pin_20_ ( cbx_1__0__0_top_grid_pin_20_ ) , - .bottom_width_0_height_0__pin_21_ ( cbx_1__0__0_top_grid_pin_21_ ) , - .bottom_width_0_height_0__pin_22_ ( cbx_1__0__0_top_grid_pin_22_ ) , - .bottom_width_0_height_0__pin_23_ ( cbx_1__0__0_top_grid_pin_23_ ) , - .bottom_width_0_height_0__pin_24_ ( cbx_1__0__0_top_grid_pin_24_ ) , - .bottom_width_0_height_0__pin_25_ ( cbx_1__0__0_top_grid_pin_25_ ) , - .bottom_width_0_height_0__pin_26_ ( cbx_1__0__0_top_grid_pin_26_ ) , - .bottom_width_0_height_0__pin_27_ ( cbx_1__0__0_top_grid_pin_27_ ) , - .bottom_width_0_height_0__pin_28_ ( cbx_1__0__0_top_grid_pin_28_ ) , - .bottom_width_0_height_0__pin_29_ ( cbx_1__0__0_top_grid_pin_29_ ) , - .bottom_width_0_height_0__pin_30_ ( cbx_1__0__0_top_grid_pin_30_ ) , - .bottom_width_0_height_0__pin_31_ ( cbx_1__0__0_top_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( cby_0__1__0_right_grid_pin_52_ ) , - .ccff_head ( { ropt_net_31 } ) , - - .right_width_0_height_0__pin_34_upper ( grid_clb_0_right_width_0_height_0__pin_34_upper ) , - .right_width_0_height_0__pin_34_lower ( grid_clb_0_right_width_0_height_0__pin_34_lower ) , - .right_width_0_height_0__pin_35_upper ( grid_clb_0_right_width_0_height_0__pin_35_upper ) , - .right_width_0_height_0__pin_35_lower ( grid_clb_0_right_width_0_height_0__pin_35_lower ) , - .right_width_0_height_0__pin_36_upper ( grid_clb_0_right_width_0_height_0__pin_36_upper ) , - .right_width_0_height_0__pin_36_lower ( grid_clb_0_right_width_0_height_0__pin_36_lower ) , - .right_width_0_height_0__pin_37_upper ( grid_clb_0_right_width_0_height_0__pin_37_upper ) , - .right_width_0_height_0__pin_37_lower ( grid_clb_0_right_width_0_height_0__pin_37_lower ) , - .right_width_0_height_0__pin_38_upper ( grid_clb_0_right_width_0_height_0__pin_38_upper ) , - .right_width_0_height_0__pin_38_lower ( grid_clb_0_right_width_0_height_0__pin_38_lower ) , - .right_width_0_height_0__pin_39_upper ( grid_clb_0_right_width_0_height_0__pin_39_upper ) , - .right_width_0_height_0__pin_39_lower ( grid_clb_0_right_width_0_height_0__pin_39_lower ) , - .right_width_0_height_0__pin_40_upper ( grid_clb_0_right_width_0_height_0__pin_40_upper ) , - .right_width_0_height_0__pin_40_lower ( grid_clb_0_right_width_0_height_0__pin_40_lower ) , - .right_width_0_height_0__pin_41_upper ( grid_clb_0_right_width_0_height_0__pin_41_upper ) , - .right_width_0_height_0__pin_41_lower ( grid_clb_0_right_width_0_height_0__pin_41_lower ) , - .bottom_width_0_height_0__pin_42_upper ( grid_clb_0_bottom_width_0_height_0__pin_42_upper ) , - .bottom_width_0_height_0__pin_42_lower ( grid_clb_0_bottom_width_0_height_0__pin_42_lower ) , - .bottom_width_0_height_0__pin_43_upper ( grid_clb_0_bottom_width_0_height_0__pin_43_upper ) , - .bottom_width_0_height_0__pin_43_lower ( grid_clb_0_bottom_width_0_height_0__pin_43_lower ) , - .bottom_width_0_height_0__pin_44_upper ( grid_clb_0_bottom_width_0_height_0__pin_44_upper ) , - .bottom_width_0_height_0__pin_44_lower ( grid_clb_0_bottom_width_0_height_0__pin_44_lower ) , - .bottom_width_0_height_0__pin_45_upper ( grid_clb_0_bottom_width_0_height_0__pin_45_upper ) , - .bottom_width_0_height_0__pin_45_lower ( grid_clb_0_bottom_width_0_height_0__pin_45_lower ) , - .bottom_width_0_height_0__pin_46_upper ( grid_clb_0_bottom_width_0_height_0__pin_46_upper ) , - .bottom_width_0_height_0__pin_46_lower ( grid_clb_0_bottom_width_0_height_0__pin_46_lower ) , - .bottom_width_0_height_0__pin_47_upper ( grid_clb_0_bottom_width_0_height_0__pin_47_upper ) , - .bottom_width_0_height_0__pin_47_lower ( grid_clb_0_bottom_width_0_height_0__pin_47_lower ) , - .bottom_width_0_height_0__pin_48_upper ( grid_clb_0_bottom_width_0_height_0__pin_48_upper ) , - .bottom_width_0_height_0__pin_48_lower ( grid_clb_0_bottom_width_0_height_0__pin_48_lower ) , - .bottom_width_0_height_0__pin_49_upper ( grid_clb_0_bottom_width_0_height_0__pin_49_upper ) , - .bottom_width_0_height_0__pin_49_lower ( grid_clb_0_bottom_width_0_height_0__pin_49_lower ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , + .top_width_0_height_0__pin_33_ ( { sc_in_wires_0_ } ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ) , + .ccff_head ( grid_io_left_0_ccff_tail ) , + .top_width_0_height_0__pin_34_upper ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , + .top_width_0_height_0__pin_34_lower ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , + .top_width_0_height_0__pin_35_upper ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , + .top_width_0_height_0__pin_35_lower ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , + .right_width_0_height_0__pin_42_upper ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , + .right_width_0_height_0__pin_42_lower ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , + .right_width_0_height_0__pin_43_upper ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , + .right_width_0_height_0__pin_43_lower ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , .bottom_width_0_height_0__pin_51_ ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( grid_clb_0_ccff_tail ) ) ; + .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_3_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2 ) , .SC_OUT_BOT ( scff_Wires_5_ ) ) ; grid_clb grid_clb_1__2_ ( - .prog_clk ( { ctsbuf_net_1318 } ) , + .prog_clk ( { ctsbuf_net_1517 } ) , .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__2__0_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__2__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__2__0_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__2__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__2__0_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__2__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__2__0_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__2__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__2__0_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__2__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , .top_width_0_height_0__pin_33_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ) , - .right_width_0_height_0__pin_0_ ( cby_1__1__1_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_ ( cby_1__1__1_left_grid_pin_1_ ) , - .right_width_0_height_0__pin_2_ ( cby_1__1__1_left_grid_pin_2_ ) , - .right_width_0_height_0__pin_3_ ( cby_1__1__1_left_grid_pin_3_ ) , - .right_width_0_height_0__pin_4_ ( cby_1__1__1_left_grid_pin_4_ ) , - .right_width_0_height_0__pin_5_ ( cby_1__1__1_left_grid_pin_5_ ) , - .right_width_0_height_0__pin_6_ ( cby_1__1__1_left_grid_pin_6_ ) , - .right_width_0_height_0__pin_7_ ( cby_1__1__1_left_grid_pin_7_ ) , - .right_width_0_height_0__pin_8_ ( cby_1__1__1_left_grid_pin_8_ ) , - .right_width_0_height_0__pin_9_ ( cby_1__1__1_left_grid_pin_9_ ) , - .right_width_0_height_0__pin_10_ ( cby_1__1__1_left_grid_pin_10_ ) , - .right_width_0_height_0__pin_11_ ( cby_1__1__1_left_grid_pin_11_ ) , - .right_width_0_height_0__pin_12_ ( cby_1__1__1_left_grid_pin_12_ ) , - .right_width_0_height_0__pin_13_ ( cby_1__1__1_left_grid_pin_13_ ) , - .right_width_0_height_0__pin_14_ ( cby_1__1__1_left_grid_pin_14_ ) , - .right_width_0_height_0__pin_15_ ( cby_1__1__1_left_grid_pin_15_ ) , - .bottom_width_0_height_0__pin_16_ ( cbx_1__1__0_top_grid_pin_16_ ) , - .bottom_width_0_height_0__pin_17_ ( cbx_1__1__0_top_grid_pin_17_ ) , - .bottom_width_0_height_0__pin_18_ ( cbx_1__1__0_top_grid_pin_18_ ) , - .bottom_width_0_height_0__pin_19_ ( cbx_1__1__0_top_grid_pin_19_ ) , - .bottom_width_0_height_0__pin_20_ ( cbx_1__1__0_top_grid_pin_20_ ) , - .bottom_width_0_height_0__pin_21_ ( cbx_1__1__0_top_grid_pin_21_ ) , - .bottom_width_0_height_0__pin_22_ ( cbx_1__1__0_top_grid_pin_22_ ) , - .bottom_width_0_height_0__pin_23_ ( cbx_1__1__0_top_grid_pin_23_ ) , - .bottom_width_0_height_0__pin_24_ ( cbx_1__1__0_top_grid_pin_24_ ) , - .bottom_width_0_height_0__pin_25_ ( cbx_1__1__0_top_grid_pin_25_ ) , - .bottom_width_0_height_0__pin_26_ ( cbx_1__1__0_top_grid_pin_26_ ) , - .bottom_width_0_height_0__pin_27_ ( cbx_1__1__0_top_grid_pin_27_ ) , - .bottom_width_0_height_0__pin_28_ ( cbx_1__1__0_top_grid_pin_28_ ) , - .bottom_width_0_height_0__pin_29_ ( cbx_1__1__0_top_grid_pin_29_ ) , - .bottom_width_0_height_0__pin_30_ ( cbx_1__1__0_top_grid_pin_30_ ) , - .bottom_width_0_height_0__pin_31_ ( cbx_1__1__0_top_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( cby_0__1__1_right_grid_pin_52_ ) , - .ccff_head ( { ropt_net_27 } ) , - - .right_width_0_height_0__pin_34_upper ( grid_clb_1_right_width_0_height_0__pin_34_upper ) , - .right_width_0_height_0__pin_34_lower ( grid_clb_1_right_width_0_height_0__pin_34_lower ) , - .right_width_0_height_0__pin_35_upper ( grid_clb_1_right_width_0_height_0__pin_35_upper ) , - .right_width_0_height_0__pin_35_lower ( grid_clb_1_right_width_0_height_0__pin_35_lower ) , - .right_width_0_height_0__pin_36_upper ( grid_clb_1_right_width_0_height_0__pin_36_upper ) , - .right_width_0_height_0__pin_36_lower ( grid_clb_1_right_width_0_height_0__pin_36_lower ) , - .right_width_0_height_0__pin_37_upper ( grid_clb_1_right_width_0_height_0__pin_37_upper ) , - .right_width_0_height_0__pin_37_lower ( grid_clb_1_right_width_0_height_0__pin_37_lower ) , - .right_width_0_height_0__pin_38_upper ( grid_clb_1_right_width_0_height_0__pin_38_upper ) , - .right_width_0_height_0__pin_38_lower ( grid_clb_1_right_width_0_height_0__pin_38_lower ) , - .right_width_0_height_0__pin_39_upper ( grid_clb_1_right_width_0_height_0__pin_39_upper ) , - .right_width_0_height_0__pin_39_lower ( grid_clb_1_right_width_0_height_0__pin_39_lower ) , - .right_width_0_height_0__pin_40_upper ( grid_clb_1_right_width_0_height_0__pin_40_upper ) , - .right_width_0_height_0__pin_40_lower ( grid_clb_1_right_width_0_height_0__pin_40_lower ) , - .right_width_0_height_0__pin_41_upper ( grid_clb_1_right_width_0_height_0__pin_41_upper ) , - .right_width_0_height_0__pin_41_lower ( grid_clb_1_right_width_0_height_0__pin_41_lower ) , - .bottom_width_0_height_0__pin_42_upper ( grid_clb_1_bottom_width_0_height_0__pin_42_upper ) , - .bottom_width_0_height_0__pin_42_lower ( grid_clb_1_bottom_width_0_height_0__pin_42_lower ) , - .bottom_width_0_height_0__pin_43_upper ( grid_clb_1_bottom_width_0_height_0__pin_43_upper ) , - .bottom_width_0_height_0__pin_43_lower ( grid_clb_1_bottom_width_0_height_0__pin_43_lower ) , - .bottom_width_0_height_0__pin_44_upper ( grid_clb_1_bottom_width_0_height_0__pin_44_upper ) , - .bottom_width_0_height_0__pin_44_lower ( grid_clb_1_bottom_width_0_height_0__pin_44_lower ) , - .bottom_width_0_height_0__pin_45_upper ( grid_clb_1_bottom_width_0_height_0__pin_45_upper ) , - .bottom_width_0_height_0__pin_45_lower ( grid_clb_1_bottom_width_0_height_0__pin_45_lower ) , - .bottom_width_0_height_0__pin_46_upper ( grid_clb_1_bottom_width_0_height_0__pin_46_upper ) , - .bottom_width_0_height_0__pin_46_lower ( grid_clb_1_bottom_width_0_height_0__pin_46_lower ) , - .bottom_width_0_height_0__pin_47_upper ( grid_clb_1_bottom_width_0_height_0__pin_47_upper ) , - .bottom_width_0_height_0__pin_47_lower ( grid_clb_1_bottom_width_0_height_0__pin_47_lower ) , - .bottom_width_0_height_0__pin_48_upper ( grid_clb_1_bottom_width_0_height_0__pin_48_upper ) , - .bottom_width_0_height_0__pin_48_lower ( grid_clb_1_bottom_width_0_height_0__pin_48_lower ) , - .bottom_width_0_height_0__pin_49_upper ( grid_clb_1_bottom_width_0_height_0__pin_49_upper ) , - .bottom_width_0_height_0__pin_49_lower ( grid_clb_1_bottom_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( grid_clb_1_bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( grid_clb_1_ccff_tail ) ) ; + .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ) , + .ccff_head ( grid_io_left_1_ccff_tail ) , + .top_width_0_height_0__pin_34_upper ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , + .top_width_0_height_0__pin_34_lower ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , + .top_width_0_height_0__pin_35_upper ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , + .top_width_0_height_0__pin_35_lower ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , + .right_width_0_height_0__pin_42_upper ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , + .right_width_0_height_0__pin_42_lower ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , + .right_width_0_height_0__pin_43_upper ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , + .right_width_0_height_0__pin_43_lower ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( { sc_out_wires_0_ } ) , + .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_2_ ) ) ; grid_clb grid_clb_2__1_ ( - .prog_clk ( { ctsbuf_net_1116 } ) , + .prog_clk ( { ctsbuf_net_57 } ) , .Test_en ( Test_en ) , .clk ( clk ) , - .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , - .top_width_0_height_0__pin_33_ ( direct_interc_4_out ) , - .right_width_0_height_0__pin_0_ ( cby_1__1__2_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_ ( cby_1__1__2_left_grid_pin_1_ ) , - .right_width_0_height_0__pin_2_ ( cby_1__1__2_left_grid_pin_2_ ) , - .right_width_0_height_0__pin_3_ ( cby_1__1__2_left_grid_pin_3_ ) , - .right_width_0_height_0__pin_4_ ( cby_1__1__2_left_grid_pin_4_ ) , - .right_width_0_height_0__pin_5_ ( cby_1__1__2_left_grid_pin_5_ ) , - .right_width_0_height_0__pin_6_ ( cby_1__1__2_left_grid_pin_6_ ) , - .right_width_0_height_0__pin_7_ ( cby_1__1__2_left_grid_pin_7_ ) , - .right_width_0_height_0__pin_8_ ( cby_1__1__2_left_grid_pin_8_ ) , - .right_width_0_height_0__pin_9_ ( cby_1__1__2_left_grid_pin_9_ ) , - .right_width_0_height_0__pin_10_ ( cby_1__1__2_left_grid_pin_10_ ) , - .right_width_0_height_0__pin_11_ ( cby_1__1__2_left_grid_pin_11_ ) , - .right_width_0_height_0__pin_12_ ( cby_1__1__2_left_grid_pin_12_ ) , - .right_width_0_height_0__pin_13_ ( cby_1__1__2_left_grid_pin_13_ ) , - .right_width_0_height_0__pin_14_ ( cby_1__1__2_left_grid_pin_14_ ) , - .right_width_0_height_0__pin_15_ ( cby_1__1__2_left_grid_pin_15_ ) , - .bottom_width_0_height_0__pin_16_ ( cbx_1__0__1_top_grid_pin_16_ ) , - .bottom_width_0_height_0__pin_17_ ( cbx_1__0__1_top_grid_pin_17_ ) , - .bottom_width_0_height_0__pin_18_ ( cbx_1__0__1_top_grid_pin_18_ ) , - .bottom_width_0_height_0__pin_19_ ( cbx_1__0__1_top_grid_pin_19_ ) , - .bottom_width_0_height_0__pin_20_ ( cbx_1__0__1_top_grid_pin_20_ ) , - .bottom_width_0_height_0__pin_21_ ( cbx_1__0__1_top_grid_pin_21_ ) , - .bottom_width_0_height_0__pin_22_ ( cbx_1__0__1_top_grid_pin_22_ ) , - .bottom_width_0_height_0__pin_23_ ( cbx_1__0__1_top_grid_pin_23_ ) , - .bottom_width_0_height_0__pin_24_ ( cbx_1__0__1_top_grid_pin_24_ ) , - .bottom_width_0_height_0__pin_25_ ( cbx_1__0__1_top_grid_pin_25_ ) , - .bottom_width_0_height_0__pin_26_ ( cbx_1__0__1_top_grid_pin_26_ ) , - .bottom_width_0_height_0__pin_27_ ( cbx_1__0__1_top_grid_pin_27_ ) , - .bottom_width_0_height_0__pin_28_ ( cbx_1__0__1_top_grid_pin_28_ ) , - .bottom_width_0_height_0__pin_29_ ( cbx_1__0__1_top_grid_pin_29_ ) , - .bottom_width_0_height_0__pin_30_ ( cbx_1__0__1_top_grid_pin_30_ ) , - .bottom_width_0_height_0__pin_31_ ( cbx_1__0__1_top_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( cby_1__1__0_right_grid_pin_52_ ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , + .top_width_0_height_0__pin_33_ ( { sc_in_wires_1_ } ) , + .right_width_0_height_0__pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_2__1__0_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_2__1__0_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_2__1__0_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_2__1__0_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_2__1__0_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_2__1__0_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_2__1__0_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_2__1__0_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_2__1__0_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_2__1__0_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_2__1__0_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_2__1__0_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_2__1__0_left_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ) , .ccff_head ( cby_1__1__0_ccff_tail ) , - .right_width_0_height_0__pin_34_upper ( grid_clb_2_right_width_0_height_0__pin_34_upper ) , - .right_width_0_height_0__pin_34_lower ( grid_clb_2_right_width_0_height_0__pin_34_lower ) , - .right_width_0_height_0__pin_35_upper ( grid_clb_2_right_width_0_height_0__pin_35_upper ) , - .right_width_0_height_0__pin_35_lower ( grid_clb_2_right_width_0_height_0__pin_35_lower ) , - .right_width_0_height_0__pin_36_upper ( grid_clb_2_right_width_0_height_0__pin_36_upper ) , - .right_width_0_height_0__pin_36_lower ( grid_clb_2_right_width_0_height_0__pin_36_lower ) , - .right_width_0_height_0__pin_37_upper ( grid_clb_2_right_width_0_height_0__pin_37_upper ) , - .right_width_0_height_0__pin_37_lower ( grid_clb_2_right_width_0_height_0__pin_37_lower ) , - .right_width_0_height_0__pin_38_upper ( grid_clb_2_right_width_0_height_0__pin_38_upper ) , - .right_width_0_height_0__pin_38_lower ( grid_clb_2_right_width_0_height_0__pin_38_lower ) , - .right_width_0_height_0__pin_39_upper ( grid_clb_2_right_width_0_height_0__pin_39_upper ) , - .right_width_0_height_0__pin_39_lower ( grid_clb_2_right_width_0_height_0__pin_39_lower ) , - .right_width_0_height_0__pin_40_upper ( grid_clb_2_right_width_0_height_0__pin_40_upper ) , - .right_width_0_height_0__pin_40_lower ( grid_clb_2_right_width_0_height_0__pin_40_lower ) , - .right_width_0_height_0__pin_41_upper ( grid_clb_2_right_width_0_height_0__pin_41_upper ) , - .right_width_0_height_0__pin_41_lower ( grid_clb_2_right_width_0_height_0__pin_41_lower ) , - .bottom_width_0_height_0__pin_42_upper ( grid_clb_2_bottom_width_0_height_0__pin_42_upper ) , - .bottom_width_0_height_0__pin_42_lower ( grid_clb_2_bottom_width_0_height_0__pin_42_lower ) , - .bottom_width_0_height_0__pin_43_upper ( grid_clb_2_bottom_width_0_height_0__pin_43_upper ) , - .bottom_width_0_height_0__pin_43_lower ( grid_clb_2_bottom_width_0_height_0__pin_43_lower ) , - .bottom_width_0_height_0__pin_44_upper ( grid_clb_2_bottom_width_0_height_0__pin_44_upper ) , - .bottom_width_0_height_0__pin_44_lower ( grid_clb_2_bottom_width_0_height_0__pin_44_lower ) , - .bottom_width_0_height_0__pin_45_upper ( grid_clb_2_bottom_width_0_height_0__pin_45_upper ) , - .bottom_width_0_height_0__pin_45_lower ( grid_clb_2_bottom_width_0_height_0__pin_45_lower ) , - .bottom_width_0_height_0__pin_46_upper ( grid_clb_2_bottom_width_0_height_0__pin_46_upper ) , - .bottom_width_0_height_0__pin_46_lower ( grid_clb_2_bottom_width_0_height_0__pin_46_lower ) , - .bottom_width_0_height_0__pin_47_upper ( grid_clb_2_bottom_width_0_height_0__pin_47_upper ) , - .bottom_width_0_height_0__pin_47_lower ( grid_clb_2_bottom_width_0_height_0__pin_47_lower ) , - .bottom_width_0_height_0__pin_48_upper ( grid_clb_2_bottom_width_0_height_0__pin_48_upper ) , - .bottom_width_0_height_0__pin_48_lower ( grid_clb_2_bottom_width_0_height_0__pin_48_lower ) , - .bottom_width_0_height_0__pin_49_upper ( grid_clb_2_bottom_width_0_height_0__pin_49_upper ) , - .bottom_width_0_height_0__pin_49_lower ( grid_clb_2_bottom_width_0_height_0__pin_49_lower ) , + .top_width_0_height_0__pin_34_upper ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , + .top_width_0_height_0__pin_34_lower ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , + .top_width_0_height_0__pin_35_upper ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , + .top_width_0_height_0__pin_35_lower ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , + .right_width_0_height_0__pin_42_upper ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , + .right_width_0_height_0__pin_42_lower ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , + .right_width_0_height_0__pin_43_upper ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , + .right_width_0_height_0__pin_43_lower ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , .bottom_width_0_height_0__pin_51_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( grid_clb_2_ccff_tail ) ) ; + .ccff_tail ( grid_clb_2_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_5 ) , .SC_IN_BOT ( scff_Wires_8_ ) , + .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6 ) ) ; grid_clb grid_clb_2__2_ ( - .prog_clk ( { ctsbuf_net_510 } ) , + .prog_clk ( { ctsbuf_net_911 } ) , .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__2__1_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__2__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__2__1_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__2__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__2__1_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__2__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__2__1_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__2__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__2__1_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__2__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , .top_width_0_height_0__pin_33_ ( direct_interc_5_out ) , - .right_width_0_height_0__pin_0_ ( cby_1__1__3_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_ ( cby_1__1__3_left_grid_pin_1_ ) , - .right_width_0_height_0__pin_2_ ( cby_1__1__3_left_grid_pin_2_ ) , - .right_width_0_height_0__pin_3_ ( cby_1__1__3_left_grid_pin_3_ ) , - .right_width_0_height_0__pin_4_ ( cby_1__1__3_left_grid_pin_4_ ) , - .right_width_0_height_0__pin_5_ ( cby_1__1__3_left_grid_pin_5_ ) , - .right_width_0_height_0__pin_6_ ( cby_1__1__3_left_grid_pin_6_ ) , - .right_width_0_height_0__pin_7_ ( cby_1__1__3_left_grid_pin_7_ ) , - .right_width_0_height_0__pin_8_ ( cby_1__1__3_left_grid_pin_8_ ) , - .right_width_0_height_0__pin_9_ ( cby_1__1__3_left_grid_pin_9_ ) , - .right_width_0_height_0__pin_10_ ( cby_1__1__3_left_grid_pin_10_ ) , - .right_width_0_height_0__pin_11_ ( cby_1__1__3_left_grid_pin_11_ ) , - .right_width_0_height_0__pin_12_ ( cby_1__1__3_left_grid_pin_12_ ) , - .right_width_0_height_0__pin_13_ ( cby_1__1__3_left_grid_pin_13_ ) , - .right_width_0_height_0__pin_14_ ( cby_1__1__3_left_grid_pin_14_ ) , - .right_width_0_height_0__pin_15_ ( cby_1__1__3_left_grid_pin_15_ ) , - .bottom_width_0_height_0__pin_16_ ( cbx_1__1__1_top_grid_pin_16_ ) , - .bottom_width_0_height_0__pin_17_ ( cbx_1__1__1_top_grid_pin_17_ ) , - .bottom_width_0_height_0__pin_18_ ( cbx_1__1__1_top_grid_pin_18_ ) , - .bottom_width_0_height_0__pin_19_ ( cbx_1__1__1_top_grid_pin_19_ ) , - .bottom_width_0_height_0__pin_20_ ( cbx_1__1__1_top_grid_pin_20_ ) , - .bottom_width_0_height_0__pin_21_ ( cbx_1__1__1_top_grid_pin_21_ ) , - .bottom_width_0_height_0__pin_22_ ( cbx_1__1__1_top_grid_pin_22_ ) , - .bottom_width_0_height_0__pin_23_ ( cbx_1__1__1_top_grid_pin_23_ ) , - .bottom_width_0_height_0__pin_24_ ( cbx_1__1__1_top_grid_pin_24_ ) , - .bottom_width_0_height_0__pin_25_ ( cbx_1__1__1_top_grid_pin_25_ ) , - .bottom_width_0_height_0__pin_26_ ( cbx_1__1__1_top_grid_pin_26_ ) , - .bottom_width_0_height_0__pin_27_ ( cbx_1__1__1_top_grid_pin_27_ ) , - .bottom_width_0_height_0__pin_28_ ( cbx_1__1__1_top_grid_pin_28_ ) , - .bottom_width_0_height_0__pin_29_ ( cbx_1__1__1_top_grid_pin_29_ ) , - .bottom_width_0_height_0__pin_30_ ( cbx_1__1__1_top_grid_pin_30_ ) , - .bottom_width_0_height_0__pin_31_ ( cbx_1__1__1_top_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( cby_1__1__1_right_grid_pin_52_ ) , + .right_width_0_height_0__pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_2__1__1_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_2__1__1_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_2__1__1_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_2__1__1_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_2__1__1_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_2__1__1_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_2__1__1_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_2__1__1_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_2__1__1_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_2__1__1_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_2__1__1_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_2__1__1_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_2__1__1_left_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ) , .ccff_head ( cby_1__1__1_ccff_tail ) , - .right_width_0_height_0__pin_34_upper ( grid_clb_3_right_width_0_height_0__pin_34_upper ) , - .right_width_0_height_0__pin_34_lower ( grid_clb_3_right_width_0_height_0__pin_34_lower ) , - .right_width_0_height_0__pin_35_upper ( grid_clb_3_right_width_0_height_0__pin_35_upper ) , - .right_width_0_height_0__pin_35_lower ( grid_clb_3_right_width_0_height_0__pin_35_lower ) , - .right_width_0_height_0__pin_36_upper ( grid_clb_3_right_width_0_height_0__pin_36_upper ) , - .right_width_0_height_0__pin_36_lower ( grid_clb_3_right_width_0_height_0__pin_36_lower ) , - .right_width_0_height_0__pin_37_upper ( grid_clb_3_right_width_0_height_0__pin_37_upper ) , - .right_width_0_height_0__pin_37_lower ( grid_clb_3_right_width_0_height_0__pin_37_lower ) , - .right_width_0_height_0__pin_38_upper ( grid_clb_3_right_width_0_height_0__pin_38_upper ) , - .right_width_0_height_0__pin_38_lower ( grid_clb_3_right_width_0_height_0__pin_38_lower ) , - .right_width_0_height_0__pin_39_upper ( grid_clb_3_right_width_0_height_0__pin_39_upper ) , - .right_width_0_height_0__pin_39_lower ( grid_clb_3_right_width_0_height_0__pin_39_lower ) , - .right_width_0_height_0__pin_40_upper ( grid_clb_3_right_width_0_height_0__pin_40_upper ) , - .right_width_0_height_0__pin_40_lower ( grid_clb_3_right_width_0_height_0__pin_40_lower ) , - .right_width_0_height_0__pin_41_upper ( grid_clb_3_right_width_0_height_0__pin_41_upper ) , - .right_width_0_height_0__pin_41_lower ( grid_clb_3_right_width_0_height_0__pin_41_lower ) , - .bottom_width_0_height_0__pin_42_upper ( grid_clb_3_bottom_width_0_height_0__pin_42_upper ) , - .bottom_width_0_height_0__pin_42_lower ( grid_clb_3_bottom_width_0_height_0__pin_42_lower ) , - .bottom_width_0_height_0__pin_43_upper ( grid_clb_3_bottom_width_0_height_0__pin_43_upper ) , - .bottom_width_0_height_0__pin_43_lower ( grid_clb_3_bottom_width_0_height_0__pin_43_lower ) , - .bottom_width_0_height_0__pin_44_upper ( grid_clb_3_bottom_width_0_height_0__pin_44_upper ) , - .bottom_width_0_height_0__pin_44_lower ( grid_clb_3_bottom_width_0_height_0__pin_44_lower ) , - .bottom_width_0_height_0__pin_45_upper ( grid_clb_3_bottom_width_0_height_0__pin_45_upper ) , - .bottom_width_0_height_0__pin_45_lower ( grid_clb_3_bottom_width_0_height_0__pin_45_lower ) , - .bottom_width_0_height_0__pin_46_upper ( grid_clb_3_bottom_width_0_height_0__pin_46_upper ) , - .bottom_width_0_height_0__pin_46_lower ( grid_clb_3_bottom_width_0_height_0__pin_46_lower ) , - .bottom_width_0_height_0__pin_47_upper ( grid_clb_3_bottom_width_0_height_0__pin_47_upper ) , - .bottom_width_0_height_0__pin_47_lower ( grid_clb_3_bottom_width_0_height_0__pin_47_lower ) , - .bottom_width_0_height_0__pin_48_upper ( grid_clb_3_bottom_width_0_height_0__pin_48_upper ) , - .bottom_width_0_height_0__pin_48_lower ( grid_clb_3_bottom_width_0_height_0__pin_48_lower ) , - .bottom_width_0_height_0__pin_49_upper ( grid_clb_3_bottom_width_0_height_0__pin_49_upper ) , - .bottom_width_0_height_0__pin_49_lower ( grid_clb_3_bottom_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( grid_clb_3_bottom_width_0_height_0__pin_51_ ) , - .ccff_tail ( grid_clb_3_ccff_tail ) ) ; -grid_io_top grid_io_top_1__3_ ( - .prog_clk ( { ctsbuf_net_914 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[0] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[0] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[0] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[0] ) , - .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , - .ccff_head ( cbx_1__2__0_ccff_tail ) , - .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , - .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_top_0_ccff_tail ) ) ; -grid_io_top grid_io_top_2__3_ ( - .prog_clk ( { ctsbuf_net_38 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[1] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[1] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[1] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[1] ) , - .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , - .ccff_head ( cbx_1__2__1_ccff_tail ) , - .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , - .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_top_1_ccff_tail ) ) ; -grid_io_right grid_io_right_3__1_ ( - .prog_clk ( { ctsbuf_net_49 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[2] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[2] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[2] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[2] ) , - .left_width_0_height_0__pin_0_ ( cby_1__1__2_right_grid_pin_52_ ) , - .ccff_head ( cby_1__1__2_ccff_tail ) , - .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_right_0_ccff_tail ) ) ; -grid_io_right grid_io_right_3__2_ ( - .prog_clk ( { ctsbuf_net_16 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[3] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[3] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[3] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[3] ) , - .left_width_0_height_0__pin_0_ ( cby_1__1__3_right_grid_pin_52_ ) , - .ccff_head ( cby_1__1__3_ccff_tail ) , - .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_right_1_ccff_tail ) ) ; -grid_io_bottom grid_io_bottom_1__0_ ( - .prog_clk ( { ctsbuf_net_611 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[4] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[4] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[4] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[4] ) , - .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , - .ccff_head ( cbx_1__0__0_ccff_tail ) , - .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , - .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_bottom_0_ccff_tail ) ) ; -grid_io_bottom grid_io_bottom_2__0_ ( - .prog_clk ( { ctsbuf_net_27 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[5] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[5] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[5] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[5] ) , - .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , - .ccff_head ( cbx_1__0__1_ccff_tail ) , - .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , - .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_bottom_1_ccff_tail ) ) ; -grid_io_left grid_io_left_0__1_ ( - .prog_clk ( { ctsbuf_net_1520 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[6] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[6] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[6] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[6] ) , - .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , - .ccff_head ( cby_0__1__0_ccff_tail ) , - .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_left_0_ccff_tail ) ) ; -grid_io_left grid_io_left_0__2_ ( - .prog_clk ( { ctsbuf_net_1419 } ) , - .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[7] ) , - .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[7] ) , - .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[7] ) , - .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[7] ) , - .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , - .ccff_head ( cby_0__1__1_ccff_tail ) , - .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , - .ccff_tail ( grid_io_left_1_ccff_tail ) ) ; + .top_width_0_height_0__pin_34_upper ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , + .top_width_0_height_0__pin_34_lower ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , + .top_width_0_height_0__pin_35_upper ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , + .top_width_0_height_0__pin_35_lower ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , + .right_width_0_height_0__pin_42_upper ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , + .right_width_0_height_0__pin_42_lower ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , + .right_width_0_height_0__pin_43_upper ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , + .right_width_0_height_0__pin_43_lower ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( { sc_out_wires_1_ } ) , + .ccff_tail ( grid_clb_3_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7 ) , .SC_IN_BOT ( scff_Wires_10_ ) , + .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8 ) ) ; sb_0__0_ sb_0__0_ ( - .prog_clk ( { ctsbuf_net_1520 } ) , + .prog_clk ( { ctsbuf_net_1315 } ) , .chany_top_in ( cby_0__1__0_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , - .right_top_grid_pin_42_ ( grid_clb_0_bottom_width_0_height_0__pin_42_upper ) , - .right_top_grid_pin_43_ ( grid_clb_0_bottom_width_0_height_0__pin_43_upper ) , - .right_top_grid_pin_44_ ( grid_clb_0_bottom_width_0_height_0__pin_44_upper ) , - .right_top_grid_pin_45_ ( grid_clb_0_bottom_width_0_height_0__pin_45_upper ) , - .right_top_grid_pin_46_ ( grid_clb_0_bottom_width_0_height_0__pin_46_upper ) , - .right_top_grid_pin_47_ ( grid_clb_0_bottom_width_0_height_0__pin_47_upper ) , - .right_top_grid_pin_48_ ( grid_clb_0_bottom_width_0_height_0__pin_48_upper ) , - .right_top_grid_pin_49_ ( grid_clb_0_bottom_width_0_height_0__pin_49_upper ) , .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , .ccff_head ( grid_io_bottom_0_ccff_tail ) , .chany_top_out ( sb_0__0__0_chany_top_out ) , .chanx_right_out ( sb_0__0__0_chanx_right_out ) , .ccff_tail ( ccff_tail ) ) ; sb_0__1_ sb_0__1_ ( - .prog_clk ( { p_abuf0 } ) , + .prog_clk ( { ctsbuf_net_1315 } ) , .chany_top_in ( cby_0__1__1_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , - .right_top_grid_pin_42_ ( grid_clb_1_bottom_width_0_height_0__pin_42_upper ) , - .right_top_grid_pin_43_ ( grid_clb_1_bottom_width_0_height_0__pin_43_upper ) , - .right_top_grid_pin_44_ ( grid_clb_1_bottom_width_0_height_0__pin_44_upper ) , - .right_top_grid_pin_45_ ( grid_clb_1_bottom_width_0_height_0__pin_45_upper ) , - .right_top_grid_pin_46_ ( grid_clb_1_bottom_width_0_height_0__pin_46_upper ) , - .right_top_grid_pin_47_ ( grid_clb_1_bottom_width_0_height_0__pin_47_upper ) , - .right_top_grid_pin_48_ ( grid_clb_1_bottom_width_0_height_0__pin_48_upper ) , - .right_top_grid_pin_49_ ( grid_clb_1_bottom_width_0_height_0__pin_49_upper ) , + .right_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , + .right_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , .chany_bottom_in ( cby_0__1__0_chany_top_out ) , .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , .ccff_head ( cbx_1__1__0_ccff_tail ) , @@ -29182,89 +32888,95 @@ sb_0__1_ sb_0__1_ ( .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , .ccff_tail ( sb_0__1__0_ccff_tail ) ) ; sb_0__2_ sb_0__2_ ( - .prog_clk ( { ctsbuf_net_1419 } ) , + .prog_clk ( { ctsbuf_net_1012 } ) , .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , + .right_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , .chany_bottom_in ( cby_0__1__1_chany_top_out ) , .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , .ccff_head ( grid_io_top_0_ccff_tail ) , .chanx_right_out ( sb_0__2__0_chanx_right_out ) , .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , - .ccff_tail ( sb_0__2__0_ccff_tail ) ) ; + .ccff_tail ( sb_0__2__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_9 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_10 ) , .SC_OUT_BOT ( scff_Wires_0_ ) ) ; sb_1__0_ sb_1__0_ ( - .prog_clk ( { ctsbuf_net_813 } ) , + .prog_clk ( { ctsbuf_net_79 } ) , .chany_top_in ( cby_1__1__0_chany_bottom_out ) , - .top_left_grid_pin_34_ ( grid_clb_0_right_width_0_height_0__pin_34_lower ) , - .top_left_grid_pin_35_ ( grid_clb_0_right_width_0_height_0__pin_35_lower ) , - .top_left_grid_pin_36_ ( grid_clb_0_right_width_0_height_0__pin_36_lower ) , - .top_left_grid_pin_37_ ( grid_clb_0_right_width_0_height_0__pin_37_lower ) , - .top_left_grid_pin_38_ ( grid_clb_0_right_width_0_height_0__pin_38_lower ) , - .top_left_grid_pin_39_ ( grid_clb_0_right_width_0_height_0__pin_39_lower ) , - .top_left_grid_pin_40_ ( grid_clb_0_right_width_0_height_0__pin_40_lower ) , - .top_left_grid_pin_41_ ( grid_clb_0_right_width_0_height_0__pin_41_lower ) , + .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , + .top_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , + .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , - .right_top_grid_pin_42_ ( grid_clb_2_bottom_width_0_height_0__pin_42_upper ) , - .right_top_grid_pin_43_ ( grid_clb_2_bottom_width_0_height_0__pin_43_upper ) , - .right_top_grid_pin_44_ ( grid_clb_2_bottom_width_0_height_0__pin_44_upper ) , - .right_top_grid_pin_45_ ( grid_clb_2_bottom_width_0_height_0__pin_45_upper ) , - .right_top_grid_pin_46_ ( grid_clb_2_bottom_width_0_height_0__pin_46_upper ) , - .right_top_grid_pin_47_ ( grid_clb_2_bottom_width_0_height_0__pin_47_upper ) , - .right_top_grid_pin_48_ ( grid_clb_2_bottom_width_0_height_0__pin_48_upper ) , - .right_top_grid_pin_49_ ( grid_clb_2_bottom_width_0_height_0__pin_49_upper ) , .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , - .left_top_grid_pin_42_ ( grid_clb_0_bottom_width_0_height_0__pin_42_lower ) , - .left_top_grid_pin_43_ ( grid_clb_0_bottom_width_0_height_0__pin_43_lower ) , - .left_top_grid_pin_44_ ( grid_clb_0_bottom_width_0_height_0__pin_44_lower ) , - .left_top_grid_pin_45_ ( grid_clb_0_bottom_width_0_height_0__pin_45_lower ) , - .left_top_grid_pin_46_ ( grid_clb_0_bottom_width_0_height_0__pin_46_lower ) , - .left_top_grid_pin_47_ ( grid_clb_0_bottom_width_0_height_0__pin_47_lower ) , - .left_top_grid_pin_48_ ( grid_clb_0_bottom_width_0_height_0__pin_48_lower ) , - .left_top_grid_pin_49_ ( grid_clb_0_bottom_width_0_height_0__pin_49_lower ) , .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , .ccff_head ( grid_io_bottom_1_ccff_tail ) , .chany_top_out ( sb_1__0__0_chany_top_out ) , .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , - .ccff_tail ( sb_1__0__0_ccff_tail ) ) ; + .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_11 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_12 ) , .SC_OUT_BOT ( scff_Wires_7_ ) ) ; sb_1__1_ sb_1__1_ ( - .prog_clk ( { ctsbuf_net_1217 } ) , + .prog_clk ( { ctsbuf_net_1214 } ) , .chany_top_in ( cby_1__1__1_chany_bottom_out ) , - .top_left_grid_pin_34_ ( grid_clb_1_right_width_0_height_0__pin_34_lower ) , - .top_left_grid_pin_35_ ( grid_clb_1_right_width_0_height_0__pin_35_lower ) , - .top_left_grid_pin_36_ ( grid_clb_1_right_width_0_height_0__pin_36_lower ) , - .top_left_grid_pin_37_ ( grid_clb_1_right_width_0_height_0__pin_37_lower ) , - .top_left_grid_pin_38_ ( grid_clb_1_right_width_0_height_0__pin_38_lower ) , - .top_left_grid_pin_39_ ( grid_clb_1_right_width_0_height_0__pin_39_lower ) , - .top_left_grid_pin_40_ ( grid_clb_1_right_width_0_height_0__pin_40_lower ) , - .top_left_grid_pin_41_ ( grid_clb_1_right_width_0_height_0__pin_41_lower ) , + .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , + .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , + .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , - .right_top_grid_pin_42_ ( grid_clb_3_bottom_width_0_height_0__pin_42_upper ) , - .right_top_grid_pin_43_ ( grid_clb_3_bottom_width_0_height_0__pin_43_upper ) , - .right_top_grid_pin_44_ ( grid_clb_3_bottom_width_0_height_0__pin_44_upper ) , - .right_top_grid_pin_45_ ( grid_clb_3_bottom_width_0_height_0__pin_45_upper ) , - .right_top_grid_pin_46_ ( grid_clb_3_bottom_width_0_height_0__pin_46_upper ) , - .right_top_grid_pin_47_ ( grid_clb_3_bottom_width_0_height_0__pin_47_upper ) , - .right_top_grid_pin_48_ ( grid_clb_3_bottom_width_0_height_0__pin_48_upper ) , - .right_top_grid_pin_49_ ( grid_clb_3_bottom_width_0_height_0__pin_49_upper ) , + .right_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , + .right_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , .chany_bottom_in ( cby_1__1__0_chany_top_out ) , - .bottom_left_grid_pin_34_ ( grid_clb_0_right_width_0_height_0__pin_34_upper ) , - .bottom_left_grid_pin_35_ ( grid_clb_0_right_width_0_height_0__pin_35_upper ) , - .bottom_left_grid_pin_36_ ( grid_clb_0_right_width_0_height_0__pin_36_upper ) , - .bottom_left_grid_pin_37_ ( grid_clb_0_right_width_0_height_0__pin_37_upper ) , - .bottom_left_grid_pin_38_ ( grid_clb_0_right_width_0_height_0__pin_38_upper ) , - .bottom_left_grid_pin_39_ ( grid_clb_0_right_width_0_height_0__pin_39_upper ) , - .bottom_left_grid_pin_40_ ( grid_clb_0_right_width_0_height_0__pin_40_upper ) , - .bottom_left_grid_pin_41_ ( grid_clb_0_right_width_0_height_0__pin_41_upper ) , + .bottom_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , + .bottom_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , - .left_top_grid_pin_42_ ( grid_clb_1_bottom_width_0_height_0__pin_42_lower ) , - .left_top_grid_pin_43_ ( grid_clb_1_bottom_width_0_height_0__pin_43_lower ) , - .left_top_grid_pin_44_ ( grid_clb_1_bottom_width_0_height_0__pin_44_lower ) , - .left_top_grid_pin_45_ ( grid_clb_1_bottom_width_0_height_0__pin_45_lower ) , - .left_top_grid_pin_46_ ( grid_clb_1_bottom_width_0_height_0__pin_46_lower ) , - .left_top_grid_pin_47_ ( grid_clb_1_bottom_width_0_height_0__pin_47_lower ) , - .left_top_grid_pin_48_ ( grid_clb_1_bottom_width_0_height_0__pin_48_lower ) , - .left_top_grid_pin_49_ ( grid_clb_1_bottom_width_0_height_0__pin_49_lower ) , + .left_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , + .left_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , .ccff_head ( cbx_1__1__1_ccff_tail ) , .chany_top_out ( sb_1__1__0_chany_top_out ) , .chanx_right_out ( sb_1__1__0_chanx_right_out ) , @@ -29272,341 +32984,466 @@ sb_1__1_ sb_1__1_ ( .chanx_left_out ( sb_1__1__0_chanx_left_out ) , .ccff_tail ( sb_1__1__0_ccff_tail ) ) ; sb_1__2_ sb_1__2_ ( - .prog_clk ( { ctsbuf_net_712 } ) , + .prog_clk ( { ctsbuf_net_810 } ) , .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , + .right_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , .chany_bottom_in ( cby_1__1__1_chany_top_out ) , - .bottom_left_grid_pin_34_ ( grid_clb_1_right_width_0_height_0__pin_34_upper ) , - .bottom_left_grid_pin_35_ ( grid_clb_1_right_width_0_height_0__pin_35_upper ) , - .bottom_left_grid_pin_36_ ( grid_clb_1_right_width_0_height_0__pin_36_upper ) , - .bottom_left_grid_pin_37_ ( grid_clb_1_right_width_0_height_0__pin_37_upper ) , - .bottom_left_grid_pin_38_ ( grid_clb_1_right_width_0_height_0__pin_38_upper ) , - .bottom_left_grid_pin_39_ ( grid_clb_1_right_width_0_height_0__pin_39_upper ) , - .bottom_left_grid_pin_40_ ( grid_clb_1_right_width_0_height_0__pin_40_upper ) , - .bottom_left_grid_pin_41_ ( grid_clb_1_right_width_0_height_0__pin_41_upper ) , + .bottom_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , + .bottom_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , .chanx_left_in ( cbx_1__2__0_chanx_right_out ) , - .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .ccff_head ( { ropt_net_29 } ) , + .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , + .left_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , + .ccff_head ( grid_io_top_1_ccff_tail ) , .chanx_right_out ( sb_1__2__0_chanx_right_out ) , .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , .chanx_left_out ( sb_1__2__0_chanx_left_out ) , - .ccff_tail ( sb_1__2__0_ccff_tail ) ) ; + .ccff_tail ( sb_1__2__0_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_13 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_14 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_15 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_16 ) ) ; sb_2__0_ sb_2__0_ ( - .prog_clk ( { ctsbuf_net_27 } ) , - .chany_top_in ( cby_1__1__2_chany_bottom_out ) , - .top_left_grid_pin_34_ ( grid_clb_2_right_width_0_height_0__pin_34_lower ) , - .top_left_grid_pin_35_ ( grid_clb_2_right_width_0_height_0__pin_35_lower ) , - .top_left_grid_pin_36_ ( grid_clb_2_right_width_0_height_0__pin_36_lower ) , - .top_left_grid_pin_37_ ( grid_clb_2_right_width_0_height_0__pin_37_lower ) , - .top_left_grid_pin_38_ ( grid_clb_2_right_width_0_height_0__pin_38_lower ) , - .top_left_grid_pin_39_ ( grid_clb_2_right_width_0_height_0__pin_39_lower ) , - .top_left_grid_pin_40_ ( grid_clb_2_right_width_0_height_0__pin_40_lower ) , - .top_left_grid_pin_41_ ( grid_clb_2_right_width_0_height_0__pin_41_lower ) , + .prog_clk ( { ctsbuf_net_13 } ) , + .chany_top_in ( cby_2__1__0_chany_bottom_out ) , + .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , + .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , + .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , - .left_top_grid_pin_42_ ( grid_clb_2_bottom_width_0_height_0__pin_42_lower ) , - .left_top_grid_pin_43_ ( grid_clb_2_bottom_width_0_height_0__pin_43_lower ) , - .left_top_grid_pin_44_ ( grid_clb_2_bottom_width_0_height_0__pin_44_lower ) , - .left_top_grid_pin_45_ ( grid_clb_2_bottom_width_0_height_0__pin_45_lower ) , - .left_top_grid_pin_46_ ( grid_clb_2_bottom_width_0_height_0__pin_46_lower ) , - .left_top_grid_pin_47_ ( grid_clb_2_bottom_width_0_height_0__pin_47_lower ) , - .left_top_grid_pin_48_ ( grid_clb_2_bottom_width_0_height_0__pin_48_lower ) , - .left_top_grid_pin_49_ ( grid_clb_2_bottom_width_0_height_0__pin_49_lower ) , .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , .ccff_head ( grid_io_right_0_ccff_tail ) , .chany_top_out ( sb_2__0__0_chany_top_out ) , .chanx_left_out ( sb_2__0__0_chanx_left_out ) , .ccff_tail ( sb_2__0__0_ccff_tail ) ) ; sb_2__1_ sb_2__1_ ( - .prog_clk ( { ctsbuf_net_49 } ) , - .chany_top_in ( cby_1__1__3_chany_bottom_out ) , - .top_left_grid_pin_34_ ( grid_clb_3_right_width_0_height_0__pin_34_lower ) , - .top_left_grid_pin_35_ ( grid_clb_3_right_width_0_height_0__pin_35_lower ) , - .top_left_grid_pin_36_ ( grid_clb_3_right_width_0_height_0__pin_36_lower ) , - .top_left_grid_pin_37_ ( grid_clb_3_right_width_0_height_0__pin_37_lower ) , - .top_left_grid_pin_38_ ( grid_clb_3_right_width_0_height_0__pin_38_lower ) , - .top_left_grid_pin_39_ ( grid_clb_3_right_width_0_height_0__pin_39_lower ) , - .top_left_grid_pin_40_ ( grid_clb_3_right_width_0_height_0__pin_40_lower ) , - .top_left_grid_pin_41_ ( grid_clb_3_right_width_0_height_0__pin_41_lower ) , + .prog_clk ( { ctsbuf_net_68 } ) , + .chany_top_in ( cby_2__1__1_chany_bottom_out ) , + .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , + .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , + .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .chany_bottom_in ( cby_1__1__2_chany_top_out ) , + .chany_bottom_in ( cby_2__1__0_chany_top_out ) , .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .bottom_left_grid_pin_34_ ( grid_clb_2_right_width_0_height_0__pin_34_upper ) , - .bottom_left_grid_pin_35_ ( grid_clb_2_right_width_0_height_0__pin_35_upper ) , - .bottom_left_grid_pin_36_ ( grid_clb_2_right_width_0_height_0__pin_36_upper ) , - .bottom_left_grid_pin_37_ ( grid_clb_2_right_width_0_height_0__pin_37_upper ) , - .bottom_left_grid_pin_38_ ( grid_clb_2_right_width_0_height_0__pin_38_upper ) , - .bottom_left_grid_pin_39_ ( grid_clb_2_right_width_0_height_0__pin_39_upper ) , - .bottom_left_grid_pin_40_ ( grid_clb_2_right_width_0_height_0__pin_40_upper ) , - .bottom_left_grid_pin_41_ ( grid_clb_2_right_width_0_height_0__pin_41_upper ) , + .bottom_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , + .bottom_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , - .left_top_grid_pin_42_ ( grid_clb_3_bottom_width_0_height_0__pin_42_lower ) , - .left_top_grid_pin_43_ ( grid_clb_3_bottom_width_0_height_0__pin_43_lower ) , - .left_top_grid_pin_44_ ( grid_clb_3_bottom_width_0_height_0__pin_44_lower ) , - .left_top_grid_pin_45_ ( grid_clb_3_bottom_width_0_height_0__pin_45_lower ) , - .left_top_grid_pin_46_ ( grid_clb_3_bottom_width_0_height_0__pin_46_lower ) , - .left_top_grid_pin_47_ ( grid_clb_3_bottom_width_0_height_0__pin_47_lower ) , - .left_top_grid_pin_48_ ( grid_clb_3_bottom_width_0_height_0__pin_48_lower ) , - .left_top_grid_pin_49_ ( grid_clb_3_bottom_width_0_height_0__pin_49_lower ) , + .left_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , + .left_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , .ccff_head ( grid_io_right_1_ccff_tail ) , .chany_top_out ( sb_2__1__0_chany_top_out ) , .chany_bottom_out ( sb_2__1__0_chany_bottom_out ) , .chanx_left_out ( sb_2__1__0_chanx_left_out ) , .ccff_tail ( sb_2__1__0_ccff_tail ) ) ; sb_2__2_ sb_2__2_ ( - .prog_clk ( { ctsbuf_net_16 } ) , - .chany_bottom_in ( cby_1__1__3_chany_top_out ) , + .prog_clk ( { ctsbuf_net_24 } ) , + .chany_bottom_in ( cby_2__1__1_chany_top_out ) , .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .bottom_left_grid_pin_34_ ( grid_clb_3_right_width_0_height_0__pin_34_upper ) , - .bottom_left_grid_pin_35_ ( grid_clb_3_right_width_0_height_0__pin_35_upper ) , - .bottom_left_grid_pin_36_ ( grid_clb_3_right_width_0_height_0__pin_36_upper ) , - .bottom_left_grid_pin_37_ ( grid_clb_3_right_width_0_height_0__pin_37_upper ) , - .bottom_left_grid_pin_38_ ( grid_clb_3_right_width_0_height_0__pin_38_upper ) , - .bottom_left_grid_pin_39_ ( grid_clb_3_right_width_0_height_0__pin_39_upper ) , - .bottom_left_grid_pin_40_ ( grid_clb_3_right_width_0_height_0__pin_40_upper ) , - .bottom_left_grid_pin_41_ ( grid_clb_3_right_width_0_height_0__pin_41_upper ) , + .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , + .bottom_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , .chanx_left_in ( cbx_1__2__1_chanx_right_out ) , .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , + .left_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , .ccff_head ( ccff_head ) , .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , .chanx_left_out ( sb_2__2__0_chanx_left_out ) , - .ccff_tail ( sb_2__2__0_ccff_tail ) ) ; + .ccff_tail ( sb_2__2__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_17 ) , .SC_OUT_TOP ( sc_tail ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_18 ) ) ; cbx_1__0_ cbx_1__0_ ( - .prog_clk ( { ctsbuf_net_611 } ) , + .prog_clk ( { ctsbuf_net_79 } ) , .chanx_left_in ( sb_0__0__0_chanx_right_out ) , .chanx_right_in ( sb_1__0__0_chanx_left_out ) , .ccff_head ( sb_1__0__0_ccff_tail ) , .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , - .top_grid_pin_16_ ( cbx_1__0__0_top_grid_pin_16_ ) , - .top_grid_pin_17_ ( cbx_1__0__0_top_grid_pin_17_ ) , - .top_grid_pin_18_ ( cbx_1__0__0_top_grid_pin_18_ ) , - .top_grid_pin_19_ ( cbx_1__0__0_top_grid_pin_19_ ) , - .top_grid_pin_20_ ( cbx_1__0__0_top_grid_pin_20_ ) , - .top_grid_pin_21_ ( cbx_1__0__0_top_grid_pin_21_ ) , - .top_grid_pin_22_ ( cbx_1__0__0_top_grid_pin_22_ ) , - .top_grid_pin_23_ ( cbx_1__0__0_top_grid_pin_23_ ) , - .top_grid_pin_24_ ( cbx_1__0__0_top_grid_pin_24_ ) , - .top_grid_pin_25_ ( cbx_1__0__0_top_grid_pin_25_ ) , - .top_grid_pin_26_ ( cbx_1__0__0_top_grid_pin_26_ ) , - .top_grid_pin_27_ ( cbx_1__0__0_top_grid_pin_27_ ) , - .top_grid_pin_28_ ( cbx_1__0__0_top_grid_pin_28_ ) , - .top_grid_pin_29_ ( cbx_1__0__0_top_grid_pin_29_ ) , - .top_grid_pin_30_ ( cbx_1__0__0_top_grid_pin_30_ ) , - .top_grid_pin_31_ ( cbx_1__0__0_top_grid_pin_31_ ) , .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , - .ccff_tail ( cbx_1__0__0_ccff_tail ) ) ; + .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , + .ccff_tail ( grid_io_bottom_0_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4:9] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4:9] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4:9] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , + .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_19 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_20 ) , .SC_OUT_BOT ( scff_Wires_6_ ) ) ; cbx_1__0_ cbx_2__0_ ( - .prog_clk ( { ctsbuf_net_27 } ) , + .prog_clk ( { ctsbuf_net_35 } ) , .chanx_left_in ( sb_1__0__0_chanx_right_out ) , .chanx_right_in ( sb_2__0__0_chanx_left_out ) , .ccff_head ( sb_2__0__0_ccff_tail ) , .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , - .top_grid_pin_16_ ( cbx_1__0__1_top_grid_pin_16_ ) , - .top_grid_pin_17_ ( cbx_1__0__1_top_grid_pin_17_ ) , - .top_grid_pin_18_ ( cbx_1__0__1_top_grid_pin_18_ ) , - .top_grid_pin_19_ ( cbx_1__0__1_top_grid_pin_19_ ) , - .top_grid_pin_20_ ( cbx_1__0__1_top_grid_pin_20_ ) , - .top_grid_pin_21_ ( cbx_1__0__1_top_grid_pin_21_ ) , - .top_grid_pin_22_ ( cbx_1__0__1_top_grid_pin_22_ ) , - .top_grid_pin_23_ ( cbx_1__0__1_top_grid_pin_23_ ) , - .top_grid_pin_24_ ( cbx_1__0__1_top_grid_pin_24_ ) , - .top_grid_pin_25_ ( cbx_1__0__1_top_grid_pin_25_ ) , - .top_grid_pin_26_ ( cbx_1__0__1_top_grid_pin_26_ ) , - .top_grid_pin_27_ ( cbx_1__0__1_top_grid_pin_27_ ) , - .top_grid_pin_28_ ( cbx_1__0__1_top_grid_pin_28_ ) , - .top_grid_pin_29_ ( cbx_1__0__1_top_grid_pin_29_ ) , - .top_grid_pin_30_ ( cbx_1__0__1_top_grid_pin_30_ ) , - .top_grid_pin_31_ ( cbx_1__0__1_top_grid_pin_31_ ) , .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , - .ccff_tail ( cbx_1__0__1_ccff_tail ) ) ; + .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , + .ccff_tail ( grid_io_bottom_1_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[10:15] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[10:15] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[10:15] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , + .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_21 ) , + .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_22 ) ) ; cbx_1__1_ cbx_1__1_ ( - .prog_clk ( { ctsbuf_net_1621 } ) , + .prog_clk ( { ctsbuf_net_1416 } ) , .chanx_left_in ( sb_0__1__0_chanx_right_out ) , .chanx_right_in ( sb_1__1__0_chanx_left_out ) , .ccff_head ( sb_1__1__0_ccff_tail ) , .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , - .top_grid_pin_16_ ( cbx_1__1__0_top_grid_pin_16_ ) , - .top_grid_pin_17_ ( cbx_1__1__0_top_grid_pin_17_ ) , - .top_grid_pin_18_ ( cbx_1__1__0_top_grid_pin_18_ ) , - .top_grid_pin_19_ ( cbx_1__1__0_top_grid_pin_19_ ) , - .top_grid_pin_20_ ( cbx_1__1__0_top_grid_pin_20_ ) , - .top_grid_pin_21_ ( cbx_1__1__0_top_grid_pin_21_ ) , - .top_grid_pin_22_ ( cbx_1__1__0_top_grid_pin_22_ ) , - .top_grid_pin_23_ ( cbx_1__1__0_top_grid_pin_23_ ) , - .top_grid_pin_24_ ( cbx_1__1__0_top_grid_pin_24_ ) , - .top_grid_pin_25_ ( cbx_1__1__0_top_grid_pin_25_ ) , - .top_grid_pin_26_ ( cbx_1__1__0_top_grid_pin_26_ ) , - .top_grid_pin_27_ ( cbx_1__1__0_top_grid_pin_27_ ) , - .top_grid_pin_28_ ( cbx_1__1__0_top_grid_pin_28_ ) , - .top_grid_pin_29_ ( cbx_1__1__0_top_grid_pin_29_ ) , - .top_grid_pin_30_ ( cbx_1__1__0_top_grid_pin_30_ ) , - .top_grid_pin_31_ ( cbx_1__1__0_top_grid_pin_31_ ) , - .ccff_tail ( cbx_1__1__0_ccff_tail ) ) ; + .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__0_ccff_tail ) , .CLB_SC_IN ( sc_out_wires_0_ ) , + .CLB_SC_OUT ( sc_in_wires_0_ ) , .SC_IN_TOP ( scff_Wires_2_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_23 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_24 ) , .SC_OUT_BOT ( scff_Wires_3_ ) ) ; cbx_1__1_ cbx_2__1_ ( - .prog_clk ( { ctsbuf_net_1015 } ) , + .prog_clk ( { ctsbuf_net_68 } ) , .chanx_left_in ( sb_1__1__0_chanx_right_out ) , .chanx_right_in ( sb_2__1__0_chanx_left_out ) , .ccff_head ( sb_2__1__0_ccff_tail ) , .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , - .top_grid_pin_16_ ( cbx_1__1__1_top_grid_pin_16_ ) , - .top_grid_pin_17_ ( cbx_1__1__1_top_grid_pin_17_ ) , - .top_grid_pin_18_ ( cbx_1__1__1_top_grid_pin_18_ ) , - .top_grid_pin_19_ ( cbx_1__1__1_top_grid_pin_19_ ) , - .top_grid_pin_20_ ( cbx_1__1__1_top_grid_pin_20_ ) , - .top_grid_pin_21_ ( cbx_1__1__1_top_grid_pin_21_ ) , - .top_grid_pin_22_ ( cbx_1__1__1_top_grid_pin_22_ ) , - .top_grid_pin_23_ ( cbx_1__1__1_top_grid_pin_23_ ) , - .top_grid_pin_24_ ( cbx_1__1__1_top_grid_pin_24_ ) , - .top_grid_pin_25_ ( cbx_1__1__1_top_grid_pin_25_ ) , - .top_grid_pin_26_ ( cbx_1__1__1_top_grid_pin_26_ ) , - .top_grid_pin_27_ ( cbx_1__1__1_top_grid_pin_27_ ) , - .top_grid_pin_28_ ( cbx_1__1__1_top_grid_pin_28_ ) , - .top_grid_pin_29_ ( cbx_1__1__1_top_grid_pin_29_ ) , - .top_grid_pin_30_ ( cbx_1__1__1_top_grid_pin_30_ ) , - .top_grid_pin_31_ ( cbx_1__1__1_top_grid_pin_31_ ) , - .ccff_tail ( cbx_1__1__1_ccff_tail ) ) ; + .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__1_ccff_tail ) , .CLB_SC_IN ( sc_out_wires_1_ ) , + .CLB_SC_OUT ( sc_in_wires_1_ ) , .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_25 ) , + .SC_IN_BOT ( scff_Wires_9_ ) , .SC_OUT_TOP ( scff_Wires_10_ ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_26 ) ) ; cbx_1__2_ cbx_1__2_ ( - .prog_clk ( { ctsbuf_net_914 } ) , + .prog_clk ( { ctsbuf_net_1012 } ) , .chanx_left_in ( sb_0__2__0_chanx_right_out ) , .chanx_right_in ( sb_1__2__0_chanx_left_out ) , .ccff_head ( sb_1__2__0_ccff_tail ) , .chanx_left_out ( cbx_1__2__0_chanx_left_out ) , .chanx_right_out ( cbx_1__2__0_chanx_right_out ) , .top_grid_pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , - .ccff_tail ( cbx_1__2__0_ccff_tail ) ) ; + .bottom_grid_pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__2__0_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__2__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__2__0_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__2__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__2__0_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__2__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__2__0_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__2__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__2__0_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__2__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_0_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_27 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_28 ) , .SC_OUT_BOT ( scff_Wires_1_ ) ) ; cbx_1__2_ cbx_2__2_ ( - .prog_clk ( { ctsbuf_net_16 } ) , + .prog_clk ( { ctsbuf_net_24 } ) , .chanx_left_in ( sb_1__2__0_chanx_right_out ) , .chanx_right_in ( sb_2__2__0_chanx_left_out ) , .ccff_head ( sb_2__2__0_ccff_tail ) , .chanx_left_out ( cbx_1__2__1_chanx_left_out ) , .chanx_right_out ( cbx_1__2__1_chanx_right_out ) , .top_grid_pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , - .ccff_tail ( cbx_1__2__1_ccff_tail ) ) ; + .bottom_grid_pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__2__1_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__2__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__2__1_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__2__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__2__1_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__2__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__2__1_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__2__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__2__1_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__2__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_1_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_29 ) , .SC_IN_BOT ( scff_Wires_11_ ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_30 ) , .SC_OUT_BOT ( scff_Wires_12_ ) ) ; cby_0__1_ cby_0__1_ ( - .prog_clk ( { ctsbuf_net_1520 } ) , + .prog_clk ( { ctsbuf_net_1315 } ) , .chany_bottom_in ( sb_0__0__0_chany_top_out ) , .chany_top_in ( sb_0__1__0_chany_bottom_out ) , .ccff_head ( sb_0__1__0_ccff_tail ) , .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , .chany_top_out ( cby_0__1__0_chany_top_out ) , - .right_grid_pin_52_ ( cby_0__1__0_right_grid_pin_52_ ) , .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , - .ccff_tail ( cby_0__1__0_ccff_tail ) ) ; + .ccff_tail ( grid_io_left_0_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[16] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[16] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[16] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ) ; cby_0__1_ cby_0__2_ ( - .prog_clk ( { ctsbuf_net_1419 } ) , + .prog_clk ( { ctsbuf_net_1315 } ) , .chany_bottom_in ( sb_0__1__0_chany_top_out ) , .chany_top_in ( sb_0__2__0_chany_bottom_out ) , .ccff_head ( sb_0__2__0_ccff_tail ) , .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , .chany_top_out ( cby_0__1__1_chany_top_out ) , - .right_grid_pin_52_ ( cby_0__1__1_right_grid_pin_52_ ) , .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , - .ccff_tail ( cby_0__1__1_ccff_tail ) ) ; + .ccff_tail ( grid_io_left_1_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[17] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[17] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[17] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ) ; cby_1__1_ cby_1__1_ ( - .prog_clk ( { ctsbuf_net_1217 } ) , + .prog_clk ( { ctsbuf_net_79 } ) , .chany_bottom_in ( sb_1__0__0_chany_top_out ) , .chany_top_in ( sb_1__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_0_ccff_tail ) , .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , .chany_top_out ( cby_1__1__0_chany_top_out ) , - .right_grid_pin_52_ ( cby_1__1__0_right_grid_pin_52_ ) , - .left_grid_pin_0_ ( cby_1__1__0_left_grid_pin_0_ ) , - .left_grid_pin_1_ ( cby_1__1__0_left_grid_pin_1_ ) , - .left_grid_pin_2_ ( cby_1__1__0_left_grid_pin_2_ ) , - .left_grid_pin_3_ ( cby_1__1__0_left_grid_pin_3_ ) , - .left_grid_pin_4_ ( cby_1__1__0_left_grid_pin_4_ ) , - .left_grid_pin_5_ ( cby_1__1__0_left_grid_pin_5_ ) , - .left_grid_pin_6_ ( cby_1__1__0_left_grid_pin_6_ ) , - .left_grid_pin_7_ ( cby_1__1__0_left_grid_pin_7_ ) , - .left_grid_pin_8_ ( cby_1__1__0_left_grid_pin_8_ ) , - .left_grid_pin_9_ ( cby_1__1__0_left_grid_pin_9_ ) , - .left_grid_pin_10_ ( cby_1__1__0_left_grid_pin_10_ ) , - .left_grid_pin_11_ ( cby_1__1__0_left_grid_pin_11_ ) , - .left_grid_pin_12_ ( cby_1__1__0_left_grid_pin_12_ ) , - .left_grid_pin_13_ ( cby_1__1__0_left_grid_pin_13_ ) , - .left_grid_pin_14_ ( cby_1__1__0_left_grid_pin_14_ ) , - .left_grid_pin_15_ ( cby_1__1__0_left_grid_pin_15_ ) , + .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__0_ccff_tail ) ) ; cby_1__1_ cby_1__2_ ( - .prog_clk ( { ctsbuf_net_712 } ) , + .prog_clk ( { ctsbuf_net_810 } ) , .chany_bottom_in ( sb_1__1__0_chany_top_out ) , .chany_top_in ( sb_1__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_1_ccff_tail ) , .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , .chany_top_out ( cby_1__1__1_chany_top_out ) , - .right_grid_pin_52_ ( cby_1__1__1_right_grid_pin_52_ ) , - .left_grid_pin_0_ ( cby_1__1__1_left_grid_pin_0_ ) , - .left_grid_pin_1_ ( cby_1__1__1_left_grid_pin_1_ ) , - .left_grid_pin_2_ ( cby_1__1__1_left_grid_pin_2_ ) , - .left_grid_pin_3_ ( cby_1__1__1_left_grid_pin_3_ ) , - .left_grid_pin_4_ ( cby_1__1__1_left_grid_pin_4_ ) , - .left_grid_pin_5_ ( cby_1__1__1_left_grid_pin_5_ ) , - .left_grid_pin_6_ ( cby_1__1__1_left_grid_pin_6_ ) , - .left_grid_pin_7_ ( cby_1__1__1_left_grid_pin_7_ ) , - .left_grid_pin_8_ ( cby_1__1__1_left_grid_pin_8_ ) , - .left_grid_pin_9_ ( cby_1__1__1_left_grid_pin_9_ ) , - .left_grid_pin_10_ ( cby_1__1__1_left_grid_pin_10_ ) , - .left_grid_pin_11_ ( cby_1__1__1_left_grid_pin_11_ ) , - .left_grid_pin_12_ ( cby_1__1__1_left_grid_pin_12_ ) , - .left_grid_pin_13_ ( cby_1__1__1_left_grid_pin_13_ ) , - .left_grid_pin_14_ ( cby_1__1__1_left_grid_pin_14_ ) , - .left_grid_pin_15_ ( cby_1__1__1_left_grid_pin_15_ ) , + .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__1_ccff_tail ) ) ; -cby_1__1_ cby_2__1_ ( - .prog_clk ( { ctsbuf_net_49 } ) , +cby_2__1_ cby_2__1_ ( + .prog_clk ( { ctsbuf_net_13 } ) , .chany_bottom_in ( sb_2__0__0_chany_top_out ) , .chany_top_in ( sb_2__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_2_ccff_tail ) , - .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) , - .chany_top_out ( cby_1__1__2_chany_top_out ) , - .right_grid_pin_52_ ( cby_1__1__2_right_grid_pin_52_ ) , - .left_grid_pin_0_ ( cby_1__1__2_left_grid_pin_0_ ) , - .left_grid_pin_1_ ( cby_1__1__2_left_grid_pin_1_ ) , - .left_grid_pin_2_ ( cby_1__1__2_left_grid_pin_2_ ) , - .left_grid_pin_3_ ( cby_1__1__2_left_grid_pin_3_ ) , - .left_grid_pin_4_ ( cby_1__1__2_left_grid_pin_4_ ) , - .left_grid_pin_5_ ( cby_1__1__2_left_grid_pin_5_ ) , - .left_grid_pin_6_ ( cby_1__1__2_left_grid_pin_6_ ) , - .left_grid_pin_7_ ( cby_1__1__2_left_grid_pin_7_ ) , - .left_grid_pin_8_ ( cby_1__1__2_left_grid_pin_8_ ) , - .left_grid_pin_9_ ( cby_1__1__2_left_grid_pin_9_ ) , - .left_grid_pin_10_ ( cby_1__1__2_left_grid_pin_10_ ) , - .left_grid_pin_11_ ( cby_1__1__2_left_grid_pin_11_ ) , - .left_grid_pin_12_ ( cby_1__1__2_left_grid_pin_12_ ) , - .left_grid_pin_13_ ( cby_1__1__2_left_grid_pin_13_ ) , - .left_grid_pin_14_ ( cby_1__1__2_left_grid_pin_14_ ) , - .left_grid_pin_15_ ( cby_1__1__2_left_grid_pin_15_ ) , - .ccff_tail ( cby_1__1__2_ccff_tail ) ) ; -cby_1__1_ cby_2__2_ ( - .prog_clk ( { ctsbuf_net_16 } ) , + .chany_bottom_out ( cby_2__1__0_chany_bottom_out ) , + .chany_top_out ( cby_2__1__0_chany_top_out ) , + .right_grid_pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_2__1__0_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_2__1__0_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_2__1__0_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_2__1__0_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_2__1__0_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_2__1__0_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_2__1__0_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_2__1__0_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_2__1__0_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_2__1__0_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_2__1__0_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_2__1__0_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_2__1__0_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_0_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .left_width_0_height_0__pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ) ; +cby_2__1_ cby_2__2_ ( + .prog_clk ( { ctsbuf_net_46 } ) , .chany_bottom_in ( sb_2__1__0_chany_top_out ) , .chany_top_in ( sb_2__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_3_ccff_tail ) , - .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) , - .chany_top_out ( cby_1__1__3_chany_top_out ) , - .right_grid_pin_52_ ( cby_1__1__3_right_grid_pin_52_ ) , - .left_grid_pin_0_ ( cby_1__1__3_left_grid_pin_0_ ) , - .left_grid_pin_1_ ( cby_1__1__3_left_grid_pin_1_ ) , - .left_grid_pin_2_ ( cby_1__1__3_left_grid_pin_2_ ) , - .left_grid_pin_3_ ( cby_1__1__3_left_grid_pin_3_ ) , - .left_grid_pin_4_ ( cby_1__1__3_left_grid_pin_4_ ) , - .left_grid_pin_5_ ( cby_1__1__3_left_grid_pin_5_ ) , - .left_grid_pin_6_ ( cby_1__1__3_left_grid_pin_6_ ) , - .left_grid_pin_7_ ( cby_1__1__3_left_grid_pin_7_ ) , - .left_grid_pin_8_ ( cby_1__1__3_left_grid_pin_8_ ) , - .left_grid_pin_9_ ( cby_1__1__3_left_grid_pin_9_ ) , - .left_grid_pin_10_ ( cby_1__1__3_left_grid_pin_10_ ) , - .left_grid_pin_11_ ( cby_1__1__3_left_grid_pin_11_ ) , - .left_grid_pin_12_ ( cby_1__1__3_left_grid_pin_12_ ) , - .left_grid_pin_13_ ( cby_1__1__3_left_grid_pin_13_ ) , - .left_grid_pin_14_ ( cby_1__1__3_left_grid_pin_14_ ) , - .left_grid_pin_15_ ( cby_1__1__3_left_grid_pin_15_ ) , - .ccff_tail ( cby_1__1__3_ccff_tail ) ) ; + .chany_bottom_out ( cby_2__1__1_chany_bottom_out ) , + .chany_top_out ( cby_2__1__1_chany_top_out ) , + .right_grid_pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_2__1__1_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_2__1__1_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_2__1__1_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_2__1__1_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_2__1__1_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_2__1__1_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_2__1__1_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_2__1__1_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_2__1__1_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_2__1__1_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_2__1__1_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_2__1__1_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_2__1__1_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_1_ccff_tail ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .left_width_0_height_0__pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ) ; direct_interc_0 direct_interc_0_ ( .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_0_out ) ) ; @@ -29616,67 +33453,43 @@ direct_interc_1 direct_interc_1_ ( direct_interc_2 direct_interc_2_ ( .in ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_2_out ) ) ; -direct_interc_3 direct_interc_3_ ( - .in ( grid_clb_1_bottom_width_0_height_0__pin_51_ ) , - .out ( direct_interc_3_out ) ) ; -direct_interc_4 direct_interc_4_ ( - .in ( grid_clb_3_bottom_width_0_height_0__pin_51_ ) , - .out ( direct_interc_4_out ) ) ; direct_interc_5 direct_interc_5_ ( .in ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , .out ( direct_interc_5_out ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7301 ( - .A ( grid_io_left_1_ccff_tail[0] ) , .X ( ropt_net_25 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69097180 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_16 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69107181 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_27 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69117182 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_38 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69127183 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_49 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69137184 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_510 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69147185 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_611 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69157186 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_712 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69167187 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_813 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69177188 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_914 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7302 ( .A ( ropt_net_25 ) , - .X ( ropt_net_26 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69197190 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_1116 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69207191 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_1217 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69217192 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_1318 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69227193 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_1419 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69237194 ( .A ( ctsbuf_net_1823 ) , - .Y ( ctsbuf_net_1520 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7303 ( .A ( ropt_net_26 ) , - .X ( ropt_net_27 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69257196 ( .A ( ctsbuf_net_1924 ) , - .Y ( ctsbuf_net_1722 ) ) ; -sky130_fd_sc_hd__bufinv_8 cts_inv_69247195_69267197 ( - .A ( SYNOPSYS_UNCONNECTED_1 ) , .Y ( SYNOPSYS_UNCONNECTED_2 ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_69187189_69277198 ( - .A ( SYNOPSYS_UNCONNECTED_3 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69397210 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_1823 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_69407211 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_1924 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7304 ( - .A ( grid_io_top_1_ccff_tail[0] ) , .X ( ropt_net_28 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_7305 ( .A ( ropt_net_28 ) , - .X ( ropt_net_29 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7306 ( - .A ( grid_io_left_0_ccff_tail[0] ) , .X ( ropt_net_30 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_7307 ( .A ( ropt_net_30 ) , - .X ( ropt_net_31 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78798147 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_13 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78808148 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_24 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78838151 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_57 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78848152 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_68 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78858153 ( .A ( ctsbuf_net_1719 ) , + .Y ( ctsbuf_net_79 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78868154 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_810 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78878155 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_911 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78888156 ( .A ( ctsbuf_net_1719 ) , + .Y ( ctsbuf_net_1012 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78898157 ( .A ( ctsbuf_net_1719 ) , + .Y ( ctsbuf_net_1113 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78918159 ( .A ( ctsbuf_net_1719 ) , + .Y ( ctsbuf_net_1315 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_78938161 ( .A ( ctsbuf_net_1618 ) , + .Y ( ctsbuf_net_1517 ) ) ; +sky130_fd_sc_hd__inv_8 cts_inv_78828150_78948162 ( + .A ( SYNOPSYS_UNCONNECTED_31 ) , .Y ( SYNOPSYS_UNCONNECTED_32 ) ) ; +sky130_fd_sc_hd__inv_6 cts_inv_78818149_78958163 ( + .A ( SYNOPSYS_UNCONNECTED_33 ) , .Y ( SYNOPSYS_UNCONNECTED_34 ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_78908158_78968164 ( + .A ( SYNOPSYS_UNCONNECTED_35 ) , .Y ( SYNOPSYS_UNCONNECTED_36 ) ) ; +sky130_fd_sc_hd__bufinv_8 cts_inv_78928160_78978165 ( + .A ( SYNOPSYS_UNCONNECTED_37 ) , .Y ( SYNOPSYS_UNCONNECTED_38 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_79058173 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_1618 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_79068174 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_1719 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv index 82ed295..c8b8a00 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv +++ b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv @@ -1,21 +1,18 @@ - Module Util Area Sites Insts Std. Cells -===================================================================== - sb_0__0_ 35.3 6606.336000 5280 1 90 - sb_0__1_ 59.65 7687.372800 6144 1 124 - sb_0__2_ 24.24 6606.336000 5280 1 95 - sb_1__0_ 73.54 7807.488000 6240 1 131 - sb_1__1_ 82.56 8888.524800 7104 1 125 - sb_1__2_ 65.87 7807.488000 6240 1 135 - sb_2__0_ 56.5 6606.336000 5280 1 88 - sb_2__1_ 69.43 7687.372800 6144 1 129 - sb_2__2_ 42.06 6606.336000 5280 1 87 - cbx_1__0_ 81.3 5044.838400 4032 2 79 - cbx_1__1_ 80.58 5044.838400 4032 2 86 - cbx_1__2_ 27.26 5044.838400 4032 2 97 - cby_0__1_ 31.0 5044.838400 4032 2 99 - cby_1__1_ 82.17 5044.838400 4032 4 85 - grid_clb_1__1_ 74.63 12411.904000 9920 4 42 -grid_io_bottom_1__0_ 8.85 1681.612800 1344 2 7 - grid_io_left_0__1_ 7.59 1401.344000 1120 2 5 - grid_io_right_3__1_ 8.39 1401.344000 1120 2 6 - grid_io_top_1__3_ 8.11 1681.612800 1344 2 6 +| Module | Util| Area| Sites| Insts| Std_Cells +|--------------------|----------|-----------------|-------|-------|------- +| sb_0__0_ | 37.06 | 6606.336000 | 5280 | 1 | 85 +| sb_0__1_ | 61.64 | 7687.372800 | 6144 | 1 | 116 +| sb_0__2_ | 42.08 | 6606.336000 | 5280 | 1 | 85 +| sb_1__0_ | 64.92 | 7807.488000 | 6240 | 1 | 125 +| sb_1__1_ | 81.63 | 8888.524800 | 7104 | 1 | 117 +| sb_1__2_ | 69.36 | 7807.488000 | 6240 | 1 | 136 +| sb_2__0_ | 50.93 | 6606.336000 | 5280 | 1 | 94 +| sb_2__1_ | 73.86 | 7687.372800 | 6144 | 1 | 123 +| sb_2__2_ | 58.11 | 6606.336000 | 5280 | 1 | 95 +| cbx_1__0_ | 60.07 | 5044.838400 | 4032 | 2 | 130 +| cbx_1__1_ | 79.61 | 5044.838400 | 4032 | 2 | 86 +| cbx_1__2_ | 81.82 | 5044.838400 | 4032 | 2 | 82 +| cby_0__1_ | 30.11 | 5044.838400 | 4032 | 2 | 109 +| cby_1__1_ | 80.46 | 5044.838400 | 4032 | 2 | 88 +| cby_2__1_ | 67.51 | 5044.838400 | 4032 | 2 | 38 +| grid_clb_1__1_ | 75.03 | 12411.904000 | 9920 | 4 | 56 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt index ed102f9..6d96902 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt +++ b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt @@ -6,7 +6,7 @@ Report : clock timing -setup Design : fpga_core Version: P-2019.03-SP4 -Date : Tue Oct 27 15:48:59 2020 +Date : Fri Nov 6 22:19:36 2020 **************************************** Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) @@ -16,7 +16,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi --- Latency --- Clock Pin Trans Source Offset Network Total Corner --------------------------------------------------------------------------------------------------- - grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxbp_1_0_/CLK 0.138 0.000 -- 0.084 0.084 rp-+ nominal + grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.061 0.000 -- 0.039 0.039 rp-+ nominal --------------------------------------------------------------------------------------------------- Mode: full_chip @@ -25,7 +25,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi --- Latency --- Clock Pin Trans Source Offset Network Total Corner --------------------------------------------------------------------------------------------------- - grid_clb_1__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxbp_1_1_/CLK 3.437 0.000 -- 5.205 5.205 rp-+ nominal + grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.187 0.000 -- 5.545 5.545 rp-+ nominal --------------------------------------------------------------------------------------------------- **************************************** Report : clock timing @@ -34,7 +34,7 @@ Report : clock timing -setup Design : fpga_core Version: P-2019.03-SP4 -Date : Tue Oct 27 15:48:59 2020 +Date : Fri Nov 6 22:19:36 2020 **************************************** Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) @@ -43,8 +43,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi Clock Pin Latency CRP Skew Corner --------------------------------------------------------------------------------------------------- - grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxbp_1_0_/CLK 0.083 rp-+ nominal - grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxbp_1_0_/CLK 0.051 0.000 0.032 rp-+ nominal + grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.032 rp-+ nominal + grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.020 0.000 0.011 rp-+ nominal --------------------------------------------------------------------------------------------------- @@ -53,8 +53,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi Clock Pin Latency CRP Skew Corner --------------------------------------------------------------------------------------------------- - sb_1__2_/mem_left_track_33/sky130_fd_sc_hd__dfxbp_1_2_/CLK 4.674 rp-+ nominal - cbx_1__2_/mem_bottom_ipin_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 2.007 0.000 2.666 rp-+ nominal + sb_1__2_/mem_left_track_33/sky130_fd_sc_hd__dfxbp_1_2_/CLK 5.061 rp-+ nominal + cbx_1__2_/mem_bottom_ipin_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.276 0.000 1.785 rp-+ nominal --------------------------------------------------------------------------------------------------- Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) @@ -63,13 +63,19 @@ Report : global timing -format { narrow } Design : fpga_core Version: P-2019.03-SP4 -Date : Tue Oct 27 15:48:59 2020 +Date : Fri Nov 6 22:19:36 2020 **************************************** No setup violations found. -No hold violations found. - +Hold violations +-------------------------------------------------------------- + Total reg->reg in->reg reg->out in->out +-------------------------------------------------------------- +WNS -0.632 -0.632 0.000 0.000 0.000 +TNS -0.750 -0.750 0.000 0.000 0.000 +NUM 2 2 0 0 0 +-------------------------------------------------------------- 1 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds index 1261001..b5d8846 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid 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sha256:418881712c873b633330c8660795ae7cd84c8914d1898f83b6e7e33e11c19400 -size 4534272 +oid sha256:b5a3320717997883f84b73efb84312db9bcbbc600d98fe8fc95ce7f861d52cf6 +size 4548608 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds index 8b2c8ab..504d806 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:95726a8e20e003360e2e3ed58e9a324aff64b3a592f7e46a6a339e55560f9e66 -size 4384768 +oid sha256:9bc4ec1356934628f5e0e246abc9a1b49dc63923ebfbd0959a8fca566d907bae +size 4427776 diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef index cc57834..2e3a72d 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -383,7 +371,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; + RECT 0 60.37 1.38 60.67 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -391,7 +379,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -399,7 +387,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 16.17 1.38 16.47 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -407,7 +395,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 8.01 1.38 8.31 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -415,7 +403,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; + RECT 0 14.81 1.38 15.11 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -423,7 +411,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; + RECT 0 57.65 1.38 57.95 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -431,7 +419,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 56.29 1.38 56.59 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -439,7 +427,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 59.01 1.38 59.31 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -447,7 +435,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -455,7 +443,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 61.73 1.38 62.03 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -463,7 +451,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 9.37 1.38 9.67 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -471,7 +459,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -479,7 +467,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; + RECT 0 54.93 1.38 55.23 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -487,7 +475,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 35.21 1.38 35.51 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -495,7 +483,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -503,15 +491,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 5.29 1.38 5.59 ; END END chanx_left_in[15] PIN chanx_left_in[16] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 35.89 1.38 36.19 ; + LAYER met2 ; + RECT 4.99 0 5.13 1.36 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -519,7 +507,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 33.85 1.38 34.15 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -527,7 +515,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 29.09 1.38 29.39 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -535,7 +523,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 32.49 1.38 32.79 ; END END chanx_left_in[19] PIN chanx_right_in[0] @@ -543,7 +531,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 6.65 77.28 6.95 ; + RECT 75.9 58.33 77.28 58.63 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -551,7 +539,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 60.37 77.28 60.67 ; + RECT 75.9 56.97 77.28 57.27 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -559,15 +547,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 20.25 77.28 20.55 ; + RECT 75.9 39.97 77.28 40.27 ; END END chanx_right_in[2] PIN chanx_right_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 75.9 49.49 77.28 49.79 ; + LAYER met2 ; + RECT 73.07 63.92 73.21 65.28 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -575,7 +563,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 26.37 77.28 26.67 ; + RECT 75.9 54.25 77.28 54.55 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -583,15 +571,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 61.73 77.28 62.03 ; + RECT 75.9 61.05 77.28 61.35 ; END END chanx_right_in[5] PIN chanx_right_in[6] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 75.9 28.41 77.28 28.71 ; + LAYER met2 ; + RECT 73.99 0 74.13 1.36 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -599,7 +587,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 42.69 77.28 42.99 ; + RECT 75.9 59.69 77.28 59.99 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -607,15 +595,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 21.61 77.28 21.91 ; + RECT 75.9 31.81 77.28 32.11 ; END END chanx_right_in[8] PIN chanx_right_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 75.9 39.97 77.28 40.27 ; + LAYER met2 ; + RECT 74.91 0 75.05 1.36 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -623,7 +611,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 24.33 77.28 24.63 ; + RECT 75.9 18.89 77.28 19.19 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -631,7 +619,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 41.33 77.28 41.63 ; + RECT 75.9 34.53 77.28 34.83 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -639,7 +627,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 31.13 77.28 31.43 ; + RECT 75.9 29.09 77.28 29.39 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -647,7 +635,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 50.85 77.28 51.15 ; + RECT 75.9 8.01 77.28 8.31 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -655,7 +643,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 22.97 77.28 23.27 ; + RECT 75.9 25.69 77.28 25.99 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -663,7 +651,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 46.09 77.28 46.39 ; + RECT 75.9 17.53 77.28 17.83 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -671,7 +659,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 8.01 77.28 8.31 ; + RECT 75.9 33.17 77.28 33.47 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -679,7 +667,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 34.53 77.28 34.83 ; + RECT 75.9 14.81 77.28 15.11 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -687,7 +675,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 18.89 77.28 19.19 ; + RECT 75.9 27.05 77.28 27.35 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -695,7 +683,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 29.77 77.28 30.07 ; + RECT 75.9 10.73 77.28 11.03 ; END END chanx_right_in[19] PIN ccff_head[0] @@ -703,7 +691,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 9.37 77.28 9.67 ; + RECT 75.9 13.45 77.28 13.75 ; END END ccff_head[0] PIN chanx_left_out[0] @@ -711,7 +699,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 36.57 1.38 36.87 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -719,7 +707,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; + RECT 0 18.89 1.38 19.19 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -727,23 +715,23 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; + RECT 0 17.53 1.38 17.83 ; END END chanx_left_out[2] PIN chanx_left_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 8.01 1.38 8.31 ; + LAYER met2 ; + RECT 3.15 0 3.29 1.36 ; END END chanx_left_out[3] PIN chanx_left_out[4] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 12.09 1.38 12.39 ; + LAYER met2 ; + RECT 2.23 0 2.37 1.36 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -751,7 +739,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 10.73 1.38 11.03 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -759,7 +747,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -767,7 +755,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 21.61 1.38 21.91 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -775,15 +763,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_out[8] PIN chanx_left_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + LAYER met2 ; + RECT 4.07 0 4.21 1.36 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -791,7 +779,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 3.93 1.38 4.23 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -799,7 +787,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -807,7 +795,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; + RECT 0 37.93 1.38 38.23 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -815,7 +803,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -823,15 +811,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 40.65 1.38 40.95 ; END END chanx_left_out[14] PIN chanx_left_out[15] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; + LAYER met4 ; + RECT 4.45 0 4.75 1.36 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -839,7 +827,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 9.37 1.38 9.67 ; + RECT 0 25.69 1.38 25.99 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -847,7 +835,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 6.65 1.38 6.95 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -855,7 +843,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 12.09 1.38 12.39 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -863,7 +851,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 13.45 1.38 13.75 ; END END chanx_left_out[19] PIN chanx_right_out[0] @@ -879,7 +867,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 52.21 77.28 52.51 ; + RECT 75.9 55.61 77.28 55.91 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -887,7 +875,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 10.73 77.28 11.03 ; + RECT 75.9 38.61 77.28 38.91 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -895,7 +883,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 53.57 77.28 53.87 ; + RECT 75.9 12.09 77.28 12.39 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -903,7 +891,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 35.89 77.28 36.19 ; + RECT 75.9 52.89 77.28 53.19 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -911,7 +899,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 12.09 77.28 12.39 ; + RECT 75.9 16.17 77.28 16.47 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -919,15 +907,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 14.81 77.28 15.11 ; + RECT 75.9 20.25 77.28 20.55 ; END END chanx_right_out[6] PIN chanx_right_out[7] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 75.9 57.65 77.28 57.95 ; + LAYER met2 ; + RECT 72.15 63.92 72.29 65.28 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -935,7 +923,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 13.45 77.28 13.75 ; + RECT 75.9 9.37 77.28 9.67 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -943,7 +931,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 56.29 77.28 56.59 ; + RECT 75.9 21.61 77.28 21.91 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -951,15 +939,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 54.93 77.28 55.23 ; + RECT 75.9 41.33 77.28 41.63 ; END END chanx_right_out[10] PIN chanx_right_out[11] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 75.9 59.01 77.28 59.31 ; + LAYER met2 ; + RECT 73.99 63.92 74.13 65.28 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -967,23 +955,23 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 37.25 77.28 37.55 ; + RECT 75.9 5.29 77.28 5.59 ; END END chanx_right_out[12] PIN chanx_right_out[13] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 75.9 38.61 77.28 38.91 ; + LAYER met4 ; + RECT 72.53 63.92 72.83 65.28 ; END END chanx_right_out[13] PIN chanx_right_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 75.9 5.29 77.28 5.59 ; + LAYER met2 ; + RECT 74.91 63.92 75.05 65.28 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -991,7 +979,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 47.45 77.28 47.75 ; + RECT 75.9 50.17 77.28 50.47 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -999,7 +987,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 32.49 77.28 32.79 ; + RECT 75.9 47.45 77.28 47.75 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1007,7 +995,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 17.53 77.28 17.83 ; + RECT 75.9 51.53 77.28 51.83 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1015,7 +1003,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 16.17 77.28 16.47 ; + RECT 75.9 22.97 77.28 23.27 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1023,153 +1011,385 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 44.73 77.28 45.03 ; + RECT 75.9 24.33 77.28 24.63 ; END END chanx_right_out[19] - PIN top_grid_pin_16_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 24.77 63.92 24.91 65.28 ; - END - END top_grid_pin_16_[0] - PIN top_grid_pin_17_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.93 63.92 23.07 65.28 ; - END - END top_grid_pin_17_[0] - PIN top_grid_pin_18_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 43.63 63.92 43.77 65.28 ; - END - END top_grid_pin_18_[0] - PIN top_grid_pin_19_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 23.85 63.92 23.99 65.28 ; - END - END top_grid_pin_19_[0] - PIN top_grid_pin_20_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.05 63.92 10.19 65.28 ; - END - END top_grid_pin_20_[0] - PIN top_grid_pin_21_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.07 63.92 4.21 65.28 ; - END - END top_grid_pin_21_[0] - PIN top_grid_pin_22_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.97 63.92 11.11 65.28 ; - END - END top_grid_pin_22_[0] - PIN top_grid_pin_23_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 11.89 63.92 12.03 65.28 ; - END - END top_grid_pin_23_[0] - PIN top_grid_pin_24_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.83 63.92 6.97 65.28 ; - END - END top_grid_pin_24_[0] - PIN top_grid_pin_25_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.99 63.92 5.13 65.28 ; - END - END top_grid_pin_25_[0] - PIN top_grid_pin_26_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.75 63.92 7.89 65.28 ; - END - END top_grid_pin_26_[0] - PIN top_grid_pin_27_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 5.91 63.92 6.05 65.28 ; - END - END top_grid_pin_27_[0] - PIN top_grid_pin_28_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.89 63.92 58.03 65.28 ; - END - END top_grid_pin_28_[0] - PIN top_grid_pin_29_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.55 63.92 44.69 65.28 ; - END - END top_grid_pin_29_[0] - PIN top_grid_pin_30_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 63.92 45.61 65.28 ; - END - END top_grid_pin_30_[0] - PIN top_grid_pin_31_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.81 63.92 58.95 65.28 ; - END - END top_grid_pin_31_[0] PIN bottom_grid_pin_0_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 0 66.77 1.36 ; + RECT 71.23 63.92 71.37 65.28 ; END END bottom_grid_pin_0_[0] - PIN ccff_tail[0] + PIN bottom_grid_pin_2_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 0 65.85 1.36 ; + RECT 23.39 63.92 23.53 65.28 ; + END + END bottom_grid_pin_2_[0] + PIN bottom_grid_pin_4_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.45 0 51.59 1.36 ; + END + END bottom_grid_pin_4_[0] + PIN bottom_grid_pin_6_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.53 63.92 4.67 65.28 ; + END + END bottom_grid_pin_6_[0] + PIN bottom_grid_pin_8_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.57 63.92 15.71 65.28 ; + END + END bottom_grid_pin_8_[0] + PIN bottom_grid_pin_10_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.41 63.92 63.55 65.28 ; + END + END bottom_grid_pin_10_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 27.05 1.38 27.35 ; END END ccff_tail[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.93 0 46.07 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_IN[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_IN[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.85 0 23.99 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_IN[1] + PIN gfpga_pad_EMBEDDED_IO_SOC_IN[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.77 0 47.91 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_IN[2] + PIN gfpga_pad_EMBEDDED_IO_SOC_IN[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.87 0 41.01 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_IN[3] + PIN gfpga_pad_EMBEDDED_IO_SOC_IN[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.65 0 37.79 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_IN[4] + PIN gfpga_pad_EMBEDDED_IO_SOC_IN[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.23 0 71.37 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_IN[5] + PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.95 0 40.09 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.97 0 11.11 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_OUT[1] + PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.95 0 17.09 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_OUT[2] + PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.61 0 49.75 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_OUT[3] + PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.25 0 65.39 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_OUT[4] + PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.53 0 27.67 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_OUT[5] + PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.79 0 41.93 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.45 0 28.59 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_DIR[1] + PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.69 0 48.83 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_DIR[2] + PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.61 0 26.75 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_DIR[3] + PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.75 0 30.89 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_DIR[4] + PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.05 0 10.19 1.36 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_DIR[5] + PIN top_width_0_height_0__pin_0_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.39 63.92 69.53 65.28 ; + END + END top_width_0_height_0__pin_0_[0] + PIN top_width_0_height_0__pin_2_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.47 63.92 22.61 65.28 ; + END + END top_width_0_height_0__pin_2_[0] + PIN top_width_0_height_0__pin_4_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.53 0 50.67 1.36 ; + END + END top_width_0_height_0__pin_4_[0] + PIN top_width_0_height_0__pin_6_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.61 63.92 3.75 65.28 ; + END + END top_width_0_height_0__pin_6_[0] + PIN top_width_0_height_0__pin_8_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.49 63.92 16.63 65.28 ; + END + END top_width_0_height_0__pin_8_[0] + PIN top_width_0_height_0__pin_10_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.33 63.92 64.47 65.28 ; + END + END top_width_0_height_0__pin_10_[0] + PIN top_width_0_height_0__pin_1_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 20.25 1.38 20.55 ; + END + END top_width_0_height_0__pin_1_upper[0] + PIN top_width_0_height_0__pin_1_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 75.9 44.05 77.28 44.35 ; + END + END top_width_0_height_0__pin_1_lower[0] + PIN top_width_0_height_0__pin_3_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.81 1.38 49.11 ; + END + END top_width_0_height_0__pin_3_upper[0] + PIN top_width_0_height_0__pin_3_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 75.9 48.81 77.28 49.11 ; + END + END top_width_0_height_0__pin_3_lower[0] + PIN top_width_0_height_0__pin_5_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.73 1.38 45.03 ; + END + END top_width_0_height_0__pin_5_upper[0] + PIN top_width_0_height_0__pin_5_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 75.9 36.57 77.28 36.87 ; + END + END top_width_0_height_0__pin_5_lower[0] + PIN top_width_0_height_0__pin_7_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 30.45 1.38 30.75 ; + END + END top_width_0_height_0__pin_7_upper[0] + PIN top_width_0_height_0__pin_7_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 75.9 30.45 77.28 30.75 ; + END + END top_width_0_height_0__pin_7_lower[0] + PIN top_width_0_height_0__pin_9_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.97 1.38 23.27 ; + END + END top_width_0_height_0__pin_9_upper[0] + PIN top_width_0_height_0__pin_9_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 75.9 42.69 77.28 42.99 ; + END + END top_width_0_height_0__pin_9_lower[0] + PIN top_width_0_height_0__pin_11_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 24.33 1.38 24.63 ; + END + END top_width_0_height_0__pin_11_upper[0] + PIN top_width_0_height_0__pin_11_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 75.9 46.09 77.28 46.39 ; + END + END top_width_0_height_0__pin_11_lower[0] + PIN SC_IN_TOP + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 63.92 70.45 65.28 ; + END + END SC_IN_TOP + PIN SC_IN_BOT + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.65 63.92 37.79 65.28 ; + END + END SC_IN_BOT + PIN SC_OUT_TOP + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.55 63.92 21.69 65.28 ; + END + END SC_OUT_TOP + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 75.9 6.65 77.28 6.95 ; + END + END SC_OUT_BOT PIN VDD DIRECTION INPUT ; USE POWER ; @@ -1258,10 +1478,10 @@ MACRO cbx_1__0_ RECT 76.36 62.475 77.28 62.645 ; RECT 0 62.475 3.68 62.645 ; RECT 76.36 59.755 77.28 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 73.6 57.035 77.28 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 73.6 54.315 77.28 54.485 ; + RECT 0 59.755 3.68 59.925 ; + RECT 76.36 57.035 77.28 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 76.36 54.315 77.28 54.485 ; RECT 0 54.315 1.84 54.485 ; RECT 76.36 51.595 77.28 51.765 ; RECT 0 51.595 1.84 51.765 ; @@ -1281,19 +1501,19 @@ MACRO cbx_1__0_ RECT 0 32.555 1.84 32.725 ; RECT 76.36 29.835 77.28 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 76.82 27.115 77.28 27.285 ; + RECT 76.36 27.115 77.28 27.285 ; RECT 0 27.115 1.84 27.285 ; RECT 76.36 24.395 77.28 24.565 ; RECT 0 24.395 1.84 24.565 ; RECT 76.36 21.675 77.28 21.845 ; - RECT 0 21.675 3.68 21.845 ; + RECT 0 21.675 1.84 21.845 ; RECT 76.36 18.955 77.28 19.125 ; - RECT 0 18.955 3.68 19.125 ; + RECT 0 18.955 1.84 19.125 ; RECT 76.36 16.235 77.28 16.405 ; RECT 0 16.235 1.84 16.405 ; - RECT 73.6 13.515 77.28 13.685 ; + RECT 76.36 13.515 77.28 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 73.6 10.795 77.28 10.965 ; + RECT 76.36 10.795 77.28 10.965 ; RECT 0 10.795 1.84 10.965 ; RECT 76.36 8.075 77.28 8.245 ; RECT 0 8.075 1.84 8.245 ; @@ -1306,37 +1526,38 @@ MACRO cbx_1__0_ RECT 67.94 65.095 68.22 65.465 ; RECT 38.5 65.095 38.78 65.465 ; RECT 9.06 65.095 9.34 65.465 ; - RECT 25.17 63.42 25.43 63.74 ; + RECT 64.73 1.54 64.99 1.86 ; RECT 67.94 -0.185 68.22 0.185 ; RECT 38.5 -0.185 38.78 0.185 ; RECT 9.06 -0.185 9.34 0.185 ; - POLYGON 77 65 77 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 0.28 0.28 0.28 65 1.95 65 1.95 63.64 2.65 63.64 2.65 65 3.79 65 3.79 63.64 4.49 63.64 4.49 65 4.71 65 4.71 63.64 5.41 63.64 5.41 65 5.63 65 5.63 63.64 6.33 63.64 6.33 65 6.55 65 6.55 63.64 7.25 63.64 7.25 65 7.47 65 7.47 63.64 8.17 63.64 8.17 65 9.77 65 9.77 63.64 10.47 63.64 10.47 65 10.69 65 10.69 63.64 11.39 63.64 11.39 65 11.61 65 11.61 63.64 12.31 63.64 12.31 65 22.65 65 22.65 63.64 23.35 63.64 23.35 65 23.57 65 23.57 63.64 24.27 63.64 24.27 65 24.49 65 24.49 63.64 25.19 63.64 25.19 65 43.35 65 43.35 63.64 44.05 63.64 44.05 65 44.27 65 44.27 63.64 44.97 63.64 44.97 65 45.19 65 45.19 63.64 45.89 63.64 45.89 65 57.61 65 57.61 63.64 58.31 63.64 58.31 65 58.53 65 58.53 63.64 59.23 63.64 59.23 65 ; + POLYGON 77 65 77 0.28 75.33 0.28 75.33 1.64 74.63 1.64 74.63 0.28 74.41 0.28 74.41 1.64 73.71 1.64 73.71 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 5.41 0.28 5.41 1.64 4.71 1.64 4.71 0.28 4.49 0.28 4.49 1.64 3.79 1.64 3.79 0.28 3.57 0.28 3.57 1.64 2.87 1.64 2.87 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 65 1.95 65 1.95 63.64 2.65 63.64 2.65 65 3.33 65 3.33 63.64 4.03 63.64 4.03 65 4.25 65 4.25 63.64 4.95 63.64 4.95 65 15.29 65 15.29 63.64 15.99 63.64 15.99 65 16.21 65 16.21 63.64 16.91 63.64 16.91 65 21.27 65 21.27 63.64 21.97 63.64 21.97 65 22.19 65 22.19 63.64 22.89 63.64 22.89 65 23.11 65 23.11 63.64 23.81 63.64 23.81 65 37.37 65 37.37 63.64 38.07 63.64 38.07 65 63.13 65 63.13 63.64 63.83 63.64 63.83 65 64.05 65 64.05 63.64 64.75 63.64 64.75 65 69.11 65 69.11 63.64 69.81 63.64 69.81 65 70.03 65 70.03 63.64 70.73 63.64 70.73 65 70.95 65 70.95 63.64 71.65 63.64 71.65 65 71.87 65 71.87 63.64 72.57 63.64 72.57 65 72.79 65 72.79 63.64 73.49 63.64 73.49 65 73.71 65 73.71 63.64 74.41 63.64 74.41 65 74.63 65 74.63 63.64 75.33 63.64 75.33 65 ; LAYER met3 ; POLYGON 68.245 65.445 68.245 65.44 68.46 65.44 68.46 65.12 68.245 65.12 68.245 65.115 67.915 65.115 67.915 65.12 67.7 65.12 67.7 65.44 67.915 65.44 67.915 65.445 ; POLYGON 38.805 65.445 38.805 65.44 39.02 65.44 39.02 65.12 38.805 65.12 38.805 65.115 38.475 65.115 38.475 65.12 38.26 65.12 38.26 65.44 38.475 65.44 38.475 65.445 ; POLYGON 9.365 65.445 9.365 65.44 9.58 65.44 9.58 65.12 9.365 65.12 9.365 65.115 9.035 65.115 9.035 65.12 8.82 65.12 8.82 65.44 9.035 65.44 9.035 65.445 ; - RECT 1.215 54.915 1.545 55.21 ; - POLYGON 1.545 51.165 1.545 51.15 12.57 51.15 12.57 50.85 1.545 50.85 1.545 50.835 1.215 50.835 1.215 51.165 ; - POLYGON 9.35 44.35 9.35 44.05 1.78 44.05 1.78 44.07 1.23 44.07 1.23 44.35 ; - POLYGON 16.25 38.91 16.25 38.61 1.23 38.61 1.23 38.89 1.78 38.89 1.78 38.91 ; - POLYGON 10.27 30.07 10.27 29.77 1.23 29.77 1.23 30.05 1.78 30.05 1.78 30.07 ; - POLYGON 2.03 25.32 2.03 25.31 7.51 25.31 7.51 25.01 2.03 25.01 2.03 25 1.65 25 1.65 25.32 ; - POLYGON 1.545 22.605 1.545 22.6 2.03 22.6 2.03 22.28 1.545 22.28 1.545 22.275 1.215 22.275 1.215 22.605 ; - POLYGON 18.55 11.71 18.55 11.41 1.78 11.41 1.78 11.43 1.23 11.43 1.23 11.71 ; + POLYGON 4.75 59.99 4.75 59.69 1.23 59.69 1.23 59.97 1.78 59.97 1.78 59.99 ; + POLYGON 2.005 53.885 2.005 53.87 37.87 53.87 37.87 53.57 2.005 53.57 2.005 53.555 1.675 53.555 1.675 53.885 ; + POLYGON 2.005 41.645 2.005 41.63 11.65 41.63 11.65 41.33 2.005 41.33 2.005 41.315 1.675 41.315 1.675 41.33 1.23 41.33 1.23 41.63 1.675 41.63 1.675 41.645 ; + POLYGON 75.63 31.44 75.63 31.12 75.25 31.12 75.25 31.13 69.77 31.13 69.77 31.43 75.25 31.43 75.25 31.44 ; + POLYGON 9.81 25.31 9.81 25.01 1.78 25.01 1.78 25.03 1.08 25.03 1.08 25.31 ; + POLYGON 2.03 23.96 2.03 23.95 30.51 23.95 30.51 23.65 2.03 23.65 2.03 23.64 1.65 23.64 1.65 23.96 ; + POLYGON 13.95 22.59 13.95 22.29 1.78 22.29 1.78 22.31 1.23 22.31 1.23 22.59 ; + POLYGON 7.05 21.23 7.05 20.93 1.99 20.93 1.99 20.25 1.78 20.25 1.78 20.95 1.69 20.95 1.69 21.23 ; + POLYGON 76.05 15.79 76.05 15.51 75.5 15.51 75.5 15.49 38.03 15.49 38.03 15.79 ; + POLYGON 12.57 11.71 12.57 11.41 1.99 11.41 1.99 10.73 1.78 10.73 1.78 11.43 1.69 11.43 1.69 11.71 ; + POLYGON 25.91 8.99 25.91 8.69 1.78 8.69 1.78 8.71 1.23 8.71 1.23 8.99 ; POLYGON 68.245 0.165 68.245 0.16 68.46 0.16 68.46 -0.16 68.245 -0.16 68.245 -0.165 67.915 -0.165 67.915 -0.16 67.7 -0.16 67.7 0.16 67.915 0.16 67.915 0.165 ; POLYGON 38.805 0.165 38.805 0.16 39.02 0.16 39.02 -0.16 38.805 -0.16 38.805 -0.165 38.475 -0.165 38.475 -0.16 38.26 -0.16 38.26 0.16 38.475 0.16 38.475 0.165 ; POLYGON 9.365 0.165 9.365 0.16 9.58 0.16 9.58 -0.16 9.365 -0.16 9.365 -0.165 9.035 -0.165 9.035 -0.16 8.82 -0.16 8.82 0.16 9.035 0.16 9.035 0.165 ; - POLYGON 76.88 64.88 76.88 62.43 75.5 62.43 75.5 61.33 76.88 61.33 76.88 61.07 75.5 61.07 75.5 59.97 76.88 59.97 76.88 59.71 75.5 59.71 75.5 58.61 76.88 58.61 76.88 58.35 75.5 58.35 75.5 57.25 76.88 57.25 76.88 56.99 75.5 56.99 75.5 55.89 76.88 55.89 76.88 55.63 75.5 55.63 75.5 54.53 76.88 54.53 76.88 54.27 75.5 54.27 75.5 53.17 76.88 53.17 76.88 52.91 75.5 52.91 75.5 51.81 76.88 51.81 76.88 51.55 75.5 51.55 75.5 50.45 76.88 50.45 76.88 50.19 75.5 50.19 75.5 49.09 76.88 49.09 76.88 48.15 75.5 48.15 75.5 47.05 76.88 47.05 76.88 46.79 75.5 46.79 75.5 45.69 76.88 45.69 76.88 45.43 75.5 45.43 75.5 44.33 76.88 44.33 76.88 43.39 75.5 43.39 75.5 42.29 76.88 42.29 76.88 42.03 75.5 42.03 75.5 40.93 76.88 40.93 76.88 40.67 75.5 40.67 75.5 39.57 76.88 39.57 76.88 39.31 75.5 39.31 75.5 38.21 76.88 38.21 76.88 37.95 75.5 37.95 75.5 36.85 76.88 36.85 76.88 36.59 75.5 36.59 75.5 35.49 76.88 35.49 76.88 35.23 75.5 35.23 75.5 34.13 76.88 34.13 76.88 33.19 75.5 33.19 75.5 32.09 76.88 32.09 76.88 31.83 75.5 31.83 75.5 30.73 76.88 30.73 76.88 30.47 75.5 30.47 75.5 29.37 76.88 29.37 76.88 29.11 75.5 29.11 75.5 28.01 76.88 28.01 76.88 27.07 75.5 27.07 75.5 25.97 76.88 25.97 76.88 25.03 75.5 25.03 75.5 23.93 76.88 23.93 76.88 23.67 75.5 23.67 75.5 22.57 76.88 22.57 76.88 22.31 75.5 22.31 75.5 21.21 76.88 21.21 76.88 20.95 75.5 20.95 75.5 19.85 76.88 19.85 76.88 19.59 75.5 19.59 75.5 18.49 76.88 18.49 76.88 18.23 75.5 18.23 75.5 17.13 76.88 17.13 76.88 16.87 75.5 16.87 75.5 15.77 76.88 15.77 76.88 15.51 75.5 15.51 75.5 14.41 76.88 14.41 76.88 14.15 75.5 14.15 75.5 13.05 76.88 13.05 76.88 12.79 75.5 12.79 75.5 11.69 76.88 11.69 76.88 11.43 75.5 11.43 75.5 10.33 76.88 10.33 76.88 10.07 75.5 10.07 75.5 8.97 76.88 8.97 76.88 8.71 75.5 8.71 75.5 7.61 76.88 7.61 76.88 7.35 75.5 7.35 75.5 6.25 76.88 6.25 76.88 5.99 75.5 5.99 75.5 4.89 76.88 4.89 76.88 4.63 75.5 4.63 75.5 3.53 76.88 3.53 76.88 0.4 0.4 0.4 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 64.88 ; + POLYGON 76.88 64.88 76.88 61.75 75.5 61.75 75.5 60.65 76.88 60.65 76.88 60.39 75.5 60.39 75.5 59.29 76.88 59.29 76.88 59.03 75.5 59.03 75.5 57.93 76.88 57.93 76.88 57.67 75.5 57.67 75.5 56.57 76.88 56.57 76.88 56.31 75.5 56.31 75.5 55.21 76.88 55.21 76.88 54.95 75.5 54.95 75.5 53.85 76.88 53.85 76.88 53.59 75.5 53.59 75.5 52.49 76.88 52.49 76.88 52.23 75.5 52.23 75.5 51.13 76.88 51.13 76.88 50.87 75.5 50.87 75.5 49.77 76.88 49.77 76.88 49.51 75.5 49.51 75.5 48.41 76.88 48.41 76.88 48.15 75.5 48.15 75.5 47.05 76.88 47.05 76.88 46.79 75.5 46.79 75.5 45.69 76.88 45.69 76.88 44.75 75.5 44.75 75.5 43.65 76.88 43.65 76.88 43.39 75.5 43.39 75.5 42.29 76.88 42.29 76.88 42.03 75.5 42.03 75.5 40.93 76.88 40.93 76.88 40.67 75.5 40.67 75.5 39.57 76.88 39.57 76.88 39.31 75.5 39.31 75.5 38.21 76.88 38.21 76.88 37.27 75.5 37.27 75.5 36.17 76.88 36.17 76.88 35.23 75.5 35.23 75.5 34.13 76.88 34.13 76.88 33.87 75.5 33.87 75.5 32.77 76.88 32.77 76.88 32.51 75.5 32.51 75.5 31.41 76.88 31.41 76.88 31.15 75.5 31.15 75.5 30.05 76.88 30.05 76.88 29.79 75.5 29.79 75.5 28.69 76.88 28.69 76.88 27.75 75.5 27.75 75.5 26.65 76.88 26.65 76.88 26.39 75.5 26.39 75.5 25.29 76.88 25.29 76.88 25.03 75.5 25.03 75.5 23.93 76.88 23.93 76.88 23.67 75.5 23.67 75.5 22.57 76.88 22.57 76.88 22.31 75.5 22.31 75.5 21.21 76.88 21.21 76.88 20.95 75.5 20.95 75.5 19.85 76.88 19.85 76.88 19.59 75.5 19.59 75.5 18.49 76.88 18.49 76.88 18.23 75.5 18.23 75.5 17.13 76.88 17.13 76.88 16.87 75.5 16.87 75.5 15.77 76.88 15.77 76.88 15.51 75.5 15.51 75.5 14.41 76.88 14.41 76.88 14.15 75.5 14.15 75.5 13.05 76.88 13.05 76.88 12.79 75.5 12.79 75.5 11.69 76.88 11.69 76.88 11.43 75.5 11.43 75.5 10.33 76.88 10.33 76.88 10.07 75.5 10.07 75.5 8.97 76.88 8.97 76.88 8.71 75.5 8.71 75.5 7.61 76.88 7.61 76.88 7.35 75.5 7.35 75.5 6.25 76.88 6.25 76.88 5.99 75.5 5.99 75.5 4.89 76.88 4.89 76.88 4.63 75.5 4.63 75.5 3.53 76.88 3.53 76.88 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 64.88 ; + LAYER met4 ; + POLYGON 76.88 64.88 76.88 0.4 68.78 0.4 68.78 1 67.38 1 67.38 0.4 54.06 0.4 54.06 1 52.66 1 52.66 0.4 39.34 0.4 39.34 1 37.94 1 37.94 0.4 24.62 0.4 24.62 1 23.22 1 23.22 0.4 9.9 0.4 9.9 1 8.5 1 8.5 0.4 5.15 0.4 5.15 1.76 4.05 1.76 4.05 0.4 0.4 0.4 0.4 64.88 8.5 64.88 8.5 64.28 9.9 64.28 9.9 64.88 23.22 64.88 23.22 64.28 24.62 64.28 24.62 64.88 37.94 64.88 37.94 64.28 39.34 64.28 39.34 64.88 52.66 64.88 52.66 64.28 54.06 64.28 54.06 64.88 67.38 64.88 67.38 64.28 68.78 64.28 68.78 64.88 72.13 64.88 72.13 63.52 73.23 63.52 73.23 64.88 ; LAYER met1 ; POLYGON 77 64.76 77 63.08 76.52 63.08 76.52 62.04 77 62.04 77 60.36 76.52 60.36 76.52 59.32 77 59.32 77 57.64 76.52 57.64 76.52 56.6 77 56.6 77 54.92 76.52 54.92 76.52 53.88 77 53.88 77 52.2 76.52 52.2 76.52 51.16 77 51.16 77 49.48 76.52 49.48 76.52 48.44 77 48.44 77 46.76 76.52 46.76 76.52 45.72 77 45.72 77 44.04 76.52 44.04 76.52 43 77 43 77 41.32 76.52 41.32 76.52 40.28 77 40.28 77 38.6 76.52 38.6 76.52 37.56 77 37.56 77 35.88 76.52 35.88 76.52 34.84 77 34.84 77 33.16 76.52 33.16 76.52 32.12 77 32.12 77 30.44 76.52 30.44 76.52 29.4 77 29.4 77 27.72 76.52 27.72 76.52 26.68 77 26.68 77 25 76.52 25 76.52 23.96 77 23.96 77 22.28 76.52 22.28 76.52 21.24 77 21.24 77 19.56 76.52 19.56 76.52 18.52 77 18.52 77 16.84 76.52 16.84 76.52 15.8 77 15.8 77 14.12 76.52 14.12 76.52 13.08 77 13.08 77 11.4 76.52 11.4 76.52 10.36 77 10.36 77 8.68 76.52 8.68 76.52 7.64 77 7.64 77 5.96 76.52 5.96 76.52 4.92 77 4.92 77 3.24 76.52 3.24 76.52 2.2 77 2.2 77 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 ; - LAYER met4 ; - POLYGON 76.88 64.88 76.88 0.4 68.78 0.4 68.78 1 67.38 1 67.38 0.4 54.06 0.4 54.06 1 52.66 1 52.66 0.4 39.34 0.4 39.34 1 37.94 1 37.94 0.4 24.62 0.4 24.62 1 23.22 1 23.22 0.4 9.9 0.4 9.9 1 8.5 1 8.5 0.4 0.4 0.4 0.4 64.88 8.5 64.88 8.5 64.28 9.9 64.28 9.9 64.88 23.22 64.88 23.22 64.28 24.62 64.28 24.62 64.88 37.94 64.88 37.94 64.28 39.34 64.28 39.34 64.88 52.66 64.88 52.66 64.28 54.06 64.28 54.06 64.88 67.38 64.88 67.38 64.28 68.78 64.28 68.78 64.88 ; LAYER met5 ; - POLYGON 74.08 62.08 74.08 57.84 70.88 57.84 70.88 48.24 74.08 48.24 74.08 37.44 70.88 37.44 70.88 27.84 74.08 27.84 74.08 17.04 70.88 17.04 70.88 7.44 74.08 7.44 74.08 3.2 3.2 3.2 3.2 7.44 6.4 7.44 6.4 17.04 3.2 17.04 3.2 27.84 6.4 27.84 6.4 37.44 3.2 37.44 3.2 48.24 6.4 48.24 6.4 57.84 3.2 57.84 3.2 62.08 ; + POLYGON 75.68 63.68 75.68 56.24 72.48 56.24 72.48 49.84 75.68 49.84 75.68 35.84 72.48 35.84 72.48 29.44 75.68 29.44 75.68 15.44 72.48 15.44 72.48 9.04 75.68 9.04 75.68 1.6 1.6 1.6 1.6 9.04 4.8 9.04 4.8 15.44 1.6 15.44 1.6 29.44 4.8 29.44 4.8 35.84 1.6 35.84 1.6 49.84 4.8 49.84 4.8 56.24 1.6 56.24 1.6 63.68 ; LAYER li1 ; - RECT 47.465 64.47 48.215 65.015 ; - RECT 47.465 0.265 48.215 0.81 ; - RECT 0.34 0.34 76.94 64.94 ; + RECT 0.17 0.17 77.11 65.11 ; LAYER mcon ; RECT 76.965 65.195 77.135 65.365 ; RECT 76.505 65.195 76.675 65.365 ; @@ -1770,8 +1991,13 @@ MACRO cbx_1__0_ RECT 68.005 65.205 68.155 65.355 ; RECT 38.565 65.205 38.715 65.355 ; RECT 9.125 65.205 9.275 65.355 ; - RECT 24.765 63.505 24.915 63.655 ; - RECT 10.965 63.505 11.115 63.655 ; + RECT 70.305 63.505 70.455 63.655 ; + RECT 37.645 63.505 37.795 63.655 ; + RECT 71.225 1.625 71.375 1.775 ; + RECT 50.525 1.625 50.675 1.775 ; + RECT 28.445 1.625 28.595 1.775 ; + RECT 16.945 1.625 17.095 1.775 ; + RECT 2.225 1.625 2.375 1.775 ; RECT 68.005 -0.075 68.155 0.075 ; RECT 38.565 -0.075 38.715 0.075 ; RECT 9.125 -0.075 9.275 0.075 ; @@ -1779,11 +2005,19 @@ MACRO cbx_1__0_ RECT 67.98 65.18 68.18 65.38 ; RECT 38.54 65.18 38.74 65.38 ; RECT 9.1 65.18 9.3 65.38 ; - RECT 1.28 59.74 1.48 59.94 ; - RECT 75.8 56.34 76 56.54 ; - RECT 1.74 16.22 1.94 16.42 ; - RECT 1.74 13.5 1.94 13.7 ; - RECT 1.28 8.06 1.48 8.26 ; + RECT 1.74 61.78 1.94 61.98 ; + RECT 75.8 59.74 76 59.94 ; + RECT 75.34 51.58 75.54 51.78 ; + RECT 75.8 47.5 76 47.7 ; + RECT 1.28 46.14 1.48 46.34 ; + RECT 75.8 41.38 76 41.58 ; + RECT 1.74 27.1 1.94 27.3 ; + RECT 75.8 23.02 76 23.22 ; + RECT 1.74 17.58 1.94 17.78 ; + RECT 1.28 13.5 1.48 13.7 ; + RECT 75.34 12.14 75.54 12.34 ; + RECT 1.74 12.14 1.94 12.34 ; + RECT 1.28 6.7 1.48 6.9 ; RECT 67.98 -0.1 68.18 0.1 ; RECT 38.54 -0.1 38.74 0.1 ; RECT 9.1 -0.1 9.3 0.1 ; @@ -1791,93 +2025,11 @@ MACRO cbx_1__0_ RECT 67.98 65.18 68.18 65.38 ; RECT 38.54 65.18 38.74 65.38 ; RECT 9.1 65.18 9.3 65.38 ; - RECT 1.74 54.3 1.94 54.5 ; - RECT 1.74 14.86 1.94 15.06 ; + RECT 75.34 58.38 75.54 58.58 ; + RECT 1.74 54.98 1.94 55.18 ; RECT 67.98 -0.1 68.18 0.1 ; RECT 38.54 -0.1 38.74 0.1 ; RECT 9.1 -0.1 9.3 0.1 ; - LAYER fieldpoly ; - RECT 0.14 0.14 77.14 65.14 ; - LAYER diff ; - RECT 0 0 77.28 65.28 ; - LAYER nwell ; - POLYGON 77.47 63.975 77.47 61.145 76.17 61.145 76.17 62.75 76.63 62.75 76.63 63.975 ; - POLYGON 3.87 63.975 3.87 62.37 2.03 62.37 2.03 61.145 -0.19 61.145 -0.19 63.975 ; - POLYGON 77.47 58.535 77.47 55.705 73.41 55.705 73.41 57.31 76.17 57.31 76.17 58.535 ; - RECT -0.19 55.705 2.03 58.535 ; - POLYGON 77.47 53.095 77.47 50.265 76.63 50.265 76.63 51.49 76.17 51.49 76.17 53.095 ; - RECT -0.19 50.265 2.03 53.095 ; - RECT 76.17 44.825 77.47 47.655 ; - RECT -0.19 44.825 2.03 47.655 ; - RECT 76.17 39.385 77.47 42.215 ; - RECT -0.19 39.385 2.03 42.215 ; - RECT 76.17 33.945 77.47 36.775 ; - RECT -0.19 33.945 2.03 36.775 ; - POLYGON 77.47 31.335 77.47 28.505 76.63 28.505 76.63 29.73 76.17 29.73 76.17 31.335 ; - RECT -0.19 28.505 2.03 31.335 ; - POLYGON 77.47 25.895 77.47 23.065 76.17 23.065 76.17 24.67 76.63 24.67 76.63 25.895 ; - RECT -0.19 23.065 2.03 25.895 ; - RECT 76.17 17.625 77.47 20.455 ; - POLYGON 3.87 20.455 3.87 18.85 2.03 18.85 2.03 17.625 -0.19 17.625 -0.19 20.455 ; - POLYGON 77.47 15.015 77.47 12.185 73.41 12.185 73.41 13.79 76.17 13.79 76.17 15.015 ; - RECT -0.19 12.185 2.03 15.015 ; - POLYGON 77.47 9.575 77.47 6.745 76.17 6.745 76.17 8.35 76.63 8.35 76.63 9.575 ; - RECT -0.19 6.745 2.03 9.575 ; - POLYGON 77.47 4.135 77.47 1.305 76.63 1.305 76.63 2.53 76.17 2.53 76.17 4.135 ; - POLYGON 2.03 4.135 2.03 2.91 3.87 2.91 3.87 1.305 -0.19 1.305 -0.19 4.135 ; - RECT 0 0 77.28 65.28 ; - LAYER pwell ; - RECT 70.51 65.23 70.73 65.4 ; - RECT 66.83 65.23 67.05 65.4 ; - RECT 63.15 65.23 63.37 65.4 ; - RECT 59.47 65.23 59.69 65.4 ; - RECT 55.79 65.23 56.01 65.4 ; - RECT 52.11 65.23 52.33 65.4 ; - RECT 48.43 65.23 48.65 65.4 ; - RECT 40.61 65.23 40.83 65.4 ; - RECT 36.93 65.23 37.15 65.4 ; - RECT 33.25 65.23 33.47 65.4 ; - RECT 29.57 65.23 29.79 65.4 ; - RECT 25.89 65.23 26.11 65.4 ; - RECT 22.21 65.23 22.43 65.4 ; - RECT 18.53 65.23 18.75 65.4 ; - RECT 14.85 65.23 15.07 65.4 ; - RECT 11.17 65.23 11.39 65.4 ; - RECT 7.49 65.23 7.71 65.4 ; - RECT 3.81 65.23 4.03 65.4 ; - RECT 0.13 65.23 0.35 65.4 ; - RECT 74.235 65.22 74.345 65.34 ; - RECT 44.335 65.22 44.445 65.34 ; - RECT 76.96 65.225 77.08 65.335 ; - RECT 47.06 65.225 47.18 65.335 ; - RECT 76.055 65.22 76.215 65.33 ; - RECT 46.155 65.22 46.315 65.33 ; - RECT 76.055 -0.05 76.215 0.06 ; - RECT 74.235 -0.06 74.345 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 76.96 -0.055 77.08 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 70.51 -0.12 70.73 0.05 ; - RECT 66.83 -0.12 67.05 0.05 ; - RECT 63.15 -0.12 63.37 0.05 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - RECT 14.85 -0.12 15.07 0.05 ; - RECT 11.17 -0.12 11.39 0.05 ; - RECT 7.49 -0.12 7.71 0.05 ; - RECT 3.81 -0.12 4.03 0.05 ; - RECT 0.13 -0.12 0.35 0.05 ; - RECT 0 0 77.28 65.28 ; LAYER OVERLAP ; POLYGON 0 0 0 65.28 77.28 65.28 77.28 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef index c1aed4f..e139580 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -375,7 +363,7 @@ MACRO cbx_1__1_ USE CLOCK ; PORT LAYER met2 ; - RECT 2.23 0 2.37 1.36 ; + RECT 2.23 63.92 2.37 65.28 ; END END prog_clk[0] PIN chanx_left_in[0] @@ -383,7 +371,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 8.01 1.38 8.31 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -391,7 +379,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; + RECT 0 16.85 1.38 17.15 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -399,7 +387,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 11.41 1.38 11.71 ; + RECT 0 26.37 1.38 26.67 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -407,7 +395,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; + RECT 0 36.57 1.38 36.87 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -415,7 +403,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -423,7 +411,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 48.13 1.38 48.43 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -431,7 +419,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.77 1.38 13.07 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -439,7 +427,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -447,7 +435,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 23.65 1.38 23.95 ; + RECT 0 60.37 1.38 60.67 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -455,7 +443,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 54.93 1.38 55.23 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -463,7 +451,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + RECT 0 31.13 1.38 31.43 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -471,7 +459,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -479,7 +467,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.13 1.38 14.43 ; + RECT 0 59.01 1.38 59.31 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -487,7 +475,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 61.73 1.38 62.03 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -495,7 +483,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 15.49 1.38 15.79 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -503,7 +491,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 56.29 1.38 56.59 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -511,7 +499,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 5.29 1.38 5.59 ; + RECT 0 28.41 1.38 28.71 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -519,7 +507,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 22.29 1.38 22.59 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -527,7 +515,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.01 1.38 25.31 ; + RECT 0 37.93 1.38 38.23 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -535,7 +523,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 49.49 1.38 49.79 ; END END chanx_left_in[19] PIN chanx_right_in[0] @@ -543,7 +531,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 37.25 77.28 37.55 ; + RECT 75.9 29.09 77.28 29.39 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -551,7 +539,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 50.17 77.28 50.47 ; + RECT 75.9 40.65 77.28 40.95 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -559,7 +547,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 51.53 77.28 51.83 ; + RECT 75.9 54.93 77.28 55.23 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -567,7 +555,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 48.81 77.28 49.11 ; + RECT 75.9 11.41 77.28 11.71 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -575,7 +563,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 20.25 77.28 20.55 ; + RECT 75.9 32.49 77.28 32.79 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -583,7 +571,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 39.29 77.28 39.59 ; + RECT 75.9 30.45 77.28 30.75 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -591,7 +579,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 11.41 77.28 11.71 ; + RECT 75.9 22.29 77.28 22.59 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -599,7 +587,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 40.65 77.28 40.95 ; + RECT 75.9 37.93 77.28 38.23 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -607,7 +595,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 15.49 77.28 15.79 ; + RECT 75.9 27.73 77.28 28.03 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -615,7 +603,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 43.37 77.28 43.67 ; + RECT 75.9 16.85 77.28 17.15 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -623,7 +611,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 25.69 77.28 25.99 ; + RECT 75.9 50.85 77.28 51.15 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -631,7 +619,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 46.09 77.28 46.39 ; + RECT 75.9 33.85 77.28 34.15 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -639,7 +627,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 12.77 77.28 13.07 ; + RECT 75.9 10.05 77.28 10.35 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -647,7 +635,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 54.25 77.28 54.55 ; + RECT 75.9 4.61 77.28 4.91 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -655,7 +643,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 7.33 77.28 7.63 ; + RECT 75.9 8.69 77.28 8.99 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -663,7 +651,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 47.45 77.28 47.75 ; + RECT 75.9 23.65 77.28 23.95 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -671,7 +659,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 18.89 77.28 19.19 ; + RECT 75.9 43.37 77.28 43.67 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -679,7 +667,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 57.65 77.28 57.95 ; + RECT 75.9 20.93 77.28 21.23 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -687,7 +675,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 24.33 77.28 24.63 ; + RECT 75.9 15.49 77.28 15.79 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -695,7 +683,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 44.73 77.28 45.03 ; + RECT 75.9 52.21 77.28 52.51 ; END END chanx_right_in[19] PIN ccff_head[0] @@ -703,7 +691,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 35.89 77.28 36.19 ; + RECT 75.9 46.77 77.28 47.07 ; END END ccff_head[0] PIN chanx_left_out[0] @@ -711,7 +699,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 19.57 1.38 19.87 ; + RECT 0 18.21 1.38 18.51 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -719,7 +707,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; + RECT 0 6.65 1.38 6.95 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -727,7 +715,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.05 1.38 10.35 ; + RECT 0 29.77 1.38 30.07 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -735,7 +723,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; + RECT 0 3.93 1.38 4.23 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -743,7 +731,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; + RECT 0 52.21 1.38 52.51 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -751,7 +739,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; + RECT 0 50.85 1.38 51.15 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -759,7 +747,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.93 1.38 21.23 ; + RECT 0 23.65 1.38 23.95 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -767,7 +755,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; + RECT 0 20.93 1.38 21.23 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -775,7 +763,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.29 1.38 22.59 ; + RECT 0 25.01 1.38 25.31 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -783,7 +771,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -791,7 +779,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.21 1.38 18.51 ; + RECT 0 5.29 1.38 5.59 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -799,7 +787,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -807,7 +795,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 15.49 1.38 15.79 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -815,7 +803,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; + RECT 0 10.73 1.38 11.03 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -823,7 +811,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 9.37 1.38 9.67 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -831,7 +819,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 12.09 1.38 12.39 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -839,7 +827,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.69 1.38 8.99 ; + RECT 0 53.57 1.38 53.87 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -847,7 +835,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 3.93 1.38 4.23 ; + RECT 0 19.57 1.38 19.87 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -855,7 +843,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.85 1.38 17.15 ; + RECT 0 40.65 1.38 40.95 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -863,7 +851,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; + RECT 0 13.45 1.38 13.75 ; END END chanx_left_out[19] PIN chanx_right_out[0] @@ -871,7 +859,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 52.89 77.28 53.19 ; + RECT 75.9 35.21 77.28 35.51 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -879,7 +867,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 61.73 77.28 62.03 ; + RECT 75.9 7.33 77.28 7.63 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -887,7 +875,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 27.05 77.28 27.35 ; + RECT 75.9 26.37 77.28 26.67 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -895,7 +883,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 59.01 77.28 59.31 ; + RECT 75.9 18.21 77.28 18.51 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -903,15 +891,15 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 55.61 77.28 55.91 ; + RECT 75.9 19.57 77.28 19.87 ; END END chanx_right_out[4] PIN chanx_right_out[5] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 74.91 0 75.05 1.36 ; + LAYER met3 ; + RECT 75.9 14.13 77.28 14.43 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -919,7 +907,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 8.69 77.28 8.99 ; + RECT 75.9 5.97 77.28 6.27 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -927,7 +915,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 14.13 77.28 14.43 ; + RECT 75.9 49.49 77.28 49.79 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -935,7 +923,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 22.29 77.28 22.59 ; + RECT 75.9 53.57 77.28 53.87 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -943,7 +931,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 60.37 77.28 60.67 ; + RECT 75.9 44.73 77.28 45.03 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -951,7 +939,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 17.53 77.28 17.83 ; + RECT 75.9 25.01 77.28 25.31 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -959,7 +947,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 3.93 77.28 4.23 ; + RECT 75.9 42.01 77.28 42.31 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -967,7 +955,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 30.45 77.28 30.75 ; + RECT 75.9 48.13 77.28 48.43 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -975,7 +963,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 42.01 77.28 42.31 ; + RECT 75.9 39.29 77.28 39.59 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -983,7 +971,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 28.41 77.28 28.71 ; + RECT 75.9 61.05 77.28 61.35 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -991,7 +979,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 33.17 77.28 33.47 ; + RECT 75.9 36.57 77.28 36.87 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -999,7 +987,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 5.29 77.28 5.59 ; + RECT 75.9 56.97 77.28 57.27 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1007,7 +995,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 10.05 77.28 10.35 ; + RECT 75.9 58.33 77.28 58.63 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1015,7 +1003,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 31.81 77.28 32.11 ; + RECT 75.9 59.69 77.28 59.99 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1023,145 +1011,193 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 34.53 77.28 34.83 ; + RECT 75.9 12.77 77.28 13.07 ; END END chanx_right_out[19] - PIN top_grid_pin_16_[0] + PIN bottom_grid_pin_0_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 63.92 24.91 65.28 ; + RECT 45.01 0 45.15 1.36 ; END - END top_grid_pin_16_[0] - PIN top_grid_pin_17_[0] + END bottom_grid_pin_0_[0] + PIN bottom_grid_pin_1_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 63.92 23.07 65.28 ; + RECT 19.71 0 19.85 1.36 ; END - END top_grid_pin_17_[0] - PIN top_grid_pin_18_[0] + END bottom_grid_pin_1_[0] + PIN bottom_grid_pin_2_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 63.92 43.77 65.28 ; + RECT 4.53 0 4.67 1.36 ; END - END top_grid_pin_18_[0] - PIN top_grid_pin_19_[0] + END bottom_grid_pin_2_[0] + PIN bottom_grid_pin_3_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 63.92 23.99 65.28 ; + RECT 22.47 0 22.61 1.36 ; END - END top_grid_pin_19_[0] - PIN top_grid_pin_20_[0] + END bottom_grid_pin_3_[0] + PIN bottom_grid_pin_4_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 10.05 63.92 10.19 65.28 ; + RECT 41.33 0 41.47 1.36 ; END - END top_grid_pin_20_[0] - PIN top_grid_pin_21_[0] + END bottom_grid_pin_4_[0] + PIN bottom_grid_pin_5_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 4.07 63.92 4.21 65.28 ; + RECT 42.25 0 42.39 1.36 ; END - END top_grid_pin_21_[0] - PIN top_grid_pin_22_[0] + END bottom_grid_pin_5_[0] + PIN bottom_grid_pin_6_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 63.92 11.11 65.28 ; + RECT 40.41 0 40.55 1.36 ; END - END top_grid_pin_22_[0] - PIN top_grid_pin_23_[0] + END bottom_grid_pin_6_[0] + PIN bottom_grid_pin_7_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 11.89 63.92 12.03 65.28 ; + RECT 24.31 0 24.45 1.36 ; END - END top_grid_pin_23_[0] - PIN top_grid_pin_24_[0] + END bottom_grid_pin_7_[0] + PIN bottom_grid_pin_8_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 6.83 63.92 6.97 65.28 ; + RECT 43.17 0 43.31 1.36 ; END - END top_grid_pin_24_[0] - PIN top_grid_pin_25_[0] + END bottom_grid_pin_8_[0] + PIN bottom_grid_pin_9_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 4.99 63.92 5.13 65.28 ; + RECT 57.89 0 58.03 1.36 ; END - END top_grid_pin_25_[0] - PIN top_grid_pin_26_[0] + END bottom_grid_pin_9_[0] + PIN bottom_grid_pin_10_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 63.92 7.89 65.28 ; + RECT 44.09 0 44.23 1.36 ; END - END top_grid_pin_26_[0] - PIN top_grid_pin_27_[0] + END bottom_grid_pin_10_[0] + PIN bottom_grid_pin_11_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 5.91 63.92 6.05 65.28 ; + RECT 58.81 0 58.95 1.36 ; END - END top_grid_pin_27_[0] - PIN top_grid_pin_28_[0] + END bottom_grid_pin_11_[0] + PIN bottom_grid_pin_12_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 63.92 58.03 65.28 ; + RECT 23.39 0 23.53 1.36 ; END - END top_grid_pin_28_[0] - PIN top_grid_pin_29_[0] + END bottom_grid_pin_12_[0] + PIN bottom_grid_pin_13_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 63.92 44.69 65.28 ; + RECT 17.87 0 18.01 1.36 ; END - END top_grid_pin_29_[0] - PIN top_grid_pin_30_[0] + END bottom_grid_pin_13_[0] + PIN bottom_grid_pin_14_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 63.92 45.61 65.28 ; + RECT 18.79 0 18.93 1.36 ; END - END top_grid_pin_30_[0] - PIN top_grid_pin_31_[0] + END bottom_grid_pin_14_[0] + PIN bottom_grid_pin_15_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 58.81 63.92 58.95 65.28 ; + RECT 16.95 0 17.09 1.36 ; END - END top_grid_pin_31_[0] + END bottom_grid_pin_15_[0] PIN ccff_tail[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 57.65 1.38 57.95 ; END END ccff_tail[0] + PIN CLB_SC_IN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.81 63.92 58.95 65.28 ; + END + END CLB_SC_IN + PIN CLB_SC_OUT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.55 0 21.69 1.36 ; + END + END CLB_SC_OUT + PIN SC_IN_TOP + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 63.92 70.45 65.28 ; + END + END SC_IN_TOP + PIN SC_IN_BOT + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 0 70.45 1.36 ; + END + END SC_IN_BOT + PIN SC_OUT_TOP + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.55 63.92 21.69 65.28 ; + END + END SC_OUT_TOP + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.63 0 20.77 1.36 ; + END + END SC_OUT_BOT PIN VDD DIRECTION INPUT ; USE POWER ; @@ -1250,34 +1286,34 @@ MACRO cbx_1__1_ RECT 76.36 62.475 77.28 62.645 ; RECT 0 62.475 3.68 62.645 ; RECT 76.36 59.755 77.28 59.925 ; - RECT 0 59.755 1.84 59.925 ; + RECT 0 59.755 3.68 59.925 ; RECT 76.36 57.035 77.28 57.205 ; - RECT 0 57.035 1.84 57.205 ; + RECT 0 57.035 3.68 57.205 ; RECT 76.36 54.315 77.28 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 73.6 51.595 77.28 51.765 ; + RECT 76.36 51.595 77.28 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 73.6 48.875 77.28 49.045 ; + RECT 76.36 48.875 77.28 49.045 ; RECT 0 48.875 1.84 49.045 ; RECT 76.36 46.155 77.28 46.325 ; RECT 0 46.155 1.84 46.325 ; RECT 76.36 43.435 77.28 43.605 ; - RECT 0 43.435 3.68 43.605 ; + RECT 0 43.435 1.84 43.605 ; RECT 76.36 40.715 77.28 40.885 ; - RECT 0 40.715 3.68 40.885 ; + RECT 0 40.715 1.84 40.885 ; RECT 76.36 37.995 77.28 38.165 ; - RECT 0 37.995 1.84 38.165 ; + RECT 0 37.995 3.68 38.165 ; RECT 76.36 35.275 77.28 35.445 ; - RECT 0 35.275 1.84 35.445 ; + RECT 0 35.275 3.68 35.445 ; RECT 76.36 32.555 77.28 32.725 ; RECT 0 32.555 1.84 32.725 ; RECT 76.36 29.835 77.28 30.005 ; RECT 0 29.835 1.84 30.005 ; RECT 76.36 27.115 77.28 27.285 ; - RECT 0 27.115 3.68 27.285 ; - RECT 76.36 24.395 77.28 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 76.36 21.675 77.28 21.845 ; + RECT 0 27.115 1.84 27.285 ; + RECT 73.6 24.395 77.28 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 73.6 21.675 77.28 21.845 ; RECT 0 21.675 1.84 21.845 ; RECT 76.36 18.955 77.28 19.125 ; RECT 0 18.955 1.84 19.125 ; @@ -1286,46 +1322,44 @@ MACRO cbx_1__1_ RECT 76.36 13.515 77.28 13.685 ; RECT 0 13.515 1.84 13.685 ; RECT 76.36 10.795 77.28 10.965 ; - RECT 0 10.795 3.68 10.965 ; + RECT 0 10.795 1.84 10.965 ; RECT 76.36 8.075 77.28 8.245 ; - RECT 0 8.075 3.68 8.245 ; - RECT 73.6 5.355 77.28 5.525 ; + RECT 0 8.075 1.84 8.245 ; + RECT 76.36 5.355 77.28 5.525 ; RECT 0 5.355 1.84 5.525 ; - RECT 73.6 2.635 77.28 2.805 ; + RECT 76.36 2.635 77.28 2.805 ; RECT 0 2.635 3.68 2.805 ; RECT 0 -0.085 77.28 0.085 ; LAYER met2 ; RECT 67.94 65.095 68.22 65.465 ; RECT 38.5 65.095 38.78 65.465 ; RECT 9.06 65.095 9.34 65.465 ; + RECT 20.11 1.54 20.37 1.86 ; RECT 67.94 -0.185 68.22 0.185 ; RECT 38.5 -0.185 38.78 0.185 ; RECT 9.06 -0.185 9.34 0.185 ; - POLYGON 77 65 77 0.28 75.33 0.28 75.33 1.64 74.63 1.64 74.63 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 65 3.79 65 3.79 63.64 4.49 63.64 4.49 65 4.71 65 4.71 63.64 5.41 63.64 5.41 65 5.63 65 5.63 63.64 6.33 63.64 6.33 65 6.55 65 6.55 63.64 7.25 63.64 7.25 65 7.47 65 7.47 63.64 8.17 63.64 8.17 65 9.77 65 9.77 63.64 10.47 63.64 10.47 65 10.69 65 10.69 63.64 11.39 63.64 11.39 65 11.61 65 11.61 63.64 12.31 63.64 12.31 65 22.65 65 22.65 63.64 23.35 63.64 23.35 65 23.57 65 23.57 63.64 24.27 63.64 24.27 65 24.49 65 24.49 63.64 25.19 63.64 25.19 65 43.35 65 43.35 63.64 44.05 63.64 44.05 65 44.27 65 44.27 63.64 44.97 63.64 44.97 65 45.19 65 45.19 63.64 45.89 63.64 45.89 65 57.61 65 57.61 63.64 58.31 63.64 58.31 65 58.53 65 58.53 63.64 59.23 63.64 59.23 65 ; + POLYGON 77 65 77 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 4.95 0.28 4.95 1.64 4.25 1.64 4.25 0.28 0.28 0.28 0.28 65 1.95 65 1.95 63.64 2.65 63.64 2.65 65 21.27 65 21.27 63.64 21.97 63.64 21.97 65 58.53 65 58.53 63.64 59.23 63.64 59.23 65 70.03 65 70.03 63.64 70.73 63.64 70.73 65 ; LAYER met3 ; POLYGON 68.245 65.445 68.245 65.44 68.46 65.44 68.46 65.12 68.245 65.12 68.245 65.115 67.915 65.115 67.915 65.12 67.7 65.12 67.7 65.44 67.915 65.44 67.915 65.445 ; POLYGON 38.805 65.445 38.805 65.44 39.02 65.44 39.02 65.12 38.805 65.12 38.805 65.115 38.475 65.115 38.475 65.12 38.26 65.12 38.26 65.44 38.475 65.44 38.475 65.445 ; POLYGON 9.365 65.445 9.365 65.44 9.58 65.44 9.58 65.12 9.365 65.12 9.365 65.115 9.035 65.115 9.035 65.12 8.82 65.12 8.82 65.44 9.035 65.44 9.035 65.445 ; - POLYGON 11.65 55.91 11.65 55.61 1.99 55.61 1.99 54.93 1.78 54.93 1.78 55.63 1.69 55.63 1.69 55.91 ; - POLYGON 75.63 45.72 75.63 45.4 75.25 45.4 75.25 45.41 74.37 45.41 74.37 45.71 75.25 45.71 75.25 45.72 ; - POLYGON 2.03 44.36 2.03 44.35 18.09 44.35 18.09 44.05 2.03 44.05 2.03 44.04 1.65 44.04 1.65 44.36 ; - POLYGON 75.5 42.99 75.5 42.97 76.05 42.97 76.05 42.69 18.25 42.69 18.25 42.99 ; - POLYGON 75.605 38.245 75.605 37.915 75.275 37.915 75.275 37.93 70.69 37.93 70.69 38.23 75.275 38.23 75.275 38.245 ; - POLYGON 76.05 31.43 76.05 31.15 75.5 31.15 75.5 31.13 74.37 31.13 74.37 31.43 ; + POLYGON 76.065 53.205 76.065 52.875 75.735 52.875 75.735 52.89 44.93 52.89 44.93 53.19 75.735 53.19 75.735 53.205 ; + POLYGON 75.59 44.35 75.59 44.07 75.5 44.07 75.5 43.355 75.275 43.355 75.275 43.685 75.29 43.685 75.29 44.05 61.49 44.05 61.49 44.35 ; + POLYGON 31.43 41.63 31.43 41.33 1.23 41.33 1.23 41.61 1.78 41.61 1.78 41.63 ; + POLYGON 75.63 40.28 75.63 39.96 75.25 39.96 75.25 39.97 62.87 39.97 62.87 40.27 75.25 40.27 75.25 40.28 ; + POLYGON 17.63 38.91 17.63 38.61 1.78 38.61 1.78 38.63 1.23 38.63 1.23 38.91 ; POLYGON 68.245 0.165 68.245 0.16 68.46 0.16 68.46 -0.16 68.245 -0.16 68.245 -0.165 67.915 -0.165 67.915 -0.16 67.7 -0.16 67.7 0.16 67.915 0.16 67.915 0.165 ; POLYGON 38.805 0.165 38.805 0.16 39.02 0.16 39.02 -0.16 38.805 -0.16 38.805 -0.165 38.475 -0.165 38.475 -0.16 38.26 -0.16 38.26 0.16 38.475 0.16 38.475 0.165 ; POLYGON 9.365 0.165 9.365 0.16 9.58 0.16 9.58 -0.16 9.365 -0.16 9.365 -0.165 9.035 -0.165 9.035 -0.16 8.82 -0.16 8.82 0.16 9.035 0.16 9.035 0.165 ; - POLYGON 76.88 64.88 76.88 62.43 75.5 62.43 75.5 61.33 76.88 61.33 76.88 61.07 75.5 61.07 75.5 59.97 76.88 59.97 76.88 59.71 75.5 59.71 75.5 58.61 76.88 58.61 76.88 58.35 75.5 58.35 75.5 57.25 76.88 57.25 76.88 56.31 75.5 56.31 75.5 55.21 76.88 55.21 76.88 54.95 75.5 54.95 75.5 53.85 76.88 53.85 76.88 53.59 75.5 53.59 75.5 52.49 76.88 52.49 76.88 52.23 75.5 52.23 75.5 51.13 76.88 51.13 76.88 50.87 75.5 50.87 75.5 49.77 76.88 49.77 76.88 49.51 75.5 49.51 75.5 48.41 76.88 48.41 76.88 48.15 75.5 48.15 75.5 47.05 76.88 47.05 76.88 46.79 75.5 46.79 75.5 45.69 76.88 45.69 76.88 45.43 75.5 45.43 75.5 44.33 76.88 44.33 76.88 44.07 75.5 44.07 75.5 42.97 76.88 42.97 76.88 42.71 75.5 42.71 75.5 41.61 76.88 41.61 76.88 41.35 75.5 41.35 75.5 40.25 76.88 40.25 76.88 39.99 75.5 39.99 75.5 38.89 76.88 38.89 76.88 37.95 75.5 37.95 75.5 36.85 76.88 36.85 76.88 36.59 75.5 36.59 75.5 35.49 76.88 35.49 76.88 35.23 75.5 35.23 75.5 34.13 76.88 34.13 76.88 33.87 75.5 33.87 75.5 32.77 76.88 32.77 76.88 32.51 75.5 32.51 75.5 31.41 76.88 31.41 76.88 31.15 75.5 31.15 75.5 30.05 76.88 30.05 76.88 29.11 75.5 29.11 75.5 28.01 76.88 28.01 76.88 27.75 75.5 27.75 75.5 26.65 76.88 26.65 76.88 26.39 75.5 26.39 75.5 25.29 76.88 25.29 76.88 25.03 75.5 25.03 75.5 23.93 76.88 23.93 76.88 22.99 75.5 22.99 75.5 21.89 76.88 21.89 76.88 20.95 75.5 20.95 75.5 19.85 76.88 19.85 76.88 19.59 75.5 19.59 75.5 18.49 76.88 18.49 76.88 18.23 75.5 18.23 75.5 17.13 76.88 17.13 76.88 16.19 75.5 16.19 75.5 15.09 76.88 15.09 76.88 14.83 75.5 14.83 75.5 13.73 76.88 13.73 76.88 13.47 75.5 13.47 75.5 12.37 76.88 12.37 76.88 12.11 75.5 12.11 75.5 11.01 76.88 11.01 76.88 10.75 75.5 10.75 75.5 9.65 76.88 9.65 76.88 9.39 75.5 9.39 75.5 8.29 76.88 8.29 76.88 8.03 75.5 8.03 75.5 6.93 76.88 6.93 76.88 5.99 75.5 5.99 75.5 4.89 76.88 4.89 76.88 4.63 75.5 4.63 75.5 3.53 76.88 3.53 76.88 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 12.37 1.78 12.37 1.78 13.47 0.4 13.47 0.4 13.73 1.78 13.73 1.78 14.83 0.4 14.83 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 64.88 ; + POLYGON 76.88 64.88 76.88 61.75 75.5 61.75 75.5 60.65 76.88 60.65 76.88 60.39 75.5 60.39 75.5 59.29 76.88 59.29 76.88 59.03 75.5 59.03 75.5 57.93 76.88 57.93 76.88 57.67 75.5 57.67 75.5 56.57 76.88 56.57 76.88 55.63 75.5 55.63 75.5 54.53 76.88 54.53 76.88 54.27 75.5 54.27 75.5 53.17 76.88 53.17 76.88 52.91 75.5 52.91 75.5 51.81 76.88 51.81 76.88 51.55 75.5 51.55 75.5 50.45 76.88 50.45 76.88 50.19 75.5 50.19 75.5 49.09 76.88 49.09 76.88 48.83 75.5 48.83 75.5 47.73 76.88 47.73 76.88 47.47 75.5 47.47 75.5 46.37 76.88 46.37 76.88 45.43 75.5 45.43 75.5 44.33 76.88 44.33 76.88 44.07 75.5 44.07 75.5 42.97 76.88 42.97 76.88 42.71 75.5 42.71 75.5 41.61 76.88 41.61 76.88 41.35 75.5 41.35 75.5 40.25 76.88 40.25 76.88 39.99 75.5 39.99 75.5 38.89 76.88 38.89 76.88 38.63 75.5 38.63 75.5 37.53 76.88 37.53 76.88 37.27 75.5 37.27 75.5 36.17 76.88 36.17 76.88 35.91 75.5 35.91 75.5 34.81 76.88 34.81 76.88 34.55 75.5 34.55 75.5 33.45 76.88 33.45 76.88 33.19 75.5 33.19 75.5 32.09 76.88 32.09 76.88 31.15 75.5 31.15 75.5 30.05 76.88 30.05 76.88 29.79 75.5 29.79 75.5 28.69 76.88 28.69 76.88 28.43 75.5 28.43 75.5 27.33 76.88 27.33 76.88 27.07 75.5 27.07 75.5 25.97 76.88 25.97 76.88 25.71 75.5 25.71 75.5 24.61 76.88 24.61 76.88 24.35 75.5 24.35 75.5 23.25 76.88 23.25 76.88 22.99 75.5 22.99 75.5 21.89 76.88 21.89 76.88 21.63 75.5 21.63 75.5 20.53 76.88 20.53 76.88 20.27 75.5 20.27 75.5 19.17 76.88 19.17 76.88 18.91 75.5 18.91 75.5 17.81 76.88 17.81 76.88 17.55 75.5 17.55 75.5 16.45 76.88 16.45 76.88 16.19 75.5 16.19 75.5 15.09 76.88 15.09 76.88 14.83 75.5 14.83 75.5 13.73 76.88 13.73 76.88 13.47 75.5 13.47 75.5 12.37 76.88 12.37 76.88 12.11 75.5 12.11 75.5 11.01 76.88 11.01 76.88 10.75 75.5 10.75 75.5 9.65 76.88 9.65 76.88 9.39 75.5 9.39 75.5 8.29 76.88 8.29 76.88 8.03 75.5 8.03 75.5 6.93 76.88 6.93 76.88 6.67 75.5 6.67 75.5 5.57 76.88 5.57 76.88 5.31 75.5 5.31 75.5 4.21 76.88 4.21 76.88 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 64.88 ; LAYER met1 ; POLYGON 77 64.76 77 63.08 76.52 63.08 76.52 62.04 77 62.04 77 60.36 76.52 60.36 76.52 59.32 77 59.32 77 57.64 76.52 57.64 76.52 56.6 77 56.6 77 54.92 76.52 54.92 76.52 53.88 77 53.88 77 52.2 76.52 52.2 76.52 51.16 77 51.16 77 49.48 76.52 49.48 76.52 48.44 77 48.44 77 46.76 76.52 46.76 76.52 45.72 77 45.72 77 44.04 76.52 44.04 76.52 43 77 43 77 41.32 76.52 41.32 76.52 40.28 77 40.28 77 38.6 76.52 38.6 76.52 37.56 77 37.56 77 35.88 76.52 35.88 76.52 34.84 77 34.84 77 33.16 76.52 33.16 76.52 32.12 77 32.12 77 30.44 76.52 30.44 76.52 29.4 77 29.4 77 27.72 76.52 27.72 76.52 26.68 77 26.68 77 25 76.52 25 76.52 23.96 77 23.96 77 22.28 76.52 22.28 76.52 21.24 77 21.24 77 19.56 76.52 19.56 76.52 18.52 77 18.52 77 16.84 76.52 16.84 76.52 15.8 77 15.8 77 14.12 76.52 14.12 76.52 13.08 77 13.08 77 11.4 76.52 11.4 76.52 10.36 77 10.36 77 8.68 76.52 8.68 76.52 7.64 77 7.64 77 5.96 76.52 5.96 76.52 4.92 77 4.92 77 3.24 76.52 3.24 76.52 2.2 77 2.2 77 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 ; LAYER met5 ; - POLYGON 74.08 62.08 74.08 57.84 70.88 57.84 70.88 48.24 74.08 48.24 74.08 37.44 70.88 37.44 70.88 27.84 74.08 27.84 74.08 17.04 70.88 17.04 70.88 7.44 74.08 7.44 74.08 3.2 3.2 3.2 3.2 7.44 6.4 7.44 6.4 17.04 3.2 17.04 3.2 27.84 6.4 27.84 6.4 37.44 3.2 37.44 3.2 48.24 6.4 48.24 6.4 57.84 3.2 57.84 3.2 62.08 ; + POLYGON 75.68 63.68 75.68 56.24 72.48 56.24 72.48 49.84 75.68 49.84 75.68 35.84 72.48 35.84 72.48 29.44 75.68 29.44 75.68 15.44 72.48 15.44 72.48 9.04 75.68 9.04 75.68 1.6 1.6 1.6 1.6 9.04 4.8 9.04 4.8 15.44 1.6 15.44 1.6 29.44 4.8 29.44 4.8 35.84 1.6 35.84 1.6 49.84 4.8 49.84 4.8 56.24 1.6 56.24 1.6 63.68 ; LAYER met4 ; POLYGON 76.88 64.88 76.88 0.4 68.78 0.4 68.78 1 67.38 1 67.38 0.4 54.06 0.4 54.06 1 52.66 1 52.66 0.4 39.34 0.4 39.34 1 37.94 1 37.94 0.4 24.62 0.4 24.62 1 23.22 1 23.22 0.4 9.9 0.4 9.9 1 8.5 1 8.5 0.4 0.4 0.4 0.4 64.88 8.5 64.88 8.5 64.28 9.9 64.28 9.9 64.88 23.22 64.88 23.22 64.28 24.62 64.28 24.62 64.88 37.94 64.88 37.94 64.28 39.34 64.28 39.34 64.88 52.66 64.88 52.66 64.28 54.06 64.28 54.06 64.88 67.38 64.88 67.38 64.28 68.78 64.28 68.78 64.88 ; LAYER li1 ; - RECT 47.465 64.47 48.215 65.015 ; - RECT 47.465 0.265 48.215 0.81 ; - RECT 0.34 0.34 76.94 64.94 ; + RECT 0.17 0.17 77.11 65.11 ; LAYER mcon ; RECT 76.965 65.195 77.135 65.365 ; RECT 76.505 65.195 76.675 65.365 ; @@ -1759,9 +1793,8 @@ MACRO cbx_1__1_ RECT 68.005 65.205 68.155 65.355 ; RECT 38.565 65.205 38.715 65.355 ; RECT 9.125 65.205 9.275 65.355 ; - RECT 44.545 63.505 44.695 63.655 ; - RECT 24.765 63.505 24.915 63.655 ; - RECT 6.825 63.505 6.975 63.655 ; + RECT 23.385 1.625 23.535 1.775 ; + RECT 22.465 1.625 22.615 1.775 ; RECT 68.005 -0.075 68.155 0.075 ; RECT 38.565 -0.075 38.715 0.075 ; RECT 9.125 -0.075 9.275 0.075 ; @@ -1769,14 +1802,18 @@ MACRO cbx_1__1_ RECT 67.98 65.18 68.18 65.38 ; RECT 38.54 65.18 38.74 65.38 ; RECT 9.1 65.18 9.3 65.38 ; - RECT 1.28 61.78 1.48 61.98 ; - RECT 1.28 35.26 1.48 35.46 ; - RECT 1.28 32.54 1.48 32.74 ; - RECT 75.8 22.34 76 22.54 ; - RECT 1.74 20.98 1.94 21.18 ; - RECT 1.28 18.26 1.48 18.46 ; - RECT 1.28 16.9 1.48 17.1 ; - RECT 1.74 10.1 1.94 10.3 ; + RECT 1.74 57.7 1.94 57.9 ; + RECT 1.74 53.62 1.94 53.82 ; + RECT 75.34 43.42 75.54 43.62 ; + RECT 75.8 39.34 76 39.54 ; + RECT 1.28 39.34 1.48 39.54 ; + RECT 75.34 36.62 75.54 36.82 ; + RECT 75.8 33.9 76 34.1 ; + RECT 1.74 23.7 1.94 23.9 ; + RECT 75.34 14.18 75.54 14.38 ; + RECT 1.74 6.7 1.94 6.9 ; + RECT 75.8 6.02 76 6.22 ; + RECT 1.28 3.98 1.48 4.18 ; RECT 67.98 -0.1 68.18 0.1 ; RECT 38.54 -0.1 38.74 0.1 ; RECT 9.1 -0.1 9.3 0.1 ; @@ -1784,93 +1821,10 @@ MACRO cbx_1__1_ RECT 67.98 65.18 68.18 65.38 ; RECT 38.54 65.18 38.74 65.38 ; RECT 9.1 65.18 9.3 65.38 ; - RECT 75.34 51.58 75.54 51.78 ; - RECT 1.74 36.62 1.94 36.82 ; + RECT 75.34 10.1 75.54 10.3 ; RECT 67.98 -0.1 68.18 0.1 ; RECT 38.54 -0.1 38.74 0.1 ; RECT 9.1 -0.1 9.3 0.1 ; - LAYER fieldpoly ; - RECT 0.14 0.14 77.14 65.14 ; - LAYER diff ; - RECT 0 0 77.28 65.28 ; - LAYER nwell ; - POLYGON 77.47 63.975 77.47 61.145 76.17 61.145 76.17 62.75 76.63 62.75 76.63 63.975 ; - POLYGON 3.87 63.975 3.87 62.37 2.03 62.37 2.03 61.145 -0.19 61.145 -0.19 63.975 ; - RECT 76.17 55.705 77.47 58.535 ; - RECT -0.19 55.705 2.03 58.535 ; - POLYGON 77.47 53.095 77.47 50.265 73.41 50.265 73.41 51.87 76.17 51.87 76.17 53.095 ; - RECT -0.19 50.265 2.03 53.095 ; - RECT 76.17 44.825 77.47 47.655 ; - RECT -0.19 44.825 2.03 47.655 ; - RECT 76.17 39.385 77.47 42.215 ; - POLYGON 3.87 42.215 3.87 40.61 2.03 40.61 2.03 39.385 -0.19 39.385 -0.19 42.215 ; - RECT 76.17 33.945 77.47 36.775 ; - RECT -0.19 33.945 2.03 36.775 ; - RECT 76.17 28.505 77.47 31.335 ; - RECT -0.19 28.505 2.03 31.335 ; - RECT 76.17 23.065 77.47 25.895 ; - POLYGON 3.87 25.895 3.87 24.29 2.03 24.29 2.03 23.065 -0.19 23.065 -0.19 25.895 ; - POLYGON 77.47 20.455 77.47 17.625 76.17 17.625 76.17 19.23 76.63 19.23 76.63 20.455 ; - RECT -0.19 17.625 2.03 20.455 ; - POLYGON 77.47 15.015 77.47 12.185 76.17 12.185 76.17 13.79 76.63 13.79 76.63 15.015 ; - RECT -0.19 12.185 2.03 15.015 ; - RECT 76.17 6.745 77.47 9.575 ; - POLYGON 3.87 9.575 3.87 7.97 2.03 7.97 2.03 6.745 -0.19 6.745 -0.19 9.575 ; - POLYGON 77.47 4.135 77.47 1.305 76.63 1.305 76.63 2.53 73.41 2.53 73.41 4.135 ; - POLYGON 2.03 4.135 2.03 2.91 3.87 2.91 3.87 1.305 -0.19 1.305 -0.19 4.135 ; - RECT 0 0 77.28 65.28 ; - LAYER pwell ; - RECT 70.51 65.23 70.73 65.4 ; - RECT 66.83 65.23 67.05 65.4 ; - RECT 63.15 65.23 63.37 65.4 ; - RECT 59.47 65.23 59.69 65.4 ; - RECT 55.79 65.23 56.01 65.4 ; - RECT 52.11 65.23 52.33 65.4 ; - RECT 48.43 65.23 48.65 65.4 ; - RECT 40.61 65.23 40.83 65.4 ; - RECT 36.93 65.23 37.15 65.4 ; - RECT 33.25 65.23 33.47 65.4 ; - RECT 29.57 65.23 29.79 65.4 ; - RECT 25.89 65.23 26.11 65.4 ; - RECT 22.21 65.23 22.43 65.4 ; - RECT 18.53 65.23 18.75 65.4 ; - RECT 14.85 65.23 15.07 65.4 ; - RECT 11.17 65.23 11.39 65.4 ; - RECT 7.49 65.23 7.71 65.4 ; - RECT 3.81 65.23 4.03 65.4 ; - RECT 0.13 65.23 0.35 65.4 ; - RECT 74.235 65.22 74.345 65.34 ; - RECT 44.335 65.22 44.445 65.34 ; - RECT 76.96 65.225 77.08 65.335 ; - RECT 47.06 65.225 47.18 65.335 ; - RECT 76.055 65.22 76.215 65.33 ; - RECT 46.155 65.22 46.315 65.33 ; - RECT 76.055 -0.05 76.215 0.06 ; - RECT 74.235 -0.06 74.345 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 76.96 -0.055 77.08 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 70.51 -0.12 70.73 0.05 ; - RECT 66.83 -0.12 67.05 0.05 ; - RECT 63.15 -0.12 63.37 0.05 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - RECT 14.85 -0.12 15.07 0.05 ; - RECT 11.17 -0.12 11.39 0.05 ; - RECT 7.49 -0.12 7.71 0.05 ; - RECT 3.81 -0.12 4.03 0.05 ; - RECT 0.13 -0.12 0.35 0.05 ; - RECT 0 0 77.28 65.28 ; LAYER OVERLAP ; POLYGON 0 0 0 65.28 77.28 65.28 77.28 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef index 4a3b19e..2527f95 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -383,7 +371,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 36.57 1.38 36.87 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -391,7 +379,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 12.77 1.38 13.07 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -399,7 +387,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; + RECT 0 33.85 1.38 34.15 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -407,7 +395,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 15.49 1.38 15.79 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -415,7 +403,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 54.25 1.38 54.55 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -423,7 +411,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 8.01 1.38 8.31 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -439,7 +427,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 35.21 1.38 35.51 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -447,7 +435,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 18.21 1.38 18.51 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -455,7 +443,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; + RECT 0 3.93 1.38 4.23 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -463,7 +451,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 3.93 1.38 4.23 ; + RECT 0 55.61 1.38 55.91 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -471,7 +459,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 14.13 1.38 14.43 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -479,7 +467,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 5.29 1.38 5.59 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -487,7 +475,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 11.41 1.38 11.71 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -495,7 +483,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 32.49 1.38 32.79 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -503,7 +491,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -511,7 +499,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; + RECT 0 41.33 1.38 41.63 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -519,7 +507,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 29.77 1.38 30.07 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -527,7 +515,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 56.97 1.38 57.27 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -535,7 +523,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_in[19] PIN chanx_right_in[0] @@ -543,7 +531,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 29.77 77.28 30.07 ; + RECT 75.9 41.33 77.28 41.63 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -551,7 +539,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 20.25 77.28 20.55 ; + RECT 75.9 50.17 77.28 50.47 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -559,7 +547,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 12.09 77.28 12.39 ; + RECT 75.9 39.29 77.28 39.59 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -567,7 +555,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 6.65 77.28 6.95 ; + RECT 75.9 31.13 77.28 31.43 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -575,7 +563,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 10.73 77.28 11.03 ; + RECT 75.9 34.53 77.28 34.83 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -583,7 +571,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 27.05 77.28 27.35 ; + RECT 75.9 12.09 77.28 12.39 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -591,7 +579,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 21.61 77.28 21.91 ; + RECT 75.9 27.05 77.28 27.35 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -599,7 +587,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 25.69 77.28 25.99 ; + RECT 75.9 14.81 77.28 15.11 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -607,15 +595,15 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 50.17 77.28 50.47 ; + RECT 75.9 56.97 77.28 57.27 ; END END chanx_right_in[8] PIN chanx_right_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 75.9 22.97 77.28 23.27 ; + LAYER met2 ; + RECT 74.91 0 75.05 1.36 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -623,7 +611,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 33.85 77.28 34.15 ; + RECT 75.9 58.33 77.28 58.63 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -631,7 +619,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 42.01 77.28 42.31 ; + RECT 75.9 18.89 77.28 19.19 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -639,7 +627,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 40.65 77.28 40.95 ; + RECT 75.9 55.61 77.28 55.91 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -647,7 +635,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 48.81 77.28 49.11 ; + RECT 75.9 37.25 77.28 37.55 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -655,7 +643,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 43.37 77.28 43.67 ; + RECT 75.9 25.69 77.28 25.99 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -663,7 +651,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 24.33 77.28 24.63 ; + RECT 75.9 32.49 77.28 32.79 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -671,7 +659,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 8.01 77.28 8.31 ; + RECT 75.9 17.53 77.28 17.83 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -679,7 +667,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 47.45 77.28 47.75 ; + RECT 75.9 16.17 77.28 16.47 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -687,7 +675,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 44.73 77.28 45.03 ; + RECT 75.9 28.41 77.28 28.71 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -695,7 +683,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 46.09 77.28 46.39 ; + RECT 75.9 22.97 77.28 23.27 ; END END chanx_right_in[19] PIN ccff_head[0] @@ -703,7 +691,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 52.89 77.28 53.19 ; + RECT 75.9 5.29 77.28 5.59 ; END END ccff_head[0] PIN chanx_left_out[0] @@ -711,7 +699,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 37.93 1.38 38.23 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -719,7 +707,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 25.69 1.38 25.99 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -727,7 +715,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -735,7 +723,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 10.05 1.38 10.35 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -743,7 +731,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 19.57 1.38 19.87 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -751,7 +739,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -759,7 +747,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.01 1.38 8.31 ; + RECT 0 16.85 1.38 17.15 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -767,7 +755,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -775,7 +763,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 27.05 1.38 27.35 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -783,15 +771,15 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.09 1.38 12.39 ; + RECT 0 59.69 1.38 59.99 ; END END chanx_left_out[9] PIN chanx_left_out[10] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 35.89 1.38 36.19 ; + LAYER met2 ; + RECT 3.61 0 3.75 1.36 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -799,7 +787,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 61.05 1.38 61.35 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -807,7 +795,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 42.69 1.38 42.99 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -815,15 +803,15 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; + RECT 0 6.65 1.38 6.95 ; END END chanx_left_out[13] PIN chanx_left_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 9.37 1.38 9.67 ; + LAYER met4 ; + RECT 4.45 0 4.75 1.36 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -831,7 +819,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -839,7 +827,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; + RECT 0 28.41 1.38 28.71 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -847,7 +835,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 5.29 1.38 5.59 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -855,7 +843,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -863,7 +851,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_out[19] PIN chanx_right_out[0] @@ -871,7 +859,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 14.81 77.28 15.11 ; + RECT 75.9 10.73 77.28 11.03 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -879,7 +867,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 5.29 77.28 5.59 ; + RECT 75.9 51.53 77.28 51.83 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -887,7 +875,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 17.53 77.28 17.83 ; + RECT 75.9 54.25 77.28 54.55 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -895,7 +883,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 18.89 77.28 19.19 ; + RECT 75.9 52.89 77.28 53.19 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -903,7 +891,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 55.61 77.28 55.91 ; + RECT 75.9 21.61 77.28 21.91 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -911,7 +899,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 36.57 77.28 36.87 ; + RECT 75.9 6.65 77.28 6.95 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -919,7 +907,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 35.21 77.28 35.51 ; + RECT 75.9 48.81 77.28 49.11 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -927,7 +915,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 31.13 77.28 31.43 ; + RECT 75.9 9.37 77.28 9.67 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -935,7 +923,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 32.49 77.28 32.79 ; + RECT 75.9 29.77 77.28 30.07 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -943,7 +931,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 13.45 77.28 13.75 ; + RECT 75.9 44.05 77.28 44.35 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -951,7 +939,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 58.33 77.28 58.63 ; + RECT 75.9 47.45 77.28 47.75 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -959,7 +947,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 28.41 77.28 28.71 ; + RECT 75.9 20.25 77.28 20.55 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -967,7 +955,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 54.25 77.28 54.55 ; + RECT 75.9 13.45 77.28 13.75 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -975,7 +963,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 37.93 77.28 38.23 ; + RECT 75.9 3.93 77.28 4.23 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -983,7 +971,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 16.17 77.28 16.47 ; + RECT 75.9 61.05 77.28 61.35 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -991,7 +979,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 51.53 77.28 51.83 ; + RECT 75.9 59.69 77.28 59.99 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -999,7 +987,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 56.97 77.28 57.27 ; + RECT 75.9 42.69 77.28 42.99 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1007,7 +995,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 9.37 77.28 9.67 ; + RECT 75.9 35.89 77.28 36.19 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1015,7 +1003,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 3.93 77.28 4.23 ; + RECT 75.9 24.33 77.28 24.63 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1023,7 +1011,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 39.29 77.28 39.59 ; + RECT 75.9 8.01 77.28 8.31 ; END END chanx_right_out[19] PIN top_grid_pin_0_[0] @@ -1031,17 +1019,225 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 63.92 45.61 65.28 ; + RECT 54.21 0 54.35 1.36 ; END END top_grid_pin_0_[0] - PIN ccff_tail[0] + PIN bottom_grid_pin_0_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 63.92 44.69 65.28 ; + RECT 45.01 0 45.15 1.36 ; + END + END bottom_grid_pin_0_[0] + PIN bottom_grid_pin_1_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.71 0 19.85 1.36 ; + END + END bottom_grid_pin_1_[0] + PIN bottom_grid_pin_2_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.53 0 4.67 1.36 ; + END + END bottom_grid_pin_2_[0] + PIN bottom_grid_pin_3_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.47 0 22.61 1.36 ; + END + END bottom_grid_pin_3_[0] + PIN bottom_grid_pin_4_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.33 0 41.47 1.36 ; + END + END bottom_grid_pin_4_[0] + PIN bottom_grid_pin_5_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.25 0 42.39 1.36 ; + END + END bottom_grid_pin_5_[0] + PIN bottom_grid_pin_6_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.41 0 40.55 1.36 ; + END + END bottom_grid_pin_6_[0] + PIN bottom_grid_pin_7_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.31 0 24.45 1.36 ; + END + END bottom_grid_pin_7_[0] + PIN bottom_grid_pin_8_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.17 0 43.31 1.36 ; + END + END bottom_grid_pin_8_[0] + PIN bottom_grid_pin_9_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.89 0 58.03 1.36 ; + END + END bottom_grid_pin_9_[0] + PIN bottom_grid_pin_10_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.09 0 44.23 1.36 ; + END + END bottom_grid_pin_10_[0] + PIN bottom_grid_pin_11_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.81 0 58.95 1.36 ; + END + END bottom_grid_pin_11_[0] + PIN bottom_grid_pin_12_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.39 0 23.53 1.36 ; + END + END bottom_grid_pin_12_[0] + PIN bottom_grid_pin_13_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.87 0 18.01 1.36 ; + END + END bottom_grid_pin_13_[0] + PIN bottom_grid_pin_14_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.79 0 18.93 1.36 ; + END + END bottom_grid_pin_14_[0] + PIN bottom_grid_pin_15_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.95 0 17.09 1.36 ; + END + END bottom_grid_pin_15_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 31.13 1.38 31.43 ; END END ccff_tail[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.07 63.92 73.21 65.28 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_IN[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.09 63.92 67.23 65.28 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.83 63.92 6.97 65.28 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] + PIN bottom_width_0_height_0__pin_0_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.13 0 55.27 1.36 ; + END + END bottom_width_0_height_0__pin_0_[0] + PIN bottom_width_0_height_0__pin_1_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 20.93 1.38 21.23 ; + END + END bottom_width_0_height_0__pin_1_upper[0] + PIN bottom_width_0_height_0__pin_1_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 75.9 46.09 77.28 46.39 ; + END + END bottom_width_0_height_0__pin_1_lower[0] + PIN SC_IN_TOP + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 24.33 1.38 24.63 ; + END + END SC_IN_TOP + PIN SC_IN_BOT + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 0 70.45 1.36 ; + END + END SC_IN_BOT + PIN SC_OUT_TOP + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.65 63.92 37.79 65.28 ; + END + END SC_OUT_TOP + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.63 0 20.77 1.36 ; + END + END SC_OUT_BOT PIN VDD DIRECTION INPUT ; USE POWER ; @@ -1130,26 +1326,26 @@ MACRO cbx_1__2_ RECT 76.36 62.475 77.28 62.645 ; RECT 0 62.475 3.68 62.645 ; RECT 76.36 59.755 77.28 59.925 ; - RECT 0 59.755 1.84 59.925 ; + RECT 0 59.755 3.68 59.925 ; RECT 76.36 57.035 77.28 57.205 ; - RECT 0 57.035 1.84 57.205 ; + RECT 0 57.035 3.68 57.205 ; RECT 76.36 54.315 77.28 54.485 ; RECT 0 54.315 1.84 54.485 ; RECT 76.36 51.595 77.28 51.765 ; RECT 0 51.595 1.84 51.765 ; RECT 76.36 48.875 77.28 49.045 ; - RECT 0 48.875 3.68 49.045 ; + RECT 0 48.875 1.84 49.045 ; RECT 76.36 46.155 77.28 46.325 ; RECT 0 46.155 3.68 46.325 ; RECT 76.36 43.435 77.28 43.605 ; - RECT 0 43.435 1.84 43.605 ; + RECT 0 43.435 3.68 43.605 ; RECT 76.36 40.715 77.28 40.885 ; RECT 0 40.715 1.84 40.885 ; RECT 76.36 37.995 77.28 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 76.36 35.275 77.28 35.445 ; + RECT 73.6 35.275 77.28 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 76.36 32.555 77.28 32.725 ; + RECT 73.6 32.555 77.28 32.725 ; RECT 0 32.555 1.84 32.725 ; RECT 76.36 29.835 77.28 30.005 ; RECT 0 29.835 1.84 30.005 ; @@ -1166,11 +1362,11 @@ MACRO cbx_1__2_ RECT 76.36 13.515 77.28 13.685 ; RECT 0 13.515 1.84 13.685 ; RECT 76.36 10.795 77.28 10.965 ; - RECT 0 10.795 1.84 10.965 ; + RECT 0 10.795 3.68 10.965 ; RECT 76.36 8.075 77.28 8.245 ; - RECT 0 8.075 1.84 8.245 ; + RECT 0 8.075 3.68 8.245 ; RECT 76.36 5.355 77.28 5.525 ; - RECT 0 5.355 3.68 5.525 ; + RECT 0 5.355 1.84 5.525 ; RECT 76.36 2.635 77.28 2.805 ; RECT 0 2.635 3.68 2.805 ; RECT 0 -0.085 77.28 0.085 ; @@ -1178,35 +1374,34 @@ MACRO cbx_1__2_ RECT 67.94 65.095 68.22 65.465 ; RECT 38.5 65.095 38.78 65.465 ; RECT 9.06 65.095 9.34 65.465 ; + RECT 41.73 1.54 41.99 1.86 ; RECT 67.94 -0.185 68.22 0.185 ; RECT 38.5 -0.185 38.78 0.185 ; RECT 9.06 -0.185 9.34 0.185 ; - POLYGON 77 65 77 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 65 44.27 65 44.27 63.64 44.97 63.64 44.97 65 45.19 65 45.19 63.64 45.89 63.64 45.89 65 ; + POLYGON 77 65 77 0.28 75.33 0.28 75.33 1.64 74.63 1.64 74.63 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 4.95 0.28 4.95 1.64 4.25 1.64 4.25 0.28 4.03 0.28 4.03 1.64 3.33 1.64 3.33 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 65 6.55 65 6.55 63.64 7.25 63.64 7.25 65 37.37 65 37.37 63.64 38.07 63.64 38.07 65 66.81 65 66.81 63.64 67.51 63.64 67.51 65 72.79 65 72.79 63.64 73.49 63.64 73.49 65 ; LAYER met3 ; POLYGON 68.245 65.445 68.245 65.44 68.46 65.44 68.46 65.12 68.245 65.12 68.245 65.115 67.915 65.115 67.915 65.12 67.7 65.12 67.7 65.44 67.915 65.44 67.915 65.445 ; POLYGON 38.805 65.445 38.805 65.44 39.02 65.44 39.02 65.12 38.805 65.12 38.805 65.115 38.475 65.115 38.475 65.12 38.26 65.12 38.26 65.44 38.475 65.44 38.475 65.445 ; POLYGON 9.365 65.445 9.365 65.44 9.58 65.44 9.58 65.12 9.365 65.12 9.365 65.115 9.035 65.115 9.035 65.12 8.82 65.12 8.82 65.44 9.035 65.44 9.035 65.445 ; - POLYGON 8.89 44.35 8.89 44.05 1.78 44.05 1.78 44.07 1.23 44.07 1.23 44.35 ; - POLYGON 10.73 29.39 10.73 29.09 1.99 29.09 1.99 28.41 1.78 28.41 1.78 29.11 1.69 29.11 1.69 29.39 ; - POLYGON 16.25 22.59 16.25 22.29 1.78 22.29 1.78 22.31 1.23 22.31 1.23 22.59 ; - POLYGON 11.65 17.15 11.65 16.85 1.99 16.85 1.99 16.17 1.78 16.17 1.78 16.87 1.69 16.87 1.69 17.15 ; - POLYGON 76.05 11.71 76.05 11.43 75.5 11.43 75.5 11.41 61.49 11.41 61.49 11.71 ; - POLYGON 9.81 11.71 9.81 11.41 1.23 11.41 1.23 11.69 1.78 11.69 1.78 11.71 ; - POLYGON 1.99 9.67 1.99 8.99 8.43 8.99 8.43 8.69 1.69 8.69 1.69 8.97 1.78 8.97 1.78 9.67 ; + POLYGON 21.31 57.95 21.31 57.65 1.23 57.65 1.23 57.93 1.78 57.93 1.78 57.95 ; + POLYGON 2.03 44.36 2.03 44.35 6.13 44.35 6.13 44.05 2.03 44.05 2.03 44.04 1.65 44.04 1.65 44.36 ; + POLYGON 75.63 29.4 75.63 29.08 75.25 29.08 75.25 29.09 71.61 29.09 71.61 29.39 75.25 29.39 75.25 29.4 ; + POLYGON 76.05 28.03 76.05 27.75 75.5 27.75 75.5 27.73 58.73 27.73 58.73 28.03 ; + POLYGON 2.03 12.4 2.03 12.39 31.89 12.39 31.89 12.09 2.03 12.09 2.03 12.08 1.65 12.08 1.65 12.4 ; + POLYGON 76.05 6.27 76.05 5.99 75.5 5.99 75.5 5.97 64.25 5.97 64.25 6.27 ; + POLYGON 9.81 4.91 9.81 4.61 1.99 4.61 1.99 3.93 1.78 3.93 1.78 4.63 1.69 4.63 1.69 4.91 ; POLYGON 68.245 0.165 68.245 0.16 68.46 0.16 68.46 -0.16 68.245 -0.16 68.245 -0.165 67.915 -0.165 67.915 -0.16 67.7 -0.16 67.7 0.16 67.915 0.16 67.915 0.165 ; POLYGON 38.805 0.165 38.805 0.16 39.02 0.16 39.02 -0.16 38.805 -0.16 38.805 -0.165 38.475 -0.165 38.475 -0.16 38.26 -0.16 38.26 0.16 38.475 0.16 38.475 0.165 ; POLYGON 9.365 0.165 9.365 0.16 9.58 0.16 9.58 -0.16 9.365 -0.16 9.365 -0.165 9.035 -0.165 9.035 -0.16 8.82 -0.16 8.82 0.16 9.035 0.16 9.035 0.165 ; - POLYGON 76.88 64.88 76.88 59.03 75.5 59.03 75.5 57.93 76.88 57.93 76.88 57.67 75.5 57.67 75.5 56.57 76.88 56.57 76.88 56.31 75.5 56.31 75.5 55.21 76.88 55.21 76.88 54.95 75.5 54.95 75.5 53.85 76.88 53.85 76.88 53.59 75.5 53.59 75.5 52.49 76.88 52.49 76.88 52.23 75.5 52.23 75.5 51.13 76.88 51.13 76.88 50.87 75.5 50.87 75.5 49.77 76.88 49.77 76.88 49.51 75.5 49.51 75.5 48.41 76.88 48.41 76.88 48.15 75.5 48.15 75.5 47.05 76.88 47.05 76.88 46.79 75.5 46.79 75.5 45.69 76.88 45.69 76.88 45.43 75.5 45.43 75.5 44.33 76.88 44.33 76.88 44.07 75.5 44.07 75.5 42.97 76.88 42.97 76.88 42.71 75.5 42.71 75.5 41.61 76.88 41.61 76.88 41.35 75.5 41.35 75.5 40.25 76.88 40.25 76.88 39.99 75.5 39.99 75.5 38.89 76.88 38.89 76.88 38.63 75.5 38.63 75.5 37.53 76.88 37.53 76.88 37.27 75.5 37.27 75.5 36.17 76.88 36.17 76.88 35.91 75.5 35.91 75.5 34.81 76.88 34.81 76.88 34.55 75.5 34.55 75.5 33.45 76.88 33.45 76.88 33.19 75.5 33.19 75.5 32.09 76.88 32.09 76.88 31.83 75.5 31.83 75.5 30.73 76.88 30.73 76.88 30.47 75.5 30.47 75.5 29.37 76.88 29.37 76.88 29.11 75.5 29.11 75.5 28.01 76.88 28.01 76.88 27.75 75.5 27.75 75.5 26.65 76.88 26.65 76.88 26.39 75.5 26.39 75.5 25.29 76.88 25.29 76.88 25.03 75.5 25.03 75.5 23.93 76.88 23.93 76.88 23.67 75.5 23.67 75.5 22.57 76.88 22.57 76.88 22.31 75.5 22.31 75.5 21.21 76.88 21.21 76.88 20.95 75.5 20.95 75.5 19.85 76.88 19.85 76.88 19.59 75.5 19.59 75.5 18.49 76.88 18.49 76.88 18.23 75.5 18.23 75.5 17.13 76.88 17.13 76.88 16.87 75.5 16.87 75.5 15.77 76.88 15.77 76.88 15.51 75.5 15.51 75.5 14.41 76.88 14.41 76.88 14.15 75.5 14.15 75.5 13.05 76.88 13.05 76.88 12.79 75.5 12.79 75.5 11.69 76.88 11.69 76.88 11.43 75.5 11.43 75.5 10.33 76.88 10.33 76.88 10.07 75.5 10.07 75.5 8.97 76.88 8.97 76.88 8.71 75.5 8.71 75.5 7.61 76.88 7.61 76.88 7.35 75.5 7.35 75.5 6.25 76.88 6.25 76.88 5.99 75.5 5.99 75.5 4.89 76.88 4.89 76.88 4.63 75.5 4.63 75.5 3.53 76.88 3.53 76.88 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 64.88 ; + POLYGON 76.88 64.88 76.88 61.75 75.5 61.75 75.5 60.65 76.88 60.65 76.88 60.39 75.5 60.39 75.5 59.29 76.88 59.29 76.88 59.03 75.5 59.03 75.5 57.93 76.88 57.93 76.88 57.67 75.5 57.67 75.5 56.57 76.88 56.57 76.88 56.31 75.5 56.31 75.5 55.21 76.88 55.21 76.88 54.95 75.5 54.95 75.5 53.85 76.88 53.85 76.88 53.59 75.5 53.59 75.5 52.49 76.88 52.49 76.88 52.23 75.5 52.23 75.5 51.13 76.88 51.13 76.88 50.87 75.5 50.87 75.5 49.77 76.88 49.77 76.88 49.51 75.5 49.51 75.5 48.41 76.88 48.41 76.88 48.15 75.5 48.15 75.5 47.05 76.88 47.05 76.88 46.79 75.5 46.79 75.5 45.69 76.88 45.69 76.88 44.75 75.5 44.75 75.5 43.65 76.88 43.65 76.88 43.39 75.5 43.39 75.5 42.29 76.88 42.29 76.88 42.03 75.5 42.03 75.5 40.93 76.88 40.93 76.88 39.99 75.5 39.99 75.5 38.89 76.88 38.89 76.88 37.95 75.5 37.95 75.5 36.85 76.88 36.85 76.88 36.59 75.5 36.59 75.5 35.49 76.88 35.49 76.88 35.23 75.5 35.23 75.5 34.13 76.88 34.13 76.88 33.19 75.5 33.19 75.5 32.09 76.88 32.09 76.88 31.83 75.5 31.83 75.5 30.73 76.88 30.73 76.88 30.47 75.5 30.47 75.5 29.37 76.88 29.37 76.88 29.11 75.5 29.11 75.5 28.01 76.88 28.01 76.88 27.75 75.5 27.75 75.5 26.65 76.88 26.65 76.88 26.39 75.5 26.39 75.5 25.29 76.88 25.29 76.88 25.03 75.5 25.03 75.5 23.93 76.88 23.93 76.88 23.67 75.5 23.67 75.5 22.57 76.88 22.57 76.88 22.31 75.5 22.31 75.5 21.21 76.88 21.21 76.88 20.95 75.5 20.95 75.5 19.85 76.88 19.85 76.88 19.59 75.5 19.59 75.5 18.49 76.88 18.49 76.88 18.23 75.5 18.23 75.5 17.13 76.88 17.13 76.88 16.87 75.5 16.87 75.5 15.77 76.88 15.77 76.88 15.51 75.5 15.51 75.5 14.41 76.88 14.41 76.88 14.15 75.5 14.15 75.5 13.05 76.88 13.05 76.88 12.79 75.5 12.79 75.5 11.69 76.88 11.69 76.88 11.43 75.5 11.43 75.5 10.33 76.88 10.33 76.88 10.07 75.5 10.07 75.5 8.97 76.88 8.97 76.88 8.71 75.5 8.71 75.5 7.61 76.88 7.61 76.88 7.35 75.5 7.35 75.5 6.25 76.88 6.25 76.88 5.99 75.5 5.99 75.5 4.89 76.88 4.89 76.88 4.63 75.5 4.63 75.5 3.53 76.88 3.53 76.88 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 12.37 1.78 12.37 1.78 13.47 0.4 13.47 0.4 13.73 1.78 13.73 1.78 14.83 0.4 14.83 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 64.88 ; + LAYER met4 ; + POLYGON 76.88 64.88 76.88 0.4 68.78 0.4 68.78 1 67.38 1 67.38 0.4 54.06 0.4 54.06 1 52.66 1 52.66 0.4 39.34 0.4 39.34 1 37.94 1 37.94 0.4 24.62 0.4 24.62 1 23.22 1 23.22 0.4 9.9 0.4 9.9 1 8.5 1 8.5 0.4 5.15 0.4 5.15 1.76 4.05 1.76 4.05 0.4 0.4 0.4 0.4 64.88 8.5 64.88 8.5 64.28 9.9 64.28 9.9 64.88 23.22 64.88 23.22 64.28 24.62 64.28 24.62 64.88 37.94 64.88 37.94 64.28 39.34 64.28 39.34 64.88 52.66 64.88 52.66 64.28 54.06 64.28 54.06 64.88 67.38 64.88 67.38 64.28 68.78 64.28 68.78 64.88 ; LAYER met1 ; POLYGON 77 64.76 77 63.08 76.52 63.08 76.52 62.04 77 62.04 77 60.36 76.52 60.36 76.52 59.32 77 59.32 77 57.64 76.52 57.64 76.52 56.6 77 56.6 77 54.92 76.52 54.92 76.52 53.88 77 53.88 77 52.2 76.52 52.2 76.52 51.16 77 51.16 77 49.48 76.52 49.48 76.52 48.44 77 48.44 77 46.76 76.52 46.76 76.52 45.72 77 45.72 77 44.04 76.52 44.04 76.52 43 77 43 77 41.32 76.52 41.32 76.52 40.28 77 40.28 77 38.6 76.52 38.6 76.52 37.56 77 37.56 77 35.88 76.52 35.88 76.52 34.84 77 34.84 77 33.16 76.52 33.16 76.52 32.12 77 32.12 77 30.44 76.52 30.44 76.52 29.4 77 29.4 77 27.72 76.52 27.72 76.52 26.68 77 26.68 77 25 76.52 25 76.52 23.96 77 23.96 77 22.28 76.52 22.28 76.52 21.24 77 21.24 77 19.56 76.52 19.56 76.52 18.52 77 18.52 77 16.84 76.52 16.84 76.52 15.8 77 15.8 77 14.12 76.52 14.12 76.52 13.08 77 13.08 77 11.4 76.52 11.4 76.52 10.36 77 10.36 77 8.68 76.52 8.68 76.52 7.64 77 7.64 77 5.96 76.52 5.96 76.52 4.92 77 4.92 77 3.24 76.52 3.24 76.52 2.2 77 2.2 77 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 ; LAYER met5 ; - POLYGON 74.08 62.08 74.08 57.84 70.88 57.84 70.88 48.24 74.08 48.24 74.08 37.44 70.88 37.44 70.88 27.84 74.08 27.84 74.08 17.04 70.88 17.04 70.88 7.44 74.08 7.44 74.08 3.2 3.2 3.2 3.2 7.44 6.4 7.44 6.4 17.04 3.2 17.04 3.2 27.84 6.4 27.84 6.4 37.44 3.2 37.44 3.2 48.24 6.4 48.24 6.4 57.84 3.2 57.84 3.2 62.08 ; - LAYER met4 ; - POLYGON 76.88 64.88 76.88 0.4 68.78 0.4 68.78 1 67.38 1 67.38 0.4 54.06 0.4 54.06 1 52.66 1 52.66 0.4 39.34 0.4 39.34 1 37.94 1 37.94 0.4 24.62 0.4 24.62 1 23.22 1 23.22 0.4 9.9 0.4 9.9 1 8.5 1 8.5 0.4 0.4 0.4 0.4 64.88 8.5 64.88 8.5 64.28 9.9 64.28 9.9 64.88 23.22 64.88 23.22 64.28 24.62 64.28 24.62 64.88 37.94 64.88 37.94 64.28 39.34 64.28 39.34 64.88 52.66 64.88 52.66 64.28 54.06 64.28 54.06 64.88 67.38 64.88 67.38 64.28 68.78 64.28 68.78 64.88 ; + POLYGON 75.68 63.68 75.68 56.24 72.48 56.24 72.48 49.84 75.68 49.84 75.68 35.84 72.48 35.84 72.48 29.44 75.68 29.44 75.68 15.44 72.48 15.44 72.48 9.04 75.68 9.04 75.68 1.6 1.6 1.6 1.6 9.04 4.8 9.04 4.8 15.44 1.6 15.44 1.6 29.44 4.8 29.44 4.8 35.84 1.6 35.84 1.6 49.84 4.8 49.84 4.8 56.24 1.6 56.24 1.6 63.68 ; LAYER li1 ; - RECT 47.465 64.47 48.215 65.015 ; - RECT 47.465 0.265 48.215 0.81 ; - RECT 0.34 0.34 76.94 64.94 ; + RECT 0.17 0.17 77.11 65.11 ; LAYER mcon ; RECT 76.965 65.195 77.135 65.365 ; RECT 76.505 65.195 76.675 65.365 ; @@ -1640,6 +1835,9 @@ MACRO cbx_1__2_ RECT 68.005 65.205 68.155 65.355 ; RECT 38.565 65.205 38.715 65.355 ; RECT 9.125 65.205 9.275 65.355 ; + RECT 37.645 63.505 37.795 63.655 ; + RECT 58.805 1.625 58.955 1.775 ; + RECT 16.945 1.625 17.095 1.775 ; RECT 68.005 -0.075 68.155 0.075 ; RECT 38.565 -0.075 38.715 0.075 ; RECT 9.125 -0.075 9.275 0.075 ; @@ -1647,11 +1845,17 @@ MACRO cbx_1__2_ RECT 67.98 65.18 68.18 65.38 ; RECT 38.54 65.18 38.74 65.38 ; RECT 9.1 65.18 9.3 65.38 ; - RECT 75.8 57.02 76 57.22 ; - RECT 1.74 55.66 1.94 55.86 ; - RECT 75.8 37.98 76 38.18 ; - RECT 75.34 20.3 75.54 20.5 ; - RECT 1.28 20.3 1.48 20.5 ; + RECT 1.74 59.74 1.94 59.94 ; + RECT 75.8 48.86 76 49.06 ; + RECT 1.28 47.5 1.48 47.7 ; + RECT 75.8 42.74 76 42.94 ; + RECT 1.74 40.02 1.94 40.22 ; + RECT 75.34 31.18 75.54 31.38 ; + RECT 75.8 29.82 76 30.02 ; + RECT 1.28 20.98 1.48 21.18 ; + RECT 1.74 19.62 1.94 19.82 ; + RECT 75.8 8.06 76 8.26 ; + RECT 1.28 5.34 1.48 5.54 ; RECT 67.98 -0.1 68.18 0.1 ; RECT 38.54 -0.1 38.74 0.1 ; RECT 9.1 -0.1 9.3 0.1 ; @@ -1659,91 +1863,11 @@ MACRO cbx_1__2_ RECT 67.98 65.18 68.18 65.38 ; RECT 38.54 65.18 38.74 65.38 ; RECT 9.1 65.18 9.3 65.38 ; + RECT 1.74 36.62 1.94 36.82 ; + RECT 1.74 14.18 1.94 14.38 ; RECT 67.98 -0.1 68.18 0.1 ; RECT 38.54 -0.1 38.74 0.1 ; RECT 9.1 -0.1 9.3 0.1 ; - LAYER fieldpoly ; - RECT 0.14 0.14 77.14 65.14 ; - LAYER diff ; - RECT 0 0 77.28 65.28 ; - LAYER nwell ; - POLYGON 77.47 63.975 77.47 61.145 76.17 61.145 76.17 62.75 76.63 62.75 76.63 63.975 ; - POLYGON 3.87 63.975 3.87 62.37 2.03 62.37 2.03 61.145 -0.19 61.145 -0.19 63.975 ; - RECT 76.17 55.705 77.47 58.535 ; - RECT -0.19 55.705 2.03 58.535 ; - RECT 76.17 50.265 77.47 53.095 ; - RECT -0.19 50.265 2.03 53.095 ; - POLYGON 77.47 47.655 77.47 44.825 76.17 44.825 76.17 46.43 76.63 46.43 76.63 47.655 ; - POLYGON 3.87 47.655 3.87 46.05 2.03 46.05 2.03 44.825 -0.19 44.825 -0.19 47.655 ; - RECT 76.17 39.385 77.47 42.215 ; - RECT -0.19 39.385 2.03 42.215 ; - RECT 76.17 33.945 77.47 36.775 ; - RECT -0.19 33.945 2.03 36.775 ; - RECT 76.17 28.505 77.47 31.335 ; - RECT -0.19 28.505 2.03 31.335 ; - RECT 76.17 23.065 77.47 25.895 ; - RECT -0.19 23.065 2.03 25.895 ; - RECT 76.17 17.625 77.47 20.455 ; - RECT -0.19 17.625 2.03 20.455 ; - RECT 76.17 12.185 77.47 15.015 ; - RECT -0.19 12.185 2.03 15.015 ; - RECT 76.17 6.745 77.47 9.575 ; - RECT -0.19 6.745 2.03 9.575 ; - POLYGON 77.47 4.135 77.47 1.305 76.63 1.305 76.63 2.53 76.17 2.53 76.17 4.135 ; - RECT -0.19 1.305 3.87 4.135 ; - RECT 0 0 77.28 65.28 ; - LAYER pwell ; - RECT 70.51 65.23 70.73 65.4 ; - RECT 66.83 65.23 67.05 65.4 ; - RECT 63.15 65.23 63.37 65.4 ; - RECT 59.47 65.23 59.69 65.4 ; - RECT 55.79 65.23 56.01 65.4 ; - RECT 52.11 65.23 52.33 65.4 ; - RECT 48.43 65.23 48.65 65.4 ; - RECT 40.61 65.23 40.83 65.4 ; - RECT 36.93 65.23 37.15 65.4 ; - RECT 33.25 65.23 33.47 65.4 ; - RECT 29.57 65.23 29.79 65.4 ; - RECT 25.89 65.23 26.11 65.4 ; - RECT 22.21 65.23 22.43 65.4 ; - RECT 18.53 65.23 18.75 65.4 ; - RECT 14.85 65.23 15.07 65.4 ; - RECT 11.17 65.23 11.39 65.4 ; - RECT 7.49 65.23 7.71 65.4 ; - RECT 3.81 65.23 4.03 65.4 ; - RECT 0.13 65.23 0.35 65.4 ; - RECT 74.235 65.22 74.345 65.34 ; - RECT 44.335 65.22 44.445 65.34 ; - RECT 76.96 65.225 77.08 65.335 ; - RECT 47.06 65.225 47.18 65.335 ; - RECT 76.055 65.22 76.215 65.33 ; - RECT 46.155 65.22 46.315 65.33 ; - RECT 76.055 -0.05 76.215 0.06 ; - RECT 74.235 -0.06 74.345 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 76.96 -0.055 77.08 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 70.51 -0.12 70.73 0.05 ; - RECT 66.83 -0.12 67.05 0.05 ; - RECT 63.15 -0.12 63.37 0.05 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - RECT 14.85 -0.12 15.07 0.05 ; - RECT 11.17 -0.12 11.39 0.05 ; - RECT 7.49 -0.12 7.71 0.05 ; - RECT 3.81 -0.12 4.03 0.05 ; - RECT 0.13 -0.12 0.35 0.05 ; - RECT 0 0 77.28 65.28 ; LAYER OVERLAP ; POLYGON 0 0 0 65.28 77.28 65.28 77.28 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef index 780ba6b..36f257d 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -383,7 +371,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 56.05 0 56.19 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -391,7 +379,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; + RECT 24.77 0 24.91 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -399,15 +387,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 50.53 0 50.67 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; + LAYER met4 ; + RECT 20.09 0 20.39 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -415,15 +403,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.59 0 32.73 1.36 ; + RECT 49.61 0 49.75 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + LAYER met4 ; + RECT 43.09 0 43.39 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -431,7 +419,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 4.45 0 4.75 1.36 ; + RECT 9.05 0 9.35 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -439,7 +427,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 49.53 0 49.83 1.36 ; + RECT 50.45 0 50.75 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -447,7 +435,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 6.29 0 6.59 1.36 ; + RECT 44.93 0 45.23 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -455,7 +443,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 8.13 0 8.43 1.36 ; + RECT 5.37 0 5.67 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -463,15 +451,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; + LAYER met4 ; + RECT 48.61 0 48.91 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -479,7 +467,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 0 7.89 1.36 ; + RECT 52.37 0 52.51 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -487,15 +475,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 23.77 0 24.07 1.36 ; + RECT 46.77 0 47.07 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 8.67 0 8.81 1.36 ; + LAYER met4 ; + RECT 29.29 0 29.59 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -503,7 +491,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 31.13 0 31.43 1.36 ; + RECT 21.93 0 22.23 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -511,15 +499,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.99 0 28.13 1.36 ; + RECT 48.69 0 48.83 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 44.09 0 44.23 1.36 ; + LAYER met4 ; + RECT 27.45 0 27.75 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -527,7 +515,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 29.29 0 29.59 1.36 ; + RECT 7.21 0 7.51 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -535,7 +523,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 27.45 0 27.75 1.36 ; + RECT 23.77 0 24.07 1.36 ; END END chany_bottom_in[19] PIN chany_top_in[0] @@ -543,7 +531,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 74.8 22.15 76.16 ; + RECT 54.21 74.8 54.35 76.16 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -551,7 +539,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.09 74.8 44.23 76.16 ; + RECT 48.23 74.8 48.37 76.16 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -559,7 +547,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 74.8 45.15 76.16 ; + RECT 57.43 74.8 57.57 76.16 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -567,7 +555,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 74.8 54.35 76.16 ; + RECT 27.53 74.8 27.67 76.16 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -575,7 +563,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 74.8 42.39 76.16 ; + RECT 56.05 74.8 56.19 76.16 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -583,7 +571,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 74.8 53.43 76.16 ; + RECT 23.85 74.8 23.99 76.16 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -591,7 +579,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 74.8 51.59 76.16 ; + RECT 26.61 74.8 26.75 76.16 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -599,7 +587,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 74.8 47.91 76.16 ; + RECT 46.39 74.8 46.53 76.16 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -607,7 +595,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 74.8 50.67 76.16 ; + RECT 47.31 74.8 47.45 76.16 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -615,7 +603,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.83 74.8 29.97 76.16 ; + RECT 24.77 74.8 24.91 76.16 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -623,15 +611,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 74.8 21.23 76.16 ; + RECT 62.03 74.8 62.17 76.16 ; END END chany_top_in[10] PIN chany_top_in[11] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 46.85 74.8 46.99 76.16 ; + LAYER met4 ; + RECT 44.93 74.8 45.23 76.16 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -639,31 +627,31 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 74.8 52.51 76.16 ; + RECT 49.15 74.8 49.29 76.16 ; END END chany_top_in[12] PIN chany_top_in[13] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 48.69 74.8 48.83 76.16 ; + LAYER met4 ; + RECT 9.05 74.8 9.35 76.16 ; END END chany_top_in[13] PIN chany_top_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 49.61 74.8 49.75 76.16 ; + LAYER met4 ; + RECT 48.61 74.8 48.91 76.16 ; END END chany_top_in[14] PIN chany_top_in[15] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 28.91 74.8 29.05 76.16 ; + LAYER met4 ; + RECT 46.77 74.8 47.07 76.16 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -671,31 +659,31 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.05 74.8 33.19 76.16 ; + RECT 40.87 74.8 41.01 76.16 ; END END chany_top_in[16] PIN chany_top_in[17] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 24.77 74.8 24.91 76.16 ; + LAYER met4 ; + RECT 5.37 74.8 5.67 76.16 ; END END chany_top_in[17] PIN chany_top_in[18] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 27.07 74.8 27.21 76.16 ; + LAYER met4 ; + RECT 23.77 74.8 24.07 76.16 ; END END chany_top_in[18] PIN chany_top_in[19] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 27.99 74.8 28.13 76.16 ; + LAYER met4 ; + RECT 7.21 74.8 7.51 76.16 ; END END chany_top_in[19] PIN ccff_head[0] @@ -703,7 +691,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.13 74.8 32.27 76.16 ; + RECT 43.63 74.8 43.77 76.16 ; END END ccff_head[0] PIN chany_bottom_out[0] @@ -711,7 +699,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; + RECT 51.45 0 51.59 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -719,7 +707,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -727,7 +715,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 0 53.43 1.36 ; + RECT 42.71 0 42.85 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -735,7 +723,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.67 0 31.81 1.36 ; + RECT 22.01 0 22.15 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -743,7 +731,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.91 0 29.05 1.36 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -751,7 +739,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; + RECT 27.53 0 27.67 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -759,7 +747,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; + RECT 29.37 0 29.51 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -767,7 +755,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; + RECT 22.93 0 23.07 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -775,23 +763,23 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; + RECT 23.85 0 23.99 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + LAYER met4 ; + RECT 36.65 0 36.95 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 27.07 0 27.21 1.36 ; + LAYER met4 ; + RECT 38.49 0 38.79 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -799,7 +787,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.75 0 30.89 1.36 ; + RECT 47.31 0 47.45 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -807,39 +795,39 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 0 57.11 1.36 ; + RECT 43.63 0 43.77 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 32.97 0 33.27 1.36 ; + LAYER met2 ; + RECT 62.03 0 62.17 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 12.73 0 13.03 1.36 ; + LAYER met2 ; + RECT 7.29 0 7.43 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 47.69 0 47.99 1.36 ; + LAYER met2 ; + RECT 26.61 0 26.75 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 42.17 0 42.47 1.36 ; + LAYER met2 ; + RECT 30.29 0 30.43 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -847,7 +835,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 14.57 0 14.87 1.36 ; + RECT 56.89 0 57.19 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -855,7 +843,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 45.85 0 46.15 1.36 ; + RECT 52.29 0 52.59 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -863,23 +851,23 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 28.45 0 28.59 1.36 ; END END chany_bottom_out[19] PIN chany_top_out[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 46.77 74.8 47.07 76.16 ; + LAYER met2 ; + RECT 51.91 74.8 52.05 76.16 ; END END chany_top_out[0] PIN chany_top_out[1] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 16.41 74.8 16.71 76.16 ; + LAYER met2 ; + RECT 45.47 74.8 45.61 76.16 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -887,15 +875,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 74.8 43.31 76.16 ; + RECT 52.83 74.8 52.97 76.16 ; END END chany_top_out[2] PIN chany_top_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 14.57 74.8 14.87 76.16 ; + LAYER met2 ; + RECT 44.55 74.8 44.69 76.16 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -903,7 +891,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 74.8 56.19 76.16 ; + RECT 42.71 74.8 42.85 76.16 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -911,7 +899,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 74.8 46.07 76.16 ; + RECT 50.07 74.8 50.21 76.16 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -919,15 +907,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 74.8 23.07 76.16 ; + RECT 20.17 74.8 20.31 76.16 ; END END chany_top_out[6] PIN chany_top_out[7] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 27.45 74.8 27.75 76.16 ; + LAYER met2 ; + RECT 22.93 74.8 23.07 76.16 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -935,7 +923,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 9.59 74.8 9.73 76.16 ; + RECT 8.21 74.8 8.35 76.16 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -943,7 +931,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.17 74.8 20.31 76.16 ; + RECT 21.09 74.8 21.23 76.16 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -951,7 +939,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 74.8 41.47 76.16 ; + RECT 33.51 74.8 33.65 76.16 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -959,7 +947,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 74.8 38.71 76.16 ; + RECT 29.37 74.8 29.51 76.16 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -967,7 +955,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.81 74.8 58.95 76.16 ; + RECT 50.99 74.8 51.13 76.16 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -975,7 +963,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 74.8 58.03 76.16 ; + RECT 30.29 74.8 30.43 76.16 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -983,7 +971,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 74.8 57.11 76.16 ; + RECT 28.45 74.8 28.59 76.16 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -991,7 +979,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 74.8 23.99 76.16 ; + RECT 22.01 74.8 22.15 76.16 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -999,7 +987,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 74.8 35.95 76.16 ; + RECT 36.27 74.8 36.41 76.16 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -1007,7 +995,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 74.8 35.03 76.16 ; + RECT 6.37 74.8 6.51 76.16 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1015,7 +1003,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.97 74.8 34.11 76.16 ; + RECT 31.21 74.8 31.35 76.16 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1023,23 +1011,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.75 74.8 30.89 76.16 ; + RECT 7.29 74.8 7.43 76.16 ; END END chany_top_out[19] - PIN right_grid_pin_52_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 40.65 66.24 40.95 ; - END - END right_grid_pin_52_[0] PIN left_grid_pin_0_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + LAYER met2 ; + RECT 20.17 0 20.31 1.36 ; END END left_grid_pin_0_[0] PIN ccff_tail[0] @@ -1047,9 +1027,57 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 64.86 40.65 66.24 40.95 ; END END ccff_tail[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 27.73 1.38 28.03 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_IN[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 62.41 1.38 62.71 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 61.05 1.38 61.35 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] + PIN right_width_0_height_0__pin_0_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.09 0 21.23 1.36 ; + END + END right_width_0_height_0__pin_0_[0] + PIN right_width_0_height_0__pin_1_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.87 74.8 64.01 76.16 ; + END + END right_width_0_height_0__pin_1_upper[0] + PIN right_width_0_height_0__pin_1_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.89 0 58.03 1.36 ; + END + END right_width_0_height_0__pin_1_lower[0] PIN VDD DIRECTION INPUT ; USE POWER ; @@ -1149,49 +1177,49 @@ MACRO cby_0__1_ RECT 0 67.915 3.68 68.085 ; RECT 65.32 65.195 66.24 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 65.32 62.475 66.24 62.645 ; + RECT 65.78 62.475 66.24 62.645 ; RECT 0 62.475 3.68 62.645 ; RECT 65.78 59.755 66.24 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 62.56 57.035 66.24 57.205 ; + RECT 65.78 57.035 66.24 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 62.56 54.315 66.24 54.485 ; + RECT 65.78 54.315 66.24 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 62.56 51.595 66.24 51.765 ; + RECT 65.32 51.595 66.24 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 62.56 48.875 66.24 49.045 ; + RECT 65.32 48.875 66.24 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 64.4 46.155 66.24 46.325 ; + RECT 62.56 46.155 66.24 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 64.4 43.435 66.24 43.605 ; + RECT 62.56 43.435 66.24 43.605 ; RECT 0 43.435 3.68 43.605 ; RECT 65.32 40.715 66.24 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 65.32 37.995 66.24 38.165 ; + RECT 64.4 37.995 66.24 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 65.78 35.275 66.24 35.445 ; + RECT 64.4 35.275 66.24 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 64.4 32.555 66.24 32.725 ; + RECT 65.78 32.555 66.24 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 64.4 29.835 66.24 30.005 ; + RECT 65.78 29.835 66.24 30.005 ; RECT 0 29.835 3.68 30.005 ; RECT 65.78 27.115 66.24 27.285 ; RECT 0 27.115 3.68 27.285 ; RECT 65.78 24.395 66.24 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 65.78 21.675 66.24 21.845 ; + RECT 64.4 21.675 66.24 21.845 ; RECT 0 21.675 3.68 21.845 ; RECT 64.4 18.955 66.24 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 64.4 16.235 66.24 16.405 ; + RECT 62.56 16.235 66.24 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 65.32 13.515 66.24 13.685 ; + RECT 62.56 13.515 66.24 13.685 ; RECT 0 13.515 3.68 13.685 ; RECT 65.32 10.795 66.24 10.965 ; RECT 0 10.795 3.68 10.965 ; RECT 65.32 8.075 66.24 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; + RECT 65.78 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; RECT 65.78 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; @@ -1201,26 +1229,21 @@ MACRO cby_0__1_ POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 75.76 65.84 41.35 64.46 41.35 64.46 40.25 65.84 40.25 65.84 0.4 0.4 0.4 0.4 2.85 1.78 2.85 1.78 3.95 0.4 3.95 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 75.76 ; + POLYGON 65.84 75.76 65.84 41.35 64.46 41.35 64.46 40.25 65.84 40.25 65.84 0.4 0.4 0.4 0.4 2.85 1.78 2.85 1.78 3.95 0.4 3.95 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 75.76 ; LAYER met2 ; RECT 55.06 75.975 55.34 76.345 ; RECT 25.62 75.975 25.9 76.345 ; - RECT 46.33 74.3 46.59 74.62 ; - RECT 30.23 74.3 30.49 74.62 ; - RECT 50.93 1.54 51.19 1.86 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 75.88 65.96 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 32.09 0.28 32.09 1.64 31.39 1.64 31.39 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 27.49 0.28 27.49 1.64 26.79 1.64 26.79 0.28 9.09 0.28 9.09 1.64 8.39 1.64 8.39 0.28 8.17 0.28 8.17 1.64 7.47 1.64 7.47 0.28 0.28 0.28 0.28 75.88 9.31 75.88 9.31 74.52 10.01 74.52 10.01 75.88 19.89 75.88 19.89 74.52 20.59 74.52 20.59 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 22.65 75.88 22.65 74.52 23.35 74.52 23.35 75.88 23.57 75.88 23.57 74.52 24.27 74.52 24.27 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 26.79 75.88 26.79 74.52 27.49 74.52 27.49 75.88 27.71 75.88 27.71 74.52 28.41 74.52 28.41 75.88 28.63 75.88 28.63 74.52 29.33 74.52 29.33 75.88 29.55 75.88 29.55 74.52 30.25 74.52 30.25 75.88 30.47 75.88 30.47 74.52 31.17 74.52 31.17 75.88 31.85 75.88 31.85 74.52 32.55 74.52 32.55 75.88 32.77 75.88 32.77 74.52 33.47 74.52 33.47 75.88 33.69 75.88 33.69 74.52 34.39 74.52 34.39 75.88 34.61 75.88 34.61 74.52 35.31 74.52 35.31 75.88 35.53 75.88 35.53 74.52 36.23 74.52 36.23 75.88 38.29 75.88 38.29 74.52 38.99 74.52 38.99 75.88 41.05 75.88 41.05 74.52 41.75 74.52 41.75 75.88 41.97 75.88 41.97 74.52 42.67 74.52 42.67 75.88 42.89 75.88 42.89 74.52 43.59 74.52 43.59 75.88 43.81 75.88 43.81 74.52 44.51 74.52 44.51 75.88 44.73 75.88 44.73 74.52 45.43 74.52 45.43 75.88 45.65 75.88 45.65 74.52 46.35 74.52 46.35 75.88 46.57 75.88 46.57 74.52 47.27 74.52 47.27 75.88 47.49 75.88 47.49 74.52 48.19 74.52 48.19 75.88 48.41 75.88 48.41 74.52 49.11 74.52 49.11 75.88 49.33 75.88 49.33 74.52 50.03 74.52 50.03 75.88 50.25 75.88 50.25 74.52 50.95 74.52 50.95 75.88 51.17 75.88 51.17 74.52 51.87 74.52 51.87 75.88 52.09 75.88 52.09 74.52 52.79 74.52 52.79 75.88 53.01 75.88 53.01 74.52 53.71 74.52 53.71 75.88 53.93 75.88 53.93 74.52 54.63 74.52 54.63 75.88 55.77 75.88 55.77 74.52 56.47 74.52 56.47 75.88 56.69 75.88 56.69 74.52 57.39 74.52 57.39 75.88 57.61 75.88 57.61 74.52 58.31 74.52 58.31 75.88 58.53 75.88 58.53 74.52 59.23 74.52 59.23 75.88 ; + POLYGON 65.96 75.88 65.96 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 0.28 0.28 0.28 75.88 6.09 75.88 6.09 74.52 6.79 74.52 6.79 75.88 7.01 75.88 7.01 74.52 7.71 74.52 7.71 75.88 7.93 75.88 7.93 74.52 8.63 74.52 8.63 75.88 19.89 75.88 19.89 74.52 20.59 74.52 20.59 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 22.65 75.88 22.65 74.52 23.35 74.52 23.35 75.88 23.57 75.88 23.57 74.52 24.27 74.52 24.27 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 26.33 75.88 26.33 74.52 27.03 74.52 27.03 75.88 27.25 75.88 27.25 74.52 27.95 74.52 27.95 75.88 28.17 75.88 28.17 74.52 28.87 74.52 28.87 75.88 29.09 75.88 29.09 74.52 29.79 74.52 29.79 75.88 30.01 75.88 30.01 74.52 30.71 74.52 30.71 75.88 30.93 75.88 30.93 74.52 31.63 74.52 31.63 75.88 33.23 75.88 33.23 74.52 33.93 74.52 33.93 75.88 35.99 75.88 35.99 74.52 36.69 74.52 36.69 75.88 40.59 75.88 40.59 74.52 41.29 74.52 41.29 75.88 42.43 75.88 42.43 74.52 43.13 74.52 43.13 75.88 43.35 75.88 43.35 74.52 44.05 74.52 44.05 75.88 44.27 75.88 44.27 74.52 44.97 74.52 44.97 75.88 45.19 75.88 45.19 74.52 45.89 74.52 45.89 75.88 46.11 75.88 46.11 74.52 46.81 74.52 46.81 75.88 47.03 75.88 47.03 74.52 47.73 74.52 47.73 75.88 47.95 75.88 47.95 74.52 48.65 74.52 48.65 75.88 48.87 75.88 48.87 74.52 49.57 74.52 49.57 75.88 49.79 75.88 49.79 74.52 50.49 74.52 50.49 75.88 50.71 75.88 50.71 74.52 51.41 74.52 51.41 75.88 51.63 75.88 51.63 74.52 52.33 74.52 52.33 75.88 52.55 75.88 52.55 74.52 53.25 74.52 53.25 75.88 53.93 75.88 53.93 74.52 54.63 74.52 54.63 75.88 55.77 75.88 55.77 74.52 56.47 74.52 56.47 75.88 57.15 75.88 57.15 74.52 57.85 74.52 57.85 75.88 61.75 75.88 61.75 74.52 62.45 74.52 62.45 75.88 63.59 75.88 63.59 74.52 64.29 74.52 64.29 75.88 ; LAYER met4 ; - POLYGON 65.84 75.76 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 50.23 0.4 50.23 1.76 49.13 1.76 49.13 0.4 48.39 0.4 48.39 1.76 47.29 1.76 47.29 0.4 46.55 0.4 46.55 1.76 45.45 1.76 45.45 0.4 42.87 0.4 42.87 1.76 41.77 1.76 41.77 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 33.67 0.4 33.67 1.76 32.57 1.76 32.57 0.4 31.83 0.4 31.83 1.76 30.73 1.76 30.73 0.4 29.99 0.4 29.99 1.76 28.89 1.76 28.89 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 24.47 0.4 24.47 1.76 23.37 1.76 23.37 0.4 15.27 0.4 15.27 1.76 14.17 1.76 14.17 0.4 13.43 0.4 13.43 1.76 12.33 1.76 12.33 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 8.83 0.4 8.83 1.76 7.73 1.76 7.73 0.4 6.99 0.4 6.99 1.76 5.89 1.76 5.89 0.4 5.15 0.4 5.15 1.76 4.05 1.76 4.05 0.4 0.4 0.4 0.4 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 14.17 75.76 14.17 74.4 15.27 74.4 15.27 75.76 16.01 75.76 16.01 74.4 17.11 74.4 17.11 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 27.05 75.76 27.05 74.4 28.15 74.4 28.15 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 46.37 75.76 46.37 74.4 47.47 74.4 47.47 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; + POLYGON 65.84 75.76 65.84 0.4 57.59 0.4 57.59 1.76 56.49 1.76 56.49 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 51.15 0.4 51.15 1.76 50.05 1.76 50.05 0.4 49.31 0.4 49.31 1.76 48.21 1.76 48.21 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 45.63 0.4 45.63 1.76 44.53 1.76 44.53 0.4 43.79 0.4 43.79 1.76 42.69 1.76 42.69 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 39.19 0.4 39.19 1.76 38.09 1.76 38.09 0.4 37.35 0.4 37.35 1.76 36.25 1.76 36.25 0.4 29.99 0.4 29.99 1.76 28.89 1.76 28.89 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 24.47 0.4 24.47 1.76 23.37 1.76 23.37 0.4 22.63 0.4 22.63 1.76 21.53 1.76 21.53 0.4 20.79 0.4 20.79 1.76 19.69 1.76 19.69 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 75.76 4.97 75.76 4.97 74.4 6.07 74.4 6.07 75.76 6.81 75.76 6.81 74.4 7.91 74.4 7.91 75.76 8.65 75.76 8.65 74.4 9.75 74.4 9.75 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 23.37 75.76 23.37 74.4 24.47 74.4 24.47 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 44.53 75.76 44.53 74.4 45.63 74.4 45.63 75.76 46.37 75.76 46.37 74.4 47.47 74.4 47.47 75.76 48.21 75.76 48.21 74.4 49.31 74.4 49.31 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; LAYER met1 ; POLYGON 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; LAYER met5 ; - POLYGON 63.04 72.96 63.04 63.28 59.84 63.28 59.84 53.68 63.04 53.68 63.04 42.88 59.84 42.88 59.84 33.28 63.04 33.28 63.04 22.48 59.84 22.48 59.84 12.88 63.04 12.88 63.04 3.2 3.2 3.2 3.2 12.88 6.4 12.88 6.4 22.48 3.2 22.48 3.2 33.28 6.4 33.28 6.4 42.88 3.2 42.88 3.2 53.68 6.4 53.68 6.4 63.28 3.2 63.28 3.2 72.96 ; + POLYGON 64.64 74.56 64.64 61.68 61.44 61.68 61.44 55.28 64.64 55.28 64.64 41.28 61.44 41.28 61.44 34.88 64.64 34.88 64.64 20.88 61.44 20.88 61.44 14.48 64.64 14.48 64.64 1.6 1.6 1.6 1.6 14.48 4.8 14.48 4.8 20.88 1.6 20.88 1.6 34.88 4.8 34.88 4.8 41.28 1.6 41.28 1.6 55.28 4.8 55.28 4.8 61.68 1.6 61.68 1.6 74.56 ; LAYER li1 ; - RECT 47.465 75.35 48.215 75.895 ; - RECT 47.465 0.265 48.215 0.81 ; - RECT 0.34 0.34 65.9 75.82 ; + RECT 0.17 0.17 66.07 75.99 ; LAYER mcon ; RECT 65.925 76.075 66.095 76.245 ; RECT 65.465 76.075 65.635 76.245 ; @@ -1621,102 +1644,22 @@ MACRO cby_0__1_ LAYER via ; RECT 55.125 76.085 55.275 76.235 ; RECT 25.685 76.085 25.835 76.235 ; - RECT 22.925 74.385 23.075 74.535 ; - RECT 9.585 74.385 9.735 74.535 ; + RECT 31.205 74.385 31.355 74.535 ; + RECT 51.445 1.625 51.595 1.775 ; + RECT 7.285 1.625 7.435 1.775 ; RECT 55.125 -0.075 55.275 0.075 ; RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; RECT 55.1 76.06 55.3 76.26 ; RECT 25.66 76.06 25.86 76.26 ; - RECT 1.28 62.46 1.48 62.66 ; - RECT 1.28 40.7 1.48 40.9 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; RECT 55.1 76.06 55.3 76.26 ; RECT 25.66 76.06 25.86 76.26 ; + RECT 1.74 3.3 1.94 3.5 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; - LAYER fieldpoly ; - RECT 0.14 0.14 66.1 76.02 ; - LAYER diff ; - RECT 0 0 66.24 76.16 ; - LAYER nwell ; - POLYGON 66.43 74.855 66.43 72.025 65.13 72.025 65.13 73.63 65.59 73.63 65.59 74.855 ; - RECT -0.19 72.025 3.87 74.855 ; - RECT 65.13 66.585 66.43 69.415 ; - RECT -0.19 66.585 3.87 69.415 ; - POLYGON 66.43 63.975 66.43 61.145 65.59 61.145 65.59 62.37 65.13 62.37 65.13 63.975 ; - RECT -0.19 61.145 3.87 63.975 ; - POLYGON 66.43 58.535 66.43 55.705 62.37 55.705 62.37 57.31 65.59 57.31 65.59 58.535 ; - RECT -0.19 55.705 3.87 58.535 ; - POLYGON 66.43 53.095 66.43 50.265 62.37 50.265 62.37 51.87 65.59 51.87 65.59 53.095 ; - RECT -0.19 50.265 3.87 53.095 ; - POLYGON 66.43 47.655 66.43 44.825 64.21 44.825 64.21 46.43 65.59 46.43 65.59 47.655 ; - RECT -0.19 44.825 3.87 47.655 ; - POLYGON 66.43 42.215 66.43 39.385 65.13 39.385 65.13 40.99 65.59 40.99 65.59 42.215 ; - POLYGON 2.03 42.215 2.03 40.99 3.87 40.99 3.87 39.385 -0.19 39.385 -0.19 42.215 ; - RECT 65.59 33.945 66.43 36.775 ; - RECT -0.19 33.945 3.87 36.775 ; - POLYGON 66.43 31.335 66.43 28.505 65.59 28.505 65.59 29.73 64.21 29.73 64.21 31.335 ; - RECT -0.19 28.505 3.87 31.335 ; - RECT 65.59 23.065 66.43 25.895 ; - RECT -0.19 23.065 3.87 25.895 ; - POLYGON 66.43 20.455 66.43 17.625 64.21 17.625 64.21 19.23 65.59 19.23 65.59 20.455 ; - RECT -0.19 17.625 3.87 20.455 ; - POLYGON 66.43 15.015 66.43 12.185 65.13 12.185 65.13 13.79 65.59 13.79 65.59 15.015 ; - RECT -0.19 12.185 3.87 15.015 ; - RECT 65.13 6.745 66.43 9.575 ; - RECT -0.19 6.745 3.87 9.575 ; - RECT 65.59 1.305 66.43 4.135 ; - RECT -0.19 1.305 3.87 4.135 ; - RECT 0 0 66.24 76.16 ; - LAYER pwell ; - RECT 59.47 76.11 59.69 76.28 ; - RECT 55.79 76.11 56.01 76.28 ; - RECT 52.11 76.11 52.33 76.28 ; - RECT 48.43 76.11 48.65 76.28 ; - RECT 40.61 76.11 40.83 76.28 ; - RECT 36.93 76.11 37.15 76.28 ; - RECT 33.25 76.11 33.47 76.28 ; - RECT 29.57 76.11 29.79 76.28 ; - RECT 25.89 76.11 26.11 76.28 ; - RECT 22.21 76.11 22.43 76.28 ; - RECT 18.53 76.11 18.75 76.28 ; - RECT 14.85 76.11 15.07 76.28 ; - RECT 11.17 76.11 11.39 76.28 ; - RECT 7.49 76.11 7.71 76.28 ; - RECT 3.81 76.11 4.03 76.28 ; - RECT 0.13 76.11 0.35 76.28 ; - RECT 63.195 76.1 63.305 76.22 ; - RECT 44.335 76.1 44.445 76.22 ; - RECT 65.92 76.105 66.04 76.215 ; - RECT 47.06 76.105 47.18 76.215 ; - RECT 65.015 76.1 65.175 76.21 ; - RECT 46.155 76.1 46.315 76.21 ; - RECT 65.015 -0.05 65.175 0.06 ; - RECT 63.195 -0.06 63.305 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 65.92 -0.055 66.04 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - RECT 14.85 -0.12 15.07 0.05 ; - RECT 11.17 -0.12 11.39 0.05 ; - RECT 7.49 -0.12 7.71 0.05 ; - RECT 3.81 -0.12 4.03 0.05 ; - RECT 0.13 -0.12 0.35 0.05 ; - RECT 0 0 66.24 76.16 ; LAYER OVERLAP ; POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef index 79b5e95..0740927 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -374,8 +362,8 @@ MACRO cby_1__1_ DIRECTION INPUT ; USE CLOCK ; PORT - LAYER met2 ; - RECT 2.23 74.8 2.37 76.16 ; + LAYER met3 ; + RECT 0 3.25 1.38 3.55 ; END END prog_clk[0] PIN chany_bottom_in[0] @@ -383,7 +371,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; + RECT 31.21 0 31.35 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -391,7 +379,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 0 22.15 1.36 ; + RECT 33.05 0 33.19 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -399,7 +387,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; + RECT 27.07 0 27.21 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -407,7 +395,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.17 0 20.31 1.36 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -415,7 +403,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + RECT 40.87 0 41.01 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -423,7 +411,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 49.61 0 49.75 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -431,7 +419,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; + RECT 32.13 0 32.27 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -439,7 +427,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 0 35.03 1.36 ; + RECT 42.71 0 42.85 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -447,7 +435,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; + RECT 24.77 0 24.91 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -455,7 +443,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + RECT 41.79 0 41.93 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -463,7 +451,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; + RECT 29.83 0 29.97 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -471,7 +459,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.83 0 29.97 1.36 ; + RECT 53.29 0 53.43 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -479,7 +467,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; + RECT 56.05 0 56.19 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -487,7 +475,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 9.13 0 9.27 1.36 ; + RECT 44.09 0 44.23 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -495,7 +483,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.79 0 41.93 1.36 ; + RECT 22.47 0 22.61 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -503,7 +491,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -511,15 +499,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; + RECT 23.85 0 23.99 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 22.85 0 23.15 1.36 ; + LAYER met2 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -527,7 +515,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.25 0 19.39 1.36 ; + RECT 27.99 0 28.13 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -535,7 +523,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 0 28.59 1.36 ; + RECT 59.27 0 59.41 1.36 ; END END chany_bottom_in[19] PIN chany_top_in[0] @@ -543,7 +531,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 74.8 37.79 76.16 ; + RECT 53.75 74.8 53.89 76.16 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -551,7 +539,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 74.8 24.91 76.16 ; + RECT 36.73 74.8 36.87 76.16 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -559,7 +547,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.03 74.8 39.17 76.16 ; + RECT 28.45 74.8 28.59 76.16 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -567,7 +555,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 74.8 27.67 76.16 ; + RECT 45.01 74.8 45.15 76.16 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -575,7 +563,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 74.8 48.37 76.16 ; + RECT 27.53 74.8 27.67 76.16 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -583,7 +571,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.59 74.8 32.73 76.16 ; + RECT 51.91 74.8 52.05 76.16 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -591,7 +579,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 74.8 44.69 76.16 ; + RECT 15.11 74.8 15.25 76.16 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -599,7 +587,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.43 74.8 34.57 76.16 ; + RECT 46.39 74.8 46.53 76.16 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -607,7 +595,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 74.8 47.45 76.16 ; + RECT 40.87 74.8 41.01 76.16 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -615,7 +603,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 74.8 29.51 76.16 ; + RECT 47.31 74.8 47.45 76.16 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -623,7 +611,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 74.8 45.61 76.16 ; + RECT 24.77 74.8 24.91 76.16 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -631,15 +619,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 74.8 28.59 76.16 ; + RECT 48.23 74.8 48.37 76.16 ; END END chany_top_in[11] PIN chany_top_in[12] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 38.49 74.8 38.79 76.16 ; + LAYER met2 ; + RECT 21.09 74.8 21.23 76.16 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -647,7 +635,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.41 74.8 17.55 76.16 ; + RECT 49.15 74.8 49.29 76.16 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -655,7 +643,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 74.8 46.53 76.16 ; + RECT 23.85 74.8 23.99 76.16 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -663,7 +651,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 74.8 35.95 76.16 ; + RECT 62.49 74.8 62.63 76.16 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -671,7 +659,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 74.8 52.97 76.16 ; + RECT 22.93 74.8 23.07 76.16 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -679,7 +667,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 74.8 36.87 76.16 ; + RECT 50.07 74.8 50.21 76.16 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -687,7 +675,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 74.8 33.65 76.16 ; + RECT 26.61 74.8 26.75 76.16 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -695,7 +683,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 74.8 23.99 76.16 ; + RECT 50.99 74.8 51.13 76.16 ; END END chany_top_in[19] PIN ccff_head[0] @@ -703,7 +691,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 58.33 1.38 58.63 ; END END ccff_head[0] PIN chany_bottom_out[0] @@ -711,7 +699,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 0 47.45 1.36 ; + RECT 54.21 0 54.35 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -719,15 +707,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; + RECT 34.89 0 35.03 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 37.57 0 37.87 1.36 ; + LAYER met2 ; + RECT 33.97 0 34.11 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -735,7 +723,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; + RECT 51.45 0 51.59 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -743,7 +731,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 31.13 0 31.43 1.36 ; + RECT 42.17 0 42.47 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -751,7 +739,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.67 0 31.81 1.36 ; + RECT 28.91 0 29.05 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -759,7 +747,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 0 36.87 1.36 ; + RECT 57.89 0 58.03 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -767,7 +755,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; + RECT 47.31 0 47.45 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -783,7 +771,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 21.55 0 21.69 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -791,7 +779,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 34.81 0 35.11 1.36 ; + RECT 37.57 0 37.87 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -799,15 +787,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.75 0 30.89 1.36 ; + RECT 52.37 0 52.51 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 29.29 0 29.59 1.36 ; + LAYER met2 ; + RECT 56.97 0 57.11 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -815,7 +803,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 0 26.75 1.36 ; + RECT 50.53 0 50.67 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -831,7 +819,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.59 0 32.73 1.36 ; + RECT 20.63 0 20.77 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -839,7 +827,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 32.97 0 33.27 1.36 ; + RECT 44.01 0 44.31 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -847,15 +835,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 0 23.07 1.36 ; + RECT 39.95 0 40.09 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 21.01 0 21.31 1.36 ; + LAYER met2 ; + RECT 36.73 0 36.87 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -863,15 +851,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 0 21.23 1.36 ; + RECT 38.57 0 38.71 1.36 ; END END chany_bottom_out[19] PIN chany_top_out[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 36.65 74.8 36.95 76.16 ; + LAYER met2 ; + RECT 32.13 74.8 32.27 76.16 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -879,7 +867,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 74.8 21.23 76.16 ; + RECT 39.49 74.8 39.63 76.16 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -887,7 +875,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 74.8 50.21 76.16 ; + RECT 38.57 74.8 38.71 76.16 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -895,7 +883,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 74.8 41.47 76.16 ; + RECT 44.09 74.8 44.23 76.16 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -903,7 +891,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 74.8 51.13 76.16 ; + RECT 30.29 74.8 30.43 76.16 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -911,7 +899,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.67 74.8 31.81 76.16 ; + RECT 41.79 74.8 41.93 76.16 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -919,7 +907,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 74.8 52.05 76.16 ; + RECT 58.81 74.8 58.95 76.16 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -927,7 +915,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 74.8 42.39 76.16 ; + RECT 33.97 74.8 34.11 76.16 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -935,7 +923,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 74.8 49.29 76.16 ; + RECT 42.71 74.8 42.85 76.16 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -943,15 +931,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 74.8 43.31 76.16 ; + RECT 22.01 74.8 22.15 76.16 ; END END chany_top_out[9] PIN chany_top_out[10] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 27.45 74.8 27.75 76.16 ; + LAYER met2 ; + RECT 37.65 74.8 37.79 76.16 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -959,7 +947,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 74.8 40.09 76.16 ; + RECT 31.21 74.8 31.35 76.16 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -967,7 +955,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.25 74.8 19.39 76.16 ; + RECT 29.37 74.8 29.51 76.16 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -975,15 +963,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 74.8 22.15 76.16 ; + RECT 52.83 74.8 52.97 76.16 ; END END chany_top_out[13] PIN chany_top_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 33.89 74.8 34.19 76.16 ; + LAYER met2 ; + RECT 56.97 74.8 57.11 76.16 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -991,7 +979,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.29 74.8 30.43 76.16 ; + RECT 14.19 74.8 14.33 76.16 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -999,7 +987,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.17 74.8 20.31 76.16 ; + RECT 33.05 74.8 33.19 76.16 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -1007,7 +995,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 74.8 23.07 76.16 ; + RECT 56.05 74.8 56.19 76.16 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1015,7 +1003,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 74.8 26.75 76.16 ; + RECT 57.89 74.8 58.03 76.16 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1023,151 +1011,143 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 74.8 53.89 76.16 ; + RECT 35.81 74.8 35.95 76.16 ; END END chany_top_out[19] - PIN right_grid_pin_52_[0] + PIN left_grid_pin_16_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 64.86 40.65 66.24 40.95 ; + RECT 0 13.45 1.38 13.75 ; END - END right_grid_pin_52_[0] - PIN left_grid_pin_0_[0] + END left_grid_pin_16_[0] + PIN left_grid_pin_17_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 22.97 1.38 23.27 ; END - END left_grid_pin_0_[0] - PIN left_grid_pin_1_[0] + END left_grid_pin_17_[0] + PIN left_grid_pin_18_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 24.33 1.38 24.63 ; END - END left_grid_pin_1_[0] - PIN left_grid_pin_2_[0] + END left_grid_pin_18_[0] + PIN left_grid_pin_19_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; + RECT 0 6.65 1.38 6.95 ; END - END left_grid_pin_2_[0] - PIN left_grid_pin_3_[0] + END left_grid_pin_19_[0] + PIN left_grid_pin_20_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; + RECT 0 20.25 1.38 20.55 ; END - END left_grid_pin_3_[0] - PIN left_grid_pin_4_[0] + END left_grid_pin_20_[0] + PIN left_grid_pin_21_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 16.17 1.38 16.47 ; END - END left_grid_pin_4_[0] - PIN left_grid_pin_5_[0] + END left_grid_pin_21_[0] + PIN left_grid_pin_22_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 14.81 1.38 15.11 ; END - END left_grid_pin_5_[0] - PIN left_grid_pin_6_[0] + END left_grid_pin_22_[0] + PIN left_grid_pin_23_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + RECT 0 5.29 1.38 5.59 ; END - END left_grid_pin_6_[0] - PIN left_grid_pin_7_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; - END - END left_grid_pin_7_[0] - PIN left_grid_pin_8_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; - END - END left_grid_pin_8_[0] - PIN left_grid_pin_9_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; - END - END left_grid_pin_9_[0] - PIN left_grid_pin_10_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; - END - END left_grid_pin_10_[0] - PIN left_grid_pin_11_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; - END - END left_grid_pin_11_[0] - PIN left_grid_pin_12_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; - END - END left_grid_pin_12_[0] - PIN left_grid_pin_13_[0] + END left_grid_pin_23_[0] + PIN left_grid_pin_24_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; RECT 0 37.93 1.38 38.23 ; END - END left_grid_pin_13_[0] - PIN left_grid_pin_14_[0] + END left_grid_pin_24_[0] + PIN left_grid_pin_25_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 17.53 1.38 17.83 ; END - END left_grid_pin_14_[0] - PIN left_grid_pin_15_[0] + END left_grid_pin_25_[0] + PIN left_grid_pin_26_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 18.89 1.38 19.19 ; + END + END left_grid_pin_26_[0] + PIN left_grid_pin_27_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 21.61 1.38 21.91 ; + END + END left_grid_pin_27_[0] + PIN left_grid_pin_28_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; RECT 0 40.65 1.38 40.95 ; END - END left_grid_pin_15_[0] + END left_grid_pin_28_[0] + PIN left_grid_pin_29_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.29 1.38 39.59 ; + END + END left_grid_pin_29_[0] + PIN left_grid_pin_30_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.01 1.38 42.31 ; + END + END left_grid_pin_30_[0] + PIN left_grid_pin_31_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 59.69 1.38 59.99 ; + END + END left_grid_pin_31_[0] PIN ccff_tail[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 64.86 39.29 66.24 39.59 ; + RECT 64.86 40.65 66.24 40.95 ; END END ccff_tail[0] PIN VDD @@ -1278,29 +1258,29 @@ MACRO cby_1__1_ RECT 65.32 54.315 66.24 54.485 ; RECT 0 54.315 1.84 54.485 ; RECT 65.32 51.595 66.24 51.765 ; - RECT 0 51.595 3.68 51.765 ; + RECT 0 51.595 1.84 51.765 ; RECT 65.32 48.875 66.24 49.045 ; - RECT 0 48.875 3.68 49.045 ; + RECT 0 48.875 1.84 49.045 ; RECT 65.32 46.155 66.24 46.325 ; - RECT 0 46.155 1.84 46.325 ; + RECT 0 46.155 3.68 46.325 ; RECT 65.32 43.435 66.24 43.605 ; - RECT 0 43.435 1.84 43.605 ; + RECT 0 43.435 3.68 43.605 ; RECT 65.32 40.715 66.24 40.885 ; RECT 0 40.715 1.84 40.885 ; RECT 65.32 37.995 66.24 38.165 ; RECT 0 37.995 1.84 38.165 ; RECT 65.32 35.275 66.24 35.445 ; - RECT 0 35.275 1.84 35.445 ; + RECT 0 35.275 3.68 35.445 ; RECT 65.32 32.555 66.24 32.725 ; - RECT 0 32.555 1.84 32.725 ; + RECT 0 32.555 3.68 32.725 ; RECT 65.32 29.835 66.24 30.005 ; RECT 0 29.835 1.84 30.005 ; RECT 65.32 27.115 66.24 27.285 ; RECT 0 27.115 1.84 27.285 ; RECT 65.32 24.395 66.24 24.565 ; - RECT 0 24.395 3.68 24.565 ; + RECT 0 24.395 1.84 24.565 ; RECT 65.32 21.675 66.24 21.845 ; - RECT 0 21.675 3.68 21.845 ; + RECT 0 21.675 1.84 21.845 ; RECT 65.32 18.955 66.24 19.125 ; RECT 0 18.955 1.84 19.125 ; RECT 65.32 16.235 66.24 16.405 ; @@ -1308,40 +1288,38 @@ MACRO cby_1__1_ RECT 65.32 13.515 66.24 13.685 ; RECT 0 13.515 1.84 13.685 ; RECT 65.32 10.795 66.24 10.965 ; - RECT 0 10.795 1.84 10.965 ; + RECT 0 10.795 3.68 10.965 ; RECT 65.32 8.075 66.24 8.245 ; - RECT 0 8.075 1.84 8.245 ; + RECT 0 8.075 3.68 8.245 ; RECT 65.32 5.355 66.24 5.525 ; RECT 0 5.355 1.84 5.525 ; RECT 65.32 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; RECT 0 -0.085 66.24 0.085 ; - LAYER met2 ; - RECT 55.06 75.975 55.34 76.345 ; - RECT 25.62 75.975 25.9 76.345 ; - RECT 42.65 74.3 42.91 74.62 ; - RECT 25.17 74.3 25.43 74.62 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 75.88 65.96 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 32.09 0.28 32.09 1.64 31.39 1.64 31.39 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 19.67 0.28 19.67 1.64 18.97 1.64 18.97 0.28 9.55 0.28 9.55 1.64 8.85 1.64 8.85 0.28 0.28 0.28 0.28 75.88 1.95 75.88 1.95 74.52 2.65 74.52 2.65 75.88 17.13 75.88 17.13 74.52 17.83 74.52 17.83 75.88 18.97 75.88 18.97 74.52 19.67 74.52 19.67 75.88 19.89 75.88 19.89 74.52 20.59 74.52 20.59 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 22.65 75.88 22.65 74.52 23.35 74.52 23.35 75.88 23.57 75.88 23.57 74.52 24.27 74.52 24.27 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 26.33 75.88 26.33 74.52 27.03 74.52 27.03 75.88 27.25 75.88 27.25 74.52 27.95 74.52 27.95 75.88 28.17 75.88 28.17 74.52 28.87 74.52 28.87 75.88 29.09 75.88 29.09 74.52 29.79 74.52 29.79 75.88 30.01 75.88 30.01 74.52 30.71 74.52 30.71 75.88 31.39 75.88 31.39 74.52 32.09 74.52 32.09 75.88 32.31 75.88 32.31 74.52 33.01 74.52 33.01 75.88 33.23 75.88 33.23 74.52 33.93 74.52 33.93 75.88 34.15 75.88 34.15 74.52 34.85 74.52 34.85 75.88 35.53 75.88 35.53 74.52 36.23 74.52 36.23 75.88 36.45 75.88 36.45 74.52 37.15 74.52 37.15 75.88 37.37 75.88 37.37 74.52 38.07 74.52 38.07 75.88 38.75 75.88 38.75 74.52 39.45 74.52 39.45 75.88 39.67 75.88 39.67 74.52 40.37 74.52 40.37 75.88 41.05 75.88 41.05 74.52 41.75 74.52 41.75 75.88 41.97 75.88 41.97 74.52 42.67 74.52 42.67 75.88 42.89 75.88 42.89 74.52 43.59 74.52 43.59 75.88 44.27 75.88 44.27 74.52 44.97 74.52 44.97 75.88 45.19 75.88 45.19 74.52 45.89 74.52 45.89 75.88 46.11 75.88 46.11 74.52 46.81 74.52 46.81 75.88 47.03 75.88 47.03 74.52 47.73 74.52 47.73 75.88 47.95 75.88 47.95 74.52 48.65 74.52 48.65 75.88 48.87 75.88 48.87 74.52 49.57 74.52 49.57 75.88 49.79 75.88 49.79 74.52 50.49 74.52 50.49 75.88 50.71 75.88 50.71 74.52 51.41 74.52 51.41 75.88 51.63 75.88 51.63 74.52 52.33 74.52 52.33 75.88 52.55 75.88 52.55 74.52 53.25 74.52 53.25 75.88 53.47 75.88 53.47 74.52 54.17 74.52 54.17 75.88 ; - LAYER met4 ; - POLYGON 65.84 75.76 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 38.27 0.4 38.27 1.76 37.17 1.76 37.17 0.4 35.51 0.4 35.51 1.76 34.41 1.76 34.41 0.4 33.67 0.4 33.67 1.76 32.57 1.76 32.57 0.4 31.83 0.4 31.83 1.76 30.73 1.76 30.73 0.4 29.99 0.4 29.99 1.76 28.89 1.76 28.89 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 23.55 0.4 23.55 1.76 22.45 1.76 22.45 0.4 21.71 0.4 21.71 1.76 20.61 1.76 20.61 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 27.05 75.76 27.05 74.4 28.15 74.4 28.15 75.76 33.49 75.76 33.49 74.4 34.59 74.4 34.59 75.76 36.25 75.76 36.25 74.4 37.35 74.4 37.35 75.76 38.09 75.76 38.09 74.4 39.19 74.4 39.19 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; LAYER met3 ; POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; - POLYGON 3.37 63.39 3.37 63.09 1.23 63.09 1.23 63.37 1.78 63.37 1.78 63.39 ; - POLYGON 2.005 43.005 2.005 42.99 20.85 42.99 20.85 42.69 2.005 42.69 2.005 42.675 1.675 42.675 1.675 43.005 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 75.76 65.84 41.35 64.46 41.35 64.46 40.25 65.84 40.25 65.84 39.99 64.46 39.99 64.46 38.89 65.84 38.89 65.84 0.4 0.4 0.4 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 75.76 ; + POLYGON 65.84 75.76 65.84 41.35 64.46 41.35 64.46 40.25 65.84 40.25 65.84 0.4 0.4 0.4 0.4 2.85 1.78 2.85 1.78 3.95 0.4 3.95 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 75.76 ; + LAYER met2 ; + RECT 55.06 75.975 55.34 76.345 ; + RECT 25.62 75.975 25.9 76.345 ; + RECT 56.45 74.3 56.71 74.62 ; + RECT 45.41 74.3 45.67 74.62 ; + RECT 23.33 74.3 23.59 74.62 ; + RECT 34.37 1.54 34.63 1.86 ; + RECT 55.06 -0.185 55.34 0.185 ; + RECT 25.62 -0.185 25.9 0.185 ; + POLYGON 65.96 75.88 65.96 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 34.39 0.28 34.39 1.64 33.69 1.64 33.69 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 27.49 0.28 27.49 1.64 26.79 1.64 26.79 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 0.28 0.28 0.28 75.88 13.91 75.88 13.91 74.52 14.61 74.52 14.61 75.88 14.83 75.88 14.83 74.52 15.53 74.52 15.53 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 22.65 75.88 22.65 74.52 23.35 74.52 23.35 75.88 23.57 75.88 23.57 74.52 24.27 74.52 24.27 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 26.33 75.88 26.33 74.52 27.03 74.52 27.03 75.88 27.25 75.88 27.25 74.52 27.95 74.52 27.95 75.88 28.17 75.88 28.17 74.52 28.87 74.52 28.87 75.88 29.09 75.88 29.09 74.52 29.79 74.52 29.79 75.88 30.01 75.88 30.01 74.52 30.71 74.52 30.71 75.88 30.93 75.88 30.93 74.52 31.63 74.52 31.63 75.88 31.85 75.88 31.85 74.52 32.55 74.52 32.55 75.88 32.77 75.88 32.77 74.52 33.47 74.52 33.47 75.88 33.69 75.88 33.69 74.52 34.39 74.52 34.39 75.88 35.53 75.88 35.53 74.52 36.23 74.52 36.23 75.88 36.45 75.88 36.45 74.52 37.15 74.52 37.15 75.88 37.37 75.88 37.37 74.52 38.07 74.52 38.07 75.88 38.29 75.88 38.29 74.52 38.99 74.52 38.99 75.88 39.21 75.88 39.21 74.52 39.91 74.52 39.91 75.88 40.59 75.88 40.59 74.52 41.29 74.52 41.29 75.88 41.51 75.88 41.51 74.52 42.21 74.52 42.21 75.88 42.43 75.88 42.43 74.52 43.13 74.52 43.13 75.88 43.81 75.88 43.81 74.52 44.51 74.52 44.51 75.88 44.73 75.88 44.73 74.52 45.43 74.52 45.43 75.88 46.11 75.88 46.11 74.52 46.81 74.52 46.81 75.88 47.03 75.88 47.03 74.52 47.73 74.52 47.73 75.88 47.95 75.88 47.95 74.52 48.65 74.52 48.65 75.88 48.87 75.88 48.87 74.52 49.57 74.52 49.57 75.88 49.79 75.88 49.79 74.52 50.49 74.52 50.49 75.88 50.71 75.88 50.71 74.52 51.41 74.52 51.41 75.88 51.63 75.88 51.63 74.52 52.33 74.52 52.33 75.88 52.55 75.88 52.55 74.52 53.25 74.52 53.25 75.88 53.47 75.88 53.47 74.52 54.17 74.52 54.17 75.88 55.77 75.88 55.77 74.52 56.47 74.52 56.47 75.88 56.69 75.88 56.69 74.52 57.39 74.52 57.39 75.88 57.61 75.88 57.61 74.52 58.31 74.52 58.31 75.88 58.53 75.88 58.53 74.52 59.23 74.52 59.23 75.88 62.21 75.88 62.21 74.52 62.91 74.52 62.91 75.88 ; + LAYER met4 ; + POLYGON 65.84 75.76 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 44.71 0.4 44.71 1.76 43.61 1.76 43.61 0.4 42.87 0.4 42.87 1.76 41.77 1.76 41.77 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 38.27 0.4 38.27 1.76 37.17 1.76 37.17 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; LAYER met5 ; - POLYGON 63.04 72.96 63.04 63.28 59.84 63.28 59.84 53.68 63.04 53.68 63.04 42.88 59.84 42.88 59.84 33.28 63.04 33.28 63.04 22.48 59.84 22.48 59.84 12.88 63.04 12.88 63.04 3.2 3.2 3.2 3.2 12.88 6.4 12.88 6.4 22.48 3.2 22.48 3.2 33.28 6.4 33.28 6.4 42.88 3.2 42.88 3.2 53.68 6.4 53.68 6.4 63.28 3.2 63.28 3.2 72.96 ; + POLYGON 64.64 74.56 64.64 61.68 61.44 61.68 61.44 55.28 64.64 55.28 64.64 41.28 61.44 41.28 61.44 34.88 64.64 34.88 64.64 20.88 61.44 20.88 61.44 14.48 64.64 14.48 64.64 1.6 1.6 1.6 1.6 14.48 4.8 14.48 4.8 20.88 1.6 20.88 1.6 34.88 4.8 34.88 4.8 41.28 1.6 41.28 1.6 55.28 4.8 55.28 4.8 61.68 1.6 61.68 1.6 74.56 ; LAYER met1 ; POLYGON 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; LAYER li1 ; - RECT 47.465 75.35 48.215 75.895 ; - RECT 47.465 0.265 48.215 0.81 ; - RECT 0.34 0.34 65.9 75.82 ; + RECT 0.17 0.17 66.07 75.99 ; LAYER mcon ; RECT 65.925 76.075 66.095 76.245 ; RECT 65.465 76.075 65.635 76.245 ; @@ -1742,18 +1720,19 @@ MACRO cby_1__1_ LAYER via ; RECT 55.125 76.085 55.275 76.235 ; RECT 25.685 76.085 25.835 76.235 ; - RECT 52.825 74.385 52.975 74.535 ; - RECT 39.945 74.385 40.095 74.535 ; - RECT 30.285 74.385 30.435 74.535 ; - RECT 39.485 1.625 39.635 1.775 ; - RECT 9.125 1.625 9.275 1.775 ; + RECT 50.985 74.385 51.135 74.535 ; + RECT 48.225 74.385 48.375 74.535 ; + RECT 33.045 74.385 33.195 74.535 ; + RECT 40.865 1.625 41.015 1.775 ; RECT 55.125 -0.075 55.275 0.075 ; RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; RECT 55.1 76.06 55.3 76.26 ; RECT 25.66 76.06 25.86 76.26 ; - RECT 1.28 67.9 1.48 68.1 ; - RECT 1.28 57.02 1.48 57.22 ; + RECT 1.74 58.38 1.94 58.58 ; + RECT 1.74 21.66 1.94 21.86 ; + RECT 1.28 16.22 1.48 16.42 ; + RECT 1.28 13.5 1.48 13.7 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; @@ -1761,86 +1740,6 @@ MACRO cby_1__1_ RECT 25.66 76.06 25.86 76.26 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; - LAYER fieldpoly ; - RECT 0.14 0.14 66.1 76.02 ; - LAYER diff ; - RECT 0 0 66.24 76.16 ; - LAYER nwell ; - POLYGON 66.43 74.855 66.43 72.025 65.13 72.025 65.13 73.63 65.59 73.63 65.59 74.855 ; - POLYGON 3.87 74.855 3.87 73.25 2.03 73.25 2.03 72.025 -0.19 72.025 -0.19 74.855 ; - RECT 65.13 66.585 66.43 69.415 ; - RECT -0.19 66.585 2.03 69.415 ; - RECT 65.13 61.145 66.43 63.975 ; - RECT -0.19 61.145 2.03 63.975 ; - RECT 65.13 55.705 66.43 58.535 ; - RECT -0.19 55.705 2.03 58.535 ; - RECT 65.13 50.265 66.43 53.095 ; - POLYGON 2.03 53.095 2.03 51.87 3.87 51.87 3.87 50.265 -0.19 50.265 -0.19 53.095 ; - RECT 65.13 44.825 66.43 47.655 ; - RECT -0.19 44.825 2.03 47.655 ; - RECT 65.13 39.385 66.43 42.215 ; - RECT -0.19 39.385 2.03 42.215 ; - RECT 65.13 33.945 66.43 36.775 ; - RECT -0.19 33.945 2.03 36.775 ; - RECT 65.13 28.505 66.43 31.335 ; - RECT -0.19 28.505 2.03 31.335 ; - RECT 65.13 23.065 66.43 25.895 ; - POLYGON 2.03 25.895 2.03 24.67 3.87 24.67 3.87 23.065 -0.19 23.065 -0.19 25.895 ; - RECT 65.13 17.625 66.43 20.455 ; - RECT -0.19 17.625 2.03 20.455 ; - RECT 65.13 12.185 66.43 15.015 ; - RECT -0.19 12.185 2.03 15.015 ; - POLYGON 66.43 9.575 66.43 6.745 65.13 6.745 65.13 8.35 65.59 8.35 65.59 9.575 ; - RECT -0.19 6.745 2.03 9.575 ; - POLYGON 66.43 4.135 66.43 1.305 65.59 1.305 65.59 2.53 65.13 2.53 65.13 4.135 ; - POLYGON 2.03 4.135 2.03 2.91 3.87 2.91 3.87 1.305 -0.19 1.305 -0.19 4.135 ; - RECT 0 0 66.24 76.16 ; - LAYER pwell ; - RECT 59.47 76.11 59.69 76.28 ; - RECT 55.79 76.11 56.01 76.28 ; - RECT 52.11 76.11 52.33 76.28 ; - RECT 48.43 76.11 48.65 76.28 ; - RECT 40.61 76.11 40.83 76.28 ; - RECT 36.93 76.11 37.15 76.28 ; - RECT 33.25 76.11 33.47 76.28 ; - RECT 29.57 76.11 29.79 76.28 ; - RECT 25.89 76.11 26.11 76.28 ; - RECT 22.21 76.11 22.43 76.28 ; - RECT 18.53 76.11 18.75 76.28 ; - RECT 14.85 76.11 15.07 76.28 ; - RECT 11.17 76.11 11.39 76.28 ; - RECT 7.49 76.11 7.71 76.28 ; - RECT 3.81 76.11 4.03 76.28 ; - RECT 0.13 76.11 0.35 76.28 ; - RECT 63.195 76.1 63.305 76.22 ; - RECT 44.335 76.1 44.445 76.22 ; - RECT 65.92 76.105 66.04 76.215 ; - RECT 47.06 76.105 47.18 76.215 ; - RECT 65.015 76.1 65.175 76.21 ; - RECT 46.155 76.1 46.315 76.21 ; - RECT 65.015 -0.05 65.175 0.06 ; - RECT 63.195 -0.06 63.305 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 65.92 -0.055 66.04 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - RECT 14.85 -0.12 15.07 0.05 ; - RECT 11.17 -0.12 11.39 0.05 ; - RECT 7.49 -0.12 7.71 0.05 ; - RECT 3.81 -0.12 4.03 0.05 ; - RECT 0.13 -0.12 0.35 0.05 ; - RECT 0 0 66.24 76.16 ; LAYER OVERLAP ; POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef new file mode 100644 index 0000000..6b8d7ab --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef @@ -0,0 +1,1802 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO cby_2__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 66.24 BY 76.16 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 2.23 0 2.37 1.36 ; + END + END prog_clk[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.47 0 22.61 1.36 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.57 0 15.71 1.36 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.99 0 28.13 1.36 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.51 0 33.65 1.36 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.77 0 24.91 1.36 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.29 0 7.43 1.36 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.95 0 17.09 1.36 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.91 0 29.05 1.36 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.25 0 19.39 1.36 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.59 0 32.73 1.36 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.33 0 18.47 1.36 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.35 0 35.49 1.36 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.97 0 11.11 1.36 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.55 0 21.69 1.36 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.21 0 8.35 1.36 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.07 0 27.21 1.36 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.37 0 6.51 1.36 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.05 0 10.19 1.36 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.85 0 23.99 1.36 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.13 0 9.27 1.36 ; + END + END chany_bottom_in[19] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.73 74.8 13.87 76.16 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.65 74.8 60.79 76.16 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.73 74.8 59.87 76.16 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.25 74.8 19.39 76.16 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.97 74.8 11.11 76.16 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.53 74.8 4.67 76.16 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.45 74.8 5.59 76.16 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.99 74.8 28.13 76.16 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.77 74.8 24.91 76.16 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.67 74.8 31.81 76.16 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.03 74.8 16.17 76.16 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.05 74.8 10.19 76.16 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.21 74.8 8.35 76.16 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.37 74.8 6.51 76.16 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.89 74.8 12.03 76.16 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.91 74.8 29.05 76.16 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.13 74.8 9.27 76.16 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.65 74.8 14.79 76.16 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 29.83 74.8 29.97 76.16 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.07 74.8 27.21 76.16 ; + END + END chany_top_in[19] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 58.33 1.38 58.63 ; + END + END ccff_head[0] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.11 0 38.25 1.36 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.65 0 14.79 1.36 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 38.49 0 38.79 1.36 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.73 0 13.87 1.36 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.53 0 4.67 1.36 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.75 0 30.89 1.36 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.47 0 45.61 1.36 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.03 0 39.17 1.36 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.63 0 43.77 1.36 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 27.45 0 27.75 1.36 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 30.21 0 30.51 1.36 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 29.83 0 29.97 1.36 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.43 0 34.57 1.36 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.39 0 46.53 1.36 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.71 0 42.85 1.36 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.87 0 41.01 1.36 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.67 0 31.81 1.36 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.55 0 44.69 1.36 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.95 0 40.09 1.36 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.79 0 41.93 1.36 ; + END + END chany_bottom_out[19] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.93 74.8 23.07 76.16 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.75 74.8 30.89 76.16 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.59 74.8 32.73 76.16 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.85 74.8 23.99 76.16 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.61 74.8 3.75 76.16 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.17 74.8 20.31 76.16 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.09 74.8 21.23 76.16 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.55 74.8 44.69 76.16 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.17 74.8 43.31 76.16 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.39 74.8 46.53 76.16 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.33 74.8 18.47 76.16 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.03 74.8 39.17 76.16 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.01 74.8 22.15 76.16 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.81 74.8 12.95 76.16 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.51 74.8 33.65 76.16 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.33 74.8 41.47 76.16 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.95 74.8 40.09 76.16 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.25 74.8 42.39 76.16 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.47 74.8 45.61 76.16 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.11 74.8 38.25 76.16 ; + END + END chany_top_out[19] + PIN right_grid_pin_0_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.41 74.8 17.55 76.16 ; + END + END right_grid_pin_0_[0] + PIN left_grid_pin_16_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 13.45 1.38 13.75 ; + END + END left_grid_pin_16_[0] + PIN left_grid_pin_17_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.97 1.38 23.27 ; + END + END left_grid_pin_17_[0] + PIN left_grid_pin_18_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 24.33 1.38 24.63 ; + END + END left_grid_pin_18_[0] + PIN left_grid_pin_19_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 6.65 1.38 6.95 ; + END + END left_grid_pin_19_[0] + PIN left_grid_pin_20_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 20.25 1.38 20.55 ; + END + END left_grid_pin_20_[0] + PIN left_grid_pin_21_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 16.17 1.38 16.47 ; + END + END left_grid_pin_21_[0] + PIN left_grid_pin_22_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 14.81 1.38 15.11 ; + END + END left_grid_pin_22_[0] + PIN left_grid_pin_23_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 5.29 1.38 5.59 ; + END + END left_grid_pin_23_[0] + PIN left_grid_pin_24_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.93 1.38 38.23 ; + END + END left_grid_pin_24_[0] + PIN left_grid_pin_25_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 17.53 1.38 17.83 ; + END + END left_grid_pin_25_[0] + PIN left_grid_pin_26_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 18.89 1.38 19.19 ; + END + END left_grid_pin_26_[0] + PIN left_grid_pin_27_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 21.61 1.38 21.91 ; + END + END left_grid_pin_27_[0] + PIN left_grid_pin_28_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.65 1.38 40.95 ; + END + END left_grid_pin_28_[0] + PIN left_grid_pin_29_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.29 1.38 39.59 ; + END + END left_grid_pin_29_[0] + PIN left_grid_pin_30_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.01 1.38 42.31 ; + END + END left_grid_pin_30_[0] + PIN left_grid_pin_31_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 59.69 1.38 59.99 ; + END + END left_grid_pin_31_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.63 0 20.77 1.36 ; + END + END ccff_tail[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 64.86 38.61 66.24 38.91 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_IN[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 64.86 8.69 66.24 8.99 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] + PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 64.86 3.25 66.24 3.55 ; + END + END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] + PIN left_width_0_height_0__pin_0_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 21.93 74.8 22.23 76.16 ; + END + END left_width_0_height_0__pin_0_[0] + PIN left_width_0_height_0__pin_1_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.29 74.8 7.43 76.16 ; + END + END left_width_0_height_0__pin_1_upper[0] + PIN left_width_0_height_0__pin_1_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.45 0 5.59 1.36 ; + END + END left_width_0_height_0__pin_1_lower[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 63.04 36.48 66.24 39.68 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 65.76 2.48 66.24 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 65.76 7.92 66.24 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 65.76 13.36 66.24 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 65.76 18.8 66.24 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 65.76 24.24 66.24 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 65.76 29.68 66.24 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 65.76 35.12 66.24 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 65.76 40.56 66.24 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 65.76 46 66.24 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 65.76 51.44 66.24 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 65.76 56.88 66.24 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 65.76 62.32 66.24 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 65.76 67.76 66.24 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 65.76 73.2 66.24 73.68 ; + LAYER met4 ; + RECT 10.74 0 11.34 0.6 ; + RECT 40.18 0 40.78 0.6 ; + RECT 10.74 75.56 11.34 76.16 ; + RECT 40.18 75.56 40.78 76.16 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 63.04 16.08 66.24 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 63.04 56.88 66.24 60.08 ; + LAYER met1 ; + RECT 0 0 66.24 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 65.76 5.2 66.24 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 65.76 10.64 66.24 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 65.76 16.08 66.24 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 65.76 21.52 66.24 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 65.76 26.96 66.24 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 65.76 32.4 66.24 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 65.76 37.84 66.24 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 65.76 43.28 66.24 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 65.76 48.72 66.24 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 65.76 54.16 66.24 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 65.76 59.6 66.24 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 65.76 65.04 66.24 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 65.76 70.48 66.24 70.96 ; + RECT 0 75.92 66.24 76.16 ; + LAYER met4 ; + RECT 25.46 0 26.06 0.6 ; + RECT 54.9 0 55.5 0.6 ; + RECT 25.46 75.56 26.06 76.16 ; + RECT 54.9 75.56 55.5 76.16 ; + END + END VSS + OBS + LAYER li1 ; + RECT 0 76.075 66.24 76.245 ; + RECT 65.78 73.355 66.24 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 65.32 70.635 66.24 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 62.56 67.915 66.24 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 62.56 65.195 66.24 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 65.32 62.475 66.24 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 65.32 59.755 66.24 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 65.32 57.035 66.24 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 65.32 54.315 66.24 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 65.32 51.595 66.24 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 65.32 48.875 66.24 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 65.32 46.155 66.24 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 65.32 43.435 66.24 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 65.32 40.715 66.24 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 65.32 37.995 66.24 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 65.32 35.275 66.24 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 65.32 32.555 66.24 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 65.32 29.835 66.24 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 65.32 27.115 66.24 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 65.32 24.395 66.24 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 65.32 21.675 66.24 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 65.32 18.955 66.24 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 65.32 16.235 66.24 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 65.32 13.515 66.24 13.685 ; + RECT 0 13.515 1.84 13.685 ; + RECT 65.32 10.795 66.24 10.965 ; + RECT 0 10.795 1.84 10.965 ; + RECT 65.32 8.075 66.24 8.245 ; + RECT 0 8.075 1.84 8.245 ; + RECT 65.32 5.355 66.24 5.525 ; + RECT 0 5.355 1.84 5.525 ; + RECT 65.32 2.635 66.24 2.805 ; + RECT 0 2.635 3.68 2.805 ; + RECT 0 -0.085 66.24 0.085 ; + LAYER met2 ; + RECT 55.06 75.975 55.34 76.345 ; + RECT 25.62 75.975 25.9 76.345 ; + RECT 4.93 74.3 5.19 74.62 ; + RECT 23.33 1.54 23.59 1.86 ; + RECT 55.06 -0.185 55.34 0.185 ; + RECT 25.62 -0.185 25.9 0.185 ; + POLYGON 65.96 75.88 65.96 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 35.77 0.28 35.77 1.64 35.07 1.64 35.07 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 32.09 0.28 32.09 1.64 31.39 1.64 31.39 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 27.49 0.28 27.49 1.64 26.79 1.64 26.79 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 19.67 0.28 19.67 1.64 18.97 1.64 18.97 0.28 18.75 0.28 18.75 1.64 18.05 1.64 18.05 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 15.99 0.28 15.99 1.64 15.29 1.64 15.29 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 14.15 0.28 14.15 1.64 13.45 1.64 13.45 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 9.55 0.28 9.55 1.64 8.85 1.64 8.85 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 6.79 0.28 6.79 1.64 6.09 1.64 6.09 0.28 5.87 0.28 5.87 1.64 5.17 1.64 5.17 0.28 4.95 0.28 4.95 1.64 4.25 1.64 4.25 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 75.88 3.33 75.88 3.33 74.52 4.03 74.52 4.03 75.88 4.25 75.88 4.25 74.52 4.95 74.52 4.95 75.88 5.17 75.88 5.17 74.52 5.87 74.52 5.87 75.88 6.09 75.88 6.09 74.52 6.79 74.52 6.79 75.88 7.01 75.88 7.01 74.52 7.71 74.52 7.71 75.88 7.93 75.88 7.93 74.52 8.63 74.52 8.63 75.88 8.85 75.88 8.85 74.52 9.55 74.52 9.55 75.88 9.77 75.88 9.77 74.52 10.47 74.52 10.47 75.88 10.69 75.88 10.69 74.52 11.39 74.52 11.39 75.88 11.61 75.88 11.61 74.52 12.31 74.52 12.31 75.88 12.53 75.88 12.53 74.52 13.23 74.52 13.23 75.88 13.45 75.88 13.45 74.52 14.15 74.52 14.15 75.88 14.37 75.88 14.37 74.52 15.07 74.52 15.07 75.88 15.75 75.88 15.75 74.52 16.45 74.52 16.45 75.88 17.13 75.88 17.13 74.52 17.83 74.52 17.83 75.88 18.05 75.88 18.05 74.52 18.75 74.52 18.75 75.88 18.97 75.88 18.97 74.52 19.67 74.52 19.67 75.88 19.89 75.88 19.89 74.52 20.59 74.52 20.59 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 22.65 75.88 22.65 74.52 23.35 74.52 23.35 75.88 23.57 75.88 23.57 74.52 24.27 74.52 24.27 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 26.79 75.88 26.79 74.52 27.49 74.52 27.49 75.88 27.71 75.88 27.71 74.52 28.41 74.52 28.41 75.88 28.63 75.88 28.63 74.52 29.33 74.52 29.33 75.88 29.55 75.88 29.55 74.52 30.25 74.52 30.25 75.88 30.47 75.88 30.47 74.52 31.17 74.52 31.17 75.88 31.39 75.88 31.39 74.52 32.09 74.52 32.09 75.88 32.31 75.88 32.31 74.52 33.01 74.52 33.01 75.88 33.23 75.88 33.23 74.52 33.93 74.52 33.93 75.88 37.83 75.88 37.83 74.52 38.53 74.52 38.53 75.88 38.75 75.88 38.75 74.52 39.45 74.52 39.45 75.88 39.67 75.88 39.67 74.52 40.37 74.52 40.37 75.88 41.05 75.88 41.05 74.52 41.75 74.52 41.75 75.88 41.97 75.88 41.97 74.52 42.67 74.52 42.67 75.88 42.89 75.88 42.89 74.52 43.59 74.52 43.59 75.88 44.27 75.88 44.27 74.52 44.97 74.52 44.97 75.88 45.19 75.88 45.19 74.52 45.89 74.52 45.89 75.88 46.11 75.88 46.11 74.52 46.81 74.52 46.81 75.88 59.45 75.88 59.45 74.52 60.15 74.52 60.15 75.88 60.37 75.88 60.37 74.52 61.07 74.52 61.07 75.88 ; + LAYER met3 ; + POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; + POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; + POLYGON 3.83 41.63 3.83 41.33 1.78 41.33 1.78 41.35 1.23 41.35 1.23 41.63 ; + POLYGON 1.545 4.925 1.545 4.91 19.47 4.91 19.47 4.61 1.545 4.61 1.545 4.595 1.215 4.595 1.215 4.925 ; + POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; + POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; + POLYGON 65.84 75.76 65.84 39.31 64.46 39.31 64.46 38.21 65.84 38.21 65.84 9.39 64.46 9.39 64.46 8.29 65.84 8.29 65.84 3.95 64.46 3.95 64.46 2.85 65.84 2.85 65.84 0.4 0.4 0.4 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 75.76 ; + LAYER met4 ; + POLYGON 65.84 75.76 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 39.19 0.4 39.19 1.76 38.09 1.76 38.09 0.4 30.91 0.4 30.91 1.76 29.81 1.76 29.81 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 21.53 75.76 21.53 74.4 22.63 74.4 22.63 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; + LAYER met1 ; + POLYGON 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + LAYER met5 ; + POLYGON 64.64 74.56 64.64 61.68 61.44 61.68 61.44 55.28 64.64 55.28 64.64 41.28 61.44 41.28 61.44 34.88 64.64 34.88 64.64 20.88 61.44 20.88 61.44 14.48 64.64 14.48 64.64 1.6 1.6 1.6 1.6 14.48 4.8 14.48 4.8 20.88 1.6 20.88 1.6 34.88 4.8 34.88 4.8 41.28 1.6 41.28 1.6 55.28 4.8 55.28 4.8 61.68 1.6 61.68 1.6 74.56 ; + LAYER li1 ; + RECT 0.17 0.17 66.07 75.99 ; + LAYER mcon ; + RECT 65.925 76.075 66.095 76.245 ; + RECT 65.465 76.075 65.635 76.245 ; + RECT 65.005 76.075 65.175 76.245 ; + RECT 64.545 76.075 64.715 76.245 ; + RECT 64.085 76.075 64.255 76.245 ; + RECT 63.625 76.075 63.795 76.245 ; + RECT 63.165 76.075 63.335 76.245 ; + RECT 62.705 76.075 62.875 76.245 ; + RECT 62.245 76.075 62.415 76.245 ; + RECT 61.785 76.075 61.955 76.245 ; + RECT 61.325 76.075 61.495 76.245 ; + RECT 60.865 76.075 61.035 76.245 ; + RECT 60.405 76.075 60.575 76.245 ; + RECT 59.945 76.075 60.115 76.245 ; + RECT 59.485 76.075 59.655 76.245 ; + RECT 59.025 76.075 59.195 76.245 ; + RECT 58.565 76.075 58.735 76.245 ; + RECT 58.105 76.075 58.275 76.245 ; + RECT 57.645 76.075 57.815 76.245 ; + RECT 57.185 76.075 57.355 76.245 ; + RECT 56.725 76.075 56.895 76.245 ; + RECT 56.265 76.075 56.435 76.245 ; + RECT 55.805 76.075 55.975 76.245 ; + RECT 55.345 76.075 55.515 76.245 ; + RECT 54.885 76.075 55.055 76.245 ; + RECT 54.425 76.075 54.595 76.245 ; + RECT 53.965 76.075 54.135 76.245 ; + RECT 53.505 76.075 53.675 76.245 ; + RECT 53.045 76.075 53.215 76.245 ; + RECT 52.585 76.075 52.755 76.245 ; + RECT 52.125 76.075 52.295 76.245 ; + RECT 51.665 76.075 51.835 76.245 ; + RECT 51.205 76.075 51.375 76.245 ; + RECT 50.745 76.075 50.915 76.245 ; + RECT 50.285 76.075 50.455 76.245 ; + RECT 49.825 76.075 49.995 76.245 ; + RECT 49.365 76.075 49.535 76.245 ; + RECT 48.905 76.075 49.075 76.245 ; + RECT 48.445 76.075 48.615 76.245 ; + RECT 47.985 76.075 48.155 76.245 ; + RECT 47.525 76.075 47.695 76.245 ; + RECT 47.065 76.075 47.235 76.245 ; + RECT 46.605 76.075 46.775 76.245 ; + RECT 46.145 76.075 46.315 76.245 ; + RECT 45.685 76.075 45.855 76.245 ; + RECT 45.225 76.075 45.395 76.245 ; + RECT 44.765 76.075 44.935 76.245 ; + RECT 44.305 76.075 44.475 76.245 ; + RECT 43.845 76.075 44.015 76.245 ; + RECT 43.385 76.075 43.555 76.245 ; + RECT 42.925 76.075 43.095 76.245 ; + RECT 42.465 76.075 42.635 76.245 ; + RECT 42.005 76.075 42.175 76.245 ; + RECT 41.545 76.075 41.715 76.245 ; + RECT 41.085 76.075 41.255 76.245 ; + RECT 40.625 76.075 40.795 76.245 ; + RECT 40.165 76.075 40.335 76.245 ; + RECT 39.705 76.075 39.875 76.245 ; + RECT 39.245 76.075 39.415 76.245 ; + RECT 38.785 76.075 38.955 76.245 ; + RECT 38.325 76.075 38.495 76.245 ; + RECT 37.865 76.075 38.035 76.245 ; + RECT 37.405 76.075 37.575 76.245 ; + RECT 36.945 76.075 37.115 76.245 ; + RECT 36.485 76.075 36.655 76.245 ; + RECT 36.025 76.075 36.195 76.245 ; + RECT 35.565 76.075 35.735 76.245 ; + RECT 35.105 76.075 35.275 76.245 ; + RECT 34.645 76.075 34.815 76.245 ; + RECT 34.185 76.075 34.355 76.245 ; + RECT 33.725 76.075 33.895 76.245 ; + RECT 33.265 76.075 33.435 76.245 ; + RECT 32.805 76.075 32.975 76.245 ; + RECT 32.345 76.075 32.515 76.245 ; + RECT 31.885 76.075 32.055 76.245 ; + RECT 31.425 76.075 31.595 76.245 ; + RECT 30.965 76.075 31.135 76.245 ; + RECT 30.505 76.075 30.675 76.245 ; + RECT 30.045 76.075 30.215 76.245 ; + RECT 29.585 76.075 29.755 76.245 ; + RECT 29.125 76.075 29.295 76.245 ; + RECT 28.665 76.075 28.835 76.245 ; + RECT 28.205 76.075 28.375 76.245 ; + RECT 27.745 76.075 27.915 76.245 ; + RECT 27.285 76.075 27.455 76.245 ; + RECT 26.825 76.075 26.995 76.245 ; + RECT 26.365 76.075 26.535 76.245 ; + RECT 25.905 76.075 26.075 76.245 ; + RECT 25.445 76.075 25.615 76.245 ; + RECT 24.985 76.075 25.155 76.245 ; + RECT 24.525 76.075 24.695 76.245 ; + RECT 24.065 76.075 24.235 76.245 ; + RECT 23.605 76.075 23.775 76.245 ; + RECT 23.145 76.075 23.315 76.245 ; + RECT 22.685 76.075 22.855 76.245 ; + RECT 22.225 76.075 22.395 76.245 ; + RECT 21.765 76.075 21.935 76.245 ; + RECT 21.305 76.075 21.475 76.245 ; + RECT 20.845 76.075 21.015 76.245 ; + RECT 20.385 76.075 20.555 76.245 ; + RECT 19.925 76.075 20.095 76.245 ; + RECT 19.465 76.075 19.635 76.245 ; + RECT 19.005 76.075 19.175 76.245 ; + RECT 18.545 76.075 18.715 76.245 ; + RECT 18.085 76.075 18.255 76.245 ; + RECT 17.625 76.075 17.795 76.245 ; + RECT 17.165 76.075 17.335 76.245 ; + RECT 16.705 76.075 16.875 76.245 ; + RECT 16.245 76.075 16.415 76.245 ; + RECT 15.785 76.075 15.955 76.245 ; + RECT 15.325 76.075 15.495 76.245 ; + RECT 14.865 76.075 15.035 76.245 ; + RECT 14.405 76.075 14.575 76.245 ; + RECT 13.945 76.075 14.115 76.245 ; + RECT 13.485 76.075 13.655 76.245 ; + RECT 13.025 76.075 13.195 76.245 ; + RECT 12.565 76.075 12.735 76.245 ; + RECT 12.105 76.075 12.275 76.245 ; + RECT 11.645 76.075 11.815 76.245 ; + RECT 11.185 76.075 11.355 76.245 ; + RECT 10.725 76.075 10.895 76.245 ; + RECT 10.265 76.075 10.435 76.245 ; + RECT 9.805 76.075 9.975 76.245 ; + RECT 9.345 76.075 9.515 76.245 ; + RECT 8.885 76.075 9.055 76.245 ; + RECT 8.425 76.075 8.595 76.245 ; + RECT 7.965 76.075 8.135 76.245 ; + RECT 7.505 76.075 7.675 76.245 ; + RECT 7.045 76.075 7.215 76.245 ; + RECT 6.585 76.075 6.755 76.245 ; + RECT 6.125 76.075 6.295 76.245 ; + RECT 5.665 76.075 5.835 76.245 ; + RECT 5.205 76.075 5.375 76.245 ; + RECT 4.745 76.075 4.915 76.245 ; + RECT 4.285 76.075 4.455 76.245 ; + RECT 3.825 76.075 3.995 76.245 ; + RECT 3.365 76.075 3.535 76.245 ; + RECT 2.905 76.075 3.075 76.245 ; + RECT 2.445 76.075 2.615 76.245 ; + RECT 1.985 76.075 2.155 76.245 ; + RECT 1.525 76.075 1.695 76.245 ; + RECT 1.065 76.075 1.235 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 65.925 73.355 66.095 73.525 ; + RECT 65.465 73.355 65.635 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 65.925 70.635 66.095 70.805 ; + RECT 65.465 70.635 65.635 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 65.925 67.915 66.095 68.085 ; + RECT 65.465 67.915 65.635 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 65.925 65.195 66.095 65.365 ; + RECT 65.465 65.195 65.635 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 65.925 62.475 66.095 62.645 ; + RECT 65.465 62.475 65.635 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 65.925 59.755 66.095 59.925 ; + RECT 65.465 59.755 65.635 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 65.925 57.035 66.095 57.205 ; + RECT 65.465 57.035 65.635 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 65.925 54.315 66.095 54.485 ; + RECT 65.465 54.315 65.635 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 65.925 51.595 66.095 51.765 ; + RECT 65.465 51.595 65.635 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 65.925 48.875 66.095 49.045 ; + RECT 65.465 48.875 65.635 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 65.925 46.155 66.095 46.325 ; + RECT 65.465 46.155 65.635 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 65.925 43.435 66.095 43.605 ; + RECT 65.465 43.435 65.635 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 65.925 40.715 66.095 40.885 ; + RECT 65.465 40.715 65.635 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 65.925 37.995 66.095 38.165 ; + RECT 65.465 37.995 65.635 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 65.925 35.275 66.095 35.445 ; + RECT 65.465 35.275 65.635 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 65.925 32.555 66.095 32.725 ; + RECT 65.465 32.555 65.635 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 65.925 29.835 66.095 30.005 ; + RECT 65.465 29.835 65.635 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 65.925 24.395 66.095 24.565 ; + RECT 65.465 24.395 65.635 24.565 ; + RECT 0.605 24.395 0.775 24.565 ; + RECT 0.145 24.395 0.315 24.565 ; + RECT 65.925 21.675 66.095 21.845 ; + RECT 65.465 21.675 65.635 21.845 ; + RECT 0.605 21.675 0.775 21.845 ; + RECT 0.145 21.675 0.315 21.845 ; + RECT 65.925 18.955 66.095 19.125 ; + RECT 65.465 18.955 65.635 19.125 ; + RECT 0.605 18.955 0.775 19.125 ; + RECT 0.145 18.955 0.315 19.125 ; + RECT 65.925 16.235 66.095 16.405 ; + RECT 65.465 16.235 65.635 16.405 ; + RECT 0.605 16.235 0.775 16.405 ; + RECT 0.145 16.235 0.315 16.405 ; + RECT 65.925 13.515 66.095 13.685 ; + RECT 65.465 13.515 65.635 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 65.925 10.795 66.095 10.965 ; + RECT 65.465 10.795 65.635 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 65.925 8.075 66.095 8.245 ; + RECT 65.465 8.075 65.635 8.245 ; + RECT 0.605 8.075 0.775 8.245 ; + RECT 0.145 8.075 0.315 8.245 ; + RECT 65.925 5.355 66.095 5.525 ; + RECT 65.465 5.355 65.635 5.525 ; + RECT 0.605 5.355 0.775 5.525 ; + RECT 0.145 5.355 0.315 5.525 ; + RECT 65.925 2.635 66.095 2.805 ; + RECT 65.465 2.635 65.635 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + RECT 28.205 -0.085 28.375 0.085 ; + RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; + RECT 25.445 -0.085 25.615 0.085 ; + RECT 24.985 -0.085 25.155 0.085 ; + RECT 24.525 -0.085 24.695 0.085 ; + RECT 24.065 -0.085 24.235 0.085 ; + RECT 23.605 -0.085 23.775 0.085 ; + RECT 23.145 -0.085 23.315 0.085 ; + RECT 22.685 -0.085 22.855 0.085 ; + RECT 22.225 -0.085 22.395 0.085 ; + RECT 21.765 -0.085 21.935 0.085 ; + RECT 21.305 -0.085 21.475 0.085 ; + RECT 20.845 -0.085 21.015 0.085 ; + RECT 20.385 -0.085 20.555 0.085 ; + RECT 19.925 -0.085 20.095 0.085 ; + RECT 19.465 -0.085 19.635 0.085 ; + RECT 19.005 -0.085 19.175 0.085 ; + RECT 18.545 -0.085 18.715 0.085 ; + RECT 18.085 -0.085 18.255 0.085 ; + RECT 17.625 -0.085 17.795 0.085 ; + RECT 17.165 -0.085 17.335 0.085 ; + RECT 16.705 -0.085 16.875 0.085 ; + RECT 16.245 -0.085 16.415 0.085 ; + RECT 15.785 -0.085 15.955 0.085 ; + RECT 15.325 -0.085 15.495 0.085 ; + RECT 14.865 -0.085 15.035 0.085 ; + RECT 14.405 -0.085 14.575 0.085 ; + RECT 13.945 -0.085 14.115 0.085 ; + RECT 13.485 -0.085 13.655 0.085 ; + RECT 13.025 -0.085 13.195 0.085 ; + RECT 12.565 -0.085 12.735 0.085 ; + RECT 12.105 -0.085 12.275 0.085 ; + RECT 11.645 -0.085 11.815 0.085 ; + RECT 11.185 -0.085 11.355 0.085 ; + RECT 10.725 -0.085 10.895 0.085 ; + RECT 10.265 -0.085 10.435 0.085 ; + RECT 9.805 -0.085 9.975 0.085 ; + RECT 9.345 -0.085 9.515 0.085 ; + RECT 8.885 -0.085 9.055 0.085 ; + RECT 8.425 -0.085 8.595 0.085 ; + RECT 7.965 -0.085 8.135 0.085 ; + RECT 7.505 -0.085 7.675 0.085 ; + RECT 7.045 -0.085 7.215 0.085 ; + RECT 6.585 -0.085 6.755 0.085 ; + RECT 6.125 -0.085 6.295 0.085 ; + RECT 5.665 -0.085 5.835 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 0.145 -0.085 0.315 0.085 ; + LAYER via ; + RECT 55.125 76.085 55.275 76.235 ; + RECT 25.685 76.085 25.835 76.235 ; + RECT 55.125 -0.075 55.275 0.075 ; + RECT 25.685 -0.075 25.835 0.075 ; + LAYER via2 ; + RECT 55.1 76.06 55.3 76.26 ; + RECT 25.66 76.06 25.86 76.26 ; + RECT 1.28 58.38 1.48 58.58 ; + RECT 1.28 20.3 1.48 20.5 ; + RECT 1.28 14.86 1.48 15.06 ; + RECT 64.76 8.74 64.96 8.94 ; + RECT 64.76 3.3 64.96 3.5 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; + LAYER via3 ; + RECT 55.1 76.06 55.3 76.26 ; + RECT 25.66 76.06 25.86 76.26 ; + RECT 1.74 21.66 1.94 21.86 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; + LAYER OVERLAP ; + POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ; + END +END cby_2__1_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef index 4cfa752..a4cfe9a 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -375,7 +363,7 @@ MACRO sb_0__0_ USE CLOCK ; PORT LAYER met2 ; - RECT 16.95 80.24 17.09 81.6 ; + RECT 14.19 80.24 14.33 81.6 ; END END prog_clk[0] PIN chany_top_in[0] @@ -383,7 +371,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 80.24 45.15 81.6 ; + RECT 51.45 80.24 51.59 81.6 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -391,7 +379,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 80.24 46.07 81.6 ; + RECT 44.55 80.24 44.69 81.6 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -399,7 +387,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 80.24 53.43 81.6 ; + RECT 42.71 80.24 42.85 81.6 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -407,7 +395,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.67 80.24 31.81 81.6 ; + RECT 22.01 80.24 22.15 81.6 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -415,7 +403,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.91 80.24 29.05 81.6 ; + RECT 45.47 80.24 45.61 81.6 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -423,7 +411,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 80.24 33.65 81.6 ; + RECT 27.53 80.24 27.67 81.6 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -431,7 +419,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 80.24 49.75 81.6 ; + RECT 29.37 80.24 29.51 81.6 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -439,7 +427,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 80.24 50.67 81.6 ; + RECT 22.93 80.24 23.07 81.6 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -447,23 +435,23 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 80.24 64.01 81.6 ; + RECT 23.85 80.24 23.99 81.6 ; END END chany_top_in[8] PIN chany_top_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 56.05 80.24 56.19 81.6 ; + LAYER met4 ; + RECT 36.65 80.24 36.95 81.6 ; END END chany_top_in[9] PIN chany_top_in[10] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 27.07 80.24 27.21 81.6 ; + LAYER met4 ; + RECT 38.49 80.24 38.79 81.6 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -471,7 +459,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.75 80.24 30.89 81.6 ; + RECT 47.31 80.24 47.45 81.6 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -479,39 +467,39 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 80.24 57.11 81.6 ; + RECT 43.63 80.24 43.77 81.6 ; END END chany_top_in[12] PIN chany_top_in[13] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 32.97 80.24 33.27 81.6 ; + LAYER met2 ; + RECT 62.03 80.24 62.17 81.6 ; END END chany_top_in[13] PIN chany_top_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 12.73 80.24 13.03 81.6 ; + LAYER met2 ; + RECT 7.29 80.24 7.43 81.6 ; END END chany_top_in[14] PIN chany_top_in[15] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 47.69 80.24 47.99 81.6 ; + LAYER met2 ; + RECT 26.61 80.24 26.75 81.6 ; END END chany_top_in[15] PIN chany_top_in[16] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 42.17 80.24 42.47 81.6 ; + LAYER met2 ; + RECT 30.29 80.24 30.43 81.6 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -519,7 +507,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 14.57 80.24 14.87 81.6 ; + RECT 56.89 80.24 57.19 81.6 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -527,7 +515,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 45.85 80.24 46.15 81.6 ; + RECT 52.29 80.24 52.59 81.6 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -535,7 +523,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 80.24 47.91 81.6 ; + RECT 28.45 80.24 28.59 81.6 ; END END chany_top_in[19] PIN top_left_grid_pin_1_[0] @@ -543,7 +531,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 2.23 80.24 2.37 81.6 ; + RECT 57.89 80.24 58.03 81.6 ; END END top_left_grid_pin_1_[0] PIN chanx_right_in[0] @@ -551,7 +539,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 17.53 84.64 17.83 ; + RECT 83.26 36.57 84.64 36.87 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -559,7 +547,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 14.81 84.64 15.11 ; + RECT 83.26 18.89 84.64 19.19 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -567,23 +555,23 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 29.09 84.64 29.39 ; + RECT 83.26 17.53 84.64 17.83 ; END END chanx_right_in[2] PIN chanx_right_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 83.26 8.01 84.64 8.31 ; + LAYER met2 ; + RECT 81.35 0 81.49 1.36 ; END END chanx_right_in[3] PIN chanx_right_in[4] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 83.26 12.09 84.64 12.39 ; + LAYER met2 ; + RECT 82.27 0 82.41 1.36 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -591,7 +579,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 6.65 84.64 6.95 ; + RECT 83.26 10.73 84.64 11.03 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -599,7 +587,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 37.93 84.64 38.23 ; + RECT 83.26 39.29 84.64 39.59 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -607,7 +595,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 42.01 84.64 42.31 ; + RECT 83.26 21.61 84.64 21.91 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -615,15 +603,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 13.45 84.64 13.75 ; + RECT 83.26 43.37 84.64 43.67 ; END END chanx_right_in[8] PIN chanx_right_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 83.26 46.09 84.64 46.39 ; + LAYER met2 ; + RECT 80.43 0 80.57 1.36 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -631,7 +619,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 18.89 84.64 19.19 ; + RECT 83.26 3.93 84.64 4.23 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -639,7 +627,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 16.17 84.64 16.47 ; + RECT 83.26 42.01 84.64 42.31 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -647,7 +635,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 31.81 84.64 32.11 ; + RECT 83.26 37.93 84.64 38.23 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -655,7 +643,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 59.69 84.64 59.99 ; + RECT 83.26 46.09 84.64 46.39 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -663,15 +651,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 24.33 84.64 24.63 ; + RECT 83.26 40.65 84.64 40.95 ; END END chanx_right_in[14] PIN chanx_right_in[15] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 83.26 33.17 84.64 33.47 ; + LAYER met4 ; + RECT 79.89 0 80.19 1.36 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -679,7 +667,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 9.37 84.64 9.67 ; + RECT 83.26 25.69 84.64 25.99 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -687,7 +675,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 40.65 84.64 40.95 ; + RECT 83.26 6.65 84.64 6.95 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -695,7 +683,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 51.53 84.64 51.83 ; + RECT 83.26 12.09 84.64 12.39 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -703,87 +691,63 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 48.81 84.64 49.11 ; + RECT 83.26 13.45 84.64 13.75 ; END END chanx_right_in[19] - PIN right_top_grid_pin_42_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 76.29 63.92 76.43 65.28 ; - END - END right_top_grid_pin_42_[0] - PIN right_top_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.95 80.24 63.09 81.6 ; - END - END right_top_grid_pin_43_[0] - PIN right_top_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 78.59 63.92 78.73 65.28 ; - END - END right_top_grid_pin_44_[0] - PIN right_top_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 81.81 63.92 81.95 65.28 ; - END - END right_top_grid_pin_45_[0] - PIN right_top_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 80.89 63.92 81.03 65.28 ; - END - END right_top_grid_pin_46_[0] - PIN right_top_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 77.21 63.92 77.35 65.28 ; - END - END right_top_grid_pin_47_[0] - PIN right_top_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 79.89 63.92 80.19 65.28 ; - END - END right_top_grid_pin_48_[0] - PIN right_top_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 79.97 63.92 80.11 65.28 ; - END - END right_top_grid_pin_49_[0] PIN right_bottom_grid_pin_1_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 81.81 0 81.95 1.36 ; + LAYER met3 ; + RECT 83.26 20.25 84.64 20.55 ; END END right_bottom_grid_pin_1_[0] + PIN right_bottom_grid_pin_3_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 48.81 84.64 49.11 ; + END + END right_bottom_grid_pin_3_[0] + PIN right_bottom_grid_pin_5_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 44.73 84.64 45.03 ; + END + END right_bottom_grid_pin_5_[0] + PIN right_bottom_grid_pin_7_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 30.45 84.64 30.75 ; + END + END right_bottom_grid_pin_7_[0] + PIN right_bottom_grid_pin_9_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 22.97 84.64 23.27 ; + END + END right_bottom_grid_pin_9_[0] + PIN right_bottom_grid_pin_11_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 24.33 84.64 24.63 ; + END + END right_bottom_grid_pin_11_[0] PIN ccff_head[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 73.53 0 73.67 1.36 ; + LAYER met3 ; + RECT 83.26 27.05 84.64 27.35 ; END END ccff_head[0] PIN chany_top_out[0] @@ -791,7 +755,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 80.24 42.39 81.6 ; + RECT 56.05 80.24 56.19 81.6 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -799,7 +763,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 80.24 46.99 81.6 ; + RECT 24.77 80.24 24.91 81.6 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -807,15 +771,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 80.24 43.31 81.6 ; + RECT 50.53 80.24 50.67 81.6 ; END END chany_top_out[2] PIN chany_top_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 51.45 80.24 51.59 81.6 ; + LAYER met4 ; + RECT 20.09 80.24 20.39 81.6 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -823,15 +787,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.59 80.24 32.73 81.6 ; + RECT 49.61 80.24 49.75 81.6 ; END END chany_top_out[4] PIN chany_top_out[5] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 54.21 80.24 54.35 81.6 ; + LAYER met4 ; + RECT 43.09 80.24 43.39 81.6 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -839,7 +803,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 4.45 80.24 4.75 81.6 ; + RECT 9.05 80.24 9.35 81.6 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -847,7 +811,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 49.53 80.24 49.83 81.6 ; + RECT 50.45 80.24 50.75 81.6 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -855,7 +819,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 6.29 80.24 6.59 81.6 ; + RECT 44.93 80.24 45.23 81.6 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -863,7 +827,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 8.13 80.24 8.43 81.6 ; + RECT 5.37 80.24 5.67 81.6 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -871,15 +835,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 80.24 48.83 81.6 ; + RECT 46.39 80.24 46.53 81.6 ; END END chany_top_out[10] PIN chany_top_out[11] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 52.37 80.24 52.51 81.6 ; + LAYER met4 ; + RECT 48.61 80.24 48.91 81.6 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -887,7 +851,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 80.24 7.89 81.6 ; + RECT 52.37 80.24 52.51 81.6 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -895,15 +859,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 23.77 80.24 24.07 81.6 ; + RECT 46.77 80.24 47.07 81.6 ; END END chany_top_out[13] PIN chany_top_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 8.67 80.24 8.81 81.6 ; + LAYER met4 ; + RECT 29.29 80.24 29.59 81.6 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -911,7 +875,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 31.13 80.24 31.43 81.6 ; + RECT 21.93 80.24 22.23 81.6 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -919,15 +883,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.99 80.24 28.13 81.6 ; + RECT 48.69 80.24 48.83 81.6 ; END END chany_top_out[16] PIN chany_top_out[17] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 44.09 80.24 44.23 81.6 ; + LAYER met4 ; + RECT 27.45 80.24 27.75 81.6 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -935,7 +899,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 29.29 80.24 29.59 81.6 ; + RECT 7.21 80.24 7.51 81.6 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -943,7 +907,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 27.45 80.24 27.75 81.6 ; + RECT 23.77 80.24 24.07 81.6 ; END END chany_top_out[19] PIN chanx_right_out[0] @@ -951,7 +915,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 10.73 84.64 11.03 ; + RECT 83.26 60.37 84.64 60.67 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -959,7 +923,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 58.33 84.64 58.63 ; + RECT 83.26 51.53 84.64 51.83 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -967,7 +931,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 54.25 84.64 54.55 ; + RECT 83.26 16.17 84.64 16.47 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -975,7 +939,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 56.97 84.64 57.27 ; + RECT 83.26 8.01 84.64 8.31 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -983,7 +947,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 27.73 84.64 28.03 ; + RECT 83.26 14.81 84.64 15.11 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -991,7 +955,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 61.73 84.64 62.03 ; + RECT 83.26 57.65 84.64 57.95 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -999,7 +963,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 34.53 84.64 34.83 ; + RECT 83.26 56.29 84.64 56.59 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -1007,7 +971,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 39.29 84.64 39.59 ; + RECT 83.26 59.01 84.64 59.31 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1015,7 +979,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 26.37 84.64 26.67 ; + RECT 83.26 52.89 84.64 53.19 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1023,7 +987,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 47.45 84.64 47.75 ; + RECT 83.26 61.73 84.64 62.03 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1031,7 +995,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 20.25 84.64 20.55 ; + RECT 83.26 9.37 84.64 9.67 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1039,7 +1003,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 52.89 84.64 53.19 ; + RECT 83.26 50.17 84.64 50.47 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1047,7 +1011,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 30.45 84.64 30.75 ; + RECT 83.26 54.93 84.64 55.23 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1055,7 +1019,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 55.61 84.64 55.91 ; + RECT 83.26 35.21 84.64 35.51 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1063,7 +1027,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 22.97 84.64 23.27 ; + RECT 83.26 47.45 84.64 47.75 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1071,15 +1035,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 44.73 84.64 45.03 ; + RECT 83.26 5.29 84.64 5.59 ; END END chanx_right_out[15] PIN chanx_right_out[16] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 83.26 35.89 84.64 36.19 ; + LAYER met2 ; + RECT 79.51 0 79.65 1.36 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1087,7 +1051,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 50.17 84.64 50.47 ; + RECT 83.26 33.85 84.64 34.15 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1095,7 +1059,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 21.61 84.64 21.91 ; + RECT 83.26 29.09 84.64 29.39 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1103,7 +1067,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 43.37 84.64 43.67 ; + RECT 83.26 32.49 84.64 32.79 ; END END chanx_right_out[19] PIN ccff_tail[0] @@ -1111,7 +1075,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; + RECT 0 11.41 1.38 11.71 ; END END ccff_tail[0] PIN VDD @@ -1211,18 +1175,18 @@ MACRO sb_0__0_ RECT 65.32 78.795 66.24 78.965 ; RECT 0 78.795 3.68 78.965 ; RECT 65.32 76.075 66.24 76.245 ; - RECT 0 76.075 1.84 76.245 ; + RECT 0 76.075 3.68 76.245 ; RECT 65.32 73.355 66.24 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 65.32 70.635 66.24 70.805 ; - RECT 0 70.635 1.84 70.805 ; + RECT 0 73.355 3.68 73.525 ; + RECT 65.78 70.635 66.24 70.805 ; + RECT 0 70.635 3.68 70.805 ; RECT 65.32 67.915 66.24 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 62.56 65.195 84.64 65.365 ; + RECT 0 67.915 3.68 68.085 ; + RECT 63.48 65.195 84.64 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 80.96 62.475 84.64 62.645 ; + RECT 83.72 62.475 84.64 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 84.18 59.755 84.64 59.925 ; + RECT 83.72 59.755 84.64 59.925 ; RECT 0 59.755 3.68 59.925 ; RECT 83.72 57.035 84.64 57.205 ; RECT 0 57.035 3.68 57.205 ; @@ -1234,11 +1198,11 @@ MACRO sb_0__0_ RECT 0 48.875 3.68 49.045 ; RECT 83.72 46.155 84.64 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 83.72 43.435 84.64 43.605 ; + RECT 84.18 43.435 84.64 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 84.18 40.715 84.64 40.885 ; + RECT 80.96 40.715 84.64 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 83.72 37.995 84.64 38.165 ; + RECT 80.96 37.995 84.64 38.165 ; RECT 0 37.995 3.68 38.165 ; RECT 83.72 35.275 84.64 35.445 ; RECT 0 35.275 3.68 35.445 ; @@ -1250,49 +1214,46 @@ MACRO sb_0__0_ RECT 0 27.115 3.68 27.285 ; RECT 83.72 24.395 84.64 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 83.72 21.675 84.64 21.845 ; + RECT 80.96 21.675 84.64 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 83.72 18.955 84.64 19.125 ; + RECT 80.96 18.955 84.64 19.125 ; RECT 0 18.955 3.68 19.125 ; RECT 83.72 16.235 84.64 16.405 ; RECT 0 16.235 3.68 16.405 ; RECT 83.72 13.515 84.64 13.685 ; RECT 0 13.515 3.68 13.685 ; RECT 83.72 10.795 84.64 10.965 ; - RECT 0 10.795 3.68 10.965 ; - RECT 80.96 8.075 84.64 8.245 ; + RECT 0 10.795 1.84 10.965 ; + RECT 83.72 8.075 84.64 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 80.96 5.355 84.64 5.525 ; + RECT 83.72 5.355 84.64 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 84.18 2.635 84.64 2.805 ; + RECT 83.72 2.635 84.64 2.805 ; RECT 0 2.635 3.68 2.805 ; RECT 0 -0.085 84.64 0.085 ; LAYER met2 ; RECT 55.06 81.415 55.34 81.785 ; RECT 25.62 81.415 25.9 81.785 ; - POLYGON 68.15 65.01 68.15 51.61 68.01 51.61 68.01 64.87 64.79 64.87 64.79 65.01 ; - RECT 79.45 63.42 79.71 63.74 ; + RECT 44.03 79.74 44.29 80.06 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 81.32 65.96 65 76.01 65 76.01 63.64 76.71 63.64 76.71 65 76.93 65 76.93 63.64 77.63 63.64 77.63 65 78.31 65 78.31 63.64 79.01 63.64 79.01 65 79.69 65 79.69 63.64 80.39 63.64 80.39 65 80.61 65 80.61 63.64 81.31 63.64 81.31 65 81.53 65 81.53 63.64 82.23 63.64 82.23 65 84.36 65 84.36 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 73.95 0.28 73.95 1.64 73.25 1.64 73.25 0.28 0.28 0.28 0.28 81.32 1.95 81.32 1.95 79.96 2.65 79.96 2.65 81.32 7.47 81.32 7.47 79.96 8.17 79.96 8.17 81.32 8.39 81.32 8.39 79.96 9.09 79.96 9.09 81.32 16.67 81.32 16.67 79.96 17.37 79.96 17.37 81.32 26.79 81.32 26.79 79.96 27.49 79.96 27.49 81.32 27.71 81.32 27.71 79.96 28.41 79.96 28.41 81.32 28.63 81.32 28.63 79.96 29.33 79.96 29.33 81.32 30.47 81.32 30.47 79.96 31.17 79.96 31.17 81.32 31.39 81.32 31.39 79.96 32.09 79.96 32.09 81.32 32.31 81.32 32.31 79.96 33.01 79.96 33.01 81.32 33.23 81.32 33.23 79.96 33.93 79.96 33.93 81.32 41.97 81.32 41.97 79.96 42.67 79.96 42.67 81.32 42.89 81.32 42.89 79.96 43.59 79.96 43.59 81.32 43.81 81.32 43.81 79.96 44.51 79.96 44.51 81.32 44.73 81.32 44.73 79.96 45.43 79.96 45.43 81.32 45.65 81.32 45.65 79.96 46.35 79.96 46.35 81.32 46.57 81.32 46.57 79.96 47.27 79.96 47.27 81.32 47.49 81.32 47.49 79.96 48.19 79.96 48.19 81.32 48.41 81.32 48.41 79.96 49.11 79.96 49.11 81.32 49.33 81.32 49.33 79.96 50.03 79.96 50.03 81.32 50.25 81.32 50.25 79.96 50.95 79.96 50.95 81.32 51.17 81.32 51.17 79.96 51.87 79.96 51.87 81.32 52.09 81.32 52.09 79.96 52.79 79.96 52.79 81.32 53.01 81.32 53.01 79.96 53.71 79.96 53.71 81.32 53.93 81.32 53.93 79.96 54.63 79.96 54.63 81.32 55.77 81.32 55.77 79.96 56.47 79.96 56.47 81.32 56.69 81.32 56.69 79.96 57.39 79.96 57.39 81.32 62.67 81.32 62.67 79.96 63.37 79.96 63.37 81.32 63.59 81.32 63.59 79.96 64.29 79.96 64.29 81.32 ; + POLYGON 65.96 81.32 65.96 65 84.36 65 84.36 0.28 82.69 0.28 82.69 1.64 81.99 1.64 81.99 0.28 81.77 0.28 81.77 1.64 81.07 1.64 81.07 0.28 80.85 0.28 80.85 1.64 80.15 1.64 80.15 0.28 79.93 0.28 79.93 1.64 79.23 1.64 79.23 0.28 0.28 0.28 0.28 81.32 7.01 81.32 7.01 79.96 7.71 79.96 7.71 81.32 13.91 81.32 13.91 79.96 14.61 79.96 14.61 81.32 21.73 81.32 21.73 79.96 22.43 79.96 22.43 81.32 22.65 81.32 22.65 79.96 23.35 79.96 23.35 81.32 23.57 81.32 23.57 79.96 24.27 79.96 24.27 81.32 24.49 81.32 24.49 79.96 25.19 79.96 25.19 81.32 26.33 81.32 26.33 79.96 27.03 79.96 27.03 81.32 27.25 81.32 27.25 79.96 27.95 79.96 27.95 81.32 28.17 81.32 28.17 79.96 28.87 79.96 28.87 81.32 29.09 81.32 29.09 79.96 29.79 79.96 29.79 81.32 30.01 81.32 30.01 79.96 30.71 79.96 30.71 81.32 42.43 81.32 42.43 79.96 43.13 79.96 43.13 81.32 43.35 81.32 43.35 79.96 44.05 79.96 44.05 81.32 44.27 81.32 44.27 79.96 44.97 79.96 44.97 81.32 45.19 81.32 45.19 79.96 45.89 79.96 45.89 81.32 46.11 81.32 46.11 79.96 46.81 79.96 46.81 81.32 47.03 81.32 47.03 79.96 47.73 79.96 47.73 81.32 48.41 81.32 48.41 79.96 49.11 79.96 49.11 81.32 49.33 81.32 49.33 79.96 50.03 79.96 50.03 81.32 50.25 81.32 50.25 79.96 50.95 79.96 50.95 81.32 51.17 81.32 51.17 79.96 51.87 79.96 51.87 81.32 52.09 81.32 52.09 79.96 52.79 79.96 52.79 81.32 55.77 81.32 55.77 79.96 56.47 79.96 56.47 81.32 57.61 81.32 57.61 79.96 58.31 79.96 58.31 81.32 61.75 81.32 61.75 79.96 62.45 79.96 62.45 81.32 ; LAYER met4 ; - POLYGON 65.84 81.2 65.84 64.88 79.49 64.88 79.49 63.52 80.59 63.52 80.59 64.88 84.24 64.88 84.24 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 81.2 4.05 81.2 4.05 79.84 5.15 79.84 5.15 81.2 5.89 81.2 5.89 79.84 6.99 79.84 6.99 81.2 7.73 81.2 7.73 79.84 8.83 79.84 8.83 81.2 10.34 81.2 10.34 80.6 11.74 80.6 11.74 81.2 12.33 81.2 12.33 79.84 13.43 79.84 13.43 81.2 14.17 81.2 14.17 79.84 15.27 79.84 15.27 81.2 23.37 81.2 23.37 79.84 24.47 79.84 24.47 81.2 25.06 81.2 25.06 80.6 26.46 80.6 26.46 81.2 27.05 81.2 27.05 79.84 28.15 79.84 28.15 81.2 28.89 81.2 28.89 79.84 29.99 79.84 29.99 81.2 30.73 81.2 30.73 79.84 31.83 79.84 31.83 81.2 32.57 81.2 32.57 79.84 33.67 79.84 33.67 81.2 39.78 81.2 39.78 80.6 41.18 80.6 41.18 81.2 41.77 81.2 41.77 79.84 42.87 79.84 42.87 81.2 45.45 81.2 45.45 79.84 46.55 79.84 46.55 81.2 47.29 81.2 47.29 79.84 48.39 79.84 48.39 81.2 49.13 81.2 49.13 79.84 50.23 79.84 50.23 81.2 54.5 81.2 54.5 80.6 55.9 80.6 55.9 81.2 ; + POLYGON 65.84 81.2 65.84 64.88 84.24 64.88 84.24 0.4 80.59 0.4 80.59 1.76 79.49 1.76 79.49 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 81.2 4.97 81.2 4.97 79.84 6.07 79.84 6.07 81.2 6.81 81.2 6.81 79.84 7.91 79.84 7.91 81.2 8.65 81.2 8.65 79.84 9.75 79.84 9.75 81.2 10.34 81.2 10.34 80.6 11.74 80.6 11.74 81.2 19.69 81.2 19.69 79.84 20.79 79.84 20.79 81.2 21.53 81.2 21.53 79.84 22.63 79.84 22.63 81.2 23.37 81.2 23.37 79.84 24.47 79.84 24.47 81.2 25.06 81.2 25.06 80.6 26.46 80.6 26.46 81.2 27.05 81.2 27.05 79.84 28.15 79.84 28.15 81.2 28.89 81.2 28.89 79.84 29.99 79.84 29.99 81.2 36.25 81.2 36.25 79.84 37.35 79.84 37.35 81.2 38.09 81.2 38.09 79.84 39.19 79.84 39.19 81.2 39.78 81.2 39.78 80.6 41.18 80.6 41.18 81.2 42.69 81.2 42.69 79.84 43.79 79.84 43.79 81.2 44.53 81.2 44.53 79.84 45.63 79.84 45.63 81.2 46.37 81.2 46.37 79.84 47.47 79.84 47.47 81.2 48.21 81.2 48.21 79.84 49.31 79.84 49.31 81.2 50.05 81.2 50.05 79.84 51.15 79.84 51.15 81.2 51.89 81.2 51.89 79.84 52.99 79.84 52.99 81.2 54.5 81.2 54.5 80.6 55.9 80.6 55.9 81.2 56.49 81.2 56.49 79.84 57.59 79.84 57.59 81.2 ; LAYER met3 ; POLYGON 55.365 81.765 55.365 81.76 55.58 81.76 55.58 81.44 55.365 81.44 55.365 81.435 55.035 81.435 55.035 81.44 54.82 81.44 54.82 81.76 55.035 81.76 55.035 81.765 ; POLYGON 25.925 81.765 25.925 81.76 26.14 81.76 26.14 81.44 25.925 81.44 25.925 81.435 25.595 81.435 25.595 81.44 25.38 81.44 25.38 81.76 25.595 81.76 25.595 81.765 ; - POLYGON 82.86 49.79 82.86 49.77 83.41 49.77 83.41 49.49 78.51 49.49 78.51 49.79 ; + POLYGON 83.41 15.79 83.41 15.51 82.86 15.51 82.86 15.49 60.11 15.49 60.11 15.79 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 81.2 65.84 64.88 84.24 64.88 84.24 62.43 82.86 62.43 82.86 61.33 84.24 61.33 84.24 60.39 82.86 60.39 82.86 59.29 84.24 59.29 84.24 59.03 82.86 59.03 82.86 57.93 84.24 57.93 84.24 57.67 82.86 57.67 82.86 56.57 84.24 56.57 84.24 56.31 82.86 56.31 82.86 55.21 84.24 55.21 84.24 54.95 82.86 54.95 82.86 53.85 84.24 53.85 84.24 53.59 82.86 53.59 82.86 52.49 84.24 52.49 84.24 52.23 82.86 52.23 82.86 51.13 84.24 51.13 84.24 50.87 82.86 50.87 82.86 49.77 84.24 49.77 84.24 49.51 82.86 49.51 82.86 48.41 84.24 48.41 84.24 48.15 82.86 48.15 82.86 47.05 84.24 47.05 84.24 46.79 82.86 46.79 82.86 45.69 84.24 45.69 84.24 45.43 82.86 45.43 82.86 44.33 84.24 44.33 84.24 44.07 82.86 44.07 82.86 42.97 84.24 42.97 84.24 42.71 82.86 42.71 82.86 41.61 84.24 41.61 84.24 41.35 82.86 41.35 82.86 40.25 84.24 40.25 84.24 39.99 82.86 39.99 82.86 38.89 84.24 38.89 84.24 38.63 82.86 38.63 82.86 37.53 84.24 37.53 84.24 36.59 82.86 36.59 82.86 35.49 84.24 35.49 84.24 35.23 82.86 35.23 82.86 34.13 84.24 34.13 84.24 33.87 82.86 33.87 82.86 32.77 84.24 32.77 84.24 32.51 82.86 32.51 82.86 31.41 84.24 31.41 84.24 31.15 82.86 31.15 82.86 30.05 84.24 30.05 84.24 29.79 82.86 29.79 82.86 28.69 84.24 28.69 84.24 28.43 82.86 28.43 82.86 27.33 84.24 27.33 84.24 27.07 82.86 27.07 82.86 25.97 84.24 25.97 84.24 25.03 82.86 25.03 82.86 23.93 84.24 23.93 84.24 23.67 82.86 23.67 82.86 22.57 84.24 22.57 84.24 22.31 82.86 22.31 82.86 21.21 84.24 21.21 84.24 20.95 82.86 20.95 82.86 19.85 84.24 19.85 84.24 19.59 82.86 19.59 82.86 18.49 84.24 18.49 84.24 18.23 82.86 18.23 82.86 17.13 84.24 17.13 84.24 16.87 82.86 16.87 82.86 15.77 84.24 15.77 84.24 15.51 82.86 15.51 82.86 14.41 84.24 14.41 84.24 14.15 82.86 14.15 82.86 13.05 84.24 13.05 84.24 12.79 82.86 12.79 82.86 11.69 84.24 11.69 84.24 11.43 82.86 11.43 82.86 10.33 84.24 10.33 84.24 10.07 82.86 10.07 82.86 8.97 84.24 8.97 84.24 8.71 82.86 8.71 82.86 7.61 84.24 7.61 84.24 7.35 82.86 7.35 82.86 6.25 84.24 6.25 84.24 0.4 0.4 0.4 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 81.2 ; + POLYGON 65.84 81.2 65.84 64.88 84.24 64.88 84.24 62.43 82.86 62.43 82.86 61.33 84.24 61.33 84.24 61.07 82.86 61.07 82.86 59.97 84.24 59.97 84.24 59.71 82.86 59.71 82.86 58.61 84.24 58.61 84.24 58.35 82.86 58.35 82.86 57.25 84.24 57.25 84.24 56.99 82.86 56.99 82.86 55.89 84.24 55.89 84.24 55.63 82.86 55.63 82.86 54.53 84.24 54.53 84.24 53.59 82.86 53.59 82.86 52.49 84.24 52.49 84.24 52.23 82.86 52.23 82.86 51.13 84.24 51.13 84.24 50.87 82.86 50.87 82.86 49.77 84.24 49.77 84.24 49.51 82.86 49.51 82.86 48.41 84.24 48.41 84.24 48.15 82.86 48.15 82.86 47.05 84.24 47.05 84.24 46.79 82.86 46.79 82.86 45.69 84.24 45.69 84.24 45.43 82.86 45.43 82.86 44.33 84.24 44.33 84.24 44.07 82.86 44.07 82.86 42.97 84.24 42.97 84.24 42.71 82.86 42.71 82.86 41.61 84.24 41.61 84.24 41.35 82.86 41.35 82.86 40.25 84.24 40.25 84.24 39.99 82.86 39.99 82.86 38.89 84.24 38.89 84.24 38.63 82.86 38.63 82.86 37.53 84.24 37.53 84.24 37.27 82.86 37.27 82.86 36.17 84.24 36.17 84.24 35.91 82.86 35.91 82.86 34.81 84.24 34.81 84.24 34.55 82.86 34.55 82.86 33.45 84.24 33.45 84.24 33.19 82.86 33.19 82.86 32.09 84.24 32.09 84.24 31.15 82.86 31.15 82.86 30.05 84.24 30.05 84.24 29.79 82.86 29.79 82.86 28.69 84.24 28.69 84.24 27.75 82.86 27.75 82.86 26.65 84.24 26.65 84.24 26.39 82.86 26.39 82.86 25.29 84.24 25.29 84.24 25.03 82.86 25.03 82.86 23.93 84.24 23.93 84.24 23.67 82.86 23.67 82.86 22.57 84.24 22.57 84.24 22.31 82.86 22.31 82.86 21.21 84.24 21.21 84.24 20.95 82.86 20.95 82.86 19.85 84.24 19.85 84.24 19.59 82.86 19.59 82.86 18.49 84.24 18.49 84.24 18.23 82.86 18.23 82.86 17.13 84.24 17.13 84.24 16.87 82.86 16.87 82.86 15.77 84.24 15.77 84.24 15.51 82.86 15.51 82.86 14.41 84.24 14.41 84.24 14.15 82.86 14.15 82.86 13.05 84.24 13.05 84.24 12.79 82.86 12.79 82.86 11.69 84.24 11.69 84.24 11.43 82.86 11.43 82.86 10.33 84.24 10.33 84.24 10.07 82.86 10.07 82.86 8.97 84.24 8.97 84.24 8.71 82.86 8.71 82.86 7.61 84.24 7.61 84.24 7.35 82.86 7.35 82.86 6.25 84.24 6.25 84.24 5.99 82.86 5.99 82.86 4.89 84.24 4.89 84.24 4.63 82.86 4.63 82.86 3.53 84.24 3.53 84.24 0.4 0.4 0.4 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 81.2 ; LAYER met5 ; - POLYGON 63.04 78.4 63.04 62.08 81.44 62.08 81.44 57.84 78.24 57.84 78.24 48.24 81.44 48.24 81.44 37.44 78.24 37.44 78.24 27.84 81.44 27.84 81.44 17.04 78.24 17.04 78.24 7.44 81.44 7.44 81.44 3.2 3.2 3.2 3.2 7.44 6.4 7.44 6.4 17.04 3.2 17.04 3.2 27.84 6.4 27.84 6.4 37.44 3.2 37.44 3.2 48.24 6.4 48.24 6.4 57.84 3.2 57.84 3.2 78.4 ; + POLYGON 64.64 80 64.64 63.68 83.04 63.68 83.04 56.24 79.84 56.24 79.84 49.84 83.04 49.84 83.04 35.84 79.84 35.84 79.84 29.44 83.04 29.44 83.04 15.44 79.84 15.44 79.84 9.04 83.04 9.04 83.04 1.6 1.6 1.6 1.6 9.04 4.8 9.04 4.8 15.44 1.6 15.44 1.6 29.44 4.8 29.44 4.8 35.84 1.6 35.84 1.6 49.84 4.8 49.84 4.8 56.24 1.6 56.24 1.6 80 ; LAYER met1 ; POLYGON 65.96 81.08 65.96 79.4 65.48 79.4 65.48 78.36 65.96 78.36 65.96 76.68 65.48 76.68 65.48 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; POLYGON 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 83.88 16.84 83.88 15.8 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 ; LAYER li1 ; - RECT 47.465 80.79 48.215 81.335 ; - RECT 47.465 0.265 48.215 0.81 ; - POLYGON 65.9 81.26 65.9 64.94 84.3 64.94 84.3 0.34 0.34 0.34 0.34 81.26 ; + POLYGON 66.07 81.43 66.07 65.11 84.47 65.11 84.47 0.17 0.17 0.17 0.17 81.43 ; LAYER mcon ; RECT 65.925 81.515 66.095 81.685 ; RECT 65.465 81.515 65.635 81.685 ; @@ -1921,9 +1882,8 @@ MACRO sb_0__0_ LAYER via ; RECT 55.125 81.525 55.275 81.675 ; RECT 25.685 81.525 25.835 81.675 ; - RECT 56.965 79.825 57.115 79.975 ; - RECT 28.905 79.825 29.055 79.975 ; - RECT 7.745 79.825 7.895 79.975 ; + RECT 45.465 79.825 45.615 79.975 ; + RECT 23.845 79.825 23.995 79.975 ; RECT 55.125 65.205 55.275 65.355 ; RECT 25.685 65.205 25.835 65.355 ; RECT 55.125 -0.075 55.275 0.075 ; @@ -1931,13 +1891,8 @@ MACRO sb_0__0_ LAYER via2 ; RECT 55.1 81.5 55.3 81.7 ; RECT 25.66 81.5 25.86 81.7 ; - RECT 83.16 58.38 83.36 58.58 ; - RECT 82.7 54.3 82.9 54.5 ; - RECT 83.16 47.5 83.36 47.7 ; - RECT 82.7 43.42 82.9 43.62 ; - RECT 83.16 39.34 83.36 39.54 ; - RECT 82.7 35.94 82.9 36.14 ; - RECT 82.7 23.02 82.9 23.22 ; + RECT 82.7 50.22 82.9 50.42 ; + RECT 82.7 10.78 82.9 10.98 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; @@ -1945,98 +1900,6 @@ MACRO sb_0__0_ RECT 25.66 81.5 25.86 81.7 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; - LAYER fieldpoly ; - POLYGON 66.1 81.46 66.1 65.14 84.5 65.14 84.5 0.14 0.14 0.14 0.14 81.46 ; - LAYER diff ; - POLYGON 66.24 81.6 66.24 65.28 84.64 65.28 84.64 0 0 0 0 81.6 ; - LAYER nwell ; - POLYGON 66.43 80.295 66.43 77.465 65.13 77.465 65.13 79.07 65.59 79.07 65.59 80.295 ; - POLYGON 3.87 80.295 3.87 78.69 2.03 78.69 2.03 77.465 -0.19 77.465 -0.19 80.295 ; - POLYGON 66.43 74.855 66.43 72.025 65.13 72.025 65.13 73.63 65.59 73.63 65.59 74.855 ; - RECT -0.19 72.025 2.03 74.855 ; - POLYGON 66.43 69.415 66.43 66.585 65.13 66.585 65.13 68.19 65.59 68.19 65.59 69.415 ; - RECT -0.19 66.585 2.03 69.415 ; - POLYGON 84.83 63.975 84.83 61.145 83.99 61.145 83.99 62.37 80.77 62.37 80.77 63.975 ; - RECT -0.19 61.145 3.87 63.975 ; - POLYGON 84.83 58.535 84.83 55.705 83.53 55.705 83.53 57.31 83.99 57.31 83.99 58.535 ; - RECT -0.19 55.705 3.87 58.535 ; - POLYGON 84.83 53.095 84.83 50.265 83.53 50.265 83.53 51.87 83.99 51.87 83.99 53.095 ; - RECT -0.19 50.265 3.87 53.095 ; - RECT 83.53 44.825 84.83 47.655 ; - RECT -0.19 44.825 3.87 47.655 ; - RECT 83.99 39.385 84.83 42.215 ; - RECT -0.19 39.385 3.87 42.215 ; - RECT 83.53 33.945 84.83 36.775 ; - RECT -0.19 33.945 3.87 36.775 ; - RECT 83.53 28.505 84.83 31.335 ; - RECT -0.19 28.505 3.87 31.335 ; - RECT 83.53 23.065 84.83 25.895 ; - RECT -0.19 23.065 3.87 25.895 ; - POLYGON 84.83 20.455 84.83 17.625 83.53 17.625 83.53 19.23 83.99 19.23 83.99 20.455 ; - RECT -0.19 17.625 3.87 20.455 ; - POLYGON 84.83 15.015 84.83 12.185 83.53 12.185 83.53 13.79 83.99 13.79 83.99 15.015 ; - RECT -0.19 12.185 3.87 15.015 ; - POLYGON 84.83 9.575 84.83 6.745 80.77 6.745 80.77 8.35 83.99 8.35 83.99 9.575 ; - RECT -0.19 6.745 3.87 9.575 ; - RECT 83.99 1.305 84.83 4.135 ; - RECT -0.19 1.305 3.87 4.135 ; - POLYGON 66.24 81.6 66.24 65.28 84.64 65.28 84.64 0 0 0 0 81.6 ; - LAYER pwell ; - RECT 59.47 81.55 59.69 81.72 ; - RECT 55.79 81.55 56.01 81.72 ; - RECT 52.11 81.55 52.33 81.72 ; - RECT 48.43 81.55 48.65 81.72 ; - RECT 40.61 81.55 40.83 81.72 ; - RECT 36.93 81.55 37.15 81.72 ; - RECT 33.25 81.55 33.47 81.72 ; - RECT 29.57 81.55 29.79 81.72 ; - RECT 25.89 81.55 26.11 81.72 ; - RECT 22.21 81.55 22.43 81.72 ; - RECT 18.53 81.55 18.75 81.72 ; - RECT 14.85 81.55 15.07 81.72 ; - RECT 11.17 81.55 11.39 81.72 ; - RECT 7.49 81.55 7.71 81.72 ; - RECT 3.81 81.55 4.03 81.72 ; - RECT 0.13 81.55 0.35 81.72 ; - RECT 63.195 81.54 63.305 81.66 ; - RECT 44.335 81.54 44.445 81.66 ; - RECT 65.92 81.545 66.04 81.655 ; - RECT 47.06 81.545 47.18 81.655 ; - RECT 65.015 81.54 65.175 81.65 ; - RECT 46.155 81.54 46.315 81.65 ; - RECT 81.09 65.23 81.31 65.4 ; - RECT 77.41 65.23 77.63 65.4 ; - RECT 73.73 65.23 73.95 65.4 ; - RECT 70.05 65.23 70.27 65.4 ; - RECT 66.37 65.23 66.59 65.4 ; - RECT 83.415 -0.05 83.575 0.06 ; - RECT 81.595 -0.06 81.705 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 84.32 -0.055 84.44 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 77.87 -0.12 78.09 0.05 ; - RECT 74.19 -0.12 74.41 0.05 ; - RECT 70.51 -0.12 70.73 0.05 ; - RECT 66.83 -0.12 67.05 0.05 ; - RECT 63.15 -0.12 63.37 0.05 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - RECT 14.85 -0.12 15.07 0.05 ; - RECT 11.17 -0.12 11.39 0.05 ; - RECT 7.49 -0.12 7.71 0.05 ; - RECT 3.81 -0.12 4.03 0.05 ; - RECT 0.13 -0.12 0.35 0.05 ; - POLYGON 66.24 81.6 66.24 65.28 84.64 65.28 84.64 0 0 0 0 81.6 ; LAYER OVERLAP ; POLYGON 0 0 0 81.6 66.24 81.6 66.24 65.28 84.64 65.28 84.64 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef index 9793fcc..ae6b4fc 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -383,7 +371,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 96.56 45.15 97.92 ; + RECT 51.45 96.56 51.59 97.92 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -391,7 +379,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 96.56 46.07 97.92 ; + RECT 44.55 96.56 44.69 97.92 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -399,7 +387,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 96.56 53.43 97.92 ; + RECT 42.71 96.56 42.85 97.92 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -407,7 +395,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.67 96.56 31.81 97.92 ; + RECT 22.01 96.56 22.15 97.92 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -415,7 +403,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.91 96.56 29.05 97.92 ; + RECT 45.47 96.56 45.61 97.92 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -423,7 +411,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 96.56 33.65 97.92 ; + RECT 27.53 96.56 27.67 97.92 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -431,7 +419,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 96.56 49.75 97.92 ; + RECT 29.37 96.56 29.51 97.92 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -439,7 +427,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 96.56 50.67 97.92 ; + RECT 22.93 96.56 23.07 97.92 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -447,23 +435,23 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 96.56 64.01 97.92 ; + RECT 23.85 96.56 23.99 97.92 ; END END chany_top_in[8] PIN chany_top_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 56.05 96.56 56.19 97.92 ; + LAYER met4 ; + RECT 36.65 96.56 36.95 97.92 ; END END chany_top_in[9] PIN chany_top_in[10] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 27.07 96.56 27.21 97.92 ; + LAYER met4 ; + RECT 38.49 96.56 38.79 97.92 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -471,7 +459,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.75 96.56 30.89 97.92 ; + RECT 47.31 96.56 47.45 97.92 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -479,39 +467,39 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 96.56 57.11 97.92 ; + RECT 43.63 96.56 43.77 97.92 ; END END chany_top_in[12] PIN chany_top_in[13] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 32.97 96.56 33.27 97.92 ; + LAYER met2 ; + RECT 62.03 96.56 62.17 97.92 ; END END chany_top_in[13] PIN chany_top_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 12.73 96.56 13.03 97.92 ; + LAYER met2 ; + RECT 7.29 96.56 7.43 97.92 ; END END chany_top_in[14] PIN chany_top_in[15] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 47.69 96.56 47.99 97.92 ; + LAYER met2 ; + RECT 26.61 96.56 26.75 97.92 ; END END chany_top_in[15] PIN chany_top_in[16] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 42.17 96.56 42.47 97.92 ; + LAYER met2 ; + RECT 30.29 96.56 30.43 97.92 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -519,7 +507,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 14.57 96.56 14.87 97.92 ; + RECT 56.89 96.56 57.19 97.92 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -527,7 +515,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 45.85 96.56 46.15 97.92 ; + RECT 52.29 96.56 52.59 97.92 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -535,7 +523,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 96.56 47.91 97.92 ; + RECT 28.45 96.56 28.59 97.92 ; END END chany_top_in[19] PIN top_left_grid_pin_1_[0] @@ -543,7 +531,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 2.23 96.56 2.37 97.92 ; + RECT 57.89 96.56 58.03 97.92 ; END END top_left_grid_pin_1_[0] PIN chanx_right_in[0] @@ -551,7 +539,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 35.89 84.64 36.19 ; + RECT 83.26 34.53 84.64 34.83 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -559,7 +547,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 78.05 84.64 78.35 ; + RECT 83.26 22.97 84.64 23.27 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -567,7 +555,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 26.37 84.64 26.67 ; + RECT 83.26 46.09 84.64 46.39 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -575,7 +563,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 75.33 84.64 75.63 ; + RECT 83.26 20.25 84.64 20.55 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -583,7 +571,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 76.69 84.64 76.99 ; + RECT 83.26 68.53 84.64 68.83 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -591,7 +579,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 72.61 84.64 72.91 ; + RECT 83.26 67.17 84.64 67.47 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -599,7 +587,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 37.25 84.64 37.55 ; + RECT 83.26 39.97 84.64 40.27 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -607,7 +595,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 51.53 84.64 51.83 ; + RECT 83.26 37.25 84.64 37.55 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -615,7 +603,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 38.61 84.64 38.91 ; + RECT 83.26 41.33 84.64 41.63 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -623,7 +611,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 46.77 84.64 47.07 ; + RECT 83.26 61.05 84.64 61.35 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -631,7 +619,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 34.53 84.64 34.83 ; + RECT 83.26 21.61 84.64 21.91 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -639,7 +627,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 73.97 84.64 74.27 ; + RECT 83.26 55.61 84.64 55.91 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -647,7 +635,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 31.81 84.64 32.11 ; + RECT 83.26 62.41 84.64 62.71 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -655,7 +643,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 71.25 84.64 71.55 ; + RECT 83.26 27.05 84.64 27.35 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -663,7 +651,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 54.25 84.64 54.55 ; + RECT 83.26 25.69 84.64 25.99 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -671,7 +659,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 48.81 84.64 49.11 ; + RECT 83.26 28.41 84.64 28.71 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -679,7 +667,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 25.01 84.64 25.31 ; + RECT 83.26 69.89 84.64 70.19 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -687,7 +675,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 20.25 84.64 20.55 ; + RECT 83.26 35.89 84.64 36.19 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -695,7 +683,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 33.17 84.64 33.47 ; + RECT 83.26 56.97 84.64 57.27 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -703,87 +691,87 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 69.89 84.64 70.19 ; + RECT 83.26 29.77 84.64 30.07 ; END END chanx_right_in[19] - PIN right_top_grid_pin_42_[0] + PIN right_bottom_grid_pin_34_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 76.29 80.24 76.43 81.6 ; + RECT 79.51 16.32 79.65 17.68 ; END - END right_top_grid_pin_42_[0] - PIN right_top_grid_pin_43_[0] + END right_bottom_grid_pin_34_[0] + PIN right_bottom_grid_pin_35_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 62.95 96.56 63.09 97.92 ; + LAYER met3 ; + RECT 64.86 9.37 66.24 9.67 ; END - END right_top_grid_pin_43_[0] - PIN right_top_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 78.59 80.24 78.73 81.6 ; - END - END right_top_grid_pin_44_[0] - PIN right_top_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 81.81 80.24 81.95 81.6 ; - END - END right_top_grid_pin_45_[0] - PIN right_top_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 80.89 80.24 81.03 81.6 ; - END - END right_top_grid_pin_46_[0] - PIN right_top_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 77.21 80.24 77.35 81.6 ; - END - END right_top_grid_pin_47_[0] - PIN right_top_grid_pin_48_[0] + END right_bottom_grid_pin_35_[0] + PIN right_bottom_grid_pin_36_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; - RECT 79.89 80.24 80.19 81.6 ; + RECT 78.97 16.32 79.27 17.68 ; END - END right_top_grid_pin_48_[0] - PIN right_top_grid_pin_49_[0] + END right_bottom_grid_pin_36_[0] + PIN right_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 64.86 6.65 66.24 6.95 ; + END + END right_bottom_grid_pin_37_[0] + PIN right_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 64.86 5.29 66.24 5.59 ; + END + END right_bottom_grid_pin_38_[0] + PIN right_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 64.86 8.01 66.24 8.31 ; + END + END right_bottom_grid_pin_39_[0] + PIN right_bottom_grid_pin_40_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 79.97 80.24 80.11 81.6 ; + RECT 78.13 16.32 78.27 17.68 ; END - END right_top_grid_pin_49_[0] + END right_bottom_grid_pin_40_[0] + PIN right_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.95 0 63.09 1.36 ; + END + END right_bottom_grid_pin_41_[0] PIN chany_bottom_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 46.77 0 47.07 1.36 ; + LAYER met2 ; + RECT 51.91 0 52.05 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 16.41 0 16.71 1.36 ; + LAYER met2 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -791,15 +779,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 52.83 0 52.97 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 14.57 0 14.87 1.36 ; + LAYER met2 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -807,7 +795,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + RECT 42.71 0 42.85 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -815,7 +803,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; + RECT 50.07 0 50.21 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -823,15 +811,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 0 23.07 1.36 ; + RECT 20.17 0 20.31 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 27.45 0 27.75 1.36 ; + LAYER met2 ; + RECT 22.93 0 23.07 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -839,7 +827,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 9.59 0 9.73 1.36 ; + RECT 8.21 0 8.35 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -847,7 +835,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.17 0 20.31 1.36 ; + RECT 21.09 0 21.23 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -855,7 +843,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 33.51 0 33.65 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -863,7 +851,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 29.37 0 29.51 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -871,7 +859,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.81 0 58.95 1.36 ; + RECT 50.99 0 51.13 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -879,7 +867,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 0 58.03 1.36 ; + RECT 30.29 0 30.43 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -887,7 +875,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 0 57.11 1.36 ; + RECT 28.45 0 28.59 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -895,7 +883,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; + RECT 22.01 0 22.15 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -903,7 +891,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + RECT 36.27 0 36.41 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -911,7 +899,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 0 35.03 1.36 ; + RECT 6.37 0 6.51 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -919,7 +907,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.97 0 34.11 1.36 ; + RECT 31.21 0 31.35 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -927,7 +915,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.75 0 30.89 1.36 ; + RECT 7.29 0 7.43 1.36 ; END END chany_bottom_in[19] PIN bottom_left_grid_pin_1_[0] @@ -935,7 +923,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 2.23 0 2.37 1.36 ; + RECT 63.87 0 64.01 1.36 ; END END bottom_left_grid_pin_1_[0] PIN ccff_head[0] @@ -943,7 +931,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 58.33 84.64 58.63 ; + RECT 83.26 73.97 84.64 74.27 ; END END ccff_head[0] PIN chany_top_out[0] @@ -951,7 +939,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 96.56 42.39 97.92 ; + RECT 56.05 96.56 56.19 97.92 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -959,7 +947,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 96.56 46.99 97.92 ; + RECT 24.77 96.56 24.91 97.92 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -967,15 +955,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 96.56 43.31 97.92 ; + RECT 50.53 96.56 50.67 97.92 ; END END chany_top_out[2] PIN chany_top_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 51.45 96.56 51.59 97.92 ; + LAYER met4 ; + RECT 20.09 96.56 20.39 97.92 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -983,15 +971,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.59 96.56 32.73 97.92 ; + RECT 49.61 96.56 49.75 97.92 ; END END chany_top_out[4] PIN chany_top_out[5] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 54.21 96.56 54.35 97.92 ; + LAYER met4 ; + RECT 43.09 96.56 43.39 97.92 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -999,7 +987,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 4.45 96.56 4.75 97.92 ; + RECT 9.05 96.56 9.35 97.92 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -1007,7 +995,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 49.53 96.56 49.83 97.92 ; + RECT 50.45 96.56 50.75 97.92 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -1015,7 +1003,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 6.29 96.56 6.59 97.92 ; + RECT 44.93 96.56 45.23 97.92 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -1023,7 +1011,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 8.13 96.56 8.43 97.92 ; + RECT 5.37 96.56 5.67 97.92 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -1031,15 +1019,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 96.56 48.83 97.92 ; + RECT 46.39 96.56 46.53 97.92 ; END END chany_top_out[10] PIN chany_top_out[11] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 52.37 96.56 52.51 97.92 ; + LAYER met4 ; + RECT 48.61 96.56 48.91 97.92 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -1047,7 +1035,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 96.56 7.89 97.92 ; + RECT 52.37 96.56 52.51 97.92 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -1055,15 +1043,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 23.77 96.56 24.07 97.92 ; + RECT 46.77 96.56 47.07 97.92 ; END END chany_top_out[13] PIN chany_top_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 8.67 96.56 8.81 97.92 ; + LAYER met4 ; + RECT 29.29 96.56 29.59 97.92 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -1071,7 +1059,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 31.13 96.56 31.43 97.92 ; + RECT 21.93 96.56 22.23 97.92 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -1079,15 +1067,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.99 96.56 28.13 97.92 ; + RECT 48.69 96.56 48.83 97.92 ; END END chany_top_out[16] PIN chany_top_out[17] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 44.09 96.56 44.23 97.92 ; + LAYER met4 ; + RECT 27.45 96.56 27.75 97.92 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1095,7 +1083,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 29.29 96.56 29.59 97.92 ; + RECT 7.21 96.56 7.51 97.92 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1103,7 +1091,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 27.45 96.56 27.75 97.92 ; + RECT 23.77 96.56 24.07 97.92 ; END END chany_top_out[19] PIN chanx_right_out[0] @@ -1111,7 +1099,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 50.17 84.64 50.47 ; + RECT 83.26 24.33 84.64 24.63 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -1119,7 +1107,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 67.17 84.64 67.47 ; + RECT 83.26 33.17 84.64 33.47 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -1127,7 +1115,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 27.73 84.64 28.03 ; + RECT 83.26 42.69 84.64 42.99 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -1135,7 +1123,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 68.53 84.64 68.83 ; + RECT 83.26 52.89 84.64 53.19 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -1143,7 +1131,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 42.69 84.64 42.99 ; + RECT 83.26 59.69 84.64 59.99 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -1151,7 +1139,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 61.05 84.64 61.35 ; + RECT 83.26 64.45 84.64 64.75 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -1159,7 +1147,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 29.09 84.64 29.39 ; + RECT 83.26 50.85 84.64 51.15 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -1167,7 +1155,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 55.61 84.64 55.91 ; + RECT 83.26 58.33 84.64 58.63 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1175,7 +1163,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 39.97 84.64 40.27 ; + RECT 83.26 76.69 84.64 76.99 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1183,7 +1171,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 59.69 84.64 59.99 ; + RECT 83.26 71.25 84.64 71.55 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1191,7 +1179,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 44.73 84.64 45.03 ; + RECT 83.26 47.45 84.64 47.75 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1199,7 +1187,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 56.97 84.64 57.27 ; + RECT 83.26 49.49 84.64 49.79 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1207,7 +1195,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 30.45 84.64 30.75 ; + RECT 83.26 75.33 84.64 75.63 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1215,7 +1203,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 52.89 84.64 53.19 ; + RECT 83.26 78.05 84.64 78.35 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1223,7 +1211,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 22.97 84.64 23.27 ; + RECT 83.26 31.81 84.64 32.11 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1231,7 +1219,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 62.41 84.64 62.71 ; + RECT 83.26 72.61 84.64 72.91 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -1239,7 +1227,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 21.61 84.64 21.91 ; + RECT 83.26 44.73 84.64 45.03 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1247,7 +1235,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 65.13 84.64 65.43 ; + RECT 83.26 38.61 84.64 38.91 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1255,7 +1243,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 41.33 84.64 41.63 ; + RECT 83.26 54.25 84.64 54.55 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1263,7 +1251,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 63.77 84.64 64.07 ; + RECT 83.26 65.81 84.64 66.11 ; END END chanx_right_out[19] PIN chany_bottom_out[0] @@ -1271,7 +1259,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 0 22.15 1.36 ; + RECT 54.21 0 54.35 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -1279,7 +1267,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.09 0 44.23 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -1287,7 +1275,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -1295,7 +1283,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 27.53 0 27.67 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -1303,7 +1291,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 56.05 0 56.19 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -1311,7 +1299,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 0 53.43 1.36 ; + RECT 23.85 0 23.99 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -1319,7 +1307,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; + RECT 26.61 0 26.75 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -1327,7 +1315,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1335,7 +1323,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; + RECT 47.31 0 47.45 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -1343,7 +1331,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.83 0 29.97 1.36 ; + RECT 24.77 0 24.91 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1351,15 +1339,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 0 21.23 1.36 ; + RECT 62.03 0 62.17 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; + LAYER met4 ; + RECT 44.93 0 45.23 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -1367,31 +1355,31 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; + RECT 49.15 0 49.29 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + LAYER met4 ; + RECT 9.05 0 9.35 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; + LAYER met4 ; + RECT 48.61 0 48.91 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 28.91 0 29.05 1.36 ; + LAYER met4 ; + RECT 46.77 0 47.07 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1399,31 +1387,31 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.05 0 33.19 1.36 ; + RECT 40.87 0 41.01 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + LAYER met4 ; + RECT 5.37 0 5.67 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 27.07 0 27.21 1.36 ; + LAYER met4 ; + RECT 23.77 0 24.07 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 27.99 0 28.13 1.36 ; + LAYER met4 ; + RECT 7.21 0 7.51 1.36 ; END END chany_bottom_out[19] PIN ccff_tail[0] @@ -1431,7 +1419,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.13 0 32.27 1.36 ; + RECT 43.63 0 43.77 1.36 ; END END ccff_tail[0] PIN VDD @@ -1539,19 +1527,19 @@ MACRO sb_0__1_ OBS LAYER li1 ; RECT 0 97.835 66.24 98.005 ; - RECT 65.32 95.115 66.24 95.285 ; + RECT 65.78 95.115 66.24 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 65.32 92.395 66.24 92.565 ; - RECT 0 92.395 3.68 92.565 ; - RECT 65.78 89.675 66.24 89.845 ; + RECT 64.4 92.395 66.24 92.565 ; + RECT 0 92.395 1.84 92.565 ; + RECT 64.4 89.675 66.24 89.845 ; RECT 0 89.675 3.68 89.845 ; RECT 65.32 86.955 66.24 87.125 ; RECT 0 86.955 3.68 87.125 ; RECT 65.32 84.235 66.24 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 63.48 81.515 84.64 81.685 ; + RECT 65.32 81.515 84.64 81.685 ; RECT 0 81.515 3.68 81.685 ; - RECT 83.72 78.795 84.64 78.965 ; + RECT 84.18 78.795 84.64 78.965 ; RECT 0 78.795 3.68 78.965 ; RECT 83.72 76.075 84.64 76.245 ; RECT 0 76.075 3.68 76.245 ; @@ -1563,80 +1551,80 @@ MACRO sb_0__1_ RECT 0 67.915 3.68 68.085 ; RECT 83.72 65.195 84.64 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 83.72 62.475 84.64 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 83.72 59.755 84.64 59.925 ; + RECT 82.8 62.475 84.64 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 82.8 59.755 84.64 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 80.96 57.035 84.64 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 80.96 54.315 84.64 54.485 ; + RECT 83.72 57.035 84.64 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 83.72 54.315 84.64 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 82.8 51.595 84.64 51.765 ; + RECT 83.72 51.595 84.64 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 82.8 48.875 84.64 49.045 ; - RECT 0 48.875 3.68 49.045 ; + RECT 84.18 48.875 84.64 49.045 ; + RECT 0 48.875 1.84 49.045 ; RECT 83.72 46.155 84.64 46.325 ; RECT 0 46.155 3.68 46.325 ; RECT 83.72 43.435 84.64 43.605 ; - RECT 0 43.435 1.84 43.605 ; - RECT 83.72 40.715 84.64 40.885 ; + RECT 0 43.435 3.68 43.605 ; + RECT 84.18 40.715 84.64 40.885 ; RECT 0 40.715 3.68 40.885 ; RECT 83.72 37.995 84.64 38.165 ; RECT 0 37.995 3.68 38.165 ; RECT 83.72 35.275 84.64 35.445 ; - RECT 0 35.275 3.68 35.445 ; + RECT 0 35.275 1.84 35.445 ; RECT 83.72 32.555 84.64 32.725 ; - RECT 0 32.555 3.68 32.725 ; + RECT 0 32.555 1.84 32.725 ; RECT 83.72 29.835 84.64 30.005 ; RECT 0 29.835 3.68 30.005 ; RECT 83.72 27.115 84.64 27.285 ; RECT 0 27.115 3.68 27.285 ; RECT 83.72 24.395 84.64 24.565 ; - RECT 0 24.395 3.68 24.565 ; + RECT 0 24.395 1.84 24.565 ; RECT 83.72 21.675 84.64 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 83.72 18.955 84.64 19.125 ; + RECT 84.18 18.955 84.64 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 65.32 16.235 84.64 16.405 ; + RECT 63.02 16.235 84.64 16.405 ; RECT 0 16.235 3.68 16.405 ; RECT 65.32 13.515 66.24 13.685 ; RECT 0 13.515 3.68 13.685 ; RECT 65.32 10.795 66.24 10.965 ; - RECT 0 10.795 3.68 10.965 ; + RECT 0 10.795 1.84 10.965 ; RECT 65.32 8.075 66.24 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 62.56 5.355 66.24 5.525 ; + RECT 65.32 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 62.56 2.635 66.24 2.805 ; + RECT 65.32 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; RECT 0 -0.085 66.24 0.085 ; LAYER met3 ; POLYGON 55.365 98.085 55.365 98.08 55.58 98.08 55.58 97.76 55.365 97.76 55.365 97.755 55.035 97.755 55.035 97.76 54.82 97.76 54.82 98.08 55.035 98.08 55.035 98.085 ; POLYGON 25.925 98.085 25.925 98.08 26.14 98.08 26.14 97.76 25.925 97.76 25.925 97.755 25.595 97.755 25.595 97.76 25.38 97.76 25.38 98.08 25.595 98.08 25.595 98.085 ; + POLYGON 84.33 66.79 84.33 66.51 82.86 66.51 82.86 66.49 81.73 66.49 81.73 66.79 ; + POLYGON 83.41 26.67 83.41 26.39 82.86 26.39 82.86 26.37 51.83 26.37 51.83 26.67 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 97.52 65.84 81.2 84.24 81.2 84.24 78.75 82.86 78.75 82.86 77.65 84.24 77.65 84.24 77.39 82.86 77.39 82.86 76.29 84.24 76.29 84.24 76.03 82.86 76.03 82.86 74.93 84.24 74.93 84.24 74.67 82.86 74.67 82.86 73.57 84.24 73.57 84.24 73.31 82.86 73.31 82.86 72.21 84.24 72.21 84.24 71.95 82.86 71.95 82.86 70.85 84.24 70.85 84.24 70.59 82.86 70.59 82.86 69.49 84.24 69.49 84.24 69.23 82.86 69.23 82.86 68.13 84.24 68.13 84.24 67.87 82.86 67.87 82.86 66.77 84.24 66.77 84.24 65.83 82.86 65.83 82.86 64.73 84.24 64.73 84.24 64.47 82.86 64.47 82.86 63.37 84.24 63.37 84.24 63.11 82.86 63.11 82.86 62.01 84.24 62.01 84.24 61.75 82.86 61.75 82.86 60.65 84.24 60.65 84.24 60.39 82.86 60.39 82.86 59.29 84.24 59.29 84.24 59.03 82.86 59.03 82.86 57.93 84.24 57.93 84.24 57.67 82.86 57.67 82.86 56.57 84.24 56.57 84.24 56.31 82.86 56.31 82.86 55.21 84.24 55.21 84.24 54.95 82.86 54.95 82.86 53.85 84.24 53.85 84.24 53.59 82.86 53.59 82.86 52.49 84.24 52.49 84.24 52.23 82.86 52.23 82.86 51.13 84.24 51.13 84.24 50.87 82.86 50.87 82.86 49.77 84.24 49.77 84.24 49.51 82.86 49.51 82.86 48.41 84.24 48.41 84.24 47.47 82.86 47.47 82.86 46.37 84.24 46.37 84.24 45.43 82.86 45.43 82.86 44.33 84.24 44.33 84.24 43.39 82.86 43.39 82.86 42.29 84.24 42.29 84.24 42.03 82.86 42.03 82.86 40.93 84.24 40.93 84.24 40.67 82.86 40.67 82.86 39.57 84.24 39.57 84.24 39.31 82.86 39.31 82.86 38.21 84.24 38.21 84.24 37.95 82.86 37.95 82.86 36.85 84.24 36.85 84.24 36.59 82.86 36.59 82.86 35.49 84.24 35.49 84.24 35.23 82.86 35.23 82.86 34.13 84.24 34.13 84.24 33.87 82.86 33.87 82.86 32.77 84.24 32.77 84.24 32.51 82.86 32.51 82.86 31.41 84.24 31.41 84.24 31.15 82.86 31.15 82.86 30.05 84.24 30.05 84.24 29.79 82.86 29.79 82.86 28.69 84.24 28.69 84.24 28.43 82.86 28.43 82.86 27.33 84.24 27.33 84.24 27.07 82.86 27.07 82.86 25.97 84.24 25.97 84.24 25.71 82.86 25.71 82.86 24.61 84.24 24.61 84.24 23.67 82.86 23.67 82.86 22.57 84.24 22.57 84.24 22.31 82.86 22.31 82.86 21.21 84.24 21.21 84.24 20.95 82.86 20.95 82.86 19.85 84.24 19.85 84.24 16.72 65.84 16.72 65.84 0.4 0.4 0.4 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 97.52 ; + POLYGON 65.84 97.52 65.84 81.2 84.24 81.2 84.24 78.75 82.86 78.75 82.86 77.65 84.24 77.65 84.24 77.39 82.86 77.39 82.86 76.29 84.24 76.29 84.24 76.03 82.86 76.03 82.86 74.93 84.24 74.93 84.24 74.67 82.86 74.67 82.86 73.57 84.24 73.57 84.24 73.31 82.86 73.31 82.86 72.21 84.24 72.21 84.24 71.95 82.86 71.95 82.86 70.85 84.24 70.85 84.24 70.59 82.86 70.59 82.86 69.49 84.24 69.49 84.24 69.23 82.86 69.23 82.86 68.13 84.24 68.13 84.24 67.87 82.86 67.87 82.86 66.77 84.24 66.77 84.24 66.51 82.86 66.51 82.86 65.41 84.24 65.41 84.24 65.15 82.86 65.15 82.86 64.05 84.24 64.05 84.24 63.11 82.86 63.11 82.86 62.01 84.24 62.01 84.24 61.75 82.86 61.75 82.86 60.65 84.24 60.65 84.24 60.39 82.86 60.39 82.86 59.29 84.24 59.29 84.24 59.03 82.86 59.03 82.86 57.93 84.24 57.93 84.24 57.67 82.86 57.67 82.86 56.57 84.24 56.57 84.24 56.31 82.86 56.31 82.86 55.21 84.24 55.21 84.24 54.95 82.86 54.95 82.86 53.85 84.24 53.85 84.24 53.59 82.86 53.59 82.86 52.49 84.24 52.49 84.24 51.55 82.86 51.55 82.86 50.45 84.24 50.45 84.24 50.19 82.86 50.19 82.86 49.09 84.24 49.09 84.24 48.15 82.86 48.15 82.86 47.05 84.24 47.05 84.24 46.79 82.86 46.79 82.86 45.69 84.24 45.69 84.24 45.43 82.86 45.43 82.86 44.33 84.24 44.33 84.24 43.39 82.86 43.39 82.86 42.29 84.24 42.29 84.24 42.03 82.86 42.03 82.86 40.93 84.24 40.93 84.24 40.67 82.86 40.67 82.86 39.57 84.24 39.57 84.24 39.31 82.86 39.31 82.86 38.21 84.24 38.21 84.24 37.95 82.86 37.95 82.86 36.85 84.24 36.85 84.24 36.59 82.86 36.59 82.86 35.49 84.24 35.49 84.24 35.23 82.86 35.23 82.86 34.13 84.24 34.13 84.24 33.87 82.86 33.87 82.86 32.77 84.24 32.77 84.24 32.51 82.86 32.51 82.86 31.41 84.24 31.41 84.24 30.47 82.86 30.47 82.86 29.37 84.24 29.37 84.24 29.11 82.86 29.11 82.86 28.01 84.24 28.01 84.24 27.75 82.86 27.75 82.86 26.65 84.24 26.65 84.24 26.39 82.86 26.39 82.86 25.29 84.24 25.29 84.24 25.03 82.86 25.03 82.86 23.93 84.24 23.93 84.24 23.67 82.86 23.67 82.86 22.57 84.24 22.57 84.24 22.31 82.86 22.31 82.86 21.21 84.24 21.21 84.24 20.95 82.86 20.95 82.86 19.85 84.24 19.85 84.24 16.72 65.84 16.72 65.84 10.07 64.46 10.07 64.46 8.97 65.84 8.97 65.84 8.71 64.46 8.71 64.46 7.61 65.84 7.61 65.84 7.35 64.46 7.35 64.46 6.25 65.84 6.25 65.84 5.99 64.46 5.99 64.46 4.89 65.84 4.89 65.84 0.4 0.4 0.4 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 97.52 ; LAYER met2 ; RECT 55.06 97.735 55.34 98.105 ; RECT 25.62 97.735 25.9 98.105 ; - RECT 58.29 1.54 58.55 1.86 ; - RECT 57.37 1.54 57.63 1.86 ; - RECT 22.41 1.54 22.67 1.86 ; + RECT 44.95 96.06 45.21 96.38 ; + RECT 48.63 1.54 48.89 1.86 ; + RECT 30.69 1.54 30.95 1.86 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 97.64 65.96 81.32 76.01 81.32 76.01 79.96 76.71 79.96 76.71 81.32 76.93 81.32 76.93 79.96 77.63 79.96 77.63 81.32 78.31 81.32 78.31 79.96 79.01 79.96 79.01 81.32 79.69 81.32 79.69 79.96 80.39 79.96 80.39 81.32 80.61 81.32 80.61 79.96 81.31 79.96 81.31 81.32 81.53 81.32 81.53 79.96 82.23 79.96 82.23 81.32 84.36 81.32 84.36 16.6 65.96 16.6 65.96 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 34.39 0.28 34.39 1.64 33.69 1.64 33.69 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 27.49 0.28 27.49 1.64 26.79 1.64 26.79 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 10.01 0.28 10.01 1.64 9.31 1.64 9.31 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 97.64 1.95 97.64 1.95 96.28 2.65 96.28 2.65 97.64 7.47 97.64 7.47 96.28 8.17 96.28 8.17 97.64 8.39 97.64 8.39 96.28 9.09 96.28 9.09 97.64 26.79 97.64 26.79 96.28 27.49 96.28 27.49 97.64 27.71 97.64 27.71 96.28 28.41 96.28 28.41 97.64 28.63 97.64 28.63 96.28 29.33 96.28 29.33 97.64 30.47 97.64 30.47 96.28 31.17 96.28 31.17 97.64 31.39 97.64 31.39 96.28 32.09 96.28 32.09 97.64 32.31 97.64 32.31 96.28 33.01 96.28 33.01 97.64 33.23 97.64 33.23 96.28 33.93 96.28 33.93 97.64 41.97 97.64 41.97 96.28 42.67 96.28 42.67 97.64 42.89 97.64 42.89 96.28 43.59 96.28 43.59 97.64 43.81 97.64 43.81 96.28 44.51 96.28 44.51 97.64 44.73 97.64 44.73 96.28 45.43 96.28 45.43 97.64 45.65 97.64 45.65 96.28 46.35 96.28 46.35 97.64 46.57 97.64 46.57 96.28 47.27 96.28 47.27 97.64 47.49 97.64 47.49 96.28 48.19 96.28 48.19 97.64 48.41 97.64 48.41 96.28 49.11 96.28 49.11 97.64 49.33 97.64 49.33 96.28 50.03 96.28 50.03 97.64 50.25 97.64 50.25 96.28 50.95 96.28 50.95 97.64 51.17 97.64 51.17 96.28 51.87 96.28 51.87 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 53.93 97.64 53.93 96.28 54.63 96.28 54.63 97.64 55.77 97.64 55.77 96.28 56.47 96.28 56.47 97.64 56.69 97.64 56.69 96.28 57.39 96.28 57.39 97.64 62.67 97.64 62.67 96.28 63.37 96.28 63.37 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 ; + POLYGON 65.96 97.64 65.96 81.32 84.36 81.32 84.36 16.6 79.93 16.6 79.93 17.96 79.23 17.96 79.23 16.6 78.55 16.6 78.55 17.96 77.85 17.96 77.85 16.6 65.96 16.6 65.96 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 6.79 0.28 6.79 1.64 6.09 1.64 6.09 0.28 0.28 0.28 0.28 97.64 7.01 97.64 7.01 96.28 7.71 96.28 7.71 97.64 21.73 97.64 21.73 96.28 22.43 96.28 22.43 97.64 22.65 97.64 22.65 96.28 23.35 96.28 23.35 97.64 23.57 97.64 23.57 96.28 24.27 96.28 24.27 97.64 24.49 97.64 24.49 96.28 25.19 96.28 25.19 97.64 26.33 97.64 26.33 96.28 27.03 96.28 27.03 97.64 27.25 97.64 27.25 96.28 27.95 96.28 27.95 97.64 28.17 97.64 28.17 96.28 28.87 96.28 28.87 97.64 29.09 97.64 29.09 96.28 29.79 96.28 29.79 97.64 30.01 97.64 30.01 96.28 30.71 96.28 30.71 97.64 42.43 97.64 42.43 96.28 43.13 96.28 43.13 97.64 43.35 97.64 43.35 96.28 44.05 96.28 44.05 97.64 44.27 97.64 44.27 96.28 44.97 96.28 44.97 97.64 45.19 97.64 45.19 96.28 45.89 96.28 45.89 97.64 46.11 97.64 46.11 96.28 46.81 96.28 46.81 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 48.41 97.64 48.41 96.28 49.11 96.28 49.11 97.64 49.33 97.64 49.33 96.28 50.03 96.28 50.03 97.64 50.25 97.64 50.25 96.28 50.95 96.28 50.95 97.64 51.17 97.64 51.17 96.28 51.87 96.28 51.87 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 55.77 97.64 55.77 96.28 56.47 96.28 56.47 97.64 57.61 97.64 57.61 96.28 58.31 96.28 58.31 97.64 61.75 97.64 61.75 96.28 62.45 96.28 62.45 97.64 ; LAYER met4 ; - POLYGON 65.84 97.52 65.84 81.2 79.49 81.2 79.49 79.84 80.59 79.84 80.59 81.2 84.24 81.2 84.24 16.72 65.84 16.72 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 17.11 0.4 17.11 1.76 16.01 1.76 16.01 0.4 15.27 0.4 15.27 1.76 14.17 1.76 14.17 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 97.52 4.05 97.52 4.05 96.16 5.15 96.16 5.15 97.52 5.89 97.52 5.89 96.16 6.99 96.16 6.99 97.52 7.73 97.52 7.73 96.16 8.83 96.16 8.83 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 12.33 97.52 12.33 96.16 13.43 96.16 13.43 97.52 14.17 97.52 14.17 96.16 15.27 96.16 15.27 97.52 23.37 97.52 23.37 96.16 24.47 96.16 24.47 97.52 25.06 97.52 25.06 96.92 26.46 96.92 26.46 97.52 27.05 97.52 27.05 96.16 28.15 96.16 28.15 97.52 28.89 97.52 28.89 96.16 29.99 96.16 29.99 97.52 30.73 97.52 30.73 96.16 31.83 96.16 31.83 97.52 32.57 97.52 32.57 96.16 33.67 96.16 33.67 97.52 39.78 97.52 39.78 96.92 41.18 96.92 41.18 97.52 41.77 97.52 41.77 96.16 42.87 96.16 42.87 97.52 45.45 97.52 45.45 96.16 46.55 96.16 46.55 97.52 47.29 97.52 47.29 96.16 48.39 96.16 48.39 97.52 49.13 97.52 49.13 96.16 50.23 96.16 50.23 97.52 54.5 97.52 54.5 96.92 55.9 96.92 55.9 97.52 ; + POLYGON 65.84 97.52 65.84 81.2 84.24 81.2 84.24 16.72 79.67 16.72 79.67 18.08 78.57 18.08 78.57 16.72 65.84 16.72 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 49.31 0.4 49.31 1.76 48.21 1.76 48.21 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 45.63 0.4 45.63 1.76 44.53 1.76 44.53 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 24.47 0.4 24.47 1.76 23.37 1.76 23.37 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 97.52 4.97 97.52 4.97 96.16 6.07 96.16 6.07 97.52 6.81 97.52 6.81 96.16 7.91 96.16 7.91 97.52 8.65 97.52 8.65 96.16 9.75 96.16 9.75 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 19.69 97.52 19.69 96.16 20.79 96.16 20.79 97.52 21.53 97.52 21.53 96.16 22.63 96.16 22.63 97.52 23.37 97.52 23.37 96.16 24.47 96.16 24.47 97.52 25.06 97.52 25.06 96.92 26.46 96.92 26.46 97.52 27.05 97.52 27.05 96.16 28.15 96.16 28.15 97.52 28.89 97.52 28.89 96.16 29.99 96.16 29.99 97.52 36.25 97.52 36.25 96.16 37.35 96.16 37.35 97.52 38.09 97.52 38.09 96.16 39.19 96.16 39.19 97.52 39.78 97.52 39.78 96.92 41.18 96.92 41.18 97.52 42.69 97.52 42.69 96.16 43.79 96.16 43.79 97.52 44.53 97.52 44.53 96.16 45.63 96.16 45.63 97.52 46.37 97.52 46.37 96.16 47.47 96.16 47.47 97.52 48.21 97.52 48.21 96.16 49.31 96.16 49.31 97.52 50.05 97.52 50.05 96.16 51.15 96.16 51.15 97.52 51.89 97.52 51.89 96.16 52.99 96.16 52.99 97.52 54.5 97.52 54.5 96.92 55.9 96.92 55.9 97.52 56.49 97.52 56.49 96.16 57.59 96.16 57.59 97.52 ; LAYER met5 ; - POLYGON 63.04 94.72 63.04 78.4 81.44 78.4 81.44 74.16 78.24 74.16 78.24 64.56 81.44 64.56 81.44 53.76 78.24 53.76 78.24 44.16 81.44 44.16 81.44 33.36 78.24 33.36 78.24 23.76 81.44 23.76 81.44 19.52 63.04 19.52 63.04 3.2 3.2 3.2 3.2 23.76 6.4 23.76 6.4 33.36 3.2 33.36 3.2 44.16 6.4 44.16 6.4 53.76 3.2 53.76 3.2 64.56 6.4 64.56 6.4 74.16 3.2 74.16 3.2 94.72 ; + POLYGON 64.64 96.32 64.64 80 83.04 80 83.04 72.56 79.84 72.56 79.84 66.16 83.04 66.16 83.04 52.16 79.84 52.16 79.84 45.76 83.04 45.76 83.04 31.76 79.84 31.76 79.84 25.36 83.04 25.36 83.04 17.92 64.64 17.92 64.64 1.6 1.6 1.6 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 96.32 ; LAYER met1 ; POLYGON 65.96 97.4 65.96 95.72 65.48 95.72 65.48 94.68 65.96 94.68 65.96 93 65.48 93 65.48 91.96 65.96 91.96 65.96 90.28 65.48 90.28 65.48 89.24 65.96 89.24 65.96 87.56 65.48 87.56 65.48 86.52 65.96 86.52 65.96 84.84 65.48 84.84 65.48 83.8 65.96 83.8 65.96 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; POLYGON 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 83.88 65.8 83.88 64.76 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; POLYGON 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 ; LAYER li1 ; - RECT 47.465 97.11 48.215 97.655 ; - RECT 47.465 0.265 48.215 0.81 ; - POLYGON 65.9 97.58 65.9 81.26 84.3 81.26 84.3 16.66 65.9 16.66 65.9 0.34 0.34 0.34 0.34 97.58 ; + POLYGON 66.07 97.75 66.07 81.43 84.47 81.43 84.47 16.49 66.07 16.49 66.07 0.17 0.17 0.17 0.17 97.75 ; LAYER mcon ; RECT 65.925 97.835 66.095 98.005 ; RECT 65.465 97.835 65.635 98.005 ; @@ -2429,24 +2417,20 @@ MACRO sb_0__1_ LAYER via ; RECT 55.125 97.845 55.275 97.995 ; RECT 25.685 97.845 25.835 97.995 ; - RECT 54.205 96.145 54.355 96.295 ; - RECT 30.745 96.145 30.895 96.295 ; RECT 55.125 81.525 55.275 81.675 ; RECT 25.685 81.525 25.835 81.675 ; - RECT 81.805 79.825 81.955 79.975 ; - RECT 80.885 79.825 81.035 79.975 ; RECT 55.125 16.245 55.275 16.395 ; RECT 25.685 16.245 25.835 16.395 ; - RECT 51.445 1.625 51.595 1.775 ; - RECT 42.245 1.625 42.395 1.775 ; + RECT 46.385 1.625 46.535 1.775 ; + RECT 26.605 1.625 26.755 1.775 ; RECT 55.125 -0.075 55.275 0.075 ; RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; RECT 55.1 97.82 55.3 98.02 ; RECT 25.66 97.82 25.86 98.02 ; - RECT 83.16 65.18 83.36 65.38 ; - RECT 83.16 42.74 83.36 42.94 ; - RECT 82.7 41.38 82.9 41.58 ; + RECT 83.16 64.5 83.36 64.7 ; + RECT 83.16 50.9 83.36 51.1 ; + RECT 83.16 20.3 83.36 20.5 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; @@ -2454,105 +2438,6 @@ MACRO sb_0__1_ RECT 25.66 97.82 25.86 98.02 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; - LAYER fieldpoly ; - POLYGON 66.1 97.78 66.1 81.46 84.5 81.46 84.5 16.46 66.1 16.46 66.1 0.14 0.14 0.14 0.14 97.78 ; - LAYER diff ; - POLYGON 66.24 97.92 66.24 81.6 84.64 81.6 84.64 16.32 66.24 16.32 66.24 0 0 0 0 97.92 ; - LAYER nwell ; - POLYGON 66.43 96.615 66.43 93.785 65.13 93.785 65.13 95.39 65.59 95.39 65.59 96.615 ; - POLYGON 3.87 96.615 3.87 95.01 2.03 95.01 2.03 93.785 -0.19 93.785 -0.19 96.615 ; - RECT 65.59 88.345 66.43 91.175 ; - RECT -0.19 88.345 3.87 91.175 ; - RECT 65.13 82.905 66.43 85.735 ; - RECT -0.19 82.905 3.87 85.735 ; - RECT 83.53 77.465 84.83 80.295 ; - RECT -0.19 77.465 3.87 80.295 ; - POLYGON 84.83 74.855 84.83 72.025 83.53 72.025 83.53 73.63 83.99 73.63 83.99 74.855 ; - RECT -0.19 72.025 3.87 74.855 ; - RECT 83.53 66.585 84.83 69.415 ; - RECT -0.19 66.585 3.87 69.415 ; - RECT 83.53 61.145 84.83 63.975 ; - RECT -0.19 61.145 2.03 63.975 ; - POLYGON 84.83 58.535 84.83 55.705 80.77 55.705 80.77 57.31 83.53 57.31 83.53 58.535 ; - POLYGON 3.87 58.535 3.87 56.93 2.03 56.93 2.03 55.705 -0.19 55.705 -0.19 58.535 ; - POLYGON 84.83 53.095 84.83 50.265 82.61 50.265 82.61 51.87 83.53 51.87 83.53 53.095 ; - POLYGON 3.87 53.095 3.87 51.49 2.03 51.49 2.03 50.265 -0.19 50.265 -0.19 53.095 ; - POLYGON 84.83 47.655 84.83 44.825 83.99 44.825 83.99 46.05 83.53 46.05 83.53 47.655 ; - POLYGON 3.87 47.655 3.87 46.05 2.03 46.05 2.03 44.825 -0.19 44.825 -0.19 47.655 ; - RECT 83.53 39.385 84.83 42.215 ; - POLYGON 2.03 42.215 2.03 40.99 3.87 40.99 3.87 39.385 -0.19 39.385 -0.19 42.215 ; - RECT 83.53 33.945 84.83 36.775 ; - RECT -0.19 33.945 3.87 36.775 ; - RECT 83.53 28.505 84.83 31.335 ; - RECT -0.19 28.505 3.87 31.335 ; - RECT 83.53 23.065 84.83 25.895 ; - RECT -0.19 23.065 3.87 25.895 ; - RECT 83.53 17.625 84.83 20.455 ; - RECT -0.19 17.625 3.87 20.455 ; - RECT 65.13 12.185 66.43 15.015 ; - RECT -0.19 12.185 3.87 15.015 ; - RECT 65.13 6.745 66.43 9.575 ; - RECT -0.19 6.745 3.87 9.575 ; - POLYGON 66.43 4.135 66.43 1.305 65.59 1.305 65.59 2.53 62.37 2.53 62.37 4.135 ; - RECT -0.19 1.305 3.87 4.135 ; - POLYGON 66.24 97.92 66.24 81.6 84.64 81.6 84.64 16.32 66.24 16.32 66.24 0 0 0 0 97.92 ; - LAYER pwell ; - RECT 59.47 97.87 59.69 98.04 ; - RECT 55.79 97.87 56.01 98.04 ; - RECT 52.11 97.87 52.33 98.04 ; - RECT 48.43 97.87 48.65 98.04 ; - RECT 40.61 97.87 40.83 98.04 ; - RECT 36.93 97.87 37.15 98.04 ; - RECT 33.25 97.87 33.47 98.04 ; - RECT 29.57 97.87 29.79 98.04 ; - RECT 25.89 97.87 26.11 98.04 ; - RECT 22.21 97.87 22.43 98.04 ; - RECT 18.53 97.87 18.75 98.04 ; - RECT 14.85 97.87 15.07 98.04 ; - RECT 11.17 97.87 11.39 98.04 ; - RECT 7.49 97.87 7.71 98.04 ; - RECT 3.81 97.87 4.03 98.04 ; - RECT 0.13 97.87 0.35 98.04 ; - RECT 63.195 97.86 63.305 97.98 ; - RECT 44.335 97.86 44.445 97.98 ; - RECT 65.92 97.865 66.04 97.975 ; - RECT 47.06 97.865 47.18 97.975 ; - RECT 65.015 97.86 65.175 97.97 ; - RECT 46.155 97.86 46.315 97.97 ; - RECT 78.33 81.55 78.55 81.72 ; - RECT 74.65 81.55 74.87 81.72 ; - RECT 70.97 81.55 71.19 81.72 ; - RECT 67.29 81.55 67.51 81.72 ; - RECT 82.055 81.54 82.165 81.66 ; - RECT 83.875 81.54 84.035 81.65 ; - RECT 83.875 16.27 84.035 16.38 ; - RECT 80.17 16.2 80.39 16.37 ; - RECT 76.49 16.2 76.71 16.37 ; - RECT 72.81 16.2 73.03 16.37 ; - RECT 69.13 16.2 69.35 16.37 ; - RECT 65.015 -0.05 65.175 0.06 ; - RECT 63.195 -0.06 63.305 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 65.92 -0.055 66.04 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - RECT 14.85 -0.12 15.07 0.05 ; - RECT 11.17 -0.12 11.39 0.05 ; - RECT 7.49 -0.12 7.71 0.05 ; - RECT 3.81 -0.12 4.03 0.05 ; - RECT 0.13 -0.12 0.35 0.05 ; - POLYGON 66.24 97.92 66.24 81.6 84.64 81.6 84.64 16.32 66.24 16.32 66.24 0 0 0 0 97.92 ; LAYER OVERLAP ; POLYGON 0 0 0 97.92 66.24 97.92 66.24 81.6 84.64 81.6 84.64 16.32 66.24 16.32 66.24 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef index 011f757..f63320b 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -375,7 +363,7 @@ MACRO sb_0__2_ USE CLOCK ; PORT LAYER met2 ; - RECT 16.95 0 17.09 1.36 ; + RECT 14.19 0 14.33 1.36 ; END END prog_clk[0] PIN chanx_right_in[0] @@ -383,7 +371,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 71.93 84.64 72.23 ; + RECT 83.26 54.25 84.64 54.55 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -391,7 +379,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 54.25 84.64 54.55 ; + RECT 83.26 42.01 84.64 42.31 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -399,7 +387,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 73.29 84.64 73.59 ; + RECT 83.26 56.29 84.64 56.59 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -407,7 +395,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 69.21 84.64 69.51 ; + RECT 83.26 26.37 84.64 26.67 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -415,7 +403,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 70.57 84.64 70.87 ; + RECT 83.26 35.89 84.64 36.19 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -423,7 +411,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 29.77 84.64 30.07 ; + RECT 83.26 69.21 84.64 69.51 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -431,7 +419,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 24.33 84.64 24.63 ; + RECT 83.26 33.17 84.64 33.47 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -439,7 +427,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 74.65 84.64 74.95 ; + RECT 83.26 63.77 84.64 64.07 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -447,7 +435,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 55.61 84.64 55.91 ; + RECT 83.26 43.37 84.64 43.67 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -455,15 +443,15 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 28.41 84.64 28.71 ; + RECT 83.26 76.01 84.64 76.31 ; END END chanx_right_in[9] PIN chanx_right_in[10] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 83.26 52.21 84.64 52.51 ; + LAYER met2 ; + RECT 82.27 16.32 82.41 17.68 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -471,7 +459,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 36.57 84.64 36.87 ; + RECT 83.26 77.37 84.64 77.67 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -479,7 +467,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 47.45 84.64 47.75 ; + RECT 83.26 59.01 84.64 59.31 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -487,15 +475,15 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 27.05 84.64 27.35 ; + RECT 83.26 22.97 84.64 23.27 ; END END chanx_right_in[13] PIN chanx_right_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 83.26 25.69 84.64 25.99 ; + LAYER met2 ; + RECT 81.35 16.32 81.49 17.68 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -503,7 +491,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 44.73 84.64 45.03 ; + RECT 83.26 67.85 84.64 68.15 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -511,7 +499,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 32.49 84.64 32.79 ; + RECT 83.26 44.73 84.64 45.03 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -519,7 +507,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 50.17 84.64 50.47 ; + RECT 83.26 21.61 84.64 21.91 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -527,7 +515,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 46.09 84.64 46.39 ; + RECT 83.26 61.05 84.64 61.35 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -535,31 +523,95 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 35.21 84.64 35.51 ; + RECT 83.26 65.13 84.64 65.43 ; END END chanx_right_in[19] PIN right_top_grid_pin_1_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 80.89 80.24 81.03 81.6 ; + LAYER met3 ; + RECT 83.26 37.25 84.64 37.55 ; END END right_top_grid_pin_1_[0] + PIN right_bottom_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 64.86 5.29 66.24 5.59 ; + END + END right_bottom_grid_pin_34_[0] + PIN right_bottom_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 64.86 8.01 66.24 8.31 ; + END + END right_bottom_grid_pin_35_[0] + PIN right_bottom_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 64.86 6.65 66.24 6.95 ; + END + END right_bottom_grid_pin_36_[0] + PIN right_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.83 16.32 75.97 17.68 ; + END + END right_bottom_grid_pin_37_[0] + PIN right_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.75 16.32 76.89 17.68 ; + END + END right_bottom_grid_pin_38_[0] + PIN right_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.43 16.32 80.57 17.68 ; + END + END right_bottom_grid_pin_39_[0] + PIN right_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.13 16.32 78.27 17.68 ; + END + END right_bottom_grid_pin_40_[0] + PIN right_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.95 0 63.09 1.36 ; + END + END right_bottom_grid_pin_41_[0] PIN chany_bottom_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 46.77 0 47.07 1.36 ; + LAYER met2 ; + RECT 51.91 0 52.05 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 16.41 0 16.71 1.36 ; + LAYER met2 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -567,15 +619,15 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 52.83 0 52.97 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 14.57 0 14.87 1.36 ; + LAYER met2 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -583,7 +635,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + RECT 42.71 0 42.85 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -591,7 +643,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; + RECT 50.07 0 50.21 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -599,15 +651,15 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 0 23.07 1.36 ; + RECT 20.17 0 20.31 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 27.45 0 27.75 1.36 ; + LAYER met2 ; + RECT 22.93 0 23.07 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -615,7 +667,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 9.59 0 9.73 1.36 ; + RECT 8.21 0 8.35 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -623,7 +675,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.17 0 20.31 1.36 ; + RECT 21.09 0 21.23 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -631,7 +683,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 33.51 0 33.65 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -639,7 +691,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 29.37 0 29.51 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -647,7 +699,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.81 0 58.95 1.36 ; + RECT 50.99 0 51.13 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -655,7 +707,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 0 58.03 1.36 ; + RECT 30.29 0 30.43 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -663,7 +715,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 0 57.11 1.36 ; + RECT 28.45 0 28.59 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -671,7 +723,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; + RECT 22.01 0 22.15 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -679,7 +731,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + RECT 36.27 0 36.41 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -687,7 +739,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 0 35.03 1.36 ; + RECT 6.37 0 6.51 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -695,7 +747,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.97 0 34.11 1.36 ; + RECT 31.21 0 31.35 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -703,7 +755,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.75 0 30.89 1.36 ; + RECT 7.29 0 7.43 1.36 ; END END chany_bottom_in[19] PIN bottom_left_grid_pin_1_[0] @@ -711,15 +763,15 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 2.23 0 2.37 1.36 ; + RECT 63.87 0 64.01 1.36 ; END END bottom_left_grid_pin_1_[0] PIN ccff_head[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 81.81 80.24 81.95 81.6 ; + LAYER met3 ; + RECT 83.26 47.45 84.64 47.75 ; END END ccff_head[0] PIN chanx_right_out[0] @@ -727,7 +779,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 48.81 84.64 49.11 ; + RECT 83.26 52.89 84.64 53.19 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -735,7 +787,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 37.93 84.64 38.23 ; + RECT 83.26 29.09 84.64 29.39 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -743,7 +795,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 31.13 84.64 31.43 ; + RECT 83.26 50.17 84.64 50.47 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -751,7 +803,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 67.85 84.64 68.15 ; + RECT 83.26 31.81 84.64 32.11 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -759,7 +811,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 33.85 84.64 34.15 ; + RECT 83.26 70.57 84.64 70.87 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -767,7 +819,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 56.97 84.64 57.27 ; + RECT 83.26 24.33 84.64 24.63 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -783,7 +835,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 58.33 84.64 58.63 ; + RECT 83.26 51.53 84.64 51.83 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -791,7 +843,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 65.13 84.64 65.43 ; + RECT 83.26 34.53 84.64 34.83 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -799,7 +851,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 42.01 84.64 42.31 ; + RECT 83.26 20.25 84.64 20.55 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -807,7 +859,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 20.25 84.64 20.55 ; + RECT 83.26 71.93 84.64 72.23 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -815,7 +867,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 59.69 84.64 59.99 ; + RECT 83.26 30.45 84.64 30.75 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -823,7 +875,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 21.61 84.64 21.91 ; + RECT 83.26 39.29 84.64 39.59 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -831,7 +883,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 39.29 84.64 39.59 ; + RECT 83.26 27.73 84.64 28.03 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -839,7 +891,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 63.77 84.64 64.07 ; + RECT 83.26 48.81 84.64 49.11 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -847,7 +899,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 40.65 84.64 40.95 ; + RECT 83.26 74.65 84.64 74.95 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -855,7 +907,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 43.37 84.64 43.67 ; + RECT 83.26 57.65 84.64 57.95 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -863,7 +915,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 61.05 84.64 61.35 ; + RECT 83.26 46.09 84.64 46.39 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -871,7 +923,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 62.41 84.64 62.71 ; + RECT 83.26 73.29 84.64 73.59 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -879,7 +931,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 22.97 84.64 23.27 ; + RECT 83.26 62.41 84.64 62.71 ; END END chanx_right_out[19] PIN chany_bottom_out[0] @@ -887,7 +939,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 0 22.15 1.36 ; + RECT 54.21 0 54.35 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -895,7 +947,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.09 0 44.23 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -903,7 +955,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -911,7 +963,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 27.53 0 27.67 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -919,7 +971,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 56.05 0 56.19 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -927,7 +979,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 0 53.43 1.36 ; + RECT 23.85 0 23.99 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -935,7 +987,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; + RECT 26.61 0 26.75 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -943,7 +995,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -951,7 +1003,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; + RECT 47.31 0 47.45 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -959,7 +1011,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.83 0 29.97 1.36 ; + RECT 24.77 0 24.91 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -967,15 +1019,15 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 0 21.23 1.36 ; + RECT 62.03 0 62.17 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; + LAYER met4 ; + RECT 44.93 0 45.23 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -983,31 +1035,31 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; + RECT 49.15 0 49.29 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + LAYER met4 ; + RECT 9.05 0 9.35 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; + LAYER met4 ; + RECT 48.61 0 48.91 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 28.91 0 29.05 1.36 ; + LAYER met4 ; + RECT 46.77 0 47.07 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1015,31 +1067,31 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.05 0 33.19 1.36 ; + RECT 40.87 0 41.01 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + LAYER met4 ; + RECT 5.37 0 5.67 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 27.07 0 27.21 1.36 ; + LAYER met4 ; + RECT 23.77 0 24.07 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 27.99 0 28.13 1.36 ; + LAYER met4 ; + RECT 7.21 0 7.51 1.36 ; END END chany_bottom_out[19] PIN ccff_tail[0] @@ -1047,9 +1099,41 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.13 0 32.27 1.36 ; + RECT 43.63 0 43.77 1.36 ; END END ccff_tail[0] + PIN SC_IN_TOP + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 64.45 1.38 64.75 ; + END + END SC_IN_TOP + PIN SC_IN_BOT + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.17 80.24 43.31 81.6 ; + END + END SC_IN_BOT + PIN SC_OUT_TOP + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.25 80.24 42.39 81.6 ; + END + END SC_OUT_TOP + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 40.65 84.64 40.95 ; + END + END SC_OUT_BOT PIN VDD DIRECTION INPUT ; USE POWER ; @@ -1152,7 +1236,7 @@ MACRO sb_0__2_ RECT 0 73.355 3.68 73.525 ; RECT 83.72 70.635 84.64 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 83.72 67.915 84.64 68.085 ; + RECT 84.18 67.915 84.64 68.085 ; RECT 0 67.915 3.68 68.085 ; RECT 83.72 65.195 84.64 65.365 ; RECT 0 65.195 3.68 65.365 ; @@ -1162,9 +1246,9 @@ MACRO sb_0__2_ RECT 0 59.755 3.68 59.925 ; RECT 83.72 57.035 84.64 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 83.72 54.315 84.64 54.485 ; + RECT 84.18 54.315 84.64 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 83.72 51.595 84.64 51.765 ; + RECT 84.18 51.595 84.64 51.765 ; RECT 0 51.595 3.68 51.765 ; RECT 83.72 48.875 84.64 49.045 ; RECT 0 48.875 3.68 49.045 ; @@ -1182,51 +1266,55 @@ MACRO sb_0__2_ RECT 0 32.555 3.68 32.725 ; RECT 83.72 29.835 84.64 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 83.72 27.115 84.64 27.285 ; + RECT 80.96 27.115 84.64 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 83.72 24.395 84.64 24.565 ; + RECT 80.96 24.395 84.64 24.565 ; RECT 0 24.395 3.68 24.565 ; RECT 83.72 21.675 84.64 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 80.96 18.955 84.64 19.125 ; + RECT 83.72 18.955 84.64 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 62.56 16.235 84.64 16.405 ; + RECT 65.32 16.235 84.64 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 62.56 13.515 66.24 13.685 ; + RECT 65.32 13.515 66.24 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 65.32 10.795 66.24 10.965 ; + RECT 62.56 10.795 66.24 10.965 ; RECT 0 10.795 3.68 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; + RECT 62.56 8.075 66.24 8.245 ; RECT 0 8.075 3.68 8.245 ; RECT 65.32 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 65.78 2.635 66.24 2.805 ; + RECT 65.32 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; RECT 0 -0.085 66.24 0.085 ; LAYER met2 ; RECT 55.06 81.415 55.34 81.785 ; RECT 25.62 81.415 25.9 81.785 ; + POLYGON 66.31 27.27 66.31 16.59 64.79 16.59 64.79 16.73 66.17 16.73 66.17 27.27 ; + RECT 80.83 17.86 81.09 18.18 ; + RECT 32.99 1.54 33.25 1.86 ; + RECT 27.01 1.54 27.27 1.86 ; RECT 55.06 -0.185 55.34 0.185 ; RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 84.36 81.32 84.36 16.6 65.96 16.6 65.96 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 34.39 0.28 34.39 1.64 33.69 1.64 33.69 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 27.49 0.28 27.49 1.64 26.79 1.64 26.79 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 10.01 0.28 10.01 1.64 9.31 1.64 9.31 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 81.32 80.61 81.32 80.61 79.96 81.31 79.96 81.31 81.32 81.53 81.32 81.53 79.96 82.23 79.96 82.23 81.32 ; + POLYGON 84.36 81.32 84.36 16.6 82.69 16.6 82.69 17.96 81.99 17.96 81.99 16.6 81.77 16.6 81.77 17.96 81.07 17.96 81.07 16.6 80.85 16.6 80.85 17.96 80.15 17.96 80.15 16.6 78.55 16.6 78.55 17.96 77.85 17.96 77.85 16.6 77.17 16.6 77.17 17.96 76.47 17.96 76.47 16.6 76.25 16.6 76.25 17.96 75.55 17.96 75.55 16.6 65.96 16.6 65.96 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 14.61 0.28 14.61 1.64 13.91 1.64 13.91 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 6.79 0.28 6.79 1.64 6.09 1.64 6.09 0.28 0.28 0.28 0.28 81.32 41.97 81.32 41.97 79.96 42.67 79.96 42.67 81.32 42.89 81.32 42.89 79.96 43.59 79.96 43.59 81.32 ; LAYER met3 ; POLYGON 55.365 81.765 55.365 81.76 55.58 81.76 55.58 81.44 55.365 81.44 55.365 81.435 55.035 81.435 55.035 81.44 54.82 81.44 54.82 81.76 55.035 81.76 55.035 81.765 ; POLYGON 25.925 81.765 25.925 81.76 26.14 81.76 26.14 81.44 25.925 81.44 25.925 81.435 25.595 81.435 25.595 81.44 25.38 81.44 25.38 81.76 25.595 81.76 25.595 81.765 ; - POLYGON 82.86 49.79 82.86 49.77 83.41 49.77 83.41 49.49 54.59 49.49 54.59 49.79 ; + POLYGON 83.425 38.245 83.425 37.915 83.095 37.915 83.095 37.93 72.07 37.93 72.07 38.23 83.095 38.23 83.095 38.245 ; + POLYGON 83.41 23.95 83.41 23.67 82.86 23.67 82.86 23.65 30.21 23.65 30.21 23.95 ; + POLYGON 64.565 9.005 64.565 8.675 64.235 8.675 64.235 8.69 57.35 8.69 57.35 8.99 64.235 8.99 64.235 9.005 ; POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 84.24 81.2 84.24 75.35 82.86 75.35 82.86 74.25 84.24 74.25 84.24 73.99 82.86 73.99 82.86 72.89 84.24 72.89 84.24 72.63 82.86 72.63 82.86 71.53 84.24 71.53 84.24 71.27 82.86 71.27 82.86 70.17 84.24 70.17 84.24 69.91 82.86 69.91 82.86 68.81 84.24 68.81 84.24 68.55 82.86 68.55 82.86 67.45 84.24 67.45 84.24 67.19 82.86 67.19 82.86 66.09 84.24 66.09 84.24 65.83 82.86 65.83 82.86 64.73 84.24 64.73 84.24 64.47 82.86 64.47 82.86 63.37 84.24 63.37 84.24 63.11 82.86 63.11 82.86 62.01 84.24 62.01 84.24 61.75 82.86 61.75 82.86 60.65 84.24 60.65 84.24 60.39 82.86 60.39 82.86 59.29 84.24 59.29 84.24 59.03 82.86 59.03 82.86 57.93 84.24 57.93 84.24 57.67 82.86 57.67 82.86 56.57 84.24 56.57 84.24 56.31 82.86 56.31 82.86 55.21 84.24 55.21 84.24 54.95 82.86 54.95 82.86 53.85 84.24 53.85 84.24 52.91 82.86 52.91 82.86 51.81 84.24 51.81 84.24 50.87 82.86 50.87 82.86 49.77 84.24 49.77 84.24 49.51 82.86 49.51 82.86 48.41 84.24 48.41 84.24 48.15 82.86 48.15 82.86 47.05 84.24 47.05 84.24 46.79 82.86 46.79 82.86 45.69 84.24 45.69 84.24 45.43 82.86 45.43 82.86 44.33 84.24 44.33 84.24 44.07 82.86 44.07 82.86 42.97 84.24 42.97 84.24 42.71 82.86 42.71 82.86 41.61 84.24 41.61 84.24 41.35 82.86 41.35 82.86 40.25 84.24 40.25 84.24 39.99 82.86 39.99 82.86 38.89 84.24 38.89 84.24 38.63 82.86 38.63 82.86 37.53 84.24 37.53 84.24 37.27 82.86 37.27 82.86 36.17 84.24 36.17 84.24 35.91 82.86 35.91 82.86 34.81 84.24 34.81 84.24 34.55 82.86 34.55 82.86 33.45 84.24 33.45 84.24 33.19 82.86 33.19 82.86 32.09 84.24 32.09 84.24 31.83 82.86 31.83 82.86 30.73 84.24 30.73 84.24 30.47 82.86 30.47 82.86 29.37 84.24 29.37 84.24 29.11 82.86 29.11 82.86 28.01 84.24 28.01 84.24 27.75 82.86 27.75 82.86 26.65 84.24 26.65 84.24 26.39 82.86 26.39 82.86 25.29 84.24 25.29 84.24 25.03 82.86 25.03 82.86 23.93 84.24 23.93 84.24 23.67 82.86 23.67 82.86 22.57 84.24 22.57 84.24 22.31 82.86 22.31 82.86 21.21 84.24 21.21 84.24 20.95 82.86 20.95 82.86 19.85 84.24 19.85 84.24 16.72 65.84 16.72 65.84 0.4 0.4 0.4 0.4 81.2 ; + POLYGON 84.24 81.2 84.24 78.07 82.86 78.07 82.86 76.97 84.24 76.97 84.24 76.71 82.86 76.71 82.86 75.61 84.24 75.61 84.24 75.35 82.86 75.35 82.86 74.25 84.24 74.25 84.24 73.99 82.86 73.99 82.86 72.89 84.24 72.89 84.24 72.63 82.86 72.63 82.86 71.53 84.24 71.53 84.24 71.27 82.86 71.27 82.86 70.17 84.24 70.17 84.24 69.91 82.86 69.91 82.86 68.81 84.24 68.81 84.24 68.55 82.86 68.55 82.86 67.45 84.24 67.45 84.24 67.19 82.86 67.19 82.86 66.09 84.24 66.09 84.24 65.83 82.86 65.83 82.86 64.73 84.24 64.73 84.24 64.47 82.86 64.47 82.86 63.37 84.24 63.37 84.24 63.11 82.86 63.11 82.86 62.01 84.24 62.01 84.24 61.75 82.86 61.75 82.86 60.65 84.24 60.65 84.24 59.71 82.86 59.71 82.86 58.61 84.24 58.61 84.24 58.35 82.86 58.35 82.86 57.25 84.24 57.25 84.24 56.99 82.86 56.99 82.86 55.89 84.24 55.89 84.24 54.95 82.86 54.95 82.86 53.85 84.24 53.85 84.24 53.59 82.86 53.59 82.86 52.49 84.24 52.49 84.24 52.23 82.86 52.23 82.86 51.13 84.24 51.13 84.24 50.87 82.86 50.87 82.86 49.77 84.24 49.77 84.24 49.51 82.86 49.51 82.86 48.41 84.24 48.41 84.24 48.15 82.86 48.15 82.86 47.05 84.24 47.05 84.24 46.79 82.86 46.79 82.86 45.69 84.24 45.69 84.24 45.43 82.86 45.43 82.86 44.33 84.24 44.33 84.24 44.07 82.86 44.07 82.86 42.97 84.24 42.97 84.24 42.71 82.86 42.71 82.86 41.61 84.24 41.61 84.24 41.35 82.86 41.35 82.86 40.25 84.24 40.25 84.24 39.99 82.86 39.99 82.86 38.89 84.24 38.89 84.24 37.95 82.86 37.95 82.86 36.85 84.24 36.85 84.24 36.59 82.86 36.59 82.86 35.49 84.24 35.49 84.24 35.23 82.86 35.23 82.86 34.13 84.24 34.13 84.24 33.87 82.86 33.87 82.86 32.77 84.24 32.77 84.24 32.51 82.86 32.51 82.86 31.41 84.24 31.41 84.24 31.15 82.86 31.15 82.86 30.05 84.24 30.05 84.24 29.79 82.86 29.79 82.86 28.69 84.24 28.69 84.24 28.43 82.86 28.43 82.86 27.33 84.24 27.33 84.24 27.07 82.86 27.07 82.86 25.97 84.24 25.97 84.24 25.03 82.86 25.03 82.86 23.93 84.24 23.93 84.24 23.67 82.86 23.67 82.86 22.57 84.24 22.57 84.24 22.31 82.86 22.31 82.86 21.21 84.24 21.21 84.24 20.95 82.86 20.95 82.86 19.85 84.24 19.85 84.24 16.72 65.84 16.72 65.84 8.71 64.46 8.71 64.46 7.61 65.84 7.61 65.84 7.35 64.46 7.35 64.46 6.25 65.84 6.25 65.84 5.99 64.46 5.99 64.46 4.89 65.84 4.89 65.84 0.4 0.4 0.4 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 81.2 ; LAYER met4 ; - POLYGON 84.24 81.2 84.24 16.72 65.84 16.72 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 17.11 0.4 17.11 1.76 16.01 1.76 16.01 0.4 15.27 0.4 15.27 1.76 14.17 1.76 14.17 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 81.2 10.34 81.2 10.34 80.6 11.74 80.6 11.74 81.2 25.06 81.2 25.06 80.6 26.46 80.6 26.46 81.2 39.78 81.2 39.78 80.6 41.18 80.6 41.18 81.2 54.5 81.2 54.5 80.6 55.9 80.6 55.9 81.2 ; + POLYGON 84.24 81.2 84.24 16.72 65.84 16.72 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 49.31 0.4 49.31 1.76 48.21 1.76 48.21 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 45.63 0.4 45.63 1.76 44.53 1.76 44.53 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 24.47 0.4 24.47 1.76 23.37 1.76 23.37 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 81.2 10.34 81.2 10.34 80.6 11.74 80.6 11.74 81.2 25.06 81.2 25.06 80.6 26.46 80.6 26.46 81.2 39.78 81.2 39.78 80.6 41.18 80.6 41.18 81.2 54.5 81.2 54.5 80.6 55.9 80.6 55.9 81.2 ; LAYER met5 ; - POLYGON 81.44 78.4 81.44 74.16 78.24 74.16 78.24 64.56 81.44 64.56 81.44 53.76 78.24 53.76 78.24 44.16 81.44 44.16 81.44 33.36 78.24 33.36 78.24 23.76 81.44 23.76 81.44 19.52 63.04 19.52 63.04 3.2 3.2 3.2 3.2 23.76 6.4 23.76 6.4 33.36 3.2 33.36 3.2 44.16 6.4 44.16 6.4 53.76 3.2 53.76 3.2 64.56 6.4 64.56 6.4 74.16 3.2 74.16 3.2 78.4 ; + POLYGON 83.04 80 83.04 72.56 79.84 72.56 79.84 66.16 83.04 66.16 83.04 52.16 79.84 52.16 79.84 45.76 83.04 45.76 83.04 31.76 79.84 31.76 79.84 25.36 83.04 25.36 83.04 17.92 64.64 17.92 64.64 1.6 1.6 1.6 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 80 ; LAYER met1 ; POLYGON 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 83.88 65.8 83.88 64.76 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; POLYGON 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 ; LAYER li1 ; - RECT 47.465 80.79 48.215 81.335 ; - RECT 47.465 0.265 48.215 0.81 ; - POLYGON 84.3 81.26 84.3 16.66 65.9 16.66 65.9 0.34 0.34 0.34 0.34 81.26 ; + POLYGON 84.47 81.43 84.47 16.49 66.07 16.49 66.07 0.17 0.17 0.17 0.17 81.43 ; LAYER mcon ; RECT 84.325 81.515 84.495 81.685 ; RECT 83.865 81.515 84.035 81.685 ; @@ -1855,19 +1943,19 @@ MACRO sb_0__2_ LAYER via ; RECT 55.125 81.525 55.275 81.675 ; RECT 25.685 81.525 25.835 81.675 ; + RECT 82.265 17.945 82.415 18.095 ; + RECT 76.745 17.945 76.895 18.095 ; RECT 55.125 16.245 55.275 16.395 ; RECT 25.685 16.245 25.835 16.395 ; - RECT 56.965 1.625 57.115 1.775 ; RECT 55.125 -0.075 55.275 0.075 ; RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; RECT 55.1 81.5 55.3 81.7 ; RECT 25.66 81.5 25.86 81.7 ; - RECT 83.16 63.82 83.36 64.02 ; - RECT 82.7 61.1 82.9 61.3 ; - RECT 82.7 58.38 82.9 58.58 ; - RECT 83.16 57.02 83.36 57.22 ; - RECT 82.7 39.34 82.9 39.54 ; + RECT 83.16 50.22 83.36 50.42 ; + RECT 83.16 44.78 83.36 44.98 ; + RECT 82.7 40.7 82.9 40.9 ; + RECT 83.16 31.86 83.36 32.06 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; @@ -1875,98 +1963,6 @@ MACRO sb_0__2_ RECT 25.66 81.5 25.86 81.7 ; RECT 55.1 -0.1 55.3 0.1 ; RECT 25.66 -0.1 25.86 0.1 ; - LAYER fieldpoly ; - POLYGON 84.5 81.46 84.5 16.46 66.1 16.46 66.1 0.14 0.14 0.14 0.14 81.46 ; - LAYER diff ; - POLYGON 84.64 81.6 84.64 16.32 66.24 16.32 66.24 0 0 0 0 81.6 ; - LAYER nwell ; - POLYGON 84.83 80.295 84.83 77.465 80.77 77.465 80.77 79.07 83.99 79.07 83.99 80.295 ; - RECT -0.19 77.465 3.87 80.295 ; - RECT 83.53 72.025 84.83 74.855 ; - RECT -0.19 72.025 3.87 74.855 ; - RECT 83.53 66.585 84.83 69.415 ; - RECT -0.19 66.585 3.87 69.415 ; - RECT 83.53 61.145 84.83 63.975 ; - RECT -0.19 61.145 3.87 63.975 ; - RECT 83.53 55.705 84.83 58.535 ; - RECT -0.19 55.705 3.87 58.535 ; - RECT 83.53 50.265 84.83 53.095 ; - RECT -0.19 50.265 3.87 53.095 ; - RECT 83.53 44.825 84.83 47.655 ; - RECT -0.19 44.825 3.87 47.655 ; - RECT 83.53 39.385 84.83 42.215 ; - RECT -0.19 39.385 3.87 42.215 ; - RECT 83.53 33.945 84.83 36.775 ; - RECT -0.19 33.945 3.87 36.775 ; - RECT 83.53 28.505 84.83 31.335 ; - RECT -0.19 28.505 3.87 31.335 ; - RECT 83.53 23.065 84.83 25.895 ; - RECT -0.19 23.065 3.87 25.895 ; - POLYGON 84.83 20.455 84.83 17.625 80.77 17.625 80.77 19.23 83.53 19.23 83.53 20.455 ; - RECT -0.19 17.625 3.87 20.455 ; - POLYGON 66.43 15.015 66.43 12.185 65.13 12.185 65.13 13.41 62.37 13.41 62.37 15.015 ; - RECT -0.19 12.185 3.87 15.015 ; - POLYGON 66.43 9.575 66.43 6.745 65.13 6.745 65.13 8.35 65.59 8.35 65.59 9.575 ; - RECT -0.19 6.745 3.87 9.575 ; - RECT 65.59 1.305 66.43 4.135 ; - RECT -0.19 1.305 3.87 4.135 ; - POLYGON 84.64 81.6 84.64 16.32 66.24 16.32 66.24 0 0 0 0 81.6 ; - LAYER pwell ; - RECT 77.87 81.55 78.09 81.72 ; - RECT 74.19 81.55 74.41 81.72 ; - RECT 70.51 81.55 70.73 81.72 ; - RECT 66.83 81.55 67.05 81.72 ; - RECT 63.15 81.55 63.37 81.72 ; - RECT 59.47 81.55 59.69 81.72 ; - RECT 55.79 81.55 56.01 81.72 ; - RECT 52.11 81.55 52.33 81.72 ; - RECT 48.43 81.55 48.65 81.72 ; - RECT 40.61 81.55 40.83 81.72 ; - RECT 36.93 81.55 37.15 81.72 ; - RECT 33.25 81.55 33.47 81.72 ; - RECT 29.57 81.55 29.79 81.72 ; - RECT 25.89 81.55 26.11 81.72 ; - RECT 22.21 81.55 22.43 81.72 ; - RECT 18.53 81.55 18.75 81.72 ; - RECT 14.85 81.55 15.07 81.72 ; - RECT 11.17 81.55 11.39 81.72 ; - RECT 7.49 81.55 7.71 81.72 ; - RECT 3.81 81.55 4.03 81.72 ; - RECT 0.13 81.55 0.35 81.72 ; - RECT 81.595 81.54 81.705 81.66 ; - RECT 44.335 81.54 44.445 81.66 ; - RECT 84.32 81.545 84.44 81.655 ; - RECT 47.06 81.545 47.18 81.655 ; - RECT 83.415 81.54 83.575 81.65 ; - RECT 46.155 81.54 46.315 81.65 ; - RECT 81.09 16.2 81.31 16.37 ; - RECT 77.41 16.2 77.63 16.37 ; - RECT 73.73 16.2 73.95 16.37 ; - RECT 70.05 16.2 70.27 16.37 ; - RECT 66.37 16.2 66.59 16.37 ; - RECT 65.015 -0.05 65.175 0.06 ; - RECT 63.195 -0.06 63.305 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 65.92 -0.055 66.04 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - RECT 14.85 -0.12 15.07 0.05 ; - RECT 11.17 -0.12 11.39 0.05 ; - RECT 7.49 -0.12 7.71 0.05 ; - RECT 3.81 -0.12 4.03 0.05 ; - RECT 0.13 -0.12 0.35 0.05 ; - POLYGON 84.64 81.6 84.64 16.32 66.24 16.32 66.24 0 0 0 0 81.6 ; LAYER OVERLAP ; POLYGON 0 0 0 81.6 84.64 81.6 84.64 16.32 66.24 16.32 66.24 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef index 4325878..dfeefc6 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -375,7 +363,7 @@ MACRO sb_1__0_ USE CLOCK ; PORT LAYER met2 ; - RECT 2.23 63.92 2.37 65.28 ; + RECT 20.63 80.24 20.77 81.6 ; END END prog_clk[0] PIN chany_top_in[0] @@ -383,7 +371,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 80.24 65.85 81.6 ; + RECT 72.61 80.24 72.75 81.6 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -391,15 +379,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 80.24 42.39 81.6 ; + RECT 53.29 80.24 53.43 81.6 ; END END chany_top_in[1] PIN chany_top_in[2] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 55.97 80.24 56.27 81.6 ; + LAYER met2 ; + RECT 52.37 80.24 52.51 81.6 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -407,7 +395,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 80.24 52.05 81.6 ; + RECT 69.85 80.24 69.99 81.6 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -415,7 +403,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 49.53 80.24 49.83 81.6 ; + RECT 60.57 80.24 60.87 81.6 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -423,7 +411,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 80.24 50.21 81.6 ; + RECT 47.31 80.24 47.45 81.6 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -431,7 +419,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 80.24 55.27 81.6 ; + RECT 76.29 80.24 76.43 81.6 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -439,7 +427,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 80.24 59.41 81.6 ; + RECT 65.71 80.24 65.85 81.6 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -455,7 +443,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 80.24 58.03 81.6 ; + RECT 39.95 80.24 40.09 81.6 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -463,7 +451,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 53.21 80.24 53.51 81.6 ; + RECT 55.97 80.24 56.27 81.6 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -471,15 +459,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 80.24 49.29 81.6 ; + RECT 70.77 80.24 70.91 81.6 ; END END chany_top_in[11] PIN chany_top_in[12] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 47.69 80.24 47.99 81.6 ; + LAYER met2 ; + RECT 75.37 80.24 75.51 81.6 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -487,7 +475,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 80.24 45.15 81.6 ; + RECT 68.93 80.24 69.07 81.6 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -503,7 +491,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 80.24 51.13 81.6 ; + RECT 39.03 80.24 39.17 81.6 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -511,7 +499,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 51.37 80.24 51.67 81.6 ; + RECT 62.41 80.24 62.71 81.6 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -519,15 +507,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 80.24 41.47 81.6 ; + RECT 58.35 80.24 58.49 81.6 ; END END chany_top_in[17] PIN chany_top_in[18] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 39.41 80.24 39.71 81.6 ; + LAYER met2 ; + RECT 55.13 80.24 55.27 81.6 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -535,79 +523,79 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 80.24 39.63 81.6 ; + RECT 56.97 80.24 57.11 81.6 ; END END chany_top_in[19] - PIN top_left_grid_pin_34_[0] + PIN top_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 23.39 80.24 23.53 81.6 ; + RECT 25.69 80.24 25.83 81.6 ; END - END top_left_grid_pin_34_[0] - PIN top_left_grid_pin_35_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 24.31 80.24 24.45 81.6 ; - END - END top_left_grid_pin_35_[0] - PIN top_left_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.47 80.24 22.61 81.6 ; - END - END top_left_grid_pin_36_[0] - PIN top_left_grid_pin_37_[0] + END top_left_grid_pin_42_[0] + PIN top_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; - RECT 8.13 63.92 8.43 65.28 ; + RECT 24.69 80.24 24.99 81.6 ; END - END top_left_grid_pin_37_[0] - PIN top_left_grid_pin_38_[0] + END top_left_grid_pin_43_[0] + PIN top_left_grid_pin_44_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 80.24 21.69 81.6 ; + RECT 23.85 80.24 23.99 81.6 ; END - END top_left_grid_pin_38_[0] - PIN top_left_grid_pin_39_[0] + END top_left_grid_pin_44_[0] + PIN top_left_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.01 80.24 22.15 81.6 ; + END + END top_left_grid_pin_45_[0] + PIN top_left_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.93 80.24 23.07 81.6 ; + END + END top_left_grid_pin_46_[0] + PIN top_left_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.67 63.92 8.81 65.28 ; + END + END top_left_grid_pin_47_[0] + PIN top_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; RECT 22.85 80.24 23.15 81.6 ; END - END top_left_grid_pin_39_[0] - PIN top_left_grid_pin_40_[0] + END top_left_grid_pin_48_[0] + PIN top_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 80.24 20.77 81.6 ; + RECT 24.77 80.24 24.91 81.6 ; END - END top_left_grid_pin_40_[0] - PIN top_left_grid_pin_41_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.75 63.92 7.89 65.28 ; - END - END top_left_grid_pin_41_[0] + END top_left_grid_pin_49_[0] PIN chanx_right_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 17.53 103.04 17.83 ; + RECT 101.66 36.57 103.04 36.87 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -615,7 +603,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 14.81 103.04 15.11 ; + RECT 101.66 18.89 103.04 19.19 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -623,23 +611,23 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 29.09 103.04 29.39 ; + RECT 101.66 17.53 103.04 17.83 ; END END chanx_right_in[2] PIN chanx_right_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 101.66 8.01 103.04 8.31 ; + LAYER met2 ; + RECT 98.83 0 98.97 1.36 ; END END chanx_right_in[3] PIN chanx_right_in[4] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 101.66 12.09 103.04 12.39 ; + LAYER met2 ; + RECT 100.67 0 100.81 1.36 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -647,7 +635,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 6.65 103.04 6.95 ; + RECT 101.66 10.73 103.04 11.03 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -655,7 +643,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 37.93 103.04 38.23 ; + RECT 101.66 39.29 103.04 39.59 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -663,7 +651,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 42.01 103.04 42.31 ; + RECT 101.66 21.61 103.04 21.91 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -671,15 +659,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 13.45 103.04 13.75 ; + RECT 101.66 43.37 103.04 43.67 ; END END chanx_right_in[8] PIN chanx_right_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 101.66 46.09 103.04 46.39 ; + LAYER met2 ; + RECT 97.91 0 98.05 1.36 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -687,7 +675,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 18.89 103.04 19.19 ; + RECT 101.66 3.93 103.04 4.23 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -695,7 +683,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 16.17 103.04 16.47 ; + RECT 101.66 42.01 103.04 42.31 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -703,7 +691,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 31.81 103.04 32.11 ; + RECT 101.66 37.93 103.04 38.23 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -711,7 +699,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 59.69 103.04 59.99 ; + RECT 101.66 46.09 103.04 46.39 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -719,15 +707,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 24.33 103.04 24.63 ; + RECT 101.66 40.65 103.04 40.95 ; END END chanx_right_in[14] PIN chanx_right_in[15] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 101.66 33.17 103.04 33.47 ; + LAYER met4 ; + RECT 98.29 0 98.59 1.36 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -735,7 +723,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 9.37 103.04 9.67 ; + RECT 101.66 25.69 103.04 25.99 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -743,7 +731,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 40.65 103.04 40.95 ; + RECT 101.66 6.65 103.04 6.95 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -751,7 +739,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 51.53 103.04 51.83 ; + RECT 101.66 12.09 103.04 12.39 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -759,81 +747,57 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 48.81 103.04 49.11 ; + RECT 101.66 13.45 103.04 13.75 ; END END chanx_right_in[19] - PIN right_top_grid_pin_42_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 94.69 63.92 94.83 65.28 ; - END - END right_top_grid_pin_42_[0] - PIN right_top_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 91.93 63.92 92.07 65.28 ; - END - END right_top_grid_pin_43_[0] - PIN right_top_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 96.99 63.92 97.13 65.28 ; - END - END right_top_grid_pin_44_[0] - PIN right_top_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 100.21 63.92 100.35 65.28 ; - END - END right_top_grid_pin_45_[0] - PIN right_top_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 99.29 63.92 99.43 65.28 ; - END - END right_top_grid_pin_46_[0] - PIN right_top_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 95.61 63.92 95.75 65.28 ; - END - END right_top_grid_pin_47_[0] - PIN right_top_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 98.29 63.92 98.59 65.28 ; - END - END right_top_grid_pin_48_[0] - PIN right_top_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 98.37 63.92 98.51 65.28 ; - END - END right_top_grid_pin_49_[0] PIN right_bottom_grid_pin_1_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 99.75 0 99.89 1.36 ; + LAYER met3 ; + RECT 101.66 20.25 103.04 20.55 ; END END right_bottom_grid_pin_1_[0] + PIN right_bottom_grid_pin_3_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 101.66 48.81 103.04 49.11 ; + END + END right_bottom_grid_pin_3_[0] + PIN right_bottom_grid_pin_5_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 101.66 44.73 103.04 45.03 ; + END + END right_bottom_grid_pin_5_[0] + PIN right_bottom_grid_pin_7_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 101.66 30.45 103.04 30.75 ; + END + END right_bottom_grid_pin_7_[0] + PIN right_bottom_grid_pin_9_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 101.66 22.97 103.04 23.27 ; + END + END right_bottom_grid_pin_9_[0] + PIN right_bottom_grid_pin_11_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 101.66 24.33 103.04 24.63 ; + END + END right_bottom_grid_pin_11_[0] PIN chanx_left_in[0] DIRECTION INPUT ; USE SIGNAL ; @@ -847,7 +811,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; + RECT 0 55.61 1.38 55.91 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -855,7 +819,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; + RECT 0 38.61 1.38 38.91 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -863,7 +827,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; + RECT 0 12.09 1.38 12.39 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -871,7 +835,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.89 1.38 36.19 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -879,7 +843,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.09 1.38 12.39 ; + RECT 0 16.17 1.38 16.47 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -887,15 +851,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; + RECT 0 20.25 1.38 20.55 ; END END chanx_left_in[6] PIN chanx_left_in[7] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; + LAYER met2 ; + RECT 3.15 63.92 3.29 65.28 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -903,7 +867,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; + RECT 0 9.37 1.38 9.67 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -911,7 +875,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; + RECT 0 21.61 1.38 21.91 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -919,15 +883,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; + RECT 0 41.33 1.38 41.63 ; END END chanx_left_in[10] PIN chanx_left_in[11] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; + LAYER met2 ; + RECT 2.23 63.92 2.37 65.28 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -935,23 +899,23 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; + RECT 0 5.29 1.38 5.59 ; END END chanx_left_in[12] PIN chanx_left_in[13] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; + LAYER met2 ; + RECT 4.99 63.92 5.13 65.28 ; END END chanx_left_in[13] PIN chanx_left_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 5.29 1.38 5.59 ; + LAYER met4 ; + RECT 4.45 63.92 4.75 65.28 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -959,7 +923,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -967,7 +931,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -975,7 +939,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -983,7 +947,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -991,87 +955,63 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 24.33 1.38 24.63 ; END END chanx_left_in[19] - PIN left_top_grid_pin_42_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.97 63.92 11.11 65.28 ; - END - END left_top_grid_pin_42_[0] - PIN left_top_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 5.45 63.92 5.59 65.28 ; - END - END left_top_grid_pin_43_[0] - PIN left_top_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 4.45 63.92 4.75 65.28 ; - END - END left_top_grid_pin_44_[0] - PIN left_top_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 6.29 63.92 6.59 65.28 ; - END - END left_top_grid_pin_45_[0] - PIN left_top_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 3.61 63.92 3.75 65.28 ; - END - END left_top_grid_pin_46_[0] - PIN left_top_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.37 63.92 6.51 65.28 ; - END - END left_top_grid_pin_47_[0] - PIN left_top_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.67 63.92 8.81 65.28 ; - END - END left_top_grid_pin_48_[0] - PIN left_top_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.53 63.92 4.67 65.28 ; - END - END left_top_grid_pin_49_[0] PIN left_bottom_grid_pin_1_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 10.97 0 11.11 1.36 ; + LAYER met3 ; + RECT 0 44.05 1.38 44.35 ; END END left_bottom_grid_pin_1_[0] + PIN left_bottom_grid_pin_3_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.81 1.38 49.11 ; + END + END left_bottom_grid_pin_3_[0] + PIN left_bottom_grid_pin_5_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.57 1.38 36.87 ; + END + END left_bottom_grid_pin_5_[0] + PIN left_bottom_grid_pin_7_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 30.45 1.38 30.75 ; + END + END left_bottom_grid_pin_7_[0] + PIN left_bottom_grid_pin_9_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.69 1.38 42.99 ; + END + END left_bottom_grid_pin_9_[0] + PIN left_bottom_grid_pin_11_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 46.09 1.38 46.39 ; + END + END left_bottom_grid_pin_11_[0] PIN ccff_head[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 100.67 0 100.81 1.36 ; + LAYER met3 ; + RECT 101.66 27.05 103.04 27.35 ; END END ccff_head[0] PIN chany_top_out[0] @@ -1079,7 +1019,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 80.24 66.77 81.6 ; + RECT 49.61 80.24 49.75 81.6 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -1087,7 +1027,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 80.24 40.55 81.6 ; + RECT 51.45 80.24 51.59 81.6 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -1095,7 +1035,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 80.24 64.93 81.6 ; + RECT 45.47 80.24 45.61 81.6 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -1103,7 +1043,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 80.24 38.71 81.6 ; + RECT 63.87 80.24 64.01 81.6 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -1111,7 +1051,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.39 80.24 69.53 81.6 ; + RECT 59.27 80.24 59.41 81.6 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -1119,7 +1059,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 80.24 57.11 81.6 ; + RECT 68.01 80.24 68.15 81.6 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -1127,7 +1067,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 80.24 68.61 81.6 ; + RECT 50.53 80.24 50.67 81.6 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -1135,7 +1075,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 80.24 53.43 81.6 ; + RECT 61.11 80.24 61.25 81.6 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -1143,7 +1083,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 80.24 67.69 81.6 ; + RECT 43.17 80.24 43.31 81.6 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -1151,7 +1091,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 80.24 43.31 81.6 ; + RECT 60.19 80.24 60.33 81.6 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -1159,7 +1099,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 80.24 70.45 81.6 ; + RECT 48.23 80.24 48.37 81.6 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -1167,7 +1107,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 80.24 48.37 81.6 ; + RECT 71.69 80.24 71.83 81.6 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -1175,7 +1115,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 80.24 71.37 81.6 ; + RECT 74.45 80.24 74.59 81.6 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -1183,7 +1123,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 80.24 27.67 81.6 ; + RECT 62.49 80.24 62.63 81.6 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -1191,7 +1131,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 80.24 60.33 81.6 ; + RECT 40.87 80.24 41.01 81.6 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -1199,7 +1139,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 80.24 46.07 81.6 ; + RECT 64.79 80.24 64.93 81.6 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -1207,15 +1147,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 80.24 61.25 81.6 ; + RECT 42.25 80.24 42.39 81.6 ; END END chany_top_out[16] PIN chany_top_out[17] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 41.25 80.24 41.55 81.6 ; + LAYER met2 ; + RECT 66.63 80.24 66.77 81.6 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1223,7 +1163,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 80.24 37.79 81.6 ; + RECT 46.39 80.24 46.53 81.6 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1231,7 +1171,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 80.24 46.99 81.6 ; + RECT 77.67 80.24 77.81 81.6 ; END END chany_top_out[19] PIN chanx_right_out[0] @@ -1239,7 +1179,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 10.73 103.04 11.03 ; + RECT 101.66 60.37 103.04 60.67 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -1247,7 +1187,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 58.33 103.04 58.63 ; + RECT 101.66 51.53 103.04 51.83 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -1255,7 +1195,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 54.25 103.04 54.55 ; + RECT 101.66 16.17 103.04 16.47 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -1263,7 +1203,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 56.97 103.04 57.27 ; + RECT 101.66 8.01 103.04 8.31 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -1271,7 +1211,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 27.73 103.04 28.03 ; + RECT 101.66 14.81 103.04 15.11 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -1279,7 +1219,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 61.73 103.04 62.03 ; + RECT 101.66 57.65 103.04 57.95 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -1287,7 +1227,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 34.53 103.04 34.83 ; + RECT 101.66 56.29 103.04 56.59 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -1295,7 +1235,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 39.29 103.04 39.59 ; + RECT 101.66 59.01 103.04 59.31 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1303,7 +1243,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 26.37 103.04 26.67 ; + RECT 101.66 52.89 103.04 53.19 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1311,7 +1251,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 47.45 103.04 47.75 ; + RECT 101.66 61.73 103.04 62.03 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1319,7 +1259,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 20.25 103.04 20.55 ; + RECT 101.66 9.37 103.04 9.67 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1327,7 +1267,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 52.89 103.04 53.19 ; + RECT 101.66 50.17 103.04 50.47 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1335,7 +1275,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 30.45 103.04 30.75 ; + RECT 101.66 54.93 103.04 55.23 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1343,7 +1283,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 55.61 103.04 55.91 ; + RECT 101.66 35.21 103.04 35.51 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1351,7 +1291,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 22.97 103.04 23.27 ; + RECT 101.66 47.45 103.04 47.75 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1359,15 +1299,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 44.73 103.04 45.03 ; + RECT 101.66 5.29 103.04 5.59 ; END END chanx_right_out[15] PIN chanx_right_out[16] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 101.66 35.89 103.04 36.19 ; + LAYER met2 ; + RECT 99.75 0 99.89 1.36 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1375,7 +1315,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 50.17 103.04 50.47 ; + RECT 101.66 33.85 103.04 34.15 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1383,7 +1323,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 21.61 103.04 21.91 ; + RECT 101.66 29.09 103.04 29.39 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1391,7 +1331,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 43.37 103.04 43.67 ; + RECT 101.66 32.49 103.04 32.79 ; END END chanx_right_out[19] PIN chanx_left_out[0] @@ -1399,7 +1339,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1407,7 +1347,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; + RECT 0 56.97 1.38 57.27 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -1415,15 +1355,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_out[2] PIN chanx_left_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 49.49 1.38 49.79 ; + LAYER met2 ; + RECT 4.07 63.92 4.21 65.28 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1431,7 +1371,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 54.25 1.38 54.55 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1439,15 +1379,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; + RECT 0 61.05 1.38 61.35 ; END END chanx_left_out[5] PIN chanx_left_out[6] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + LAYER met2 ; + RECT 2.23 0 2.37 1.36 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1455,7 +1395,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.69 1.38 42.99 ; + RECT 0 59.69 1.38 59.99 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1463,15 +1403,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 31.81 1.38 32.11 ; END END chanx_left_out[8] PIN chanx_left_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; + LAYER met2 ; + RECT 3.15 0 3.29 1.36 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1479,7 +1419,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 18.89 1.38 19.19 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1487,7 +1427,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1495,7 +1435,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 29.09 1.38 29.39 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1503,7 +1443,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; + RECT 0 8.01 1.38 8.31 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1511,7 +1451,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 25.69 1.38 25.99 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1519,7 +1459,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 17.53 1.38 17.83 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1527,7 +1467,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.01 1.38 8.31 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1535,7 +1475,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 14.81 1.38 15.11 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1543,7 +1483,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 27.05 1.38 27.35 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1551,7 +1491,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 10.73 1.38 11.03 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1559,9 +1499,41 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 9.37 1.38 9.67 ; + RECT 0 13.45 1.38 13.75 ; END END ccff_tail[0] + PIN SC_IN_TOP + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 6.65 1.38 6.95 ; + END + END SC_IN_TOP + PIN SC_IN_BOT + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 49.53 80.24 49.83 81.6 ; + END + END SC_IN_BOT + PIN SC_OUT_TOP + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 51.37 80.24 51.67 81.6 ; + END + END SC_OUT_TOP + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 98.83 63.92 98.97 65.28 ; + END + END SC_OUT_BOT PIN VDD DIRECTION INPUT ; USE POWER ; @@ -1662,18 +1634,18 @@ MACRO sb_1__0_ RECT 18.4 76.075 22.08 76.245 ; RECT 83.72 73.355 84.64 73.525 ; RECT 18.4 73.355 22.08 73.525 ; - RECT 80.96 70.635 84.64 70.805 ; + RECT 83.72 70.635 84.64 70.805 ; RECT 18.4 70.635 22.08 70.805 ; RECT 80.96 67.915 84.64 68.085 ; - RECT 18.4 67.915 20.24 68.085 ; - RECT 83.72 65.195 103.04 65.365 ; + RECT 18.4 67.915 22.08 68.085 ; + RECT 80.96 65.195 103.04 65.365 ; RECT 0 65.195 22.08 65.365 ; RECT 102.12 62.475 103.04 62.645 ; RECT 0 62.475 3.68 62.645 ; RECT 102.12 59.755 103.04 59.925 ; - RECT 0 59.755 1.84 59.925 ; + RECT 0 59.755 3.68 59.925 ; RECT 102.12 57.035 103.04 57.205 ; - RECT 0 57.035 1.84 57.205 ; + RECT 0 57.035 3.68 57.205 ; RECT 102.12 54.315 103.04 54.485 ; RECT 0 54.315 1.84 54.485 ; RECT 102.12 51.595 103.04 51.765 ; @@ -1683,9 +1655,9 @@ MACRO sb_1__0_ RECT 102.12 46.155 103.04 46.325 ; RECT 0 46.155 1.84 46.325 ; RECT 102.12 43.435 103.04 43.605 ; - RECT 0 43.435 1.84 43.605 ; + RECT 0 43.435 3.68 43.605 ; RECT 102.12 40.715 103.04 40.885 ; - RECT 0 40.715 1.84 40.885 ; + RECT 0 40.715 3.68 40.885 ; RECT 102.12 37.995 103.04 38.165 ; RECT 0 37.995 1.84 38.165 ; RECT 102.12 35.275 103.04 35.445 ; @@ -1696,12 +1668,12 @@ MACRO sb_1__0_ RECT 0 29.835 1.84 30.005 ; RECT 102.12 27.115 103.04 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 102.12 24.395 103.04 24.565 ; + RECT 101.2 24.395 103.04 24.565 ; RECT 0 24.395 1.84 24.565 ; - RECT 102.12 21.675 103.04 21.845 ; - RECT 0 21.675 3.68 21.845 ; + RECT 101.2 21.675 103.04 21.845 ; + RECT 0 21.675 1.84 21.845 ; RECT 102.12 18.955 103.04 19.125 ; - RECT 0 18.955 3.68 19.125 ; + RECT 0 18.955 1.84 19.125 ; RECT 102.12 16.235 103.04 16.405 ; RECT 0 16.235 1.84 16.405 ; RECT 102.12 13.515 103.04 13.685 ; @@ -1711,46 +1683,43 @@ MACRO sb_1__0_ RECT 102.12 8.075 103.04 8.245 ; RECT 0 8.075 1.84 8.245 ; RECT 102.12 5.355 103.04 5.525 ; - RECT 0 5.355 3.68 5.525 ; + RECT 0 5.355 1.84 5.525 ; RECT 102.12 2.635 103.04 2.805 ; RECT 0 2.635 3.68 2.805 ; RECT 0 -0.085 103.04 0.085 ; LAYER met2 ; RECT 73.46 81.415 73.74 81.785 ; RECT 44.02 81.415 44.3 81.785 ; - RECT 58.29 79.74 58.55 80.06 ; - RECT 45.41 79.74 45.67 80.06 ; + RECT 74.85 79.74 75.11 80.06 ; + RECT 59.67 79.74 59.93 80.06 ; RECT 73.46 -0.185 73.74 0.185 ; RECT 44.02 -0.185 44.3 0.185 ; - POLYGON 84.36 81.32 84.36 65 91.65 65 91.65 63.64 92.35 63.64 92.35 65 94.41 65 94.41 63.64 95.11 63.64 95.11 65 95.33 65 95.33 63.64 96.03 63.64 96.03 65 96.71 65 96.71 63.64 97.41 63.64 97.41 65 98.09 65 98.09 63.64 98.79 63.64 98.79 65 99.01 65 99.01 63.64 99.71 63.64 99.71 65 99.93 65 99.93 63.64 100.63 63.64 100.63 65 102.76 65 102.76 0.28 101.09 0.28 101.09 1.64 100.39 1.64 100.39 0.28 100.17 0.28 100.17 1.64 99.47 1.64 99.47 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 0.28 0.28 0.28 65 1.95 65 1.95 63.64 2.65 63.64 2.65 65 3.33 65 3.33 63.64 4.03 63.64 4.03 65 4.25 65 4.25 63.64 4.95 63.64 4.95 65 5.17 65 5.17 63.64 5.87 63.64 5.87 65 6.09 65 6.09 63.64 6.79 63.64 6.79 65 7.47 65 7.47 63.64 8.17 63.64 8.17 65 8.39 65 8.39 63.64 9.09 63.64 9.09 65 10.69 65 10.69 63.64 11.39 63.64 11.39 65 18.68 65 18.68 81.32 20.35 81.32 20.35 79.96 21.05 79.96 21.05 81.32 21.27 81.32 21.27 79.96 21.97 79.96 21.97 81.32 22.19 81.32 22.19 79.96 22.89 79.96 22.89 81.32 23.11 81.32 23.11 79.96 23.81 79.96 23.81 81.32 24.03 81.32 24.03 79.96 24.73 79.96 24.73 81.32 27.25 81.32 27.25 79.96 27.95 79.96 27.95 81.32 37.37 81.32 37.37 79.96 38.07 79.96 38.07 81.32 38.29 81.32 38.29 79.96 38.99 79.96 38.99 81.32 39.21 81.32 39.21 79.96 39.91 79.96 39.91 81.32 40.13 81.32 40.13 79.96 40.83 79.96 40.83 81.32 41.05 81.32 41.05 79.96 41.75 79.96 41.75 81.32 41.97 81.32 41.97 79.96 42.67 79.96 42.67 81.32 42.89 81.32 42.89 79.96 43.59 79.96 43.59 81.32 44.73 81.32 44.73 79.96 45.43 79.96 45.43 81.32 45.65 81.32 45.65 79.96 46.35 79.96 46.35 81.32 46.57 81.32 46.57 79.96 47.27 79.96 47.27 81.32 47.95 81.32 47.95 79.96 48.65 79.96 48.65 81.32 48.87 81.32 48.87 79.96 49.57 79.96 49.57 81.32 49.79 81.32 49.79 79.96 50.49 79.96 50.49 81.32 50.71 81.32 50.71 79.96 51.41 79.96 51.41 81.32 51.63 81.32 51.63 79.96 52.33 79.96 52.33 81.32 53.01 81.32 53.01 79.96 53.71 79.96 53.71 81.32 53.93 81.32 53.93 79.96 54.63 79.96 54.63 81.32 54.85 81.32 54.85 79.96 55.55 79.96 55.55 81.32 55.77 81.32 55.77 79.96 56.47 79.96 56.47 81.32 56.69 81.32 56.69 79.96 57.39 79.96 57.39 81.32 57.61 81.32 57.61 79.96 58.31 79.96 58.31 81.32 58.99 81.32 58.99 79.96 59.69 79.96 59.69 81.32 59.91 81.32 59.91 79.96 60.61 79.96 60.61 81.32 60.83 81.32 60.83 79.96 61.53 79.96 61.53 81.32 64.51 81.32 64.51 79.96 65.21 79.96 65.21 81.32 65.43 81.32 65.43 79.96 66.13 79.96 66.13 81.32 66.35 81.32 66.35 79.96 67.05 79.96 67.05 81.32 67.27 81.32 67.27 79.96 67.97 79.96 67.97 81.32 68.19 81.32 68.19 79.96 68.89 79.96 68.89 81.32 69.11 81.32 69.11 79.96 69.81 79.96 69.81 81.32 70.03 81.32 70.03 79.96 70.73 79.96 70.73 81.32 70.95 81.32 70.95 79.96 71.65 79.96 71.65 81.32 ; + POLYGON 84.36 81.32 84.36 65 98.55 65 98.55 63.64 99.25 63.64 99.25 65 102.76 65 102.76 0.28 101.09 0.28 101.09 1.64 100.39 1.64 100.39 0.28 100.17 0.28 100.17 1.64 99.47 1.64 99.47 0.28 99.25 0.28 99.25 1.64 98.55 1.64 98.55 0.28 98.33 0.28 98.33 1.64 97.63 1.64 97.63 0.28 3.57 0.28 3.57 1.64 2.87 1.64 2.87 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 65 1.95 65 1.95 63.64 2.65 63.64 2.65 65 2.87 65 2.87 63.64 3.57 63.64 3.57 65 3.79 65 3.79 63.64 4.49 63.64 4.49 65 4.71 65 4.71 63.64 5.41 63.64 5.41 65 8.39 65 8.39 63.64 9.09 63.64 9.09 65 18.68 65 18.68 81.32 20.35 81.32 20.35 79.96 21.05 79.96 21.05 81.32 21.73 81.32 21.73 79.96 22.43 79.96 22.43 81.32 22.65 81.32 22.65 79.96 23.35 79.96 23.35 81.32 23.57 81.32 23.57 79.96 24.27 79.96 24.27 81.32 24.49 81.32 24.49 79.96 25.19 79.96 25.19 81.32 25.41 81.32 25.41 79.96 26.11 79.96 26.11 81.32 38.75 81.32 38.75 79.96 39.45 79.96 39.45 81.32 39.67 81.32 39.67 79.96 40.37 79.96 40.37 81.32 40.59 81.32 40.59 79.96 41.29 79.96 41.29 81.32 41.97 81.32 41.97 79.96 42.67 79.96 42.67 81.32 42.89 81.32 42.89 79.96 43.59 79.96 43.59 81.32 45.19 81.32 45.19 79.96 45.89 79.96 45.89 81.32 46.11 81.32 46.11 79.96 46.81 79.96 46.81 81.32 47.03 81.32 47.03 79.96 47.73 79.96 47.73 81.32 47.95 81.32 47.95 79.96 48.65 79.96 48.65 81.32 49.33 81.32 49.33 79.96 50.03 79.96 50.03 81.32 50.25 81.32 50.25 79.96 50.95 79.96 50.95 81.32 51.17 81.32 51.17 79.96 51.87 79.96 51.87 81.32 52.09 81.32 52.09 79.96 52.79 79.96 52.79 81.32 53.01 81.32 53.01 79.96 53.71 79.96 53.71 81.32 53.93 81.32 53.93 79.96 54.63 79.96 54.63 81.32 54.85 81.32 54.85 79.96 55.55 79.96 55.55 81.32 55.77 81.32 55.77 79.96 56.47 79.96 56.47 81.32 56.69 81.32 56.69 79.96 57.39 79.96 57.39 81.32 58.07 81.32 58.07 79.96 58.77 79.96 58.77 81.32 58.99 81.32 58.99 79.96 59.69 79.96 59.69 81.32 59.91 81.32 59.91 79.96 60.61 79.96 60.61 81.32 60.83 81.32 60.83 79.96 61.53 79.96 61.53 81.32 62.21 81.32 62.21 79.96 62.91 79.96 62.91 81.32 63.59 81.32 63.59 79.96 64.29 79.96 64.29 81.32 64.51 81.32 64.51 79.96 65.21 79.96 65.21 81.32 65.43 81.32 65.43 79.96 66.13 79.96 66.13 81.32 66.35 81.32 66.35 79.96 67.05 79.96 67.05 81.32 67.73 81.32 67.73 79.96 68.43 79.96 68.43 81.32 68.65 81.32 68.65 79.96 69.35 79.96 69.35 81.32 69.57 81.32 69.57 79.96 70.27 79.96 70.27 81.32 70.49 81.32 70.49 79.96 71.19 79.96 71.19 81.32 71.41 81.32 71.41 79.96 72.11 79.96 72.11 81.32 72.33 81.32 72.33 79.96 73.03 79.96 73.03 81.32 74.17 81.32 74.17 79.96 74.87 79.96 74.87 81.32 75.09 81.32 75.09 79.96 75.79 79.96 75.79 81.32 76.01 81.32 76.01 79.96 76.71 79.96 76.71 81.32 77.39 81.32 77.39 79.96 78.09 79.96 78.09 81.32 ; LAYER met4 ; - POLYGON 84.24 81.2 84.24 64.88 97.89 64.88 97.89 63.52 98.99 63.52 98.99 64.88 102.64 64.88 102.64 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 0.4 0.4 0.4 64.88 4.05 64.88 4.05 63.52 5.15 63.52 5.15 64.88 5.89 64.88 5.89 63.52 6.99 63.52 6.99 64.88 7.73 64.88 7.73 63.52 8.83 63.52 8.83 64.88 18.8 64.88 18.8 81.2 22.45 81.2 22.45 79.84 23.55 79.84 23.55 81.2 28.74 81.2 28.74 80.6 30.14 80.6 30.14 81.2 39.01 81.2 39.01 79.84 40.11 79.84 40.11 81.2 40.85 81.2 40.85 79.84 41.95 79.84 41.95 81.2 43.46 81.2 43.46 80.6 44.86 80.6 44.86 81.2 47.29 81.2 47.29 79.84 48.39 79.84 48.39 81.2 49.13 81.2 49.13 79.84 50.23 79.84 50.23 81.2 50.97 81.2 50.97 79.84 52.07 79.84 52.07 81.2 52.81 81.2 52.81 79.84 53.91 79.84 53.91 81.2 55.57 81.2 55.57 79.84 56.67 79.84 56.67 81.2 58.18 81.2 58.18 80.6 59.58 80.6 59.58 81.2 72.9 81.2 72.9 80.6 74.3 80.6 74.3 81.2 ; + POLYGON 84.24 81.2 84.24 64.88 102.64 64.88 102.64 0.4 98.99 0.4 98.99 1.76 97.89 1.76 97.89 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 0.4 0.4 0.4 64.88 4.05 64.88 4.05 63.52 5.15 63.52 5.15 64.88 18.8 64.88 18.8 81.2 22.45 81.2 22.45 79.84 23.55 79.84 23.55 81.2 24.29 81.2 24.29 79.84 25.39 79.84 25.39 81.2 28.74 81.2 28.74 80.6 30.14 80.6 30.14 81.2 43.46 81.2 43.46 80.6 44.86 80.6 44.86 81.2 49.13 81.2 49.13 79.84 50.23 79.84 50.23 81.2 50.97 81.2 50.97 79.84 52.07 79.84 52.07 81.2 55.57 81.2 55.57 79.84 56.67 79.84 56.67 81.2 58.18 81.2 58.18 80.6 59.58 80.6 59.58 81.2 60.17 81.2 60.17 79.84 61.27 79.84 61.27 81.2 62.01 81.2 62.01 79.84 63.11 79.84 63.11 81.2 72.9 81.2 72.9 80.6 74.3 80.6 74.3 81.2 ; LAYER met3 ; POLYGON 73.765 81.765 73.765 81.76 73.98 81.76 73.98 81.44 73.765 81.44 73.765 81.435 73.435 81.435 73.435 81.44 73.22 81.44 73.22 81.76 73.435 81.76 73.435 81.765 ; POLYGON 44.325 81.765 44.325 81.76 44.54 81.76 44.54 81.44 44.325 81.44 44.325 81.435 43.995 81.435 43.995 81.44 43.78 81.44 43.78 81.76 43.995 81.76 43.995 81.765 ; - POLYGON 2.03 54.56 2.03 54.55 36.95 54.55 36.95 54.25 2.03 54.25 2.03 54.24 1.65 54.24 1.65 54.56 ; - POLYGON 1.545 45.725 1.545 45.71 13.03 45.71 13.03 45.41 1.545 45.41 1.545 45.395 1.215 45.395 1.215 45.725 ; - POLYGON 101.825 44.365 101.825 44.035 101.495 44.035 101.495 44.05 87.71 44.05 87.71 44.35 101.495 44.35 101.495 44.365 ; - POLYGON 101.35 40.27 101.35 39.99 101.26 39.99 101.26 39.29 101.05 39.29 101.05 39.97 96.91 39.97 96.91 40.27 ; - POLYGON 6.59 29.39 6.59 29.09 1.78 29.09 1.78 29.11 1.23 29.11 1.23 29.39 ; - POLYGON 101.825 23.965 101.825 23.635 101.495 23.635 101.495 23.65 91.85 23.65 91.85 23.95 101.495 23.95 101.495 23.965 ; - POLYGON 101.35 22.59 101.35 22.31 101.26 22.31 101.26 21.61 101.05 21.61 101.05 22.29 94.61 22.29 94.61 22.59 ; - POLYGON 101.26 14.43 101.26 14.41 101.81 14.41 101.81 14.13 72.53 14.13 72.53 14.43 ; - POLYGON 2.03 4.92 2.03 4.91 60.87 4.91 60.87 4.61 2.03 4.61 2.03 4.6 1.65 4.6 1.65 4.92 ; + POLYGON 101.81 42.99 101.81 42.71 101.26 42.71 101.26 42.69 61.95 42.69 61.95 42.99 ; + POLYGON 101.81 36.19 101.81 35.91 101.26 35.91 101.26 35.89 92.77 35.89 92.77 36.19 ; + POLYGON 2.03 25.32 2.03 25.31 63.63 25.31 63.63 25.01 2.03 25.01 2.03 25 1.65 25 1.65 25.32 ; + POLYGON 101.26 19.87 101.26 19.85 101.81 19.85 101.81 19.57 74.83 19.57 74.83 19.87 ; + POLYGON 101.26 18.51 101.26 18.49 101.81 18.49 101.81 18.21 88.17 18.21 88.17 18.51 ; + POLYGON 1.99 15.11 1.99 14.43 5.21 14.43 5.21 14.13 1.69 14.13 1.69 14.41 1.78 14.41 1.78 15.11 ; + POLYGON 7.05 8.99 7.05 8.69 1.99 8.69 1.99 8.01 1.78 8.01 1.78 8.71 1.69 8.71 1.69 8.99 ; + POLYGON 101.81 7.63 101.81 7.35 101.26 7.35 101.26 7.33 65.17 7.33 65.17 7.63 ; + POLYGON 11.65 6.27 11.65 5.97 1.23 5.97 1.23 6.25 1.78 6.25 1.78 6.27 ; POLYGON 73.765 0.165 73.765 0.16 73.98 0.16 73.98 -0.16 73.765 -0.16 73.765 -0.165 73.435 -0.165 73.435 -0.16 73.22 -0.16 73.22 0.16 73.435 0.16 73.435 0.165 ; POLYGON 44.325 0.165 44.325 0.16 44.54 0.16 44.54 -0.16 44.325 -0.16 44.325 -0.165 43.995 -0.165 43.995 -0.16 43.78 -0.16 43.78 0.16 43.995 0.16 43.995 0.165 ; - POLYGON 84.24 81.2 84.24 64.88 102.64 64.88 102.64 62.43 101.26 62.43 101.26 61.33 102.64 61.33 102.64 60.39 101.26 60.39 101.26 59.29 102.64 59.29 102.64 59.03 101.26 59.03 101.26 57.93 102.64 57.93 102.64 57.67 101.26 57.67 101.26 56.57 102.64 56.57 102.64 56.31 101.26 56.31 101.26 55.21 102.64 55.21 102.64 54.95 101.26 54.95 101.26 53.85 102.64 53.85 102.64 53.59 101.26 53.59 101.26 52.49 102.64 52.49 102.64 52.23 101.26 52.23 101.26 51.13 102.64 51.13 102.64 50.87 101.26 50.87 101.26 49.77 102.64 49.77 102.64 49.51 101.26 49.51 101.26 48.41 102.64 48.41 102.64 48.15 101.26 48.15 101.26 47.05 102.64 47.05 102.64 46.79 101.26 46.79 101.26 45.69 102.64 45.69 102.64 45.43 101.26 45.43 101.26 44.33 102.64 44.33 102.64 44.07 101.26 44.07 101.26 42.97 102.64 42.97 102.64 42.71 101.26 42.71 101.26 41.61 102.64 41.61 102.64 41.35 101.26 41.35 101.26 40.25 102.64 40.25 102.64 39.99 101.26 39.99 101.26 38.89 102.64 38.89 102.64 38.63 101.26 38.63 101.26 37.53 102.64 37.53 102.64 36.59 101.26 36.59 101.26 35.49 102.64 35.49 102.64 35.23 101.26 35.23 101.26 34.13 102.64 34.13 102.64 33.87 101.26 33.87 101.26 32.77 102.64 32.77 102.64 32.51 101.26 32.51 101.26 31.41 102.64 31.41 102.64 31.15 101.26 31.15 101.26 30.05 102.64 30.05 102.64 29.79 101.26 29.79 101.26 28.69 102.64 28.69 102.64 28.43 101.26 28.43 101.26 27.33 102.64 27.33 102.64 27.07 101.26 27.07 101.26 25.97 102.64 25.97 102.64 25.03 101.26 25.03 101.26 23.93 102.64 23.93 102.64 23.67 101.26 23.67 101.26 22.57 102.64 22.57 102.64 22.31 101.26 22.31 101.26 21.21 102.64 21.21 102.64 20.95 101.26 20.95 101.26 19.85 102.64 19.85 102.64 19.59 101.26 19.59 101.26 18.49 102.64 18.49 102.64 18.23 101.26 18.23 101.26 17.13 102.64 17.13 102.64 16.87 101.26 16.87 101.26 15.77 102.64 15.77 102.64 15.51 101.26 15.51 101.26 14.41 102.64 14.41 102.64 14.15 101.26 14.15 101.26 13.05 102.64 13.05 102.64 12.79 101.26 12.79 101.26 11.69 102.64 11.69 102.64 11.43 101.26 11.43 101.26 10.33 102.64 10.33 102.64 10.07 101.26 10.07 101.26 8.97 102.64 8.97 102.64 8.71 101.26 8.71 101.26 7.61 102.64 7.61 102.64 7.35 101.26 7.35 101.26 6.25 102.64 6.25 102.64 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 64.88 18.8 64.88 18.8 81.2 ; + POLYGON 84.24 81.2 84.24 64.88 102.64 64.88 102.64 62.43 101.26 62.43 101.26 61.33 102.64 61.33 102.64 61.07 101.26 61.07 101.26 59.97 102.64 59.97 102.64 59.71 101.26 59.71 101.26 58.61 102.64 58.61 102.64 58.35 101.26 58.35 101.26 57.25 102.64 57.25 102.64 56.99 101.26 56.99 101.26 55.89 102.64 55.89 102.64 55.63 101.26 55.63 101.26 54.53 102.64 54.53 102.64 53.59 101.26 53.59 101.26 52.49 102.64 52.49 102.64 52.23 101.26 52.23 101.26 51.13 102.64 51.13 102.64 50.87 101.26 50.87 101.26 49.77 102.64 49.77 102.64 49.51 101.26 49.51 101.26 48.41 102.64 48.41 102.64 48.15 101.26 48.15 101.26 47.05 102.64 47.05 102.64 46.79 101.26 46.79 101.26 45.69 102.64 45.69 102.64 45.43 101.26 45.43 101.26 44.33 102.64 44.33 102.64 44.07 101.26 44.07 101.26 42.97 102.64 42.97 102.64 42.71 101.26 42.71 101.26 41.61 102.64 41.61 102.64 41.35 101.26 41.35 101.26 40.25 102.64 40.25 102.64 39.99 101.26 39.99 101.26 38.89 102.64 38.89 102.64 38.63 101.26 38.63 101.26 37.53 102.64 37.53 102.64 37.27 101.26 37.27 101.26 36.17 102.64 36.17 102.64 35.91 101.26 35.91 101.26 34.81 102.64 34.81 102.64 34.55 101.26 34.55 101.26 33.45 102.64 33.45 102.64 33.19 101.26 33.19 101.26 32.09 102.64 32.09 102.64 31.15 101.26 31.15 101.26 30.05 102.64 30.05 102.64 29.79 101.26 29.79 101.26 28.69 102.64 28.69 102.64 27.75 101.26 27.75 101.26 26.65 102.64 26.65 102.64 26.39 101.26 26.39 101.26 25.29 102.64 25.29 102.64 25.03 101.26 25.03 101.26 23.93 102.64 23.93 102.64 23.67 101.26 23.67 101.26 22.57 102.64 22.57 102.64 22.31 101.26 22.31 101.26 21.21 102.64 21.21 102.64 20.95 101.26 20.95 101.26 19.85 102.64 19.85 102.64 19.59 101.26 19.59 101.26 18.49 102.64 18.49 102.64 18.23 101.26 18.23 101.26 17.13 102.64 17.13 102.64 16.87 101.26 16.87 101.26 15.77 102.64 15.77 102.64 15.51 101.26 15.51 101.26 14.41 102.64 14.41 102.64 14.15 101.26 14.15 101.26 13.05 102.64 13.05 102.64 12.79 101.26 12.79 101.26 11.69 102.64 11.69 102.64 11.43 101.26 11.43 101.26 10.33 102.64 10.33 102.64 10.07 101.26 10.07 101.26 8.97 102.64 8.97 102.64 8.71 101.26 8.71 101.26 7.61 102.64 7.61 102.64 7.35 101.26 7.35 101.26 6.25 102.64 6.25 102.64 5.99 101.26 5.99 101.26 4.89 102.64 4.89 102.64 4.63 101.26 4.63 101.26 3.53 102.64 3.53 102.64 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 64.88 18.8 64.88 18.8 81.2 ; LAYER met5 ; - POLYGON 81.44 78.4 81.44 62.08 99.84 62.08 99.84 57.84 96.64 57.84 96.64 48.24 99.84 48.24 99.84 37.44 96.64 37.44 96.64 27.84 99.84 27.84 99.84 17.04 96.64 17.04 96.64 7.44 99.84 7.44 99.84 3.2 3.2 3.2 3.2 7.44 6.4 7.44 6.4 17.04 3.2 17.04 3.2 27.84 6.4 27.84 6.4 37.44 3.2 37.44 3.2 48.24 6.4 48.24 6.4 57.84 3.2 57.84 3.2 62.08 21.6 62.08 21.6 78.4 ; + POLYGON 83.04 80 83.04 63.68 101.44 63.68 101.44 56.24 98.24 56.24 98.24 49.84 101.44 49.84 101.44 35.84 98.24 35.84 98.24 29.44 101.44 29.44 101.44 15.44 98.24 15.44 98.24 9.04 101.44 9.04 101.44 1.6 1.6 1.6 1.6 9.04 4.8 9.04 4.8 15.44 1.6 15.44 1.6 29.44 4.8 29.44 4.8 35.84 1.6 35.84 1.6 49.84 4.8 49.84 4.8 56.24 1.6 56.24 1.6 63.68 20 63.68 20 80 ; LAYER met1 ; + RECT 33.315 65.77 33.605 66 ; POLYGON 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 18.68 65.8 18.68 67.48 19.16 67.48 19.16 68.52 18.68 68.52 18.68 70.2 19.16 70.2 19.16 71.24 18.68 71.24 18.68 72.92 19.16 72.92 19.16 73.96 18.68 73.96 18.68 75.64 19.16 75.64 19.16 76.68 18.68 76.68 18.68 78.36 19.16 78.36 19.16 79.4 18.68 79.4 18.68 81.08 ; POLYGON 102.76 64.76 102.76 63.08 102.28 63.08 102.28 62.04 102.76 62.04 102.76 60.36 102.28 60.36 102.28 59.32 102.76 59.32 102.76 57.64 102.28 57.64 102.28 56.6 102.76 56.6 102.76 54.92 102.28 54.92 102.28 53.88 102.76 53.88 102.76 52.2 102.28 52.2 102.28 51.16 102.76 51.16 102.76 49.48 102.28 49.48 102.28 48.44 102.76 48.44 102.76 46.76 102.28 46.76 102.28 45.72 102.76 45.72 102.76 44.04 102.28 44.04 102.28 43 102.76 43 102.76 41.32 102.28 41.32 102.28 40.28 102.76 40.28 102.76 38.6 102.28 38.6 102.28 37.56 102.76 37.56 102.76 35.88 102.28 35.88 102.28 34.84 102.76 34.84 102.76 33.16 102.28 33.16 102.28 32.12 102.76 32.12 102.76 30.44 102.28 30.44 102.28 29.4 102.76 29.4 102.76 27.72 102.28 27.72 102.28 26.68 102.76 26.68 102.76 25 102.28 25 102.28 23.96 102.76 23.96 102.76 22.28 102.28 22.28 102.28 21.24 102.76 21.24 102.76 19.56 102.28 19.56 102.28 18.52 102.76 18.52 102.76 16.84 102.28 16.84 102.28 15.8 102.76 15.8 102.76 14.12 102.28 14.12 102.28 13.08 102.76 13.08 102.76 11.4 102.28 11.4 102.28 10.36 102.76 10.36 102.76 8.68 102.28 8.68 102.28 7.64 102.76 7.64 102.76 5.96 102.28 5.96 102.28 4.92 102.76 4.92 102.76 3.24 102.28 3.24 102.28 2.2 102.76 2.2 102.76 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 ; LAYER li1 ; - RECT 47.465 80.79 48.215 81.335 ; - RECT 96.225 64.47 96.975 65.015 ; - RECT 96.225 0.265 96.975 0.81 ; - RECT 47.465 0.265 48.215 0.81 ; - POLYGON 84.3 81.26 84.3 64.94 102.7 64.94 102.7 0.34 0.34 0.34 0.34 64.94 18.74 64.94 18.74 81.26 ; + POLYGON 84.47 81.43 84.47 65.11 102.87 65.11 102.87 0.17 0.17 0.17 0.17 65.11 18.57 65.11 18.57 81.43 ; LAYER mcon ; RECT 84.325 81.515 84.495 81.685 ; RECT 83.865 81.515 84.035 81.685 ; @@ -2459,141 +2428,37 @@ MACRO sb_1__0_ LAYER via ; RECT 73.525 81.525 73.675 81.675 ; RECT 44.085 81.525 44.235 81.675 ; - RECT 69.385 79.825 69.535 79.975 ; - RECT 66.625 79.825 66.775 79.975 ; - RECT 50.985 79.825 51.135 79.975 ; - RECT 20.625 79.825 20.775 79.975 ; + RECT 71.685 79.825 71.835 79.975 ; + RECT 68.005 79.825 68.155 79.975 ; RECT 73.525 65.205 73.675 65.355 ; RECT 44.085 65.205 44.235 65.355 ; - RECT 96.985 63.505 97.135 63.655 ; - RECT 94.685 63.505 94.835 63.655 ; + RECT 3.145 63.505 3.295 63.655 ; RECT 100.665 1.625 100.815 1.775 ; + RECT 98.825 1.625 98.975 1.775 ; RECT 73.525 -0.075 73.675 0.075 ; RECT 44.085 -0.075 44.235 0.075 ; LAYER via2 ; RECT 73.5 81.5 73.7 81.7 ; RECT 44.06 81.5 44.26 81.7 ; - RECT 101.56 61.78 101.76 61.98 ; - RECT 101.56 52.94 101.76 53.14 ; - RECT 1.74 46.14 1.94 46.34 ; - RECT 1.74 40.02 1.94 40.22 ; - RECT 1.74 24.38 1.94 24.58 ; - RECT 1.28 23.02 1.48 23.22 ; - RECT 101.1 20.3 101.3 20.5 ; - RECT 1.74 20.3 1.94 20.5 ; - RECT 101.56 13.5 101.76 13.7 ; - RECT 1.28 12.14 1.48 12.34 ; + RECT 1.28 59.74 1.48 59.94 ; + RECT 101.1 59.06 101.3 59.26 ; + RECT 1.28 44.1 1.48 44.3 ; + RECT 1.74 42.74 1.94 42.94 ; + RECT 1.28 34.58 1.48 34.78 ; + RECT 101.1 33.9 101.3 34.1 ; + RECT 1.74 25.74 1.94 25.94 ; + RECT 1.74 17.58 1.94 17.78 ; + RECT 101.56 16.22 101.76 16.42 ; + RECT 1.28 10.78 1.48 10.98 ; + RECT 1.28 5.34 1.48 5.54 ; RECT 73.5 -0.1 73.7 0.1 ; RECT 44.06 -0.1 44.26 0.1 ; LAYER via3 ; RECT 73.5 81.5 73.7 81.7 ; RECT 44.06 81.5 44.26 81.7 ; - RECT 1.74 38.66 1.94 38.86 ; - RECT 1.74 16.22 1.94 16.42 ; + RECT 1.74 20.3 1.94 20.5 ; RECT 73.5 -0.1 73.7 0.1 ; RECT 44.06 -0.1 44.26 0.1 ; - LAYER fieldpoly ; - POLYGON 84.5 81.46 84.5 65.14 102.9 65.14 102.9 0.14 0.14 0.14 0.14 65.14 18.54 65.14 18.54 81.46 ; - LAYER diff ; - POLYGON 84.64 81.6 84.64 65.28 103.04 65.28 103.04 0 0 0 0 65.28 18.4 65.28 18.4 81.6 ; - LAYER nwell ; - POLYGON 84.83 80.295 84.83 77.465 83.53 77.465 83.53 79.07 83.99 79.07 83.99 80.295 ; - RECT 18.21 77.465 22.27 80.295 ; - POLYGON 84.83 74.855 84.83 72.025 83.99 72.025 83.99 73.25 83.53 73.25 83.53 74.855 ; - POLYGON 20.43 74.855 20.43 73.63 22.27 73.63 22.27 72.025 18.21 72.025 18.21 74.855 ; - POLYGON 84.83 69.415 84.83 66.585 83.53 66.585 83.53 67.81 80.77 67.81 80.77 69.415 ; - RECT 18.21 66.585 20.43 69.415 ; - POLYGON 103.23 63.975 103.23 61.145 101.93 61.145 101.93 62.75 102.39 62.75 102.39 63.975 ; - POLYGON 3.87 63.975 3.87 62.37 2.03 62.37 2.03 61.145 -0.19 61.145 -0.19 63.975 ; - POLYGON 103.23 58.535 103.23 55.705 102.39 55.705 102.39 56.93 101.93 56.93 101.93 58.535 ; - RECT -0.19 55.705 2.03 58.535 ; - RECT 101.93 50.265 103.23 53.095 ; - RECT -0.19 50.265 2.03 53.095 ; - POLYGON 103.23 47.655 103.23 44.825 102.39 44.825 102.39 46.05 101.93 46.05 101.93 47.655 ; - RECT -0.19 44.825 2.03 47.655 ; - POLYGON 103.23 42.215 103.23 39.385 102.39 39.385 102.39 40.61 101.93 40.61 101.93 42.215 ; - RECT -0.19 39.385 2.03 42.215 ; - POLYGON 103.23 36.775 103.23 33.945 102.39 33.945 102.39 35.17 101.93 35.17 101.93 36.775 ; - RECT -0.19 33.945 2.03 36.775 ; - RECT 101.93 28.505 103.23 31.335 ; - RECT -0.19 28.505 2.03 31.335 ; - RECT 101.93 23.065 103.23 25.895 ; - RECT -0.19 23.065 2.03 25.895 ; - POLYGON 103.23 20.455 103.23 17.625 102.39 17.625 102.39 18.85 101.93 18.85 101.93 20.455 ; - POLYGON 3.87 20.455 3.87 18.85 2.03 18.85 2.03 17.625 -0.19 17.625 -0.19 20.455 ; - POLYGON 103.23 15.015 103.23 12.185 102.39 12.185 102.39 13.41 101.93 13.41 101.93 15.015 ; - RECT -0.19 12.185 2.03 15.015 ; - POLYGON 103.23 9.575 103.23 6.745 102.39 6.745 102.39 7.97 101.93 7.97 101.93 9.575 ; - RECT -0.19 6.745 2.03 9.575 ; - POLYGON 103.23 4.135 103.23 1.305 102.39 1.305 102.39 2.53 101.93 2.53 101.93 4.135 ; - RECT -0.19 1.305 3.87 4.135 ; - POLYGON 84.64 81.6 84.64 65.28 103.04 65.28 103.04 0 0 0 0 65.28 18.4 65.28 18.4 81.6 ; - LAYER pwell ; - RECT 77.87 81.55 78.09 81.72 ; - RECT 74.19 81.55 74.41 81.72 ; - RECT 70.51 81.55 70.73 81.72 ; - RECT 66.83 81.55 67.05 81.72 ; - RECT 63.15 81.55 63.37 81.72 ; - RECT 59.47 81.55 59.69 81.72 ; - RECT 55.79 81.55 56.01 81.72 ; - RECT 52.11 81.55 52.33 81.72 ; - RECT 48.43 81.55 48.65 81.72 ; - RECT 40.61 81.55 40.83 81.72 ; - RECT 36.93 81.55 37.15 81.72 ; - RECT 33.25 81.55 33.47 81.72 ; - RECT 29.57 81.55 29.79 81.72 ; - RECT 25.89 81.55 26.11 81.72 ; - RECT 22.21 81.55 22.43 81.72 ; - RECT 18.53 81.55 18.75 81.72 ; - RECT 81.595 81.54 81.705 81.66 ; - RECT 44.335 81.54 44.445 81.66 ; - RECT 84.32 81.545 84.44 81.655 ; - RECT 47.06 81.545 47.18 81.655 ; - RECT 83.415 81.54 83.575 81.65 ; - RECT 46.155 81.54 46.315 81.65 ; - RECT 97.19 65.23 97.41 65.4 ; - RECT 91.67 65.23 91.89 65.4 ; - RECT 87.99 65.23 88.21 65.4 ; - RECT 14.85 65.23 15.07 65.4 ; - RECT 11.17 65.23 11.39 65.4 ; - RECT 7.49 65.23 7.71 65.4 ; - RECT 3.81 65.23 4.03 65.4 ; - RECT 0.13 65.23 0.35 65.4 ; - RECT 100.915 65.22 101.025 65.34 ; - RECT 102.72 65.225 102.84 65.335 ; - RECT 95.375 65.22 95.535 65.33 ; - RECT 100.915 -0.06 101.025 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 102.72 -0.055 102.84 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 97.19 -0.12 97.41 0.05 ; - RECT 92.59 -0.12 92.81 0.05 ; - RECT 88.91 -0.12 89.13 0.05 ; - RECT 85.23 -0.12 85.45 0.05 ; - RECT 81.55 -0.12 81.77 0.05 ; - RECT 77.87 -0.12 78.09 0.05 ; - RECT 74.19 -0.12 74.41 0.05 ; - RECT 70.51 -0.12 70.73 0.05 ; - RECT 66.83 -0.12 67.05 0.05 ; - RECT 63.15 -0.12 63.37 0.05 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - RECT 14.85 -0.12 15.07 0.05 ; - RECT 11.17 -0.12 11.39 0.05 ; - RECT 7.49 -0.12 7.71 0.05 ; - RECT 3.81 -0.12 4.03 0.05 ; - RECT 0.13 -0.12 0.35 0.05 ; - POLYGON 84.64 81.6 84.64 65.28 103.04 65.28 103.04 0 0 0 0 65.28 18.4 65.28 18.4 81.6 ; LAYER OVERLAP ; POLYGON 0 0 0 65.28 18.4 65.28 18.4 81.6 84.64 81.6 84.64 65.28 103.04 65.28 103.04 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef index 52f19e5..fdd0622 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -375,7 +363,7 @@ MACRO sb_1__1_ USE CLOCK ; PORT LAYER met2 ; - RECT 2.23 16.32 2.37 17.68 ; + RECT 2.23 80.24 2.37 81.6 ; END END prog_clk[0] PIN chany_top_in[0] @@ -383,7 +371,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 96.56 65.85 97.92 ; + RECT 72.61 96.56 72.75 97.92 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -391,15 +379,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 96.56 42.39 97.92 ; + RECT 53.29 96.56 53.43 97.92 ; END END chany_top_in[1] PIN chany_top_in[2] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 55.97 96.56 56.27 97.92 ; + LAYER met2 ; + RECT 52.37 96.56 52.51 97.92 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -407,7 +395,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 96.56 52.05 97.92 ; + RECT 69.85 96.56 69.99 97.92 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -415,7 +403,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 49.53 96.56 49.83 97.92 ; + RECT 60.57 96.56 60.87 97.92 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -423,7 +411,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 96.56 50.21 97.92 ; + RECT 47.31 96.56 47.45 97.92 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -431,7 +419,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 96.56 55.27 97.92 ; + RECT 76.29 96.56 76.43 97.92 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -439,7 +427,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 96.56 59.41 97.92 ; + RECT 65.71 96.56 65.85 97.92 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -455,7 +443,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 96.56 58.03 97.92 ; + RECT 39.95 96.56 40.09 97.92 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -463,7 +451,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 53.21 96.56 53.51 97.92 ; + RECT 55.97 96.56 56.27 97.92 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -471,15 +459,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 96.56 49.29 97.92 ; + RECT 70.77 96.56 70.91 97.92 ; END END chany_top_in[11] PIN chany_top_in[12] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 47.69 96.56 47.99 97.92 ; + LAYER met2 ; + RECT 75.37 96.56 75.51 97.92 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -487,7 +475,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 96.56 45.15 97.92 ; + RECT 68.93 96.56 69.07 97.92 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -503,7 +491,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 96.56 51.13 97.92 ; + RECT 39.03 96.56 39.17 97.92 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -511,7 +499,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 51.37 96.56 51.67 97.92 ; + RECT 62.41 96.56 62.71 97.92 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -519,15 +507,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 96.56 41.47 97.92 ; + RECT 58.35 96.56 58.49 97.92 ; END END chany_top_in[17] PIN chany_top_in[18] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 39.41 96.56 39.71 97.92 ; + LAYER met2 ; + RECT 55.13 96.56 55.27 97.92 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -535,79 +523,79 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 96.56 39.63 97.92 ; + RECT 56.97 96.56 57.11 97.92 ; END END chany_top_in[19] - PIN top_left_grid_pin_34_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 22.85 96.56 23.15 97.92 ; - END - END top_left_grid_pin_34_[0] - PIN top_left_grid_pin_35_[0] + PIN top_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; RECT 24.31 96.56 24.45 97.92 ; END - END top_left_grid_pin_35_[0] - PIN top_left_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.47 96.56 22.61 97.92 ; - END - END top_left_grid_pin_36_[0] - PIN top_left_grid_pin_37_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 2.69 80.24 2.83 81.6 ; - END - END top_left_grid_pin_37_[0] - PIN top_left_grid_pin_38_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 21.55 96.56 21.69 97.92 ; - END - END top_left_grid_pin_38_[0] - PIN top_left_grid_pin_39_[0] + END top_left_grid_pin_42_[0] + PIN top_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; RECT 23.39 96.56 23.53 97.92 ; END - END top_left_grid_pin_39_[0] - PIN top_left_grid_pin_40_[0] + END top_left_grid_pin_43_[0] + PIN top_left_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 22.85 96.56 23.15 97.92 ; + END + END top_left_grid_pin_44_[0] + PIN top_left_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.47 96.56 22.61 97.92 ; + END + END top_left_grid_pin_45_[0] + PIN top_left_grid_pin_46_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; RECT 20.63 96.56 20.77 97.92 ; END - END top_left_grid_pin_40_[0] - PIN top_left_grid_pin_41_[0] + END top_left_grid_pin_46_[0] + PIN top_left_grid_pin_47_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 80.24 7.89 81.6 ; + RECT 8.67 80.24 8.81 81.6 ; END - END top_left_grid_pin_41_[0] + END top_left_grid_pin_47_[0] + PIN top_left_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.55 96.56 21.69 97.92 ; + END + END top_left_grid_pin_48_[0] + PIN top_left_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 24.69 96.56 24.99 97.92 ; + END + END top_left_grid_pin_49_[0] PIN chanx_right_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 35.89 103.04 36.19 ; + RECT 101.66 34.53 103.04 34.83 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -615,7 +603,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 78.05 103.04 78.35 ; + RECT 101.66 22.97 103.04 23.27 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -623,7 +611,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 26.37 103.04 26.67 ; + RECT 101.66 46.09 103.04 46.39 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -631,7 +619,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 75.33 103.04 75.63 ; + RECT 101.66 20.25 103.04 20.55 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -639,7 +627,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 76.69 103.04 76.99 ; + RECT 101.66 68.53 103.04 68.83 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -647,7 +635,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 72.61 103.04 72.91 ; + RECT 101.66 67.17 103.04 67.47 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -655,7 +643,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 37.25 103.04 37.55 ; + RECT 101.66 39.97 103.04 40.27 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -663,7 +651,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 51.53 103.04 51.83 ; + RECT 101.66 37.25 103.04 37.55 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -671,7 +659,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 38.61 103.04 38.91 ; + RECT 101.66 41.33 103.04 41.63 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -679,7 +667,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 46.77 103.04 47.07 ; + RECT 101.66 61.05 103.04 61.35 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -687,7 +675,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 34.53 103.04 34.83 ; + RECT 101.66 21.61 103.04 21.91 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -695,7 +683,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 73.97 103.04 74.27 ; + RECT 101.66 55.61 103.04 55.91 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -703,7 +691,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 31.81 103.04 32.11 ; + RECT 101.66 62.41 103.04 62.71 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -711,7 +699,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 71.25 103.04 71.55 ; + RECT 101.66 27.05 103.04 27.35 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -719,7 +707,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 54.25 103.04 54.55 ; + RECT 101.66 25.69 103.04 25.99 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -727,7 +715,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 48.81 103.04 49.11 ; + RECT 101.66 28.41 103.04 28.71 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -735,7 +723,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 25.01 103.04 25.31 ; + RECT 101.66 69.89 103.04 70.19 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -743,7 +731,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 20.25 103.04 20.55 ; + RECT 101.66 35.89 103.04 36.19 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -751,7 +739,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 33.17 103.04 33.47 ; + RECT 101.66 56.97 103.04 57.27 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -759,79 +747,79 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 69.89 103.04 70.19 ; + RECT 101.66 29.77 103.04 30.07 ; END END chanx_right_in[19] - PIN right_top_grid_pin_42_[0] + PIN right_bottom_grid_pin_34_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 94.69 80.24 94.83 81.6 ; + RECT 97.91 16.32 98.05 17.68 ; END - END right_top_grid_pin_42_[0] - PIN right_top_grid_pin_43_[0] + END right_bottom_grid_pin_34_[0] + PIN right_bottom_grid_pin_35_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 91.93 80.24 92.07 81.6 ; + RECT 100.67 16.32 100.81 17.68 ; END - END right_top_grid_pin_43_[0] - PIN right_top_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 96.99 80.24 97.13 81.6 ; - END - END right_top_grid_pin_44_[0] - PIN right_top_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 100.21 80.24 100.35 81.6 ; - END - END right_top_grid_pin_45_[0] - PIN right_top_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 99.29 80.24 99.43 81.6 ; - END - END right_top_grid_pin_46_[0] - PIN right_top_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 95.61 80.24 95.75 81.6 ; - END - END right_top_grid_pin_47_[0] - PIN right_top_grid_pin_48_[0] + END right_bottom_grid_pin_35_[0] + PIN right_bottom_grid_pin_36_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; - RECT 98.29 80.24 98.59 81.6 ; + RECT 97.37 16.32 97.67 17.68 ; END - END right_top_grid_pin_48_[0] - PIN right_top_grid_pin_49_[0] + END right_bottom_grid_pin_36_[0] + PIN right_bottom_grid_pin_37_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 98.37 80.24 98.51 81.6 ; + RECT 94.23 16.32 94.37 17.68 ; END - END right_top_grid_pin_49_[0] + END right_bottom_grid_pin_37_[0] + PIN right_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 95.15 16.32 95.29 17.68 ; + END + END right_bottom_grid_pin_38_[0] + PIN right_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 98.83 16.32 98.97 17.68 ; + END + END right_bottom_grid_pin_39_[0] + PIN right_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.53 16.32 96.67 17.68 ; + END + END right_bottom_grid_pin_40_[0] + PIN right_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.27 0 82.41 1.36 ; + END + END right_bottom_grid_pin_41_[0] PIN chany_bottom_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 55.05 0 55.35 1.36 ; + LAYER met2 ; + RECT 50.53 0 50.67 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -839,7 +827,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 57.89 0 58.03 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -847,7 +835,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 0 68.61 1.36 ; + RECT 56.97 0 57.11 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -855,7 +843,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.73 0 59.87 1.36 ; + RECT 62.49 0 62.63 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -863,7 +851,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.39 0 69.53 1.36 ; + RECT 48.69 0 48.83 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -871,7 +859,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -879,7 +867,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 0 70.45 1.36 ; + RECT 77.21 0 77.35 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -887,7 +875,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.65 0 60.79 1.36 ; + RECT 52.37 0 52.51 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -895,7 +883,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 0 67.69 1.36 ; + RECT 61.11 0 61.25 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -903,15 +891,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.57 0 61.71 1.36 ; + RECT 40.41 0 40.55 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 45.85 0 46.15 1.36 ; + LAYER met2 ; + RECT 56.05 0 56.19 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -919,7 +907,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; + RECT 49.61 0 49.75 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -927,7 +915,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + RECT 47.77 0 47.91 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -935,15 +923,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 71.23 0 71.37 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 52.29 0 52.59 1.36 ; + LAYER met2 ; + RECT 75.37 0 75.51 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -951,7 +939,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + RECT 32.59 0 32.73 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -959,7 +947,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 51.45 0 51.59 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -967,7 +955,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 74.45 0 74.59 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -975,7 +963,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; + RECT 76.29 0 76.43 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -983,79 +971,79 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 72.15 0 72.29 1.36 ; + RECT 54.21 0 54.35 1.36 ; END END chany_bottom_in[19] - PIN bottom_left_grid_pin_34_[0] + PIN bottom_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 3.61 16.32 3.75 17.68 ; END - END bottom_left_grid_pin_34_[0] - PIN bottom_left_grid_pin_35_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 22.85 0 23.15 1.36 ; - END - END bottom_left_grid_pin_35_[0] - PIN bottom_left_grid_pin_36_[0] + END bottom_left_grid_pin_42_[0] + PIN bottom_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; RECT 22.47 0 22.61 1.36 ; END - END bottom_left_grid_pin_36_[0] - PIN bottom_left_grid_pin_37_[0] + END bottom_left_grid_pin_43_[0] + PIN bottom_left_grid_pin_44_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 16.32 11.11 17.68 ; + RECT 6.37 16.32 6.51 17.68 ; END - END bottom_left_grid_pin_37_[0] - PIN bottom_left_grid_pin_38_[0] + END bottom_left_grid_pin_44_[0] + PIN bottom_left_grid_pin_45_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 0 21.69 1.36 ; + RECT 4.53 16.32 4.67 17.68 ; END - END bottom_left_grid_pin_38_[0] - PIN bottom_left_grid_pin_39_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.67 16.32 8.81 17.68 ; - END - END bottom_left_grid_pin_39_[0] - PIN bottom_left_grid_pin_40_[0] + END bottom_left_grid_pin_45_[0] + PIN bottom_left_grid_pin_46_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; RECT 18.4 6.65 19.78 6.95 ; END - END bottom_left_grid_pin_40_[0] - PIN bottom_left_grid_pin_41_[0] + END bottom_left_grid_pin_46_[0] + PIN bottom_left_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 16.32 2.37 17.68 ; + END + END bottom_left_grid_pin_47_[0] + PIN bottom_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; RECT 18.4 5.29 19.78 5.59 ; END - END bottom_left_grid_pin_41_[0] + END bottom_left_grid_pin_48_[0] + PIN bottom_left_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 18.4 8.01 19.78 8.31 ; + END + END bottom_left_grid_pin_49_[0] PIN chanx_left_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -1063,7 +1051,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 78.05 1.38 78.35 ; + RECT 0 23.65 1.38 23.95 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -1071,7 +1059,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 42.69 1.38 42.99 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -1079,7 +1067,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 75.33 1.38 75.63 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -1087,15 +1075,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; + RECT 0 35.89 1.38 36.19 ; END END chanx_left_in[4] PIN chanx_left_in[5] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 3.61 16.32 3.75 17.68 ; + LAYER met3 ; + RECT 0 30.45 1.38 30.75 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -1103,7 +1091,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.01 1.38 25.31 ; + RECT 0 22.29 1.38 22.59 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -1111,7 +1099,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; + RECT 0 65.81 1.38 66.11 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -1119,7 +1107,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; + RECT 0 69.89 1.38 70.19 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -1127,7 +1115,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.69 1.38 76.99 ; + RECT 0 61.05 1.38 61.35 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -1135,7 +1123,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 41.33 1.38 41.63 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -1143,7 +1131,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -1151,7 +1139,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.77 1.38 47.07 ; + RECT 0 64.45 1.38 64.75 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -1159,7 +1147,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 55.61 1.38 55.91 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -1167,7 +1155,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 77.37 1.38 77.67 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -1175,7 +1163,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 49.49 1.38 49.79 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -1183,7 +1171,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -1191,7 +1179,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 74.65 1.38 74.95 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -1199,7 +1187,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.13 1.38 48.43 ; + RECT 0 76.01 1.38 76.31 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -1207,79 +1195,79 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; + RECT 0 29.09 1.38 29.39 ; END END chanx_left_in[19] - PIN left_top_grid_pin_42_[0] + PIN left_bottom_grid_pin_34_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; - RECT 24.69 96.56 24.99 97.92 ; + RECT 6.29 16.32 6.59 17.68 ; END - END left_top_grid_pin_42_[0] - PIN left_top_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 5.45 80.24 5.59 81.6 ; - END - END left_top_grid_pin_43_[0] - PIN left_top_grid_pin_44_[0] + END left_bottom_grid_pin_34_[0] + PIN left_bottom_grid_pin_35_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; - RECT 4.45 80.24 4.75 81.6 ; + RECT 4.45 16.32 4.75 17.68 ; END - END left_top_grid_pin_44_[0] - PIN left_top_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 6.29 80.24 6.59 81.6 ; - END - END left_top_grid_pin_45_[0] - PIN left_top_grid_pin_46_[0] + END left_bottom_grid_pin_35_[0] + PIN left_bottom_grid_pin_36_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 3.61 80.24 3.75 81.6 ; + RECT 8.67 16.32 8.81 17.68 ; END - END left_top_grid_pin_46_[0] - PIN left_top_grid_pin_47_[0] + END left_bottom_grid_pin_36_[0] + PIN left_bottom_grid_pin_37_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 6.37 80.24 6.51 81.6 ; + RECT 5.45 16.32 5.59 17.68 ; END - END left_top_grid_pin_47_[0] - PIN left_top_grid_pin_48_[0] + END left_bottom_grid_pin_37_[0] + PIN left_bottom_grid_pin_38_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 8.67 80.24 8.81 81.6 ; + RECT 20.63 0 20.77 1.36 ; END - END left_top_grid_pin_48_[0] - PIN left_top_grid_pin_49_[0] + END left_bottom_grid_pin_38_[0] + PIN left_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 19.57 1.38 19.87 ; + END + END left_bottom_grid_pin_39_[0] + PIN left_bottom_grid_pin_40_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 4.53 80.24 4.67 81.6 ; + RECT 21.55 0 21.69 1.36 ; END - END left_top_grid_pin_49_[0] + END left_bottom_grid_pin_40_[0] + PIN left_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.75 16.32 7.89 17.68 ; + END + END left_bottom_grid_pin_41_[0] PIN ccff_head[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 58.33 103.04 58.63 ; + RECT 101.66 73.97 103.04 74.27 ; END END ccff_head[0] PIN chany_top_out[0] @@ -1287,7 +1275,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 96.56 66.77 97.92 ; + RECT 49.61 96.56 49.75 97.92 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -1295,7 +1283,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 96.56 40.55 97.92 ; + RECT 51.45 96.56 51.59 97.92 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -1303,7 +1291,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 96.56 64.93 97.92 ; + RECT 45.47 96.56 45.61 97.92 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -1311,7 +1299,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 96.56 38.71 97.92 ; + RECT 63.87 96.56 64.01 97.92 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -1319,7 +1307,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.39 96.56 69.53 97.92 ; + RECT 59.27 96.56 59.41 97.92 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -1327,7 +1315,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 96.56 57.11 97.92 ; + RECT 68.01 96.56 68.15 97.92 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -1335,7 +1323,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 96.56 68.61 97.92 ; + RECT 50.53 96.56 50.67 97.92 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -1343,7 +1331,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 96.56 53.43 97.92 ; + RECT 61.11 96.56 61.25 97.92 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -1351,7 +1339,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 96.56 67.69 97.92 ; + RECT 43.17 96.56 43.31 97.92 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -1359,7 +1347,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 96.56 43.31 97.92 ; + RECT 60.19 96.56 60.33 97.92 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -1367,7 +1355,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 96.56 70.45 97.92 ; + RECT 48.23 96.56 48.37 97.92 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -1375,7 +1363,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 96.56 48.37 97.92 ; + RECT 71.69 96.56 71.83 97.92 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -1383,7 +1371,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 96.56 71.37 97.92 ; + RECT 74.45 96.56 74.59 97.92 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -1391,7 +1379,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 96.56 27.67 97.92 ; + RECT 62.49 96.56 62.63 97.92 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -1399,7 +1387,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 96.56 60.33 97.92 ; + RECT 40.87 96.56 41.01 97.92 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -1407,7 +1395,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 96.56 46.07 97.92 ; + RECT 64.79 96.56 64.93 97.92 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -1415,15 +1403,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 96.56 61.25 97.92 ; + RECT 42.25 96.56 42.39 97.92 ; END END chany_top_out[16] PIN chany_top_out[17] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 41.25 96.56 41.55 97.92 ; + LAYER met2 ; + RECT 66.63 96.56 66.77 97.92 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1431,7 +1419,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 96.56 37.79 97.92 ; + RECT 46.39 96.56 46.53 97.92 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1439,7 +1427,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 96.56 46.99 97.92 ; + RECT 77.67 96.56 77.81 97.92 ; END END chany_top_out[19] PIN chanx_right_out[0] @@ -1447,7 +1435,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 50.17 103.04 50.47 ; + RECT 101.66 24.33 103.04 24.63 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -1455,7 +1443,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 67.17 103.04 67.47 ; + RECT 101.66 33.17 103.04 33.47 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -1463,7 +1451,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 27.73 103.04 28.03 ; + RECT 101.66 42.69 103.04 42.99 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -1471,7 +1459,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 68.53 103.04 68.83 ; + RECT 101.66 52.89 103.04 53.19 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -1479,7 +1467,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 42.69 103.04 42.99 ; + RECT 101.66 59.69 103.04 59.99 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -1487,7 +1475,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 61.05 103.04 61.35 ; + RECT 101.66 64.45 103.04 64.75 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -1495,7 +1483,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 29.09 103.04 29.39 ; + RECT 101.66 50.85 103.04 51.15 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -1503,7 +1491,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 55.61 103.04 55.91 ; + RECT 101.66 58.33 103.04 58.63 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1511,7 +1499,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 39.97 103.04 40.27 ; + RECT 101.66 76.69 103.04 76.99 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1519,7 +1507,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 59.69 103.04 59.99 ; + RECT 101.66 71.25 103.04 71.55 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1527,7 +1515,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 44.73 103.04 45.03 ; + RECT 101.66 47.45 103.04 47.75 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1535,7 +1523,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 56.97 103.04 57.27 ; + RECT 101.66 49.49 103.04 49.79 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1543,7 +1531,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 30.45 103.04 30.75 ; + RECT 101.66 75.33 103.04 75.63 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1551,7 +1539,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 52.89 103.04 53.19 ; + RECT 101.66 78.05 103.04 78.35 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1559,7 +1547,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 22.97 103.04 23.27 ; + RECT 101.66 31.81 103.04 32.11 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1567,7 +1555,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 62.41 103.04 62.71 ; + RECT 101.66 72.61 103.04 72.91 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -1575,7 +1563,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 21.61 103.04 21.91 ; + RECT 101.66 44.73 103.04 45.03 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1583,7 +1571,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 65.13 103.04 65.43 ; + RECT 101.66 38.61 103.04 38.91 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1591,7 +1579,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 41.33 103.04 41.63 ; + RECT 101.66 54.25 103.04 54.55 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1599,7 +1587,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 63.77 103.04 64.07 ; + RECT 101.66 65.81 103.04 66.11 ; END END chanx_right_out[19] PIN chany_bottom_out[0] @@ -1607,7 +1595,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + RECT 72.15 0 72.29 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -1615,7 +1603,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 55.13 0 55.27 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -1623,7 +1611,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 46.85 0 46.99 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -1631,7 +1619,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; + RECT 63.41 0 63.55 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -1639,7 +1627,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 0 66.77 1.36 ; + RECT 45.93 0 46.07 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -1647,7 +1635,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + RECT 70.31 0 70.45 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -1655,7 +1643,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; + RECT 33.51 0 33.65 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -1663,7 +1651,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; + RECT 64.79 0 64.93 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1671,7 +1659,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 0 65.85 1.36 ; + RECT 59.27 0 59.41 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -1679,7 +1667,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 65.71 0 65.85 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1687,7 +1675,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; + RECT 43.17 0 43.31 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -1695,15 +1683,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; + RECT 66.63 0 66.77 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 56.89 0 57.19 1.36 ; + LAYER met2 ; + RECT 39.49 0 39.63 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -1711,7 +1699,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + RECT 67.55 0 67.69 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -1719,7 +1707,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 0 64.93 1.36 ; + RECT 42.25 0 42.39 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -1727,7 +1715,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 80.89 0 81.03 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1735,7 +1723,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 0 71.37 1.36 ; + RECT 41.33 0 41.47 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -1743,7 +1731,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 68.47 0 68.61 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -1751,7 +1739,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; + RECT 45.01 0 45.15 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -1759,7 +1747,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 69.39 0 69.53 1.36 ; END END chany_bottom_out[19] PIN chanx_left_out[0] @@ -1767,7 +1755,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; + RECT 0 45.41 1.38 45.71 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1775,7 +1763,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; + RECT 0 56.97 1.38 57.27 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -1783,7 +1771,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; + RECT 0 71.25 1.38 71.55 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1791,7 +1779,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; + RECT 0 27.73 1.38 28.03 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1799,7 +1787,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1807,7 +1795,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 46.77 1.38 47.07 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1815,7 +1803,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; + RECT 0 38.61 1.38 38.91 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1823,7 +1811,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 54.25 1.38 54.55 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1831,7 +1819,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; + RECT 0 44.05 1.38 44.35 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -1839,7 +1827,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1847,7 +1835,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 67.17 1.38 67.47 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1855,7 +1843,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1863,7 +1851,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; + RECT 0 26.37 1.38 26.67 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1871,7 +1859,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; + RECT 0 20.93 1.38 21.23 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1879,7 +1867,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 23.65 1.38 23.95 ; + RECT 0 25.01 1.38 25.31 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1887,7 +1875,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1895,7 +1883,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; + RECT 0 59.69 1.38 59.99 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1903,7 +1891,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.97 1.38 74.27 ; + RECT 0 37.25 1.38 37.55 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1911,7 +1899,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 31.81 1.38 32.11 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1919,7 +1907,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 68.53 1.38 68.83 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1927,7 +1915,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; + RECT 0 63.09 1.38 63.39 ; END END ccff_tail[0] PIN VDD @@ -2038,13 +2026,13 @@ MACRO sb_1__1_ RECT 83.72 95.115 84.64 95.285 ; RECT 18.4 95.115 22.08 95.285 ; RECT 83.72 92.395 84.64 92.565 ; - RECT 18.4 92.395 20.24 92.565 ; + RECT 18.4 92.395 22.08 92.565 ; RECT 83.72 89.675 84.64 89.845 ; RECT 18.4 89.675 20.24 89.845 ; - RECT 84.18 86.955 84.64 87.125 ; - RECT 18.4 86.955 20.24 87.125 ; + RECT 83.72 86.955 84.64 87.125 ; + RECT 18.4 86.955 22.08 87.125 ; RECT 83.72 84.235 84.64 84.405 ; - RECT 18.4 84.235 20.24 84.405 ; + RECT 18.4 84.235 22.08 84.405 ; RECT 81.88 81.515 103.04 81.685 ; RECT 0 81.515 20.24 81.685 ; RECT 102.58 78.795 103.04 78.965 ; @@ -2052,9 +2040,9 @@ MACRO sb_1__1_ RECT 102.12 76.075 103.04 76.245 ; RECT 0 76.075 1.84 76.245 ; RECT 102.12 73.355 103.04 73.525 ; - RECT 0 73.355 1.84 73.525 ; + RECT 0 73.355 3.68 73.525 ; RECT 102.12 70.635 103.04 70.805 ; - RECT 0 70.635 1.84 70.805 ; + RECT 0 70.635 3.68 70.805 ; RECT 102.12 67.915 103.04 68.085 ; RECT 0 67.915 1.84 68.085 ; RECT 102.12 65.195 103.04 65.365 ; @@ -2070,9 +2058,9 @@ MACRO sb_1__1_ RECT 102.12 51.595 103.04 51.765 ; RECT 0 51.595 1.84 51.765 ; RECT 102.12 48.875 103.04 49.045 ; - RECT 0 48.875 3.68 49.045 ; + RECT 0 48.875 1.84 49.045 ; RECT 102.12 46.155 103.04 46.325 ; - RECT 0 46.155 3.68 46.325 ; + RECT 0 46.155 1.84 46.325 ; RECT 102.12 43.435 103.04 43.605 ; RECT 0 43.435 1.84 43.605 ; RECT 102.12 40.715 103.04 40.885 ; @@ -2083,22 +2071,22 @@ MACRO sb_1__1_ RECT 0 35.275 1.84 35.445 ; RECT 102.12 32.555 103.04 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 102.12 29.835 103.04 30.005 ; - RECT 0 29.835 3.68 30.005 ; - RECT 102.12 27.115 103.04 27.285 ; - RECT 0 27.115 3.68 27.285 ; + RECT 99.36 29.835 103.04 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 99.36 27.115 103.04 27.285 ; + RECT 0 27.115 1.84 27.285 ; RECT 102.12 24.395 103.04 24.565 ; RECT 0 24.395 1.84 24.565 ; RECT 102.12 21.675 103.04 21.845 ; - RECT 0 21.675 1.84 21.845 ; + RECT 0 21.675 3.68 21.845 ; RECT 102.12 18.955 103.04 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 80.96 16.235 103.04 16.405 ; - RECT 0 16.235 20.24 16.405 ; + RECT 81.88 16.235 103.04 16.405 ; + RECT 0 16.235 22.08 16.405 ; RECT 83.72 13.515 84.64 13.685 ; - RECT 18.4 13.515 22.08 13.685 ; + RECT 18.4 13.515 20.24 13.685 ; RECT 83.72 10.795 84.64 10.965 ; - RECT 18.4 10.795 22.08 10.965 ; + RECT 18.4 10.795 20.24 10.965 ; RECT 83.72 8.075 84.64 8.245 ; RECT 18.4 8.075 20.24 8.245 ; RECT 83.72 5.355 84.64 5.525 ; @@ -2109,43 +2097,40 @@ MACRO sb_1__1_ LAYER met2 ; RECT 73.46 97.735 73.74 98.105 ; RECT 44.02 97.735 44.3 98.105 ; - RECT 54.61 96.06 54.87 96.38 ; - RECT 49.55 96.06 49.81 96.38 ; - RECT 97.39 79.74 97.65 80.06 ; - RECT 57.83 1.54 58.09 1.86 ; - RECT 42.65 1.54 42.91 1.86 ; + POLYGON 21.23 96.63 21.23 96.38 21.29 96.38 21.29 96.06 21.03 96.06 21.03 96.28 21.05 96.28 21.05 96.63 ; + RECT 73.01 96.06 73.27 96.38 ; + RECT 60.59 96.06 60.85 96.38 ; + RECT 96.93 17.86 97.19 18.18 ; + RECT 75.77 1.54 76.03 1.86 ; + RECT 61.51 1.54 61.77 1.86 ; RECT 73.46 -0.185 73.74 0.185 ; RECT 44.02 -0.185 44.3 0.185 ; - POLYGON 84.36 97.64 84.36 81.32 91.65 81.32 91.65 79.96 92.35 79.96 92.35 81.32 94.41 81.32 94.41 79.96 95.11 79.96 95.11 81.32 95.33 81.32 95.33 79.96 96.03 79.96 96.03 81.32 96.71 81.32 96.71 79.96 97.41 79.96 97.41 81.32 98.09 81.32 98.09 79.96 98.79 79.96 98.79 81.32 99.01 81.32 99.01 79.96 99.71 79.96 99.71 81.32 99.93 81.32 99.93 79.96 100.63 79.96 100.63 81.32 102.76 81.32 102.76 16.6 84.36 16.6 84.36 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 18.68 0.28 18.68 16.6 11.39 16.6 11.39 17.96 10.69 17.96 10.69 16.6 9.09 16.6 9.09 17.96 8.39 17.96 8.39 16.6 4.03 16.6 4.03 17.96 3.33 17.96 3.33 16.6 2.65 16.6 2.65 17.96 1.95 17.96 1.95 16.6 0.28 16.6 0.28 81.32 2.41 81.32 2.41 79.96 3.11 79.96 3.11 81.32 3.33 81.32 3.33 79.96 4.03 79.96 4.03 81.32 4.25 81.32 4.25 79.96 4.95 79.96 4.95 81.32 5.17 81.32 5.17 79.96 5.87 79.96 5.87 81.32 6.09 81.32 6.09 79.96 6.79 79.96 6.79 81.32 7.47 81.32 7.47 79.96 8.17 79.96 8.17 81.32 8.39 81.32 8.39 79.96 9.09 79.96 9.09 81.32 18.68 81.32 18.68 97.64 20.35 97.64 20.35 96.28 21.05 96.28 21.05 97.64 21.27 97.64 21.27 96.28 21.97 96.28 21.97 97.64 22.19 97.64 22.19 96.28 22.89 96.28 22.89 97.64 23.11 97.64 23.11 96.28 23.81 96.28 23.81 97.64 24.03 97.64 24.03 96.28 24.73 96.28 24.73 97.64 27.25 97.64 27.25 96.28 27.95 96.28 27.95 97.64 37.37 97.64 37.37 96.28 38.07 96.28 38.07 97.64 38.29 97.64 38.29 96.28 38.99 96.28 38.99 97.64 39.21 97.64 39.21 96.28 39.91 96.28 39.91 97.64 40.13 97.64 40.13 96.28 40.83 96.28 40.83 97.64 41.05 97.64 41.05 96.28 41.75 96.28 41.75 97.64 41.97 97.64 41.97 96.28 42.67 96.28 42.67 97.64 42.89 97.64 42.89 96.28 43.59 96.28 43.59 97.64 44.73 97.64 44.73 96.28 45.43 96.28 45.43 97.64 45.65 97.64 45.65 96.28 46.35 96.28 46.35 97.64 46.57 97.64 46.57 96.28 47.27 96.28 47.27 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 48.87 97.64 48.87 96.28 49.57 96.28 49.57 97.64 49.79 97.64 49.79 96.28 50.49 96.28 50.49 97.64 50.71 97.64 50.71 96.28 51.41 96.28 51.41 97.64 51.63 97.64 51.63 96.28 52.33 96.28 52.33 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 53.93 97.64 53.93 96.28 54.63 96.28 54.63 97.64 54.85 97.64 54.85 96.28 55.55 96.28 55.55 97.64 55.77 97.64 55.77 96.28 56.47 96.28 56.47 97.64 56.69 97.64 56.69 96.28 57.39 96.28 57.39 97.64 57.61 97.64 57.61 96.28 58.31 96.28 58.31 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 60.83 97.64 60.83 96.28 61.53 96.28 61.53 97.64 64.51 97.64 64.51 96.28 65.21 96.28 65.21 97.64 65.43 97.64 65.43 96.28 66.13 96.28 66.13 97.64 66.35 97.64 66.35 96.28 67.05 96.28 67.05 97.64 67.27 97.64 67.27 96.28 67.97 96.28 67.97 97.64 68.19 97.64 68.19 96.28 68.89 96.28 68.89 97.64 69.11 97.64 69.11 96.28 69.81 96.28 69.81 97.64 70.03 97.64 70.03 96.28 70.73 96.28 70.73 97.64 70.95 97.64 70.95 96.28 71.65 96.28 71.65 97.64 ; + POLYGON 84.36 97.64 84.36 81.32 102.76 81.32 102.76 16.6 101.09 16.6 101.09 17.96 100.39 17.96 100.39 16.6 99.25 16.6 99.25 17.96 98.55 17.96 98.55 16.6 98.33 16.6 98.33 17.96 97.63 17.96 97.63 16.6 96.95 16.6 96.95 17.96 96.25 17.96 96.25 16.6 95.57 16.6 95.57 17.96 94.87 17.96 94.87 16.6 94.65 16.6 94.65 17.96 93.95 17.96 93.95 16.6 84.36 16.6 84.36 0.28 82.69 0.28 82.69 1.64 81.99 1.64 81.99 0.28 81.31 0.28 81.31 1.64 80.61 1.64 80.61 0.28 77.63 0.28 77.63 1.64 76.93 1.64 76.93 0.28 76.71 0.28 76.71 1.64 76.01 1.64 76.01 0.28 75.79 0.28 75.79 1.64 75.09 1.64 75.09 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 63.83 0.28 63.83 1.64 63.13 1.64 63.13 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 18.68 0.28 18.68 16.6 9.09 16.6 9.09 17.96 8.39 17.96 8.39 16.6 8.17 16.6 8.17 17.96 7.47 17.96 7.47 16.6 6.79 16.6 6.79 17.96 6.09 17.96 6.09 16.6 5.87 16.6 5.87 17.96 5.17 17.96 5.17 16.6 4.95 16.6 4.95 17.96 4.25 17.96 4.25 16.6 4.03 16.6 4.03 17.96 3.33 17.96 3.33 16.6 2.65 16.6 2.65 17.96 1.95 17.96 1.95 16.6 0.28 16.6 0.28 81.32 1.95 81.32 1.95 79.96 2.65 79.96 2.65 81.32 8.39 81.32 8.39 79.96 9.09 79.96 9.09 81.32 18.68 81.32 18.68 97.64 20.35 97.64 20.35 96.28 21.05 96.28 21.05 97.64 21.27 97.64 21.27 96.28 21.97 96.28 21.97 97.64 22.19 97.64 22.19 96.28 22.89 96.28 22.89 97.64 23.11 97.64 23.11 96.28 23.81 96.28 23.81 97.64 24.03 97.64 24.03 96.28 24.73 96.28 24.73 97.64 38.75 97.64 38.75 96.28 39.45 96.28 39.45 97.64 39.67 97.64 39.67 96.28 40.37 96.28 40.37 97.64 40.59 97.64 40.59 96.28 41.29 96.28 41.29 97.64 41.97 97.64 41.97 96.28 42.67 96.28 42.67 97.64 42.89 97.64 42.89 96.28 43.59 96.28 43.59 97.64 45.19 97.64 45.19 96.28 45.89 96.28 45.89 97.64 46.11 97.64 46.11 96.28 46.81 96.28 46.81 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 49.33 97.64 49.33 96.28 50.03 96.28 50.03 97.64 50.25 97.64 50.25 96.28 50.95 96.28 50.95 97.64 51.17 97.64 51.17 96.28 51.87 96.28 51.87 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 53.93 97.64 53.93 96.28 54.63 96.28 54.63 97.64 54.85 97.64 54.85 96.28 55.55 96.28 55.55 97.64 55.77 97.64 55.77 96.28 56.47 96.28 56.47 97.64 56.69 97.64 56.69 96.28 57.39 96.28 57.39 97.64 58.07 97.64 58.07 96.28 58.77 96.28 58.77 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 60.83 97.64 60.83 96.28 61.53 96.28 61.53 97.64 62.21 97.64 62.21 96.28 62.91 96.28 62.91 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 64.51 97.64 64.51 96.28 65.21 96.28 65.21 97.64 65.43 97.64 65.43 96.28 66.13 96.28 66.13 97.64 66.35 97.64 66.35 96.28 67.05 96.28 67.05 97.64 67.73 97.64 67.73 96.28 68.43 96.28 68.43 97.64 68.65 97.64 68.65 96.28 69.35 96.28 69.35 97.64 69.57 97.64 69.57 96.28 70.27 96.28 70.27 97.64 70.49 97.64 70.49 96.28 71.19 96.28 71.19 97.64 71.41 97.64 71.41 96.28 72.11 96.28 72.11 97.64 72.33 97.64 72.33 96.28 73.03 96.28 73.03 97.64 74.17 97.64 74.17 96.28 74.87 96.28 74.87 97.64 75.09 97.64 75.09 96.28 75.79 96.28 75.79 97.64 76.01 97.64 76.01 96.28 76.71 96.28 76.71 97.64 77.39 97.64 77.39 96.28 78.09 96.28 78.09 97.64 ; LAYER met4 ; - POLYGON 84.24 97.52 84.24 81.2 97.89 81.2 97.89 79.84 98.99 79.84 98.99 81.2 102.64 81.2 102.64 16.72 84.24 16.72 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 57.59 0.4 57.59 1.76 56.49 1.76 56.49 0.4 55.75 0.4 55.75 1.76 54.65 1.76 54.65 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 46.55 0.4 46.55 1.76 45.45 1.76 45.45 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 23.55 0.4 23.55 1.76 22.45 1.76 22.45 0.4 18.8 0.4 18.8 16.72 0.4 16.72 0.4 81.2 4.05 81.2 4.05 79.84 5.15 79.84 5.15 81.2 5.89 81.2 5.89 79.84 6.99 79.84 6.99 81.2 18.8 81.2 18.8 97.52 22.45 97.52 22.45 96.16 23.55 96.16 23.55 97.52 24.29 97.52 24.29 96.16 25.39 96.16 25.39 97.52 28.74 97.52 28.74 96.92 30.14 96.92 30.14 97.52 39.01 97.52 39.01 96.16 40.11 96.16 40.11 97.52 40.85 97.52 40.85 96.16 41.95 96.16 41.95 97.52 43.46 97.52 43.46 96.92 44.86 96.92 44.86 97.52 47.29 97.52 47.29 96.16 48.39 96.16 48.39 97.52 49.13 97.52 49.13 96.16 50.23 96.16 50.23 97.52 50.97 97.52 50.97 96.16 52.07 96.16 52.07 97.52 52.81 97.52 52.81 96.16 53.91 96.16 53.91 97.52 55.57 97.52 55.57 96.16 56.67 96.16 56.67 97.52 58.18 97.52 58.18 96.92 59.58 96.92 59.58 97.52 72.9 97.52 72.9 96.92 74.3 96.92 74.3 97.52 ; + POLYGON 84.24 97.52 84.24 81.2 102.64 81.2 102.64 16.72 98.07 16.72 98.07 18.08 96.97 18.08 96.97 16.72 84.24 16.72 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 18.8 0.4 18.8 16.72 6.99 16.72 6.99 18.08 5.89 18.08 5.89 16.72 5.15 16.72 5.15 18.08 4.05 18.08 4.05 16.72 0.4 16.72 0.4 81.2 18.8 81.2 18.8 97.52 22.45 97.52 22.45 96.16 23.55 96.16 23.55 97.52 24.29 97.52 24.29 96.16 25.39 96.16 25.39 97.52 28.74 97.52 28.74 96.92 30.14 96.92 30.14 97.52 43.46 97.52 43.46 96.92 44.86 96.92 44.86 97.52 55.57 97.52 55.57 96.16 56.67 96.16 56.67 97.52 58.18 97.52 58.18 96.92 59.58 96.92 59.58 97.52 60.17 97.52 60.17 96.16 61.27 96.16 61.27 97.52 62.01 97.52 62.01 96.16 63.11 96.16 63.11 97.52 72.9 97.52 72.9 96.92 74.3 96.92 74.3 97.52 ; LAYER met3 ; POLYGON 73.765 98.085 73.765 98.08 73.98 98.08 73.98 97.76 73.765 97.76 73.765 97.755 73.435 97.755 73.435 97.76 73.22 97.76 73.22 98.08 73.435 98.08 73.435 98.085 ; POLYGON 44.325 98.085 44.325 98.08 44.54 98.08 44.54 97.76 44.325 97.76 44.325 97.755 43.995 97.755 43.995 97.76 43.78 97.76 43.78 98.08 43.995 98.08 43.995 98.085 ; - POLYGON 101.825 73.605 101.825 73.275 101.495 73.275 101.495 73.29 63.33 73.29 63.33 73.59 101.495 73.59 101.495 73.605 ; - POLYGON 2.005 66.125 2.005 66.11 26.83 66.11 26.83 65.81 2.005 65.81 2.005 65.795 1.675 65.795 1.675 66.125 ; - POLYGON 8.89 62.03 8.89 61.73 1.78 61.73 1.78 61.75 1.23 61.75 1.23 62.03 ; - POLYGON 101.365 60.685 101.365 60.355 101.035 60.355 101.035 60.37 86.79 60.37 86.79 60.67 101.035 60.67 101.035 60.685 ; - POLYGON 6.59 44.35 6.59 44.05 1.78 44.05 1.78 44.07 1.23 44.07 1.23 44.35 ; - POLYGON 101.26 40.95 101.26 40.93 101.81 40.93 101.81 40.65 93.69 40.65 93.69 40.95 ; - POLYGON 1.545 37.565 1.545 37.55 16.25 37.55 16.25 37.25 1.545 37.25 1.545 37.235 1.215 37.235 1.215 37.565 ; - POLYGON 101.39 31.44 101.39 31.12 101.01 31.12 101.01 31.13 68.39 31.13 68.39 31.43 101.01 31.43 101.01 31.44 ; + POLYGON 37.87 74.27 37.87 73.97 1.23 73.97 1.23 74.25 1.78 74.25 1.78 74.27 ; + POLYGON 2.005 59.325 2.005 59.32 2.03 59.32 2.03 59 2.005 59 2.005 58.995 1.275 58.995 1.275 59.325 ; + POLYGON 2.005 55.245 2.005 55.23 5.67 55.23 5.67 54.93 2.005 54.93 2.005 54.915 1.675 54.915 1.675 55.245 ; + POLYGON 101.26 51.15 101.26 50.45 101.35 50.45 101.35 50.17 100.13 50.17 100.13 50.47 101.05 50.47 101.05 51.15 ; + POLYGON 33.27 43.67 33.27 43.37 1.78 43.37 1.78 43.39 1.23 43.39 1.23 43.67 ; + POLYGON 101.26 35.51 101.26 35.49 101.81 35.49 101.81 35.21 63.33 35.21 63.33 35.51 ; + POLYGON 1.545 32.805 1.545 32.79 28.21 32.79 28.21 32.49 1.545 32.49 1.545 32.475 1.215 32.475 1.215 32.805 ; + POLYGON 2.03 31.44 2.03 31.43 47.07 31.43 47.07 31.13 2.03 31.13 2.03 31.12 1.65 31.12 1.65 31.44 ; + POLYGON 18.55 24.63 18.55 24.33 1.78 24.33 1.78 24.35 1.23 24.35 1.23 24.63 ; POLYGON 73.765 0.165 73.765 0.16 73.98 0.16 73.98 -0.16 73.765 -0.16 73.765 -0.165 73.435 -0.165 73.435 -0.16 73.22 -0.16 73.22 0.16 73.435 0.16 73.435 0.165 ; POLYGON 44.325 0.165 44.325 0.16 44.54 0.16 44.54 -0.16 44.325 -0.16 44.325 -0.165 43.995 -0.165 43.995 -0.16 43.78 -0.16 43.78 0.16 43.995 0.16 43.995 0.165 ; - POLYGON 84.24 97.52 84.24 81.2 102.64 81.2 102.64 78.75 101.26 78.75 101.26 77.65 102.64 77.65 102.64 77.39 101.26 77.39 101.26 76.29 102.64 76.29 102.64 76.03 101.26 76.03 101.26 74.93 102.64 74.93 102.64 74.67 101.26 74.67 101.26 73.57 102.64 73.57 102.64 73.31 101.26 73.31 101.26 72.21 102.64 72.21 102.64 71.95 101.26 71.95 101.26 70.85 102.64 70.85 102.64 70.59 101.26 70.59 101.26 69.49 102.64 69.49 102.64 69.23 101.26 69.23 101.26 68.13 102.64 68.13 102.64 67.87 101.26 67.87 101.26 66.77 102.64 66.77 102.64 65.83 101.26 65.83 101.26 64.73 102.64 64.73 102.64 64.47 101.26 64.47 101.26 63.37 102.64 63.37 102.64 63.11 101.26 63.11 101.26 62.01 102.64 62.01 102.64 61.75 101.26 61.75 101.26 60.65 102.64 60.65 102.64 60.39 101.26 60.39 101.26 59.29 102.64 59.29 102.64 59.03 101.26 59.03 101.26 57.93 102.64 57.93 102.64 57.67 101.26 57.67 101.26 56.57 102.64 56.57 102.64 56.31 101.26 56.31 101.26 55.21 102.64 55.21 102.64 54.95 101.26 54.95 101.26 53.85 102.64 53.85 102.64 53.59 101.26 53.59 101.26 52.49 102.64 52.49 102.64 52.23 101.26 52.23 101.26 51.13 102.64 51.13 102.64 50.87 101.26 50.87 101.26 49.77 102.64 49.77 102.64 49.51 101.26 49.51 101.26 48.41 102.64 48.41 102.64 47.47 101.26 47.47 101.26 46.37 102.64 46.37 102.64 45.43 101.26 45.43 101.26 44.33 102.64 44.33 102.64 43.39 101.26 43.39 101.26 42.29 102.64 42.29 102.64 42.03 101.26 42.03 101.26 40.93 102.64 40.93 102.64 40.67 101.26 40.67 101.26 39.57 102.64 39.57 102.64 39.31 101.26 39.31 101.26 38.21 102.64 38.21 102.64 37.95 101.26 37.95 101.26 36.85 102.64 36.85 102.64 36.59 101.26 36.59 101.26 35.49 102.64 35.49 102.64 35.23 101.26 35.23 101.26 34.13 102.64 34.13 102.64 33.87 101.26 33.87 101.26 32.77 102.64 32.77 102.64 32.51 101.26 32.51 101.26 31.41 102.64 31.41 102.64 31.15 101.26 31.15 101.26 30.05 102.64 30.05 102.64 29.79 101.26 29.79 101.26 28.69 102.64 28.69 102.64 28.43 101.26 28.43 101.26 27.33 102.64 27.33 102.64 27.07 101.26 27.07 101.26 25.97 102.64 25.97 102.64 25.71 101.26 25.71 101.26 24.61 102.64 24.61 102.64 23.67 101.26 23.67 101.26 22.57 102.64 22.57 102.64 22.31 101.26 22.31 101.26 21.21 102.64 21.21 102.64 20.95 101.26 20.95 101.26 19.85 102.64 19.85 102.64 16.72 84.24 16.72 84.24 0.4 18.8 0.4 18.8 4.89 20.18 4.89 20.18 5.99 18.8 5.99 18.8 6.25 20.18 6.25 20.18 7.35 18.8 7.35 18.8 16.72 0.4 16.72 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 77.65 1.78 77.65 1.78 78.75 0.4 78.75 0.4 81.2 18.8 81.2 18.8 97.52 ; + POLYGON 84.24 97.52 84.24 81.2 102.64 81.2 102.64 78.75 101.26 78.75 101.26 77.65 102.64 77.65 102.64 77.39 101.26 77.39 101.26 76.29 102.64 76.29 102.64 76.03 101.26 76.03 101.26 74.93 102.64 74.93 102.64 74.67 101.26 74.67 101.26 73.57 102.64 73.57 102.64 73.31 101.26 73.31 101.26 72.21 102.64 72.21 102.64 71.95 101.26 71.95 101.26 70.85 102.64 70.85 102.64 70.59 101.26 70.59 101.26 69.49 102.64 69.49 102.64 69.23 101.26 69.23 101.26 68.13 102.64 68.13 102.64 67.87 101.26 67.87 101.26 66.77 102.64 66.77 102.64 66.51 101.26 66.51 101.26 65.41 102.64 65.41 102.64 65.15 101.26 65.15 101.26 64.05 102.64 64.05 102.64 63.11 101.26 63.11 101.26 62.01 102.64 62.01 102.64 61.75 101.26 61.75 101.26 60.65 102.64 60.65 102.64 60.39 101.26 60.39 101.26 59.29 102.64 59.29 102.64 59.03 101.26 59.03 101.26 57.93 102.64 57.93 102.64 57.67 101.26 57.67 101.26 56.57 102.64 56.57 102.64 56.31 101.26 56.31 101.26 55.21 102.64 55.21 102.64 54.95 101.26 54.95 101.26 53.85 102.64 53.85 102.64 53.59 101.26 53.59 101.26 52.49 102.64 52.49 102.64 51.55 101.26 51.55 101.26 50.45 102.64 50.45 102.64 50.19 101.26 50.19 101.26 49.09 102.64 49.09 102.64 48.15 101.26 48.15 101.26 47.05 102.64 47.05 102.64 46.79 101.26 46.79 101.26 45.69 102.64 45.69 102.64 45.43 101.26 45.43 101.26 44.33 102.64 44.33 102.64 43.39 101.26 43.39 101.26 42.29 102.64 42.29 102.64 42.03 101.26 42.03 101.26 40.93 102.64 40.93 102.64 40.67 101.26 40.67 101.26 39.57 102.64 39.57 102.64 39.31 101.26 39.31 101.26 38.21 102.64 38.21 102.64 37.95 101.26 37.95 101.26 36.85 102.64 36.85 102.64 36.59 101.26 36.59 101.26 35.49 102.64 35.49 102.64 35.23 101.26 35.23 101.26 34.13 102.64 34.13 102.64 33.87 101.26 33.87 101.26 32.77 102.64 32.77 102.64 32.51 101.26 32.51 101.26 31.41 102.64 31.41 102.64 30.47 101.26 30.47 101.26 29.37 102.64 29.37 102.64 29.11 101.26 29.11 101.26 28.01 102.64 28.01 102.64 27.75 101.26 27.75 101.26 26.65 102.64 26.65 102.64 26.39 101.26 26.39 101.26 25.29 102.64 25.29 102.64 25.03 101.26 25.03 101.26 23.93 102.64 23.93 102.64 23.67 101.26 23.67 101.26 22.57 102.64 22.57 102.64 22.31 101.26 22.31 101.26 21.21 102.64 21.21 102.64 20.95 101.26 20.95 101.26 19.85 102.64 19.85 102.64 16.72 84.24 16.72 84.24 0.4 18.8 0.4 18.8 4.89 20.18 4.89 20.18 5.99 18.8 5.99 18.8 6.25 20.18 6.25 20.18 7.35 18.8 7.35 18.8 7.61 20.18 7.61 20.18 8.71 18.8 8.71 18.8 16.72 0.4 16.72 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 66.77 1.78 66.77 1.78 67.87 0.4 67.87 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 81.2 18.8 81.2 18.8 97.52 ; LAYER met5 ; - POLYGON 81.44 94.72 81.44 78.4 99.84 78.4 99.84 74.16 96.64 74.16 96.64 64.56 99.84 64.56 99.84 53.76 96.64 53.76 96.64 44.16 99.84 44.16 99.84 33.36 96.64 33.36 96.64 23.76 99.84 23.76 99.84 19.52 81.44 19.52 81.44 3.2 21.6 3.2 21.6 19.52 3.2 19.52 3.2 23.76 6.4 23.76 6.4 33.36 3.2 33.36 3.2 44.16 6.4 44.16 6.4 53.76 3.2 53.76 3.2 64.56 6.4 64.56 6.4 74.16 3.2 74.16 3.2 78.4 21.6 78.4 21.6 94.72 ; + POLYGON 83.04 96.32 83.04 80 101.44 80 101.44 72.56 98.24 72.56 98.24 66.16 101.44 66.16 101.44 52.16 98.24 52.16 98.24 45.76 101.44 45.76 101.44 31.76 98.24 31.76 98.24 25.36 101.44 25.36 101.44 17.92 83.04 17.92 83.04 1.6 20 1.6 20 17.92 1.6 17.92 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 80 20 80 20 96.32 ; LAYER met1 ; - RECT 71.355 80.85 71.645 81.14 ; POLYGON 84.36 97.4 84.36 95.72 83.88 95.72 83.88 94.68 84.36 94.68 84.36 93 83.88 93 83.88 91.96 84.36 91.96 84.36 90.28 83.88 90.28 83.88 89.24 84.36 89.24 84.36 87.56 83.88 87.56 83.88 86.52 84.36 86.52 84.36 84.84 83.88 84.84 83.88 83.8 84.36 83.8 84.36 82.12 18.68 82.12 18.68 83.8 19.16 83.8 19.16 84.84 18.68 84.84 18.68 86.52 19.16 86.52 19.16 87.56 18.68 87.56 18.68 89.24 19.16 89.24 19.16 90.28 18.68 90.28 18.68 91.96 19.16 91.96 19.16 93 18.68 93 18.68 94.68 19.16 94.68 19.16 95.72 18.68 95.72 18.68 97.4 ; POLYGON 102.76 81.08 102.76 79.4 102.28 79.4 102.28 78.36 102.76 78.36 102.76 76.68 102.28 76.68 102.28 75.64 102.76 75.64 102.76 73.96 102.28 73.96 102.28 72.92 102.76 72.92 102.76 71.24 102.28 71.24 102.28 70.2 102.76 70.2 102.76 68.52 102.28 68.52 102.28 67.48 102.76 67.48 102.76 65.8 102.28 65.8 102.28 64.76 102.76 64.76 102.76 63.08 102.28 63.08 102.28 62.04 102.76 62.04 102.76 60.36 102.28 60.36 102.28 59.32 102.76 59.32 102.76 57.64 102.28 57.64 102.28 56.6 102.76 56.6 102.76 54.92 102.28 54.92 102.28 53.88 102.76 53.88 102.76 52.2 102.28 52.2 102.28 51.16 102.76 51.16 102.76 49.48 102.28 49.48 102.28 48.44 102.76 48.44 102.76 46.76 102.28 46.76 102.28 45.72 102.76 45.72 102.76 44.04 102.28 44.04 102.28 43 102.76 43 102.76 41.32 102.28 41.32 102.28 40.28 102.76 40.28 102.76 38.6 102.28 38.6 102.28 37.56 102.76 37.56 102.76 35.88 102.28 35.88 102.28 34.84 102.76 34.84 102.76 33.16 102.28 33.16 102.28 32.12 102.76 32.12 102.76 30.44 102.28 30.44 102.28 29.4 102.76 29.4 102.76 27.72 102.28 27.72 102.28 26.68 102.76 26.68 102.76 25 102.28 25 102.28 23.96 102.76 23.96 102.76 22.28 102.28 22.28 102.28 21.24 102.76 21.24 102.76 19.56 102.28 19.56 102.28 18.52 102.76 18.52 102.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; POLYGON 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 18.68 0.52 18.68 2.2 19.16 2.2 19.16 3.24 18.68 3.24 18.68 4.92 19.16 4.92 19.16 5.96 18.68 5.96 18.68 7.64 19.16 7.64 19.16 8.68 18.68 8.68 18.68 10.36 19.16 10.36 19.16 11.4 18.68 11.4 18.68 13.08 19.16 13.08 19.16 14.12 18.68 14.12 18.68 15.8 ; LAYER li1 ; - RECT 47.465 97.11 48.215 97.655 ; - RECT 96.225 80.79 96.975 81.335 ; - RECT 96.225 16.585 96.975 17.13 ; - RECT 47.465 0.265 48.215 0.81 ; - POLYGON 84.3 97.58 84.3 81.26 102.7 81.26 102.7 16.66 84.3 16.66 84.3 0.34 18.74 0.34 18.74 16.66 0.34 16.66 0.34 81.26 18.74 81.26 18.74 97.58 ; + POLYGON 84.47 97.75 84.47 81.43 102.87 81.43 102.87 16.49 84.47 16.49 84.47 0.17 18.57 0.17 18.57 16.49 0.17 16.49 0.17 81.43 18.57 81.43 18.57 97.75 ; LAYER mcon ; RECT 84.325 97.835 84.495 98.005 ; RECT 83.865 97.835 84.035 98.005 ; @@ -3018,153 +3003,49 @@ MACRO sb_1__1_ LAYER via ; RECT 73.525 97.845 73.675 97.995 ; RECT 44.085 97.845 44.235 97.995 ; - RECT 64.785 96.145 64.935 96.295 ; + RECT 68.005 96.145 68.155 96.295 ; + RECT 56.045 96.145 56.195 96.295 ; + RECT 51.445 96.145 51.595 96.295 ; + RECT 45.465 96.145 45.615 96.295 ; RECT 73.525 81.525 73.675 81.675 ; RECT 44.085 81.525 44.235 81.675 ; - RECT 2.685 79.825 2.835 79.975 ; - RECT 10.965 17.945 11.115 18.095 ; + RECT 97.905 17.945 98.055 18.095 ; + RECT 94.225 17.945 94.375 18.095 ; + RECT 6.365 17.945 6.515 18.095 ; + RECT 4.525 17.945 4.675 18.095 ; RECT 73.525 16.245 73.675 16.395 ; RECT 44.085 16.245 44.235 16.395 ; - RECT 71.225 1.625 71.375 1.775 ; - RECT 47.765 1.625 47.915 1.775 ; + RECT 80.885 1.625 81.035 1.775 ; + RECT 63.405 1.625 63.555 1.775 ; RECT 46.845 1.625 46.995 1.775 ; - RECT 21.545 1.625 21.695 1.775 ; RECT 73.525 -0.075 73.675 0.075 ; RECT 44.085 -0.075 44.235 0.075 ; LAYER via2 ; RECT 73.5 97.82 73.7 98.02 ; RECT 44.06 97.82 44.26 98.02 ; - RECT 101.56 78.1 101.76 78.3 ; - RECT 101.1 72.66 101.3 72.86 ; - RECT 1.28 70.62 1.48 70.82 ; - RECT 1.28 65.18 1.48 65.38 ; - RECT 101.56 62.46 101.76 62.66 ; - RECT 1.74 62.46 1.94 62.66 ; - RECT 1.28 38.66 1.48 38.86 ; - RECT 1.28 31.86 1.48 32.06 ; - RECT 1.74 29.14 1.94 29.34 ; - RECT 19.68 5.34 19.88 5.54 ; + RECT 1.74 77.42 1.94 77.62 ; + RECT 1.28 67.22 1.48 67.42 ; + RECT 101.56 59.74 101.76 59.94 ; + RECT 1.74 51.58 1.94 51.78 ; + RECT 101.56 49.54 101.76 49.74 ; + RECT 101.1 47.5 101.3 47.7 ; + RECT 1.28 40.02 1.48 40.22 ; + RECT 1.74 38.66 1.94 38.86 ; + RECT 1.28 35.94 1.48 36.14 ; + RECT 101.56 33.22 101.76 33.42 ; + RECT 1.74 33.22 1.94 33.42 ; + RECT 1.74 25.06 1.94 25.26 ; + RECT 1.74 20.98 1.94 21.18 ; + RECT 19.68 6.7 19.88 6.9 ; RECT 73.5 -0.1 73.7 0.1 ; RECT 44.06 -0.1 44.26 0.1 ; LAYER via3 ; RECT 73.5 97.82 73.7 98.02 ; RECT 44.06 97.82 44.26 98.02 ; - RECT 101.1 74.02 101.3 74.22 ; + RECT 1.74 55.66 1.94 55.86 ; + RECT 1.74 34.58 1.94 34.78 ; RECT 73.5 -0.1 73.7 0.1 ; RECT 44.06 -0.1 44.26 0.1 ; - LAYER fieldpoly ; - POLYGON 84.5 97.78 84.5 81.46 102.9 81.46 102.9 16.46 84.5 16.46 84.5 0.14 18.54 0.14 18.54 16.46 0.14 16.46 0.14 81.46 18.54 81.46 18.54 97.78 ; - LAYER diff ; - POLYGON 84.64 97.92 84.64 81.6 103.04 81.6 103.04 16.32 84.64 16.32 84.64 0 18.4 0 18.4 16.32 0 16.32 0 81.6 18.4 81.6 18.4 97.92 ; - LAYER nwell ; - POLYGON 84.83 96.615 84.83 93.785 83.53 93.785 83.53 95.39 83.99 95.39 83.99 96.615 ; - POLYGON 22.27 96.615 22.27 95.01 20.43 95.01 20.43 93.785 18.21 93.785 18.21 96.615 ; - POLYGON 84.83 91.175 84.83 88.345 83.99 88.345 83.99 89.57 83.53 89.57 83.53 91.175 ; - RECT 18.21 88.345 20.43 91.175 ; - POLYGON 84.83 85.735 84.83 82.905 83.53 82.905 83.53 84.51 83.99 84.51 83.99 85.735 ; - RECT 18.21 82.905 20.43 85.735 ; - RECT 102.39 77.465 103.23 80.295 ; - POLYGON 3.87 80.295 3.87 78.69 2.03 78.69 2.03 77.465 -0.19 77.465 -0.19 80.295 ; - RECT 101.93 72.025 103.23 74.855 ; - RECT -0.19 72.025 2.03 74.855 ; - POLYGON 103.23 69.415 103.23 66.585 102.39 66.585 102.39 67.81 101.93 67.81 101.93 69.415 ; - RECT -0.19 66.585 2.03 69.415 ; - RECT 101.93 61.145 103.23 63.975 ; - RECT -0.19 61.145 2.03 63.975 ; - RECT 101.93 55.705 103.23 58.535 ; - RECT -0.19 55.705 2.03 58.535 ; - POLYGON 103.23 53.095 103.23 50.265 102.39 50.265 102.39 51.49 101.93 51.49 101.93 53.095 ; - RECT -0.19 50.265 2.03 53.095 ; - RECT 101.93 44.825 103.23 47.655 ; - POLYGON 3.87 47.655 3.87 46.05 2.03 46.05 2.03 44.825 -0.19 44.825 -0.19 47.655 ; - RECT 101.93 39.385 103.23 42.215 ; - RECT -0.19 39.385 2.03 42.215 ; - POLYGON 103.23 36.775 103.23 33.945 102.39 33.945 102.39 35.17 99.17 35.17 99.17 36.775 ; - RECT -0.19 33.945 2.03 36.775 ; - POLYGON 103.23 31.335 103.23 28.505 102.39 28.505 102.39 29.73 101.93 29.73 101.93 31.335 ; - POLYGON 2.03 31.335 2.03 30.11 3.87 30.11 3.87 28.505 -0.19 28.505 -0.19 31.335 ; - RECT 101.93 23.065 103.23 25.895 ; - RECT -0.19 23.065 2.03 25.895 ; - POLYGON 103.23 20.455 103.23 17.625 102.39 17.625 102.39 18.85 101.93 18.85 101.93 20.455 ; - POLYGON 2.03 20.455 2.03 19.23 3.87 19.23 3.87 17.625 -0.19 17.625 -0.19 20.455 ; - RECT 83.53 12.185 84.83 15.015 ; - POLYGON 20.43 15.015 20.43 13.79 22.27 13.79 22.27 12.185 18.21 12.185 18.21 15.015 ; - RECT 83.53 6.745 84.83 9.575 ; - RECT 18.21 6.745 20.43 9.575 ; - POLYGON 84.83 4.135 84.83 1.305 83.99 1.305 83.99 2.53 83.53 2.53 83.53 4.135 ; - POLYGON 20.43 4.135 20.43 2.91 22.27 2.91 22.27 1.305 18.21 1.305 18.21 4.135 ; - POLYGON 84.64 97.92 84.64 81.6 103.04 81.6 103.04 16.32 84.64 16.32 84.64 0 18.4 0 18.4 16.32 0 16.32 0 81.6 18.4 81.6 18.4 97.92 ; - LAYER pwell ; - RECT 77.87 97.87 78.09 98.04 ; - RECT 74.19 97.87 74.41 98.04 ; - RECT 70.51 97.87 70.73 98.04 ; - RECT 66.83 97.87 67.05 98.04 ; - RECT 63.15 97.87 63.37 98.04 ; - RECT 59.47 97.87 59.69 98.04 ; - RECT 55.79 97.87 56.01 98.04 ; - RECT 52.11 97.87 52.33 98.04 ; - RECT 48.43 97.87 48.65 98.04 ; - RECT 40.61 97.87 40.83 98.04 ; - RECT 36.93 97.87 37.15 98.04 ; - RECT 33.25 97.87 33.47 98.04 ; - RECT 29.57 97.87 29.79 98.04 ; - RECT 25.89 97.87 26.11 98.04 ; - RECT 22.21 97.87 22.43 98.04 ; - RECT 18.53 97.87 18.75 98.04 ; - RECT 81.595 97.86 81.705 97.98 ; - RECT 44.335 97.86 44.445 97.98 ; - RECT 84.32 97.865 84.44 97.975 ; - RECT 47.06 97.865 47.18 97.975 ; - RECT 83.415 97.86 83.575 97.97 ; - RECT 46.155 97.86 46.315 97.97 ; - RECT 97.19 81.55 97.41 81.72 ; - RECT 89.37 81.55 89.59 81.72 ; - RECT 85.69 81.55 85.91 81.72 ; - RECT 14.85 81.55 15.07 81.72 ; - RECT 11.17 81.55 11.39 81.72 ; - RECT 7.49 81.55 7.71 81.72 ; - RECT 3.81 81.55 4.03 81.72 ; - RECT 0.13 81.55 0.35 81.72 ; - RECT 100.915 81.54 101.025 81.66 ; - RECT 93.095 81.54 93.205 81.66 ; - RECT 102.72 81.545 102.84 81.655 ; - RECT 95.82 81.545 95.94 81.655 ; - RECT 94.915 81.54 95.075 81.65 ; - RECT 100.915 16.26 101.025 16.38 ; - RECT 102.72 16.265 102.84 16.375 ; - RECT 95.82 16.265 95.94 16.375 ; - RECT 97.19 16.2 97.41 16.37 ; - RECT 92.13 16.2 92.35 16.37 ; - RECT 88.45 16.2 88.67 16.37 ; - RECT 84.77 16.2 84.99 16.37 ; - RECT 14.85 16.2 15.07 16.37 ; - RECT 11.17 16.2 11.39 16.37 ; - RECT 7.49 16.2 7.71 16.37 ; - RECT 3.81 16.2 4.03 16.37 ; - RECT 0.13 16.2 0.35 16.37 ; - RECT 83.415 -0.05 83.575 0.06 ; - RECT 81.595 -0.06 81.705 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 84.32 -0.055 84.44 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 77.87 -0.12 78.09 0.05 ; - RECT 74.19 -0.12 74.41 0.05 ; - RECT 70.51 -0.12 70.73 0.05 ; - RECT 66.83 -0.12 67.05 0.05 ; - RECT 63.15 -0.12 63.37 0.05 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - POLYGON 84.64 97.92 84.64 81.6 103.04 81.6 103.04 16.32 84.64 16.32 84.64 0 18.4 0 18.4 16.32 0 16.32 0 81.6 18.4 81.6 18.4 97.92 ; LAYER OVERLAP ; POLYGON 18.4 0 18.4 16.32 0 16.32 0 81.6 18.4 81.6 18.4 97.92 84.64 97.92 84.64 81.6 103.04 81.6 103.04 16.32 84.64 16.32 84.64 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef index ed38f04..44a8877 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -375,7 +363,7 @@ MACRO sb_1__2_ USE CLOCK ; PORT LAYER met2 ; - RECT 2.23 16.32 2.37 17.68 ; + RECT 20.63 0 20.77 1.36 ; END END prog_clk[0] PIN chanx_right_in[0] @@ -383,7 +371,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 71.93 103.04 72.23 ; + RECT 101.66 54.25 103.04 54.55 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -391,7 +379,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 54.25 103.04 54.55 ; + RECT 101.66 42.01 103.04 42.31 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -399,7 +387,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 73.29 103.04 73.59 ; + RECT 101.66 56.29 103.04 56.59 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -407,7 +395,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 69.21 103.04 69.51 ; + RECT 101.66 26.37 103.04 26.67 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -415,7 +403,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 70.57 103.04 70.87 ; + RECT 101.66 35.89 103.04 36.19 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -423,7 +411,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 29.77 103.04 30.07 ; + RECT 101.66 69.21 103.04 69.51 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -431,7 +419,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 24.33 103.04 24.63 ; + RECT 101.66 33.17 103.04 33.47 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -439,7 +427,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 74.65 103.04 74.95 ; + RECT 101.66 63.77 103.04 64.07 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -447,7 +435,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 55.61 103.04 55.91 ; + RECT 101.66 43.37 103.04 43.67 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -455,7 +443,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 28.41 103.04 28.71 ; + RECT 101.66 76.01 103.04 76.31 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -463,7 +451,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 52.21 103.04 52.51 ; + RECT 101.66 40.65 103.04 40.95 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -471,7 +459,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 36.57 103.04 36.87 ; + RECT 101.66 77.37 103.04 77.67 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -479,7 +467,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 47.45 103.04 47.75 ; + RECT 101.66 59.01 103.04 59.31 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -487,15 +475,15 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 27.05 103.04 27.35 ; + RECT 101.66 22.97 103.04 23.27 ; END END chanx_right_in[13] PIN chanx_right_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 101.66 25.69 103.04 25.99 ; + LAYER met2 ; + RECT 100.67 16.32 100.81 17.68 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -503,7 +491,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 44.73 103.04 45.03 ; + RECT 101.66 67.85 103.04 68.15 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -511,7 +499,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 32.49 103.04 32.79 ; + RECT 101.66 44.73 103.04 45.03 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -519,7 +507,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 50.17 103.04 50.47 ; + RECT 101.66 21.61 103.04 21.91 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -527,7 +515,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 46.09 103.04 46.39 ; + RECT 101.66 61.05 103.04 61.35 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -535,23 +523,87 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 35.21 103.04 35.51 ; + RECT 101.66 65.13 103.04 65.43 ; END END chanx_right_in[19] PIN right_top_grid_pin_1_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 100.67 80.24 100.81 81.6 ; + LAYER met3 ; + RECT 101.66 37.25 103.04 37.55 ; END END right_top_grid_pin_1_[0] - PIN chany_bottom_in[0] + PIN right_bottom_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.91 16.32 98.05 17.68 ; + END + END right_bottom_grid_pin_34_[0] + PIN right_bottom_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 99.75 16.32 99.89 17.68 ; + END + END right_bottom_grid_pin_35_[0] + PIN right_bottom_grid_pin_36_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; - RECT 55.05 0 55.35 1.36 ; + RECT 97.37 16.32 97.67 17.68 ; + END + END right_bottom_grid_pin_36_[0] + PIN right_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.23 16.32 94.37 17.68 ; + END + END right_bottom_grid_pin_37_[0] + PIN right_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 95.15 16.32 95.29 17.68 ; + END + END right_bottom_grid_pin_38_[0] + PIN right_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 5.29 84.64 5.59 ; + END + END right_bottom_grid_pin_39_[0] + PIN right_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.53 16.32 96.67 17.68 ; + END + END right_bottom_grid_pin_40_[0] + PIN right_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.27 0 82.41 1.36 ; + END + END right_bottom_grid_pin_41_[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.53 0 50.67 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -559,7 +611,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 57.89 0 58.03 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -567,7 +619,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 0 68.61 1.36 ; + RECT 56.97 0 57.11 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -575,7 +627,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.73 0 59.87 1.36 ; + RECT 62.49 0 62.63 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -583,7 +635,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.39 0 69.53 1.36 ; + RECT 48.69 0 48.83 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -591,7 +643,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -599,7 +651,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 0 70.45 1.36 ; + RECT 77.21 0 77.35 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -607,7 +659,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.65 0 60.79 1.36 ; + RECT 52.37 0 52.51 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -615,7 +667,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 0 67.69 1.36 ; + RECT 61.11 0 61.25 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -623,15 +675,15 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.57 0 61.71 1.36 ; + RECT 40.41 0 40.55 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 45.85 0 46.15 1.36 ; + LAYER met2 ; + RECT 56.05 0 56.19 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -639,7 +691,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; + RECT 49.61 0 49.75 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -647,7 +699,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + RECT 47.77 0 47.91 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -655,15 +707,15 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 71.23 0 71.37 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 52.29 0 52.59 1.36 ; + LAYER met2 ; + RECT 75.37 0 75.51 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -671,7 +723,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + RECT 32.59 0 32.73 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -679,7 +731,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 51.45 0 51.59 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -687,7 +739,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 74.45 0 74.59 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -695,7 +747,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; + RECT 76.29 0 76.43 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -703,79 +755,79 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 72.15 0 72.29 1.36 ; + RECT 54.21 0 54.35 1.36 ; END END chany_bottom_in[19] - PIN bottom_left_grid_pin_34_[0] + PIN bottom_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 16.32 11.11 17.68 ; + RECT 3.61 16.32 3.75 17.68 ; END - END bottom_left_grid_pin_34_[0] - PIN bottom_left_grid_pin_35_[0] + END bottom_left_grid_pin_42_[0] + PIN bottom_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; - RECT 10.89 16.32 11.19 17.68 ; + RECT 22.85 0 23.15 1.36 ; END - END bottom_left_grid_pin_35_[0] - PIN bottom_left_grid_pin_36_[0] + END bottom_left_grid_pin_43_[0] + PIN bottom_left_grid_pin_44_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 22.47 0 22.61 1.36 ; + RECT 10.51 16.32 10.65 17.68 ; END - END bottom_left_grid_pin_36_[0] - PIN bottom_left_grid_pin_37_[0] + END bottom_left_grid_pin_44_[0] + PIN bottom_left_grid_pin_45_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 4.53 16.32 4.67 17.68 ; END - END bottom_left_grid_pin_37_[0] - PIN bottom_left_grid_pin_38_[0] + END bottom_left_grid_pin_45_[0] + PIN bottom_left_grid_pin_46_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 0 21.69 1.36 ; + RECT 2.69 16.32 2.83 17.68 ; END - END bottom_left_grid_pin_38_[0] - PIN bottom_left_grid_pin_39_[0] + END bottom_left_grid_pin_46_[0] + PIN bottom_left_grid_pin_47_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 8.67 16.32 8.81 17.68 ; + LAYER met3 ; + RECT 18.4 12.09 19.78 12.39 ; END - END bottom_left_grid_pin_39_[0] - PIN bottom_left_grid_pin_40_[0] + END bottom_left_grid_pin_47_[0] + PIN bottom_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; RECT 6.83 16.32 6.97 17.68 ; END - END bottom_left_grid_pin_40_[0] - PIN bottom_left_grid_pin_41_[0] + END bottom_left_grid_pin_48_[0] + PIN bottom_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 16.32 7.89 17.68 ; + RECT 9.59 16.32 9.73 17.68 ; END - END bottom_left_grid_pin_41_[0] + END bottom_left_grid_pin_49_[0] PIN chanx_left_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 27.05 1.38 27.35 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -783,7 +835,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 67.85 1.38 68.15 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -791,7 +843,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -799,7 +851,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -807,7 +859,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; + RECT 0 37.93 1.38 38.23 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -815,7 +867,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -823,7 +875,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -831,7 +883,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 25.69 1.38 25.99 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -839,7 +891,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -847,7 +899,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 60.37 1.38 60.67 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -855,7 +907,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; + RECT 0 63.77 1.38 64.07 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -863,7 +915,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 36.57 1.38 36.87 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -871,7 +923,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; + RECT 0 29.77 1.38 30.07 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -879,7 +931,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 20.25 1.38 20.55 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -887,7 +939,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 77.37 1.38 77.67 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -895,7 +947,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; + RECT 0 76.01 1.38 76.31 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -903,7 +955,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; + RECT 0 59.01 1.38 59.31 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -911,7 +963,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; + RECT 0 52.21 1.38 52.51 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -919,7 +971,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 40.65 1.38 40.95 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -927,23 +979,87 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 24.33 1.38 24.63 ; END END chanx_left_in[19] PIN left_top_grid_pin_1_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 2.23 80.24 2.37 81.6 ; + LAYER met3 ; + RECT 0 62.41 1.38 62.71 ; END END left_top_grid_pin_1_[0] - PIN ccff_head[0] + PIN left_bottom_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 18.4 6.65 19.78 6.95 ; + END + END left_bottom_grid_pin_34_[0] + PIN left_bottom_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 4.45 16.32 4.75 17.68 ; + END + END left_bottom_grid_pin_35_[0] + PIN left_bottom_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 18.4 5.29 19.78 5.59 ; + END + END left_bottom_grid_pin_36_[0] + PIN left_bottom_grid_pin_37_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 99.75 80.24 99.89 81.6 ; + RECT 5.45 16.32 5.59 17.68 ; + END + END left_bottom_grid_pin_37_[0] + PIN left_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.01 0 22.15 1.36 ; + END + END left_bottom_grid_pin_38_[0] + PIN left_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.67 16.32 8.81 17.68 ; + END + END left_bottom_grid_pin_39_[0] + PIN left_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.93 0 23.07 1.36 ; + END + END left_bottom_grid_pin_40_[0] + PIN left_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.75 16.32 7.89 17.68 ; + END + END left_bottom_grid_pin_41_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 101.66 47.45 103.04 47.75 ; END END ccff_head[0] PIN chanx_right_out[0] @@ -951,7 +1067,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 48.81 103.04 49.11 ; + RECT 101.66 52.89 103.04 53.19 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -959,7 +1075,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 37.93 103.04 38.23 ; + RECT 101.66 29.09 103.04 29.39 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -967,7 +1083,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 31.13 103.04 31.43 ; + RECT 101.66 50.17 103.04 50.47 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -975,7 +1091,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 67.85 103.04 68.15 ; + RECT 101.66 31.81 103.04 32.11 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -983,7 +1099,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 33.85 103.04 34.15 ; + RECT 101.66 70.57 103.04 70.87 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -991,7 +1107,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 56.97 103.04 57.27 ; + RECT 101.66 24.33 103.04 24.63 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -1007,7 +1123,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 58.33 103.04 58.63 ; + RECT 101.66 51.53 103.04 51.83 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1015,7 +1131,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 65.13 103.04 65.43 ; + RECT 101.66 34.53 103.04 34.83 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1023,7 +1139,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 42.01 103.04 42.31 ; + RECT 101.66 20.25 103.04 20.55 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1031,7 +1147,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 20.25 103.04 20.55 ; + RECT 101.66 71.93 103.04 72.23 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1039,7 +1155,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 59.69 103.04 59.99 ; + RECT 101.66 30.45 103.04 30.75 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1047,7 +1163,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 21.61 103.04 21.91 ; + RECT 101.66 39.29 103.04 39.59 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1055,7 +1171,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 39.29 103.04 39.59 ; + RECT 101.66 27.73 103.04 28.03 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1063,7 +1179,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 63.77 103.04 64.07 ; + RECT 101.66 48.81 103.04 49.11 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1071,7 +1187,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 40.65 103.04 40.95 ; + RECT 101.66 74.65 103.04 74.95 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -1079,7 +1195,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 43.37 103.04 43.67 ; + RECT 101.66 57.65 103.04 57.95 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1087,7 +1203,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 61.05 103.04 61.35 ; + RECT 101.66 46.09 103.04 46.39 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1095,7 +1211,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 62.41 103.04 62.71 ; + RECT 101.66 73.29 103.04 73.59 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1103,7 +1219,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 22.97 103.04 23.27 ; + RECT 101.66 62.41 103.04 62.71 ; END END chanx_right_out[19] PIN chany_bottom_out[0] @@ -1111,7 +1227,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + RECT 72.15 0 72.29 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -1119,7 +1235,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 55.13 0 55.27 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -1127,7 +1243,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 46.85 0 46.99 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -1135,7 +1251,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; + RECT 63.41 0 63.55 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -1143,7 +1259,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 0 66.77 1.36 ; + RECT 45.93 0 46.07 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -1151,7 +1267,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + RECT 70.31 0 70.45 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -1159,7 +1275,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; + RECT 33.51 0 33.65 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -1167,7 +1283,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; + RECT 64.79 0 64.93 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1175,7 +1291,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 0 65.85 1.36 ; + RECT 59.27 0 59.41 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -1183,7 +1299,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 65.71 0 65.85 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1191,7 +1307,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; + RECT 43.17 0 43.31 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -1199,15 +1315,15 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; + RECT 66.63 0 66.77 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 56.89 0 57.19 1.36 ; + LAYER met2 ; + RECT 39.49 0 39.63 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -1215,7 +1331,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + RECT 67.55 0 67.69 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -1223,7 +1339,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 0 64.93 1.36 ; + RECT 42.25 0 42.39 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -1231,7 +1347,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 80.89 0 81.03 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1239,7 +1355,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 0 71.37 1.36 ; + RECT 41.33 0 41.47 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -1247,7 +1363,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 68.47 0 68.61 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -1255,7 +1371,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; + RECT 45.01 0 45.15 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -1263,7 +1379,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 69.39 0 69.53 1.36 ; END END chany_bottom_out[19] PIN chanx_left_out[0] @@ -1271,7 +1387,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 57.65 1.38 57.95 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1279,7 +1395,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 66.49 1.38 66.79 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -1287,7 +1403,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + RECT 0 55.61 1.38 55.91 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1295,7 +1411,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1303,7 +1419,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; + RECT 0 50.85 1.38 51.15 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1311,7 +1427,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 28.41 1.38 28.71 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1319,7 +1435,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1327,7 +1443,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 31.13 1.38 31.43 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1335,15 +1451,15 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_out[8] PIN chanx_left_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + LAYER met4 ; + RECT 6.29 16.32 6.59 17.68 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1351,7 +1467,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 74.65 1.38 74.95 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1359,7 +1475,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 35.21 1.38 35.51 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1367,7 +1483,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 71.93 1.38 72.23 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1375,7 +1491,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; + RECT 0 53.57 1.38 53.87 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1383,7 +1499,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1391,7 +1507,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1399,7 +1515,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 33.85 1.38 34.15 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1407,7 +1523,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; + RECT 0 32.49 1.38 32.79 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1415,7 +1531,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1423,7 +1539,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1431,9 +1547,41 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 21.61 1.38 21.91 ; END END ccff_tail[0] + PIN SC_IN_TOP + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.21 80.24 54.35 81.6 ; + END + END SC_IN_TOP + PIN SC_IN_BOT + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.29 80.24 53.43 81.6 ; + END + END SC_IN_BOT + PIN SC_OUT_TOP + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.37 80.24 52.51 81.6 ; + END + END SC_OUT_TOP + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.45 80.24 51.59 81.6 ; + END + END SC_OUT_BOT PIN VDD DIRECTION INPUT ; USE POWER ; @@ -1528,13 +1676,13 @@ MACRO sb_1__2_ OBS LAYER li1 ; RECT 0 81.515 103.04 81.685 ; - RECT 102.58 78.795 103.04 78.965 ; + RECT 102.12 78.795 103.04 78.965 ; RECT 0 78.795 3.68 78.965 ; RECT 102.12 76.075 103.04 76.245 ; - RECT 0 76.075 3.68 76.245 ; - RECT 102.12 73.355 103.04 73.525 ; + RECT 0 76.075 1.84 76.245 ; + RECT 99.36 73.355 103.04 73.525 ; RECT 0 73.355 1.84 73.525 ; - RECT 102.12 70.635 103.04 70.805 ; + RECT 99.36 70.635 103.04 70.805 ; RECT 0 70.635 1.84 70.805 ; RECT 102.12 67.915 103.04 68.085 ; RECT 0 67.915 1.84 68.085 ; @@ -1590,33 +1738,33 @@ MACRO sb_1__2_ LAYER met2 ; RECT 73.46 81.415 73.74 81.785 ; RECT 44.02 81.415 44.3 81.785 ; - POLYGON 8.41 18.18 8.41 17.86 8.35 17.86 8.35 17.61 8.17 17.61 8.17 17.96 8.15 17.96 8.15 18.18 ; - RECT 67.03 1.54 67.29 1.86 ; - RECT 59.21 1.54 59.47 1.86 ; + RECT 53.69 1.54 53.95 1.86 ; + RECT 47.25 1.54 47.51 1.86 ; RECT 73.46 -0.185 73.74 0.185 ; RECT 44.02 -0.185 44.3 0.185 ; - POLYGON 102.76 81.32 102.76 16.6 84.36 16.6 84.36 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 18.68 0.28 18.68 16.6 11.39 16.6 11.39 17.96 10.69 17.96 10.69 16.6 9.09 16.6 9.09 17.96 8.39 17.96 8.39 16.6 8.17 16.6 8.17 17.96 7.47 17.96 7.47 16.6 7.25 16.6 7.25 17.96 6.55 17.96 6.55 16.6 2.65 16.6 2.65 17.96 1.95 17.96 1.95 16.6 0.28 16.6 0.28 81.32 1.95 81.32 1.95 79.96 2.65 79.96 2.65 81.32 99.47 81.32 99.47 79.96 100.17 79.96 100.17 81.32 100.39 81.32 100.39 79.96 101.09 79.96 101.09 81.32 ; + POLYGON 102.76 81.32 102.76 16.6 101.09 16.6 101.09 17.96 100.39 17.96 100.39 16.6 100.17 16.6 100.17 17.96 99.47 17.96 99.47 16.6 98.33 16.6 98.33 17.96 97.63 17.96 97.63 16.6 96.95 16.6 96.95 17.96 96.25 17.96 96.25 16.6 95.57 16.6 95.57 17.96 94.87 17.96 94.87 16.6 94.65 16.6 94.65 17.96 93.95 17.96 93.95 16.6 84.36 16.6 84.36 0.28 82.69 0.28 82.69 1.64 81.99 1.64 81.99 0.28 81.31 0.28 81.31 1.64 80.61 1.64 80.61 0.28 77.63 0.28 77.63 1.64 76.93 1.64 76.93 0.28 76.71 0.28 76.71 1.64 76.01 1.64 76.01 0.28 75.79 0.28 75.79 1.64 75.09 1.64 75.09 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 63.83 0.28 63.83 1.64 63.13 1.64 63.13 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 18.68 0.28 18.68 16.6 10.93 16.6 10.93 17.96 10.23 17.96 10.23 16.6 10.01 16.6 10.01 17.96 9.31 17.96 9.31 16.6 9.09 16.6 9.09 17.96 8.39 17.96 8.39 16.6 8.17 16.6 8.17 17.96 7.47 17.96 7.47 16.6 7.25 16.6 7.25 17.96 6.55 17.96 6.55 16.6 5.87 16.6 5.87 17.96 5.17 17.96 5.17 16.6 4.95 16.6 4.95 17.96 4.25 17.96 4.25 16.6 4.03 16.6 4.03 17.96 3.33 17.96 3.33 16.6 3.11 16.6 3.11 17.96 2.41 17.96 2.41 16.6 0.28 16.6 0.28 81.32 51.17 81.32 51.17 79.96 51.87 79.96 51.87 81.32 52.09 81.32 52.09 79.96 52.79 79.96 52.79 81.32 53.01 81.32 53.01 79.96 53.71 79.96 53.71 81.32 53.93 81.32 53.93 79.96 54.63 79.96 54.63 81.32 ; LAYER met3 ; POLYGON 73.765 81.765 73.765 81.76 73.98 81.76 73.98 81.44 73.765 81.44 73.765 81.435 73.435 81.435 73.435 81.44 73.22 81.44 73.22 81.76 73.435 81.76 73.435 81.765 ; POLYGON 44.325 81.765 44.325 81.76 44.54 81.76 44.54 81.44 44.325 81.44 44.325 81.435 43.995 81.435 43.995 81.44 43.78 81.44 43.78 81.76 43.995 81.76 43.995 81.765 ; - POLYGON 101.81 56.59 101.81 56.31 101.26 56.31 101.26 56.29 47.23 56.29 47.23 56.59 ; - POLYGON 101.35 38.91 101.35 38.63 101.26 38.63 101.26 37.93 101.05 37.93 101.05 38.61 95.07 38.61 95.07 38.91 ; + POLYGON 8.89 72.91 8.89 72.61 1.99 72.61 1.99 71.93 1.78 71.93 1.78 72.63 1.69 72.63 1.69 72.91 ; + POLYGON 101.81 49.79 101.81 49.51 101.26 49.51 101.26 49.49 99.67 49.49 99.67 49.79 ; + POLYGON 101.365 38.925 101.365 38.595 101.035 38.595 101.035 38.61 91.85 38.61 91.85 38.91 101.035 38.91 101.035 38.925 ; + POLYGON 1.545 36.205 1.545 36.2 2.03 36.2 2.03 35.88 1.545 35.88 1.545 35.875 1.215 35.875 1.215 36.205 ; + POLYGON 2.005 28.045 2.005 28.04 2.03 28.04 2.03 27.72 2.005 27.72 2.005 27.715 1.675 27.715 1.675 27.72 0.97 27.72 0.97 28.04 1.675 28.04 1.675 28.045 ; + POLYGON 101.81 23.95 101.81 23.67 101.26 23.67 101.26 23.65 51.37 23.65 51.37 23.95 ; + POLYGON 20.405 13.085 20.405 13.08 20.43 13.08 20.43 12.76 20.405 12.76 20.405 12.755 19.675 12.755 19.675 13.085 ; POLYGON 73.765 0.165 73.765 0.16 73.98 0.16 73.98 -0.16 73.765 -0.16 73.765 -0.165 73.435 -0.165 73.435 -0.16 73.22 -0.16 73.22 0.16 73.435 0.16 73.435 0.165 ; POLYGON 44.325 0.165 44.325 0.16 44.54 0.16 44.54 -0.16 44.325 -0.16 44.325 -0.165 43.995 -0.165 43.995 -0.16 43.78 -0.16 43.78 0.16 43.995 0.16 43.995 0.165 ; - POLYGON 102.64 81.2 102.64 75.35 101.26 75.35 101.26 74.25 102.64 74.25 102.64 73.99 101.26 73.99 101.26 72.89 102.64 72.89 102.64 72.63 101.26 72.63 101.26 71.53 102.64 71.53 102.64 71.27 101.26 71.27 101.26 70.17 102.64 70.17 102.64 69.91 101.26 69.91 101.26 68.81 102.64 68.81 102.64 68.55 101.26 68.55 101.26 67.45 102.64 67.45 102.64 67.19 101.26 67.19 101.26 66.09 102.64 66.09 102.64 65.83 101.26 65.83 101.26 64.73 102.64 64.73 102.64 64.47 101.26 64.47 101.26 63.37 102.64 63.37 102.64 63.11 101.26 63.11 101.26 62.01 102.64 62.01 102.64 61.75 101.26 61.75 101.26 60.65 102.64 60.65 102.64 60.39 101.26 60.39 101.26 59.29 102.64 59.29 102.64 59.03 101.26 59.03 101.26 57.93 102.64 57.93 102.64 57.67 101.26 57.67 101.26 56.57 102.64 56.57 102.64 56.31 101.26 56.31 101.26 55.21 102.64 55.21 102.64 54.95 101.26 54.95 101.26 53.85 102.64 53.85 102.64 52.91 101.26 52.91 101.26 51.81 102.64 51.81 102.64 50.87 101.26 50.87 101.26 49.77 102.64 49.77 102.64 49.51 101.26 49.51 101.26 48.41 102.64 48.41 102.64 48.15 101.26 48.15 101.26 47.05 102.64 47.05 102.64 46.79 101.26 46.79 101.26 45.69 102.64 45.69 102.64 45.43 101.26 45.43 101.26 44.33 102.64 44.33 102.64 44.07 101.26 44.07 101.26 42.97 102.64 42.97 102.64 42.71 101.26 42.71 101.26 41.61 102.64 41.61 102.64 41.35 101.26 41.35 101.26 40.25 102.64 40.25 102.64 39.99 101.26 39.99 101.26 38.89 102.64 38.89 102.64 38.63 101.26 38.63 101.26 37.53 102.64 37.53 102.64 37.27 101.26 37.27 101.26 36.17 102.64 36.17 102.64 35.91 101.26 35.91 101.26 34.81 102.64 34.81 102.64 34.55 101.26 34.55 101.26 33.45 102.64 33.45 102.64 33.19 101.26 33.19 101.26 32.09 102.64 32.09 102.64 31.83 101.26 31.83 101.26 30.73 102.64 30.73 102.64 30.47 101.26 30.47 101.26 29.37 102.64 29.37 102.64 29.11 101.26 29.11 101.26 28.01 102.64 28.01 102.64 27.75 101.26 27.75 101.26 26.65 102.64 26.65 102.64 26.39 101.26 26.39 101.26 25.29 102.64 25.29 102.64 25.03 101.26 25.03 101.26 23.93 102.64 23.93 102.64 23.67 101.26 23.67 101.26 22.57 102.64 22.57 102.64 22.31 101.26 22.31 101.26 21.21 102.64 21.21 102.64 20.95 101.26 20.95 101.26 19.85 102.64 19.85 102.64 16.72 84.24 16.72 84.24 0.4 18.8 0.4 18.8 16.72 0.4 16.72 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 81.2 ; + POLYGON 102.64 81.2 102.64 78.07 101.26 78.07 101.26 76.97 102.64 76.97 102.64 76.71 101.26 76.71 101.26 75.61 102.64 75.61 102.64 75.35 101.26 75.35 101.26 74.25 102.64 74.25 102.64 73.99 101.26 73.99 101.26 72.89 102.64 72.89 102.64 72.63 101.26 72.63 101.26 71.53 102.64 71.53 102.64 71.27 101.26 71.27 101.26 70.17 102.64 70.17 102.64 69.91 101.26 69.91 101.26 68.81 102.64 68.81 102.64 68.55 101.26 68.55 101.26 67.45 102.64 67.45 102.64 67.19 101.26 67.19 101.26 66.09 102.64 66.09 102.64 65.83 101.26 65.83 101.26 64.73 102.64 64.73 102.64 64.47 101.26 64.47 101.26 63.37 102.64 63.37 102.64 63.11 101.26 63.11 101.26 62.01 102.64 62.01 102.64 61.75 101.26 61.75 101.26 60.65 102.64 60.65 102.64 59.71 101.26 59.71 101.26 58.61 102.64 58.61 102.64 58.35 101.26 58.35 101.26 57.25 102.64 57.25 102.64 56.99 101.26 56.99 101.26 55.89 102.64 55.89 102.64 54.95 101.26 54.95 101.26 53.85 102.64 53.85 102.64 53.59 101.26 53.59 101.26 52.49 102.64 52.49 102.64 52.23 101.26 52.23 101.26 51.13 102.64 51.13 102.64 50.87 101.26 50.87 101.26 49.77 102.64 49.77 102.64 49.51 101.26 49.51 101.26 48.41 102.64 48.41 102.64 48.15 101.26 48.15 101.26 47.05 102.64 47.05 102.64 46.79 101.26 46.79 101.26 45.69 102.64 45.69 102.64 45.43 101.26 45.43 101.26 44.33 102.64 44.33 102.64 44.07 101.26 44.07 101.26 42.97 102.64 42.97 102.64 42.71 101.26 42.71 101.26 41.61 102.64 41.61 102.64 41.35 101.26 41.35 101.26 40.25 102.64 40.25 102.64 39.99 101.26 39.99 101.26 38.89 102.64 38.89 102.64 37.95 101.26 37.95 101.26 36.85 102.64 36.85 102.64 36.59 101.26 36.59 101.26 35.49 102.64 35.49 102.64 35.23 101.26 35.23 101.26 34.13 102.64 34.13 102.64 33.87 101.26 33.87 101.26 32.77 102.64 32.77 102.64 32.51 101.26 32.51 101.26 31.41 102.64 31.41 102.64 31.15 101.26 31.15 101.26 30.05 102.64 30.05 102.64 29.79 101.26 29.79 101.26 28.69 102.64 28.69 102.64 28.43 101.26 28.43 101.26 27.33 102.64 27.33 102.64 27.07 101.26 27.07 101.26 25.97 102.64 25.97 102.64 25.03 101.26 25.03 101.26 23.93 102.64 23.93 102.64 23.67 101.26 23.67 101.26 22.57 102.64 22.57 102.64 22.31 101.26 22.31 101.26 21.21 102.64 21.21 102.64 20.95 101.26 20.95 101.26 19.85 102.64 19.85 102.64 16.72 84.24 16.72 84.24 5.99 82.86 5.99 82.86 4.89 84.24 4.89 84.24 0.4 18.8 0.4 18.8 4.89 20.18 4.89 20.18 5.99 18.8 5.99 18.8 6.25 20.18 6.25 20.18 7.35 18.8 7.35 18.8 11.69 20.18 11.69 20.18 12.79 18.8 12.79 18.8 16.72 0.4 16.72 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 81.2 ; LAYER met4 ; - POLYGON 102.64 81.2 102.64 16.72 84.24 16.72 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 57.59 0.4 57.59 1.76 56.49 1.76 56.49 0.4 55.75 0.4 55.75 1.76 54.65 1.76 54.65 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 46.55 0.4 46.55 1.76 45.45 1.76 45.45 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 18.8 0.4 18.8 16.72 11.59 16.72 11.59 18.08 10.49 18.08 10.49 16.72 0.4 16.72 0.4 81.2 28.74 81.2 28.74 80.6 30.14 80.6 30.14 81.2 43.46 81.2 43.46 80.6 44.86 80.6 44.86 81.2 58.18 81.2 58.18 80.6 59.58 80.6 59.58 81.2 72.9 81.2 72.9 80.6 74.3 80.6 74.3 81.2 ; + POLYGON 102.64 81.2 102.64 16.72 98.07 16.72 98.07 18.08 96.97 18.08 96.97 16.72 84.24 16.72 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 23.55 0.4 23.55 1.76 22.45 1.76 22.45 0.4 18.8 0.4 18.8 16.72 6.99 16.72 6.99 18.08 5.89 18.08 5.89 16.72 5.15 16.72 5.15 18.08 4.05 18.08 4.05 16.72 0.4 16.72 0.4 81.2 28.74 81.2 28.74 80.6 30.14 80.6 30.14 81.2 43.46 81.2 43.46 80.6 44.86 80.6 44.86 81.2 58.18 81.2 58.18 80.6 59.58 80.6 59.58 81.2 72.9 81.2 72.9 80.6 74.3 80.6 74.3 81.2 ; LAYER met5 ; - POLYGON 99.84 78.4 99.84 74.16 96.64 74.16 96.64 64.56 99.84 64.56 99.84 53.76 96.64 53.76 96.64 44.16 99.84 44.16 99.84 33.36 96.64 33.36 96.64 23.76 99.84 23.76 99.84 19.52 81.44 19.52 81.44 3.2 21.6 3.2 21.6 19.52 3.2 19.52 3.2 23.76 6.4 23.76 6.4 33.36 3.2 33.36 3.2 44.16 6.4 44.16 6.4 53.76 3.2 53.76 3.2 64.56 6.4 64.56 6.4 74.16 3.2 74.16 3.2 78.4 ; + POLYGON 101.44 80 101.44 72.56 98.24 72.56 98.24 66.16 101.44 66.16 101.44 52.16 98.24 52.16 98.24 45.76 101.44 45.76 101.44 31.76 98.24 31.76 98.24 25.36 101.44 25.36 101.44 17.92 83.04 17.92 83.04 1.6 20 1.6 20 17.92 1.6 17.92 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 80 ; LAYER met1 ; POLYGON 102.76 81.08 102.76 79.4 102.28 79.4 102.28 78.36 102.76 78.36 102.76 76.68 102.28 76.68 102.28 75.64 102.76 75.64 102.76 73.96 102.28 73.96 102.28 72.92 102.76 72.92 102.76 71.24 102.28 71.24 102.28 70.2 102.76 70.2 102.76 68.52 102.28 68.52 102.28 67.48 102.76 67.48 102.76 65.8 102.28 65.8 102.28 64.76 102.76 64.76 102.76 63.08 102.28 63.08 102.28 62.04 102.76 62.04 102.76 60.36 102.28 60.36 102.28 59.32 102.76 59.32 102.76 57.64 102.28 57.64 102.28 56.6 102.76 56.6 102.76 54.92 102.28 54.92 102.28 53.88 102.76 53.88 102.76 52.2 102.28 52.2 102.28 51.16 102.76 51.16 102.76 49.48 102.28 49.48 102.28 48.44 102.76 48.44 102.76 46.76 102.28 46.76 102.28 45.72 102.76 45.72 102.76 44.04 102.28 44.04 102.28 43 102.76 43 102.76 41.32 102.28 41.32 102.28 40.28 102.76 40.28 102.76 38.6 102.28 38.6 102.28 37.56 102.76 37.56 102.76 35.88 102.28 35.88 102.28 34.84 102.76 34.84 102.76 33.16 102.28 33.16 102.28 32.12 102.76 32.12 102.76 30.44 102.28 30.44 102.28 29.4 102.76 29.4 102.76 27.72 102.28 27.72 102.28 26.68 102.76 26.68 102.76 25 102.28 25 102.28 23.96 102.76 23.96 102.76 22.28 102.28 22.28 102.28 21.24 102.76 21.24 102.76 19.56 102.28 19.56 102.28 18.52 102.76 18.52 102.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; POLYGON 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 18.68 0.52 18.68 2.2 19.16 2.2 19.16 3.24 18.68 3.24 18.68 4.92 19.16 4.92 19.16 5.96 18.68 5.96 18.68 7.64 19.16 7.64 19.16 8.68 18.68 8.68 18.68 10.36 19.16 10.36 19.16 11.4 18.68 11.4 18.68 13.08 19.16 13.08 19.16 14.12 18.68 14.12 18.68 15.8 ; LAYER li1 ; - RECT 96.225 80.79 96.975 81.335 ; - RECT 47.465 80.79 48.215 81.335 ; - RECT 96.225 16.585 96.975 17.13 ; - RECT 47.465 0.265 48.215 0.81 ; - POLYGON 102.7 81.26 102.7 16.66 84.3 16.66 84.3 0.34 18.74 0.34 18.74 16.66 0.34 16.66 0.34 81.26 ; + POLYGON 102.87 81.43 102.87 16.49 84.47 16.49 84.47 0.17 18.57 0.17 18.57 16.49 0.17 16.49 0.17 81.43 ; LAYER mcon ; RECT 102.725 81.515 102.895 81.685 ; RECT 102.265 81.515 102.435 81.685 ; @@ -2325,134 +2473,39 @@ MACRO sb_1__2_ LAYER via ; RECT 73.525 81.525 73.675 81.675 ; RECT 44.085 81.525 44.235 81.675 ; + RECT 96.525 17.945 96.675 18.095 ; + RECT 10.505 17.945 10.655 18.095 ; + RECT 4.525 17.945 4.675 18.095 ; RECT 73.525 16.245 73.675 16.395 ; RECT 44.085 16.245 44.235 16.395 ; - RECT 66.625 1.625 66.775 1.775 ; - RECT 56.045 1.625 56.195 1.775 ; + RECT 48.685 1.625 48.835 1.775 ; + RECT 46.845 1.625 46.995 1.775 ; RECT 73.525 -0.075 73.675 0.075 ; RECT 44.085 -0.075 44.235 0.075 ; LAYER via2 ; RECT 73.5 81.5 73.7 81.7 ; RECT 44.06 81.5 44.26 81.7 ; - RECT 1.74 69.26 1.94 69.46 ; - RECT 101.1 61.1 101.3 61.3 ; - RECT 1.74 61.1 1.94 61.3 ; - RECT 1.74 58.38 1.94 58.58 ; - RECT 101.1 57.02 101.3 57.22 ; - RECT 1.74 43.42 1.94 43.62 ; - RECT 1.28 40.7 1.48 40.9 ; - RECT 101.1 39.34 101.3 39.54 ; - RECT 1.28 31.18 1.48 31.38 ; + RECT 1.28 77.42 1.48 77.62 ; + RECT 101.1 66.54 101.3 66.74 ; + RECT 1.28 57.7 1.48 57.9 ; + RECT 101.1 52.94 101.3 53.14 ; + RECT 1.74 46.14 1.94 46.34 ; + RECT 1.74 39.34 1.94 39.54 ; + RECT 101.56 31.86 101.76 32.06 ; + RECT 1.74 31.18 1.94 31.38 ; + RECT 1.74 25.74 1.94 25.94 ; + RECT 101.56 24.38 101.76 24.58 ; + RECT 1.74 24.38 1.94 24.58 ; + RECT 19.68 12.14 19.88 12.34 ; RECT 73.5 -0.1 73.7 0.1 ; RECT 44.06 -0.1 44.26 0.1 ; LAYER via3 ; RECT 73.5 81.5 73.7 81.7 ; RECT 44.06 81.5 44.26 81.7 ; + RECT 101.1 40.7 101.3 40.9 ; + RECT 20.14 6.7 20.34 6.9 ; RECT 73.5 -0.1 73.7 0.1 ; RECT 44.06 -0.1 44.26 0.1 ; - LAYER fieldpoly ; - POLYGON 102.9 81.46 102.9 16.46 84.5 16.46 84.5 0.14 18.54 0.14 18.54 16.46 0.14 16.46 0.14 81.46 ; - LAYER diff ; - POLYGON 103.04 81.6 103.04 16.32 84.64 16.32 84.64 0 18.4 0 18.4 16.32 0 16.32 0 81.6 ; - LAYER nwell ; - RECT 102.39 77.465 103.23 80.295 ; - RECT -0.19 77.465 3.87 80.295 ; - POLYGON 103.23 74.855 103.23 72.025 102.39 72.025 102.39 73.25 101.93 73.25 101.93 74.855 ; - RECT -0.19 72.025 2.03 74.855 ; - RECT 101.93 66.585 103.23 69.415 ; - RECT -0.19 66.585 2.03 69.415 ; - POLYGON 103.23 63.975 103.23 61.145 102.39 61.145 102.39 62.37 101.93 62.37 101.93 63.975 ; - RECT -0.19 61.145 2.03 63.975 ; - RECT 101.93 55.705 103.23 58.535 ; - RECT -0.19 55.705 2.03 58.535 ; - POLYGON 103.23 53.095 103.23 50.265 102.39 50.265 102.39 51.49 101.93 51.49 101.93 53.095 ; - RECT -0.19 50.265 2.03 53.095 ; - POLYGON 103.23 47.655 103.23 44.825 102.39 44.825 102.39 46.05 101.93 46.05 101.93 47.655 ; - RECT -0.19 44.825 2.03 47.655 ; - POLYGON 103.23 42.215 103.23 39.385 102.39 39.385 102.39 40.61 101.93 40.61 101.93 42.215 ; - RECT -0.19 39.385 2.03 42.215 ; - POLYGON 103.23 36.775 103.23 33.945 102.39 33.945 102.39 35.17 101.93 35.17 101.93 36.775 ; - RECT -0.19 33.945 2.03 36.775 ; - RECT 101.93 28.505 103.23 31.335 ; - RECT -0.19 28.505 2.03 31.335 ; - POLYGON 103.23 25.895 103.23 23.065 102.39 23.065 102.39 24.29 101.93 24.29 101.93 25.895 ; - RECT -0.19 23.065 2.03 25.895 ; - POLYGON 103.23 20.455 103.23 17.625 102.39 17.625 102.39 18.85 101.93 18.85 101.93 20.455 ; - POLYGON 2.03 20.455 2.03 19.23 3.87 19.23 3.87 17.625 -0.19 17.625 -0.19 20.455 ; - POLYGON 84.83 15.015 84.83 12.185 83.53 12.185 83.53 13.79 83.99 13.79 83.99 15.015 ; - POLYGON 20.43 15.015 20.43 13.79 22.27 13.79 22.27 12.185 18.21 12.185 18.21 15.015 ; - POLYGON 84.83 9.575 84.83 6.745 83.99 6.745 83.99 7.97 83.53 7.97 83.53 9.575 ; - POLYGON 20.43 9.575 20.43 8.35 22.27 8.35 22.27 6.745 18.21 6.745 18.21 9.575 ; - POLYGON 84.83 4.135 84.83 1.305 83.99 1.305 83.99 2.53 83.53 2.53 83.53 4.135 ; - RECT 18.21 1.305 22.27 4.135 ; - POLYGON 103.04 81.6 103.04 16.32 84.64 16.32 84.64 0 18.4 0 18.4 16.32 0 16.32 0 81.6 ; - LAYER pwell ; - RECT 97.19 81.55 97.41 81.72 ; - RECT 92.59 81.55 92.81 81.72 ; - RECT 88.91 81.55 89.13 81.72 ; - RECT 85.23 81.55 85.45 81.72 ; - RECT 81.55 81.55 81.77 81.72 ; - RECT 77.87 81.55 78.09 81.72 ; - RECT 74.19 81.55 74.41 81.72 ; - RECT 70.51 81.55 70.73 81.72 ; - RECT 66.83 81.55 67.05 81.72 ; - RECT 63.15 81.55 63.37 81.72 ; - RECT 59.47 81.55 59.69 81.72 ; - RECT 55.79 81.55 56.01 81.72 ; - RECT 52.11 81.55 52.33 81.72 ; - RECT 48.43 81.55 48.65 81.72 ; - RECT 40.61 81.55 40.83 81.72 ; - RECT 36.93 81.55 37.15 81.72 ; - RECT 33.25 81.55 33.47 81.72 ; - RECT 29.57 81.55 29.79 81.72 ; - RECT 25.89 81.55 26.11 81.72 ; - RECT 22.21 81.55 22.43 81.72 ; - RECT 18.53 81.55 18.75 81.72 ; - RECT 14.85 81.55 15.07 81.72 ; - RECT 11.17 81.55 11.39 81.72 ; - RECT 7.49 81.55 7.71 81.72 ; - RECT 3.81 81.55 4.03 81.72 ; - RECT 0.13 81.55 0.35 81.72 ; - RECT 100.915 81.54 101.025 81.66 ; - RECT 44.335 81.54 44.445 81.66 ; - RECT 102.72 81.545 102.84 81.655 ; - RECT 47.06 81.545 47.18 81.655 ; - RECT 46.155 81.54 46.315 81.65 ; - RECT 100.915 16.26 101.025 16.38 ; - RECT 95.375 16.27 95.535 16.38 ; - RECT 93.555 16.26 93.665 16.38 ; - RECT 102.72 16.265 102.84 16.375 ; - RECT 97.19 16.2 97.41 16.37 ; - RECT 89.83 16.2 90.05 16.37 ; - RECT 86.15 16.2 86.37 16.37 ; - RECT 14.85 16.2 15.07 16.37 ; - RECT 11.17 16.2 11.39 16.37 ; - RECT 7.49 16.2 7.71 16.37 ; - RECT 3.81 16.2 4.03 16.37 ; - RECT 0.13 16.2 0.35 16.37 ; - RECT 83.415 -0.05 83.575 0.06 ; - RECT 81.595 -0.06 81.705 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 84.32 -0.055 84.44 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 77.87 -0.12 78.09 0.05 ; - RECT 74.19 -0.12 74.41 0.05 ; - RECT 70.51 -0.12 70.73 0.05 ; - RECT 66.83 -0.12 67.05 0.05 ; - RECT 63.15 -0.12 63.37 0.05 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - POLYGON 103.04 81.6 103.04 16.32 84.64 16.32 84.64 0 18.4 0 18.4 16.32 0 16.32 0 81.6 ; LAYER OVERLAP ; POLYGON 18.4 0 18.4 16.32 0 16.32 0 81.6 103.04 81.6 103.04 16.32 84.64 16.32 84.64 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef index 0b0e82b..61898b7 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -383,7 +371,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 80.24 65.85 81.6 ; + RECT 56.51 80.24 56.65 81.6 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -391,7 +379,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 80.24 42.39 81.6 ; + RECT 33.05 80.24 33.19 81.6 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -399,7 +387,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 55.97 80.24 56.27 81.6 ; + RECT 56.89 80.24 57.19 81.6 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -407,15 +395,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 80.24 52.05 81.6 ; + RECT 32.13 80.24 32.27 81.6 ; END END chany_top_in[3] PIN chany_top_in[4] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 49.53 80.24 49.83 81.6 ; + LAYER met2 ; + RECT 22.93 80.24 23.07 81.6 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -423,7 +411,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 80.24 50.21 81.6 ; + RECT 49.15 80.24 49.29 81.6 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -431,7 +419,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 80.24 55.27 81.6 ; + RECT 63.87 80.24 64.01 81.6 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -439,7 +427,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 80.24 59.41 81.6 ; + RECT 57.43 80.24 57.57 81.6 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -447,15 +435,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 80.24 56.19 81.6 ; + RECT 62.03 80.24 62.17 81.6 ; END END chany_top_in[8] PIN chany_top_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 57.89 80.24 58.03 81.6 ; + LAYER met4 ; + RECT 45.85 80.24 46.15 81.6 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -463,7 +451,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 53.21 80.24 53.51 81.6 ; + RECT 48.61 80.24 48.91 81.6 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -471,15 +459,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 80.24 49.29 81.6 ; + RECT 48.23 80.24 48.37 81.6 ; END END chany_top_in[11] PIN chany_top_in[12] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 47.69 80.24 47.99 81.6 ; + LAYER met2 ; + RECT 52.83 80.24 52.97 81.6 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -487,7 +475,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 80.24 45.15 81.6 ; + RECT 64.79 80.24 64.93 81.6 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -495,7 +483,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 80.24 54.35 81.6 ; + RECT 61.11 80.24 61.25 81.6 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -503,15 +491,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 80.24 51.13 81.6 ; + RECT 59.27 80.24 59.41 81.6 ; END END chany_top_in[15] PIN chany_top_in[16] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 51.37 80.24 51.67 81.6 ; + LAYER met2 ; + RECT 50.07 80.24 50.21 81.6 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -519,15 +507,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 80.24 41.47 81.6 ; + RECT 62.95 80.24 63.09 81.6 ; END END chany_top_in[17] PIN chany_top_in[18] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 39.41 80.24 39.71 81.6 ; + LAYER met2 ; + RECT 58.35 80.24 58.49 81.6 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -535,79 +523,79 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 80.24 39.63 81.6 ; + RECT 60.19 80.24 60.33 81.6 ; END END chany_top_in[19] - PIN top_left_grid_pin_34_[0] + PIN top_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; - RECT 22.85 80.24 23.15 81.6 ; + RECT 24.69 80.24 24.99 81.6 ; END - END top_left_grid_pin_34_[0] - PIN top_left_grid_pin_35_[0] + END top_left_grid_pin_42_[0] + PIN top_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; RECT 10.97 63.92 11.11 65.28 ; END - END top_left_grid_pin_35_[0] - PIN top_left_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.47 80.24 22.61 81.6 ; - END - END top_left_grid_pin_36_[0] - PIN top_left_grid_pin_37_[0] + END top_left_grid_pin_43_[0] + PIN top_left_grid_pin_44_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; - RECT 8.13 63.92 8.43 65.28 ; + RECT 22.85 80.24 23.15 81.6 ; END - END top_left_grid_pin_37_[0] - PIN top_left_grid_pin_38_[0] + END top_left_grid_pin_44_[0] + PIN top_left_grid_pin_45_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 80.24 21.69 81.6 ; + RECT 13.27 63.92 13.41 65.28 ; END - END top_left_grid_pin_38_[0] - PIN top_left_grid_pin_39_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 23.39 80.24 23.53 81.6 ; - END - END top_left_grid_pin_39_[0] - PIN top_left_grid_pin_40_[0] + END top_left_grid_pin_45_[0] + PIN top_left_grid_pin_46_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; RECT 20.63 80.24 20.77 81.6 ; END - END top_left_grid_pin_40_[0] - PIN top_left_grid_pin_41_[0] + END top_left_grid_pin_46_[0] + PIN top_left_grid_pin_47_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 63.92 7.89 65.28 ; + RECT 8.67 63.92 8.81 65.28 ; END - END top_left_grid_pin_41_[0] + END top_left_grid_pin_47_[0] + PIN top_left_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.55 80.24 21.69 81.6 ; + END + END top_left_grid_pin_48_[0] + PIN top_left_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 26.53 80.24 26.83 81.6 ; + END + END top_left_grid_pin_49_[0] PIN top_right_grid_pin_1_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 80.43 80.24 80.57 81.6 ; + RECT 23.85 80.24 23.99 81.6 ; END END top_right_grid_pin_1_[0] PIN chanx_left_in[0] @@ -623,7 +611,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; + RECT 0 55.61 1.38 55.91 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -631,7 +619,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; + RECT 0 38.61 1.38 38.91 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -639,7 +627,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; + RECT 0 12.09 1.38 12.39 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -647,7 +635,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.89 1.38 36.19 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -655,7 +643,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.09 1.38 12.39 ; + RECT 0 16.17 1.38 16.47 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -663,7 +651,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; + RECT 0 20.25 1.38 20.55 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -671,7 +659,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; + RECT 0 6.65 1.38 6.95 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -679,7 +667,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; + RECT 0 9.37 1.38 9.67 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -687,7 +675,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; + RECT 0 21.61 1.38 21.91 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -695,15 +683,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; + RECT 0 41.33 1.38 41.63 ; END END chanx_left_in[10] PIN chanx_left_in[11] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; + LAYER met2 ; + RECT 4.53 63.92 4.67 65.28 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -711,23 +699,23 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; + RECT 0 5.29 1.38 5.59 ; END END chanx_left_in[12] PIN chanx_left_in[13] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; + LAYER met4 ; + RECT 4.45 63.92 4.75 65.28 ; END END chanx_left_in[13] PIN chanx_left_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 5.29 1.38 5.59 ; + LAYER met2 ; + RECT 3.61 63.92 3.75 65.28 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -735,7 +723,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -743,7 +731,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -751,7 +739,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -759,7 +747,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -767,87 +755,63 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 24.33 1.38 24.63 ; END END chanx_left_in[19] - PIN left_top_grid_pin_42_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 24.31 80.24 24.45 81.6 ; - END - END left_top_grid_pin_42_[0] - PIN left_top_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 5.45 63.92 5.59 65.28 ; - END - END left_top_grid_pin_43_[0] - PIN left_top_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 4.45 63.92 4.75 65.28 ; - END - END left_top_grid_pin_44_[0] - PIN left_top_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 6.29 63.92 6.59 65.28 ; - END - END left_top_grid_pin_45_[0] - PIN left_top_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 3.61 63.92 3.75 65.28 ; - END - END left_top_grid_pin_46_[0] - PIN left_top_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.37 63.92 6.51 65.28 ; - END - END left_top_grid_pin_47_[0] - PIN left_top_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.67 63.92 8.81 65.28 ; - END - END left_top_grid_pin_48_[0] - PIN left_top_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.53 63.92 4.67 65.28 ; - END - END left_top_grid_pin_49_[0] PIN left_bottom_grid_pin_1_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 2.23 0 2.37 1.36 ; + LAYER met3 ; + RECT 0 44.05 1.38 44.35 ; END END left_bottom_grid_pin_1_[0] + PIN left_bottom_grid_pin_3_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.81 1.38 49.11 ; + END + END left_bottom_grid_pin_3_[0] + PIN left_bottom_grid_pin_5_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.57 1.38 36.87 ; + END + END left_bottom_grid_pin_5_[0] + PIN left_bottom_grid_pin_7_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 30.45 1.38 30.75 ; + END + END left_bottom_grid_pin_7_[0] + PIN left_bottom_grid_pin_9_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.69 1.38 42.99 ; + END + END left_bottom_grid_pin_9_[0] + PIN left_bottom_grid_pin_11_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 46.09 1.38 46.39 ; + END + END left_bottom_grid_pin_11_[0] PIN ccff_head[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 79.89 80.24 80.19 81.6 ; + LAYER met2 ; + RECT 39.03 80.24 39.17 81.6 ; END END ccff_head[0] PIN chany_top_out[0] @@ -855,7 +819,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 80.24 66.77 81.6 ; + RECT 40.87 80.24 41.01 81.6 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -863,7 +827,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 80.24 40.55 81.6 ; + RECT 33.97 80.24 34.11 81.6 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -871,7 +835,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 80.24 64.93 81.6 ; + RECT 46.39 80.24 46.53 81.6 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -879,7 +843,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 80.24 38.71 81.6 ; + RECT 51.91 80.24 52.05 81.6 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -887,7 +851,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.39 80.24 69.53 81.6 ; + RECT 43.17 80.24 43.31 81.6 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -895,7 +859,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 80.24 57.11 81.6 ; + RECT 25.69 80.24 25.83 81.6 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -903,7 +867,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 80.24 68.61 81.6 ; + RECT 35.35 80.24 35.49 81.6 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -911,7 +875,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 80.24 53.43 81.6 ; + RECT 47.31 80.24 47.45 81.6 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -919,7 +883,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 80.24 67.69 81.6 ; + RECT 37.65 80.24 37.79 81.6 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -927,7 +891,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 80.24 43.31 81.6 ; + RECT 50.99 80.24 51.13 81.6 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -935,7 +899,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 80.24 70.45 81.6 ; + RECT 36.73 80.24 36.87 81.6 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -943,7 +907,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 80.24 48.37 81.6 ; + RECT 53.75 80.24 53.89 81.6 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -951,7 +915,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 80.24 71.37 81.6 ; + RECT 29.37 80.24 29.51 81.6 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -959,7 +923,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 80.24 27.67 81.6 ; + RECT 39.95 80.24 40.09 81.6 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -967,7 +931,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 80.24 60.33 81.6 ; + RECT 26.61 80.24 26.75 81.6 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -975,7 +939,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 80.24 46.07 81.6 ; + RECT 45.47 80.24 45.61 81.6 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -983,15 +947,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 80.24 61.25 81.6 ; + RECT 24.77 80.24 24.91 81.6 ; END END chany_top_out[16] PIN chany_top_out[17] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 41.25 80.24 41.55 81.6 ; + LAYER met2 ; + RECT 28.45 80.24 28.59 81.6 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -999,7 +963,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 80.24 37.79 81.6 ; + RECT 42.25 80.24 42.39 81.6 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1007,7 +971,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 80.24 46.99 81.6 ; + RECT 27.53 80.24 27.67 81.6 ; END END chany_top_out[19] PIN chanx_left_out[0] @@ -1015,7 +979,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1023,7 +987,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; + RECT 0 56.97 1.38 57.27 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -1031,15 +995,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_out[2] PIN chanx_left_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 49.49 1.38 49.79 ; + LAYER met2 ; + RECT 5.45 63.92 5.59 65.28 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1047,7 +1011,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 54.25 1.38 54.55 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1055,15 +1019,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; + RECT 0 61.05 1.38 61.35 ; END END chanx_left_out[5] PIN chanx_left_out[6] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + LAYER met2 ; + RECT 3.15 0 3.29 1.36 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1071,7 +1035,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.69 1.38 42.99 ; + RECT 0 59.69 1.38 59.99 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1079,15 +1043,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 31.81 1.38 32.11 ; END END chanx_left_out[8] PIN chanx_left_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; + LAYER met2 ; + RECT 2.23 0 2.37 1.36 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1095,7 +1059,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 18.89 1.38 19.19 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1103,7 +1067,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1111,7 +1075,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 29.09 1.38 29.39 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1119,7 +1083,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; + RECT 0 8.01 1.38 8.31 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1127,7 +1091,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 25.69 1.38 25.99 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1135,7 +1099,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 17.53 1.38 17.83 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1143,7 +1107,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.01 1.38 8.31 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1151,7 +1115,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 14.81 1.38 15.11 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1159,7 +1123,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 27.05 1.38 27.35 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1167,7 +1131,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 10.73 1.38 11.03 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1175,7 +1139,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 9.37 1.38 9.67 ; + RECT 0 13.45 1.38 13.75 ; END END ccff_tail[0] PIN VDD @@ -1276,30 +1240,30 @@ MACRO sb_2__0_ RECT 18.4 78.795 22.08 78.965 ; RECT 80.96 76.075 84.64 76.245 ; RECT 18.4 76.075 22.08 76.245 ; - RECT 83.72 73.355 84.64 73.525 ; + RECT 80.96 73.355 84.64 73.525 ; RECT 18.4 73.355 22.08 73.525 ; RECT 80.96 70.635 84.64 70.805 ; - RECT 18.4 70.635 22.08 70.805 ; + RECT 18.4 70.635 20.24 70.805 ; RECT 80.96 67.915 84.64 68.085 ; RECT 18.4 67.915 22.08 68.085 ; - RECT 83.72 65.195 84.64 65.365 ; + RECT 80.96 65.195 84.64 65.365 ; RECT 0 65.195 22.08 65.365 ; - RECT 83.72 62.475 84.64 62.645 ; + RECT 84.18 62.475 84.64 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 82.8 59.755 84.64 59.925 ; + RECT 84.18 59.755 84.64 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 82.8 57.035 84.64 57.205 ; - RECT 0 57.035 1.84 57.205 ; + RECT 80.96 57.035 84.64 57.205 ; + RECT 0 57.035 3.68 57.205 ; RECT 80.96 54.315 84.64 54.485 ; - RECT 0 54.315 1.84 54.485 ; + RECT 0 54.315 3.68 54.485 ; RECT 80.96 51.595 84.64 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 83.72 48.875 84.64 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 83.72 46.155 84.64 46.325 ; - RECT 0 46.155 1.84 46.325 ; + RECT 0 51.595 3.68 51.765 ; + RECT 80.96 48.875 84.64 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 80.96 46.155 84.64 46.325 ; + RECT 0 46.155 3.68 46.325 ; RECT 83.72 43.435 84.64 43.605 ; - RECT 0 43.435 1.84 43.605 ; + RECT 0 43.435 3.68 43.605 ; RECT 84.18 40.715 84.64 40.885 ; RECT 0 40.715 1.84 40.885 ; RECT 84.18 37.995 84.64 38.165 ; @@ -1312,51 +1276,47 @@ MACRO sb_2__0_ RECT 0 29.835 1.84 30.005 ; RECT 83.72 27.115 84.64 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 83.72 24.395 84.64 24.565 ; + RECT 80.96 24.395 84.64 24.565 ; RECT 0 24.395 1.84 24.565 ; RECT 80.96 21.675 84.64 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 80.96 18.955 84.64 19.125 ; + RECT 82.8 18.955 84.64 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 84.18 16.235 84.64 16.405 ; + RECT 80.96 16.235 84.64 16.405 ; RECT 0 16.235 1.84 16.405 ; - RECT 82.8 13.515 84.64 13.685 ; + RECT 80.96 13.515 84.64 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 82.8 10.795 84.64 10.965 ; + RECT 83.72 10.795 84.64 10.965 ; RECT 0 10.795 1.84 10.965 ; - RECT 84.18 8.075 84.64 8.245 ; + RECT 83.72 8.075 84.64 8.245 ; RECT 0 8.075 1.84 8.245 ; - RECT 82.8 5.355 84.64 5.525 ; + RECT 83.72 5.355 84.64 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 82.8 2.635 84.64 2.805 ; + RECT 84.18 2.635 84.64 2.805 ; RECT 0 2.635 3.68 2.805 ; RECT 0 -0.085 84.64 0.085 ; LAYER met2 ; RECT 73.46 81.415 73.74 81.785 ; RECT 44.02 81.415 44.3 81.785 ; - RECT 3.09 63.42 3.35 63.74 ; + RECT 34.37 79.74 34.63 80.06 ; RECT 73.46 -0.185 73.74 0.185 ; RECT 44.02 -0.185 44.3 0.185 ; - POLYGON 84.36 81.32 84.36 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 65 1.95 65 1.95 63.64 2.65 63.64 2.65 65 3.33 65 3.33 63.64 4.03 63.64 4.03 65 4.25 65 4.25 63.64 4.95 63.64 4.95 65 5.17 65 5.17 63.64 5.87 63.64 5.87 65 6.09 65 6.09 63.64 6.79 63.64 6.79 65 7.47 65 7.47 63.64 8.17 63.64 8.17 65 8.39 65 8.39 63.64 9.09 63.64 9.09 65 10.69 65 10.69 63.64 11.39 63.64 11.39 65 18.68 65 18.68 81.32 20.35 81.32 20.35 79.96 21.05 79.96 21.05 81.32 21.27 81.32 21.27 79.96 21.97 79.96 21.97 81.32 22.19 81.32 22.19 79.96 22.89 79.96 22.89 81.32 23.11 81.32 23.11 79.96 23.81 79.96 23.81 81.32 24.03 81.32 24.03 79.96 24.73 79.96 24.73 81.32 27.25 81.32 27.25 79.96 27.95 79.96 27.95 81.32 37.37 81.32 37.37 79.96 38.07 79.96 38.07 81.32 38.29 81.32 38.29 79.96 38.99 79.96 38.99 81.32 39.21 81.32 39.21 79.96 39.91 79.96 39.91 81.32 40.13 81.32 40.13 79.96 40.83 79.96 40.83 81.32 41.05 81.32 41.05 79.96 41.75 79.96 41.75 81.32 41.97 81.32 41.97 79.96 42.67 79.96 42.67 81.32 42.89 81.32 42.89 79.96 43.59 79.96 43.59 81.32 44.73 81.32 44.73 79.96 45.43 79.96 45.43 81.32 45.65 81.32 45.65 79.96 46.35 79.96 46.35 81.32 46.57 81.32 46.57 79.96 47.27 79.96 47.27 81.32 47.95 81.32 47.95 79.96 48.65 79.96 48.65 81.32 48.87 81.32 48.87 79.96 49.57 79.96 49.57 81.32 49.79 81.32 49.79 79.96 50.49 79.96 50.49 81.32 50.71 81.32 50.71 79.96 51.41 79.96 51.41 81.32 51.63 81.32 51.63 79.96 52.33 79.96 52.33 81.32 53.01 81.32 53.01 79.96 53.71 79.96 53.71 81.32 53.93 81.32 53.93 79.96 54.63 79.96 54.63 81.32 54.85 81.32 54.85 79.96 55.55 79.96 55.55 81.32 55.77 81.32 55.77 79.96 56.47 79.96 56.47 81.32 56.69 81.32 56.69 79.96 57.39 79.96 57.39 81.32 57.61 81.32 57.61 79.96 58.31 79.96 58.31 81.32 58.99 81.32 58.99 79.96 59.69 79.96 59.69 81.32 59.91 81.32 59.91 79.96 60.61 79.96 60.61 81.32 60.83 81.32 60.83 79.96 61.53 79.96 61.53 81.32 64.51 81.32 64.51 79.96 65.21 79.96 65.21 81.32 65.43 81.32 65.43 79.96 66.13 79.96 66.13 81.32 66.35 81.32 66.35 79.96 67.05 79.96 67.05 81.32 67.27 81.32 67.27 79.96 67.97 79.96 67.97 81.32 68.19 81.32 68.19 79.96 68.89 79.96 68.89 81.32 69.11 81.32 69.11 79.96 69.81 79.96 69.81 81.32 70.03 81.32 70.03 79.96 70.73 79.96 70.73 81.32 70.95 81.32 70.95 79.96 71.65 79.96 71.65 81.32 80.15 81.32 80.15 79.96 80.85 79.96 80.85 81.32 ; + POLYGON 84.36 81.32 84.36 0.28 3.57 0.28 3.57 1.64 2.87 1.64 2.87 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 65 1.95 65 1.95 63.64 2.65 63.64 2.65 65 3.33 65 3.33 63.64 4.03 63.64 4.03 65 4.25 65 4.25 63.64 4.95 63.64 4.95 65 5.17 65 5.17 63.64 5.87 63.64 5.87 65 8.39 65 8.39 63.64 9.09 63.64 9.09 65 10.69 65 10.69 63.64 11.39 63.64 11.39 65 12.99 65 12.99 63.64 13.69 63.64 13.69 65 18.68 65 18.68 81.32 20.35 81.32 20.35 79.96 21.05 79.96 21.05 81.32 21.27 81.32 21.27 79.96 21.97 79.96 21.97 81.32 22.65 81.32 22.65 79.96 23.35 79.96 23.35 81.32 23.57 81.32 23.57 79.96 24.27 79.96 24.27 81.32 24.49 81.32 24.49 79.96 25.19 79.96 25.19 81.32 25.41 81.32 25.41 79.96 26.11 79.96 26.11 81.32 26.33 81.32 26.33 79.96 27.03 79.96 27.03 81.32 27.25 81.32 27.25 79.96 27.95 79.96 27.95 81.32 28.17 81.32 28.17 79.96 28.87 79.96 28.87 81.32 29.09 81.32 29.09 79.96 29.79 79.96 29.79 81.32 31.85 81.32 31.85 79.96 32.55 79.96 32.55 81.32 32.77 81.32 32.77 79.96 33.47 79.96 33.47 81.32 33.69 81.32 33.69 79.96 34.39 79.96 34.39 81.32 35.07 81.32 35.07 79.96 35.77 79.96 35.77 81.32 36.45 81.32 36.45 79.96 37.15 79.96 37.15 81.32 37.37 81.32 37.37 79.96 38.07 79.96 38.07 81.32 38.75 81.32 38.75 79.96 39.45 79.96 39.45 81.32 39.67 81.32 39.67 79.96 40.37 79.96 40.37 81.32 40.59 81.32 40.59 79.96 41.29 79.96 41.29 81.32 41.97 81.32 41.97 79.96 42.67 79.96 42.67 81.32 42.89 81.32 42.89 79.96 43.59 79.96 43.59 81.32 45.19 81.32 45.19 79.96 45.89 79.96 45.89 81.32 46.11 81.32 46.11 79.96 46.81 79.96 46.81 81.32 47.03 81.32 47.03 79.96 47.73 79.96 47.73 81.32 47.95 81.32 47.95 79.96 48.65 79.96 48.65 81.32 48.87 81.32 48.87 79.96 49.57 79.96 49.57 81.32 49.79 81.32 49.79 79.96 50.49 79.96 50.49 81.32 50.71 81.32 50.71 79.96 51.41 79.96 51.41 81.32 51.63 81.32 51.63 79.96 52.33 79.96 52.33 81.32 52.55 81.32 52.55 79.96 53.25 79.96 53.25 81.32 53.47 81.32 53.47 79.96 54.17 79.96 54.17 81.32 56.23 81.32 56.23 79.96 56.93 79.96 56.93 81.32 57.15 81.32 57.15 79.96 57.85 79.96 57.85 81.32 58.07 81.32 58.07 79.96 58.77 79.96 58.77 81.32 58.99 81.32 58.99 79.96 59.69 79.96 59.69 81.32 59.91 81.32 59.91 79.96 60.61 79.96 60.61 81.32 60.83 81.32 60.83 79.96 61.53 79.96 61.53 81.32 61.75 81.32 61.75 79.96 62.45 79.96 62.45 81.32 62.67 81.32 62.67 79.96 63.37 79.96 63.37 81.32 63.59 81.32 63.59 79.96 64.29 79.96 64.29 81.32 64.51 81.32 64.51 79.96 65.21 79.96 65.21 81.32 ; LAYER met4 ; - POLYGON 84.24 81.2 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 0.4 0.4 0.4 64.88 4.05 64.88 4.05 63.52 5.15 63.52 5.15 64.88 5.89 64.88 5.89 63.52 6.99 63.52 6.99 64.88 7.73 64.88 7.73 63.52 8.83 63.52 8.83 64.88 18.8 64.88 18.8 81.2 22.45 81.2 22.45 79.84 23.55 79.84 23.55 81.2 28.74 81.2 28.74 80.6 30.14 80.6 30.14 81.2 39.01 81.2 39.01 79.84 40.11 79.84 40.11 81.2 40.85 81.2 40.85 79.84 41.95 79.84 41.95 81.2 43.46 81.2 43.46 80.6 44.86 80.6 44.86 81.2 47.29 81.2 47.29 79.84 48.39 79.84 48.39 81.2 49.13 81.2 49.13 79.84 50.23 79.84 50.23 81.2 50.97 81.2 50.97 79.84 52.07 79.84 52.07 81.2 52.81 81.2 52.81 79.84 53.91 79.84 53.91 81.2 55.57 81.2 55.57 79.84 56.67 79.84 56.67 81.2 58.18 81.2 58.18 80.6 59.58 80.6 59.58 81.2 72.9 81.2 72.9 80.6 74.3 80.6 74.3 81.2 79.49 81.2 79.49 79.84 80.59 79.84 80.59 81.2 ; + POLYGON 84.24 81.2 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 0.4 0.4 0.4 64.88 4.05 64.88 4.05 63.52 5.15 63.52 5.15 64.88 18.8 64.88 18.8 81.2 22.45 81.2 22.45 79.84 23.55 79.84 23.55 81.2 24.29 81.2 24.29 79.84 25.39 79.84 25.39 81.2 26.13 81.2 26.13 79.84 27.23 79.84 27.23 81.2 28.74 81.2 28.74 80.6 30.14 80.6 30.14 81.2 43.46 81.2 43.46 80.6 44.86 80.6 44.86 81.2 45.45 81.2 45.45 79.84 46.55 79.84 46.55 81.2 48.21 81.2 48.21 79.84 49.31 79.84 49.31 81.2 56.49 81.2 56.49 79.84 57.59 79.84 57.59 81.2 58.18 81.2 58.18 80.6 59.58 80.6 59.58 81.2 72.9 81.2 72.9 80.6 74.3 80.6 74.3 81.2 ; LAYER met3 ; POLYGON 73.765 81.765 73.765 81.76 73.98 81.76 73.98 81.44 73.765 81.44 73.765 81.435 73.435 81.435 73.435 81.44 73.22 81.44 73.22 81.76 73.435 81.76 73.435 81.765 ; POLYGON 44.325 81.765 44.325 81.76 44.54 81.76 44.54 81.44 44.325 81.44 44.325 81.435 43.995 81.435 43.995 81.44 43.78 81.44 43.78 81.76 43.995 81.76 43.995 81.765 ; - POLYGON 67.31 17.15 67.31 16.85 1.78 16.85 1.78 16.87 1.23 16.87 1.23 17.15 ; - POLYGON 42.47 13.07 42.47 12.77 1.78 12.77 1.78 12.79 1.23 12.79 1.23 13.07 ; POLYGON 73.765 0.165 73.765 0.16 73.98 0.16 73.98 -0.16 73.765 -0.16 73.765 -0.165 73.435 -0.165 73.435 -0.16 73.22 -0.16 73.22 0.16 73.435 0.16 73.435 0.165 ; POLYGON 44.325 0.165 44.325 0.16 44.54 0.16 44.54 -0.16 44.325 -0.16 44.325 -0.165 43.995 -0.165 43.995 -0.16 43.78 -0.16 43.78 0.16 43.995 0.16 43.995 0.165 ; - POLYGON 84.24 81.2 84.24 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 64.88 18.8 64.88 18.8 81.2 ; + POLYGON 84.24 81.2 84.24 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 64.88 18.8 64.88 18.8 81.2 ; LAYER met5 ; - POLYGON 81.44 78.4 81.44 57.84 78.24 57.84 78.24 48.24 81.44 48.24 81.44 37.44 78.24 37.44 78.24 27.84 81.44 27.84 81.44 17.04 78.24 17.04 78.24 7.44 81.44 7.44 81.44 3.2 3.2 3.2 3.2 7.44 6.4 7.44 6.4 17.04 3.2 17.04 3.2 27.84 6.4 27.84 6.4 37.44 3.2 37.44 3.2 48.24 6.4 48.24 6.4 57.84 3.2 57.84 3.2 62.08 21.6 62.08 21.6 78.4 ; + POLYGON 83.04 80 83.04 56.24 79.84 56.24 79.84 49.84 83.04 49.84 83.04 35.84 79.84 35.84 79.84 29.44 83.04 29.44 83.04 15.44 79.84 15.44 79.84 9.04 83.04 9.04 83.04 1.6 1.6 1.6 1.6 9.04 4.8 9.04 4.8 15.44 1.6 15.44 1.6 29.44 4.8 29.44 4.8 35.84 1.6 35.84 1.6 49.84 4.8 49.84 4.8 56.24 1.6 56.24 1.6 63.68 20 63.68 20 80 ; LAYER met1 ; POLYGON 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 18.68 65.8 18.68 67.48 19.16 67.48 19.16 68.52 18.68 68.52 18.68 70.2 19.16 70.2 19.16 71.24 18.68 71.24 18.68 72.92 19.16 72.92 19.16 73.96 18.68 73.96 18.68 75.64 19.16 75.64 19.16 76.68 18.68 76.68 18.68 78.36 19.16 78.36 19.16 79.4 18.68 79.4 18.68 81.08 ; POLYGON 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 83.88 16.84 83.88 15.8 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 ; LAYER li1 ; - RECT 47.465 80.79 48.215 81.335 ; - RECT 47.465 0.265 48.215 0.81 ; - POLYGON 84.3 81.26 84.3 0.34 0.34 0.34 0.34 64.94 18.74 64.94 18.74 81.26 ; + POLYGON 84.47 81.43 84.47 0.17 0.17 0.17 0.17 65.11 18.57 65.11 18.57 81.43 ; LAYER mcon ; RECT 84.325 81.515 84.495 81.685 ; RECT 83.865 81.515 84.035 81.685 ; @@ -1985,10 +1945,10 @@ MACRO sb_2__0_ LAYER via ; RECT 73.525 81.525 73.675 81.675 ; RECT 44.085 81.525 44.235 81.675 ; - RECT 69.385 79.825 69.535 79.975 ; + RECT 49.145 79.825 49.295 79.975 ; RECT 73.525 65.205 73.675 65.355 ; RECT 44.085 65.205 44.235 65.355 ; - RECT 5.445 63.505 5.595 63.655 ; + RECT 4.525 63.505 4.675 63.655 ; RECT 3.605 63.505 3.755 63.655 ; RECT 2.225 1.625 2.375 1.775 ; RECT 73.525 -0.075 73.675 0.075 ; @@ -1996,10 +1956,10 @@ MACRO sb_2__0_ LAYER via2 ; RECT 73.5 81.5 73.7 81.7 ; RECT 44.06 81.5 44.26 81.7 ; - RECT 1.28 42.74 1.48 42.94 ; - RECT 1.28 28.46 1.48 28.66 ; - RECT 1.74 26.42 1.94 26.62 ; - RECT 1.74 20.3 1.94 20.5 ; + RECT 1.28 57.02 1.48 57.22 ; + RECT 1.28 41.38 1.48 41.58 ; + RECT 1.74 24.38 1.94 24.58 ; + RECT 1.74 8.06 1.94 8.26 ; RECT 73.5 -0.1 73.7 0.1 ; RECT 44.06 -0.1 44.26 0.1 ; LAYER via3 ; @@ -2007,98 +1967,6 @@ MACRO sb_2__0_ RECT 44.06 81.5 44.26 81.7 ; RECT 73.5 -0.1 73.7 0.1 ; RECT 44.06 -0.1 44.26 0.1 ; - LAYER fieldpoly ; - POLYGON 84.5 81.46 84.5 0.14 0.14 0.14 0.14 65.14 18.54 65.14 18.54 81.46 ; - LAYER diff ; - POLYGON 84.64 81.6 84.64 0 0 0 0 65.28 18.4 65.28 18.4 81.6 ; - LAYER nwell ; - POLYGON 84.83 80.295 84.83 77.465 80.77 77.465 80.77 79.07 83.99 79.07 83.99 80.295 ; - POLYGON 22.27 80.295 22.27 78.69 20.43 78.69 20.43 77.465 18.21 77.465 18.21 80.295 ; - RECT 83.53 72.025 84.83 74.855 ; - RECT 18.21 72.025 22.27 74.855 ; - POLYGON 84.83 69.415 84.83 66.585 83.53 66.585 83.53 67.81 80.77 67.81 80.77 69.415 ; - POLYGON 20.43 69.415 20.43 68.19 22.27 68.19 22.27 66.585 18.21 66.585 18.21 69.415 ; - POLYGON 84.83 63.975 84.83 61.145 83.53 61.145 83.53 62.75 83.99 62.75 83.99 63.975 ; - RECT -0.19 61.145 3.87 63.975 ; - POLYGON 84.83 58.535 84.83 55.705 83.99 55.705 83.99 56.93 82.61 56.93 82.61 58.535 ; - RECT -0.19 55.705 2.03 58.535 ; - POLYGON 84.83 53.095 84.83 50.265 83.99 50.265 83.99 51.49 80.77 51.49 80.77 53.095 ; - RECT -0.19 50.265 2.03 53.095 ; - RECT 83.53 44.825 84.83 47.655 ; - RECT -0.19 44.825 2.03 47.655 ; - RECT 83.99 39.385 84.83 42.215 ; - RECT -0.19 39.385 2.03 42.215 ; - RECT 83.99 33.945 84.83 36.775 ; - RECT -0.19 33.945 2.03 36.775 ; - POLYGON 84.83 31.335 84.83 28.505 83.99 28.505 83.99 29.73 83.53 29.73 83.53 31.335 ; - RECT -0.19 28.505 2.03 31.335 ; - RECT 83.53 23.065 84.83 25.895 ; - RECT -0.19 23.065 2.03 25.895 ; - POLYGON 84.83 20.455 84.83 17.625 83.99 17.625 83.99 18.85 80.77 18.85 80.77 20.455 ; - RECT -0.19 17.625 2.03 20.455 ; - POLYGON 84.83 15.015 84.83 12.185 82.61 12.185 82.61 13.79 83.99 13.79 83.99 15.015 ; - RECT -0.19 12.185 2.03 15.015 ; - RECT 83.99 6.745 84.83 9.575 ; - RECT -0.19 6.745 2.03 9.575 ; - POLYGON 84.83 4.135 84.83 1.305 83.99 1.305 83.99 2.53 82.61 2.53 82.61 4.135 ; - RECT -0.19 1.305 3.87 4.135 ; - POLYGON 84.64 81.6 84.64 0 0 0 0 65.28 18.4 65.28 18.4 81.6 ; - LAYER pwell ; - RECT 77.87 81.55 78.09 81.72 ; - RECT 74.19 81.55 74.41 81.72 ; - RECT 70.51 81.55 70.73 81.72 ; - RECT 66.83 81.55 67.05 81.72 ; - RECT 63.15 81.55 63.37 81.72 ; - RECT 59.47 81.55 59.69 81.72 ; - RECT 55.79 81.55 56.01 81.72 ; - RECT 52.11 81.55 52.33 81.72 ; - RECT 48.43 81.55 48.65 81.72 ; - RECT 40.61 81.55 40.83 81.72 ; - RECT 36.93 81.55 37.15 81.72 ; - RECT 33.25 81.55 33.47 81.72 ; - RECT 29.57 81.55 29.79 81.72 ; - RECT 25.89 81.55 26.11 81.72 ; - RECT 22.21 81.55 22.43 81.72 ; - RECT 18.53 81.55 18.75 81.72 ; - RECT 81.595 81.54 81.705 81.66 ; - RECT 44.335 81.54 44.445 81.66 ; - RECT 84.32 81.545 84.44 81.655 ; - RECT 47.06 81.545 47.18 81.655 ; - RECT 83.415 81.54 83.575 81.65 ; - RECT 46.155 81.54 46.315 81.65 ; - RECT 14.85 65.23 15.07 65.4 ; - RECT 11.17 65.23 11.39 65.4 ; - RECT 7.49 65.23 7.71 65.4 ; - RECT 3.81 65.23 4.03 65.4 ; - RECT 0.13 65.23 0.35 65.4 ; - RECT 83.415 -0.05 83.575 0.06 ; - RECT 81.595 -0.06 81.705 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 84.32 -0.055 84.44 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 77.87 -0.12 78.09 0.05 ; - RECT 74.19 -0.12 74.41 0.05 ; - RECT 70.51 -0.12 70.73 0.05 ; - RECT 66.83 -0.12 67.05 0.05 ; - RECT 63.15 -0.12 63.37 0.05 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - RECT 14.85 -0.12 15.07 0.05 ; - RECT 11.17 -0.12 11.39 0.05 ; - RECT 7.49 -0.12 7.71 0.05 ; - RECT 3.81 -0.12 4.03 0.05 ; - RECT 0.13 -0.12 0.35 0.05 ; - POLYGON 84.64 81.6 84.64 0 0 0 0 65.28 18.4 65.28 18.4 81.6 ; LAYER OVERLAP ; POLYGON 0 0 0 65.28 18.4 65.28 18.4 81.6 84.64 81.6 84.64 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef index 87ebae6..c443aa8 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -375,7 +363,7 @@ MACRO sb_2__1_ USE CLOCK ; PORT LAYER met2 ; - RECT 2.23 16.32 2.37 17.68 ; + RECT 2.23 80.24 2.37 81.6 ; END END prog_clk[0] PIN chany_top_in[0] @@ -383,7 +371,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 96.56 65.85 97.92 ; + RECT 56.51 96.56 56.65 97.92 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -391,7 +379,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 96.56 42.39 97.92 ; + RECT 33.05 96.56 33.19 97.92 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -399,7 +387,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 55.97 96.56 56.27 97.92 ; + RECT 56.89 96.56 57.19 97.92 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -407,15 +395,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 96.56 52.05 97.92 ; + RECT 32.13 96.56 32.27 97.92 ; END END chany_top_in[3] PIN chany_top_in[4] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 49.53 96.56 49.83 97.92 ; + LAYER met2 ; + RECT 22.93 96.56 23.07 97.92 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -423,7 +411,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 96.56 50.21 97.92 ; + RECT 49.15 96.56 49.29 97.92 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -431,7 +419,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 96.56 55.27 97.92 ; + RECT 63.87 96.56 64.01 97.92 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -439,7 +427,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 96.56 59.41 97.92 ; + RECT 57.43 96.56 57.57 97.92 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -447,15 +435,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 96.56 56.19 97.92 ; + RECT 62.03 96.56 62.17 97.92 ; END END chany_top_in[8] PIN chany_top_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 57.89 96.56 58.03 97.92 ; + LAYER met4 ; + RECT 45.85 96.56 46.15 97.92 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -463,7 +451,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 53.21 96.56 53.51 97.92 ; + RECT 48.61 96.56 48.91 97.92 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -471,15 +459,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 96.56 49.29 97.92 ; + RECT 48.23 96.56 48.37 97.92 ; END END chany_top_in[11] PIN chany_top_in[12] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 47.69 96.56 47.99 97.92 ; + LAYER met2 ; + RECT 52.83 96.56 52.97 97.92 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -487,7 +475,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 96.56 45.15 97.92 ; + RECT 64.79 96.56 64.93 97.92 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -495,7 +483,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 96.56 54.35 97.92 ; + RECT 61.11 96.56 61.25 97.92 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -503,15 +491,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 96.56 51.13 97.92 ; + RECT 59.27 96.56 59.41 97.92 ; END END chany_top_in[15] PIN chany_top_in[16] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 51.37 96.56 51.67 97.92 ; + LAYER met2 ; + RECT 50.07 96.56 50.21 97.92 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -519,15 +507,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 96.56 41.47 97.92 ; + RECT 62.95 96.56 63.09 97.92 ; END END chany_top_in[17] PIN chany_top_in[18] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 39.41 96.56 39.71 97.92 ; + LAYER met2 ; + RECT 58.35 96.56 58.49 97.92 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -535,87 +523,87 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 96.56 39.63 97.92 ; + RECT 60.19 96.56 60.33 97.92 ; END END chany_top_in[19] - PIN top_left_grid_pin_34_[0] + PIN top_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 21.55 96.56 21.69 97.92 ; + LAYER met4 ; + RECT 24.69 96.56 24.99 97.92 ; END - END top_left_grid_pin_34_[0] - PIN top_left_grid_pin_35_[0] + END top_left_grid_pin_42_[0] + PIN top_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 24.31 96.56 24.45 97.92 ; + LAYER met4 ; + RECT 36.65 96.56 36.95 97.92 ; END - END top_left_grid_pin_35_[0] - PIN top_left_grid_pin_36_[0] + END top_left_grid_pin_43_[0] + PIN top_left_grid_pin_44_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; RECT 22.85 96.56 23.15 97.92 ; END - END top_left_grid_pin_36_[0] - PIN top_left_grid_pin_37_[0] + END top_left_grid_pin_44_[0] + PIN top_left_grid_pin_45_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 2.69 80.24 2.83 81.6 ; + RECT 21.55 96.56 21.69 97.92 ; END - END top_left_grid_pin_37_[0] - PIN top_left_grid_pin_38_[0] + END top_left_grid_pin_45_[0] + PIN top_left_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 34.81 96.56 35.11 97.92 ; + END + END top_left_grid_pin_46_[0] + PIN top_left_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.67 80.24 8.81 81.6 ; + END + END top_left_grid_pin_47_[0] + PIN top_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; RECT 20.63 96.56 20.77 97.92 ; END - END top_left_grid_pin_38_[0] - PIN top_left_grid_pin_39_[0] + END top_left_grid_pin_48_[0] + PIN top_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 23.39 96.56 23.53 97.92 ; + RECT 13.27 80.24 13.41 81.6 ; END - END top_left_grid_pin_39_[0] - PIN top_left_grid_pin_40_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.47 96.56 22.61 97.92 ; - END - END top_left_grid_pin_40_[0] - PIN top_left_grid_pin_41_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.75 80.24 7.89 81.6 ; - END - END top_left_grid_pin_41_[0] + END top_left_grid_pin_49_[0] PIN top_right_grid_pin_1_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 80.43 96.56 80.57 97.92 ; + RECT 23.85 96.56 23.99 97.92 ; END END top_right_grid_pin_1_[0] PIN chany_bottom_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 55.05 0 55.35 1.36 ; + LAYER met2 ; + RECT 41.33 0 41.47 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -623,7 +611,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 49.15 0 49.29 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -631,7 +619,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 0 68.61 1.36 ; + RECT 50.99 0 51.13 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -639,7 +627,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.73 0 59.87 1.36 ; + RECT 42.25 0 42.39 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -647,7 +635,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.39 0 69.53 1.36 ; + RECT 22.01 0 22.15 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -655,7 +643,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; + RECT 38.57 0 38.71 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -663,7 +651,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 0 70.45 1.36 ; + RECT 39.49 0 39.63 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -671,7 +659,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.65 0 60.79 1.36 ; + RECT 62.95 0 63.09 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -679,7 +667,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 0 67.69 1.36 ; + RECT 61.57 0 61.71 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -687,15 +675,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.57 0 61.71 1.36 ; + RECT 64.79 0 64.93 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 45.85 0 46.15 1.36 ; + LAYER met2 ; + RECT 36.73 0 36.87 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -703,7 +691,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -711,7 +699,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + RECT 40.41 0 40.55 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -719,15 +707,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 31.21 0 31.35 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 52.29 0 52.59 1.36 ; + LAYER met2 ; + RECT 51.91 0 52.05 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -735,7 +723,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + RECT 59.73 0 59.87 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -743,7 +731,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 58.35 0 58.49 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -751,7 +739,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 60.65 0 60.79 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -759,7 +747,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; + RECT 63.87 0 64.01 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -767,7 +755,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 72.15 0 72.29 1.36 ; + RECT 56.51 0 56.65 1.36 ; END END chany_bottom_in[19] PIN bottom_right_grid_pin_1_[0] @@ -775,79 +763,79 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.43 0 80.57 1.36 ; + RECT 25.69 0 25.83 1.36 ; END END bottom_right_grid_pin_1_[0] - PIN bottom_left_grid_pin_34_[0] + PIN bottom_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 3.61 16.32 3.75 17.68 ; END - END bottom_left_grid_pin_34_[0] - PIN bottom_left_grid_pin_35_[0] + END bottom_left_grid_pin_42_[0] + PIN bottom_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; RECT 22.85 0 23.15 1.36 ; END - END bottom_left_grid_pin_35_[0] - PIN bottom_left_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 23.39 0 23.53 1.36 ; - END - END bottom_left_grid_pin_36_[0] - PIN bottom_left_grid_pin_37_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 21.55 0 21.69 1.36 ; - END - END bottom_left_grid_pin_37_[0] - PIN bottom_left_grid_pin_38_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.47 0 22.61 1.36 ; - END - END bottom_left_grid_pin_38_[0] - PIN bottom_left_grid_pin_39_[0] + END bottom_left_grid_pin_43_[0] + PIN bottom_left_grid_pin_44_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 18.4 5.29 19.78 5.59 ; + RECT 0 22.29 1.38 22.59 ; END - END bottom_left_grid_pin_39_[0] - PIN bottom_left_grid_pin_40_[0] + END bottom_left_grid_pin_44_[0] + PIN bottom_left_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.53 16.32 4.67 17.68 ; + END + END bottom_left_grid_pin_45_[0] + PIN bottom_left_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.69 16.32 2.83 17.68 ; + END + END bottom_left_grid_pin_46_[0] + PIN bottom_left_grid_pin_47_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 18.4 6.65 19.78 6.95 ; + RECT 0 20.93 1.38 21.23 ; END - END bottom_left_grid_pin_40_[0] - PIN bottom_left_grid_pin_41_[0] + END bottom_left_grid_pin_47_[0] + PIN bottom_left_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.83 16.32 6.97 17.68 ; + END + END bottom_left_grid_pin_48_[0] + PIN bottom_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 18.4 8.01 19.78 8.31 ; + RECT 0 19.57 1.38 19.87 ; END - END bottom_left_grid_pin_41_[0] + END bottom_left_grid_pin_49_[0] PIN chanx_left_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -855,7 +843,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 78.05 1.38 78.35 ; + RECT 0 23.65 1.38 23.95 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -863,7 +851,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 42.69 1.38 42.99 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -871,7 +859,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 75.33 1.38 75.63 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -879,23 +867,23 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; + RECT 0 35.89 1.38 36.19 ; END END chanx_left_in[4] PIN chanx_left_in[5] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 3.61 16.32 3.75 17.68 ; + LAYER met3 ; + RECT 0 30.45 1.38 30.75 ; END END chanx_left_in[5] PIN chanx_left_in[6] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 25.01 1.38 25.31 ; + LAYER met4 ; + RECT 4.45 16.32 4.75 17.68 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -903,7 +891,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; + RECT 0 65.81 1.38 66.11 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -911,7 +899,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; + RECT 0 69.89 1.38 70.19 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -919,7 +907,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.69 1.38 76.99 ; + RECT 0 61.05 1.38 61.35 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -927,7 +915,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 41.33 1.38 41.63 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -935,7 +923,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -943,7 +931,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.77 1.38 47.07 ; + RECT 0 64.45 1.38 64.75 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -951,7 +939,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 55.61 1.38 55.91 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -959,7 +947,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 77.37 1.38 77.67 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -967,7 +955,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 49.49 1.38 49.79 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -975,7 +963,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -983,7 +971,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 74.65 1.38 74.95 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -991,7 +979,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.13 1.38 48.43 ; + RECT 0 76.01 1.38 76.31 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -999,79 +987,79 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; + RECT 0 29.09 1.38 29.39 ; END END chanx_left_in[19] - PIN left_top_grid_pin_42_[0] + PIN left_bottom_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 18.4 6.65 19.78 6.95 ; + END + END left_bottom_grid_pin_34_[0] + PIN left_bottom_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 18.4 5.29 19.78 5.59 ; + END + END left_bottom_grid_pin_35_[0] + PIN left_bottom_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.67 16.32 8.81 17.68 ; + END + END left_bottom_grid_pin_36_[0] + PIN left_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.45 16.32 5.59 17.68 ; + END + END left_bottom_grid_pin_37_[0] + PIN left_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.63 0 20.77 1.36 ; + END + END left_bottom_grid_pin_38_[0] + PIN left_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.59 16.32 9.73 17.68 ; + END + END left_bottom_grid_pin_39_[0] + PIN left_bottom_grid_pin_40_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; - RECT 24.69 96.56 24.99 97.92 ; + RECT 24.69 0 24.99 1.36 ; END - END left_top_grid_pin_42_[0] - PIN left_top_grid_pin_43_[0] + END left_bottom_grid_pin_40_[0] + PIN left_bottom_grid_pin_41_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 5.45 80.24 5.59 81.6 ; + RECT 7.75 16.32 7.89 17.68 ; END - END left_top_grid_pin_43_[0] - PIN left_top_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 4.45 80.24 4.75 81.6 ; - END - END left_top_grid_pin_44_[0] - PIN left_top_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 6.29 80.24 6.59 81.6 ; - END - END left_top_grid_pin_45_[0] - PIN left_top_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 3.61 80.24 3.75 81.6 ; - END - END left_top_grid_pin_46_[0] - PIN left_top_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.37 80.24 6.51 81.6 ; - END - END left_top_grid_pin_47_[0] - PIN left_top_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.67 80.24 8.81 81.6 ; - END - END left_top_grid_pin_48_[0] - PIN left_top_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.53 80.24 4.67 81.6 ; - END - END left_top_grid_pin_49_[0] + END left_bottom_grid_pin_41_[0] PIN ccff_head[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 79.89 96.56 80.19 97.92 ; + LAYER met2 ; + RECT 39.03 96.56 39.17 97.92 ; END END ccff_head[0] PIN chany_top_out[0] @@ -1079,7 +1067,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 96.56 66.77 97.92 ; + RECT 40.87 96.56 41.01 97.92 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -1087,7 +1075,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 96.56 40.55 97.92 ; + RECT 33.97 96.56 34.11 97.92 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -1095,7 +1083,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 96.56 64.93 97.92 ; + RECT 46.39 96.56 46.53 97.92 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -1103,7 +1091,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 96.56 38.71 97.92 ; + RECT 51.91 96.56 52.05 97.92 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -1111,7 +1099,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.39 96.56 69.53 97.92 ; + RECT 43.17 96.56 43.31 97.92 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -1119,7 +1107,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 96.56 57.11 97.92 ; + RECT 25.69 96.56 25.83 97.92 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -1127,7 +1115,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 96.56 68.61 97.92 ; + RECT 35.35 96.56 35.49 97.92 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -1135,7 +1123,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 96.56 53.43 97.92 ; + RECT 47.31 96.56 47.45 97.92 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -1143,7 +1131,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 96.56 67.69 97.92 ; + RECT 37.65 96.56 37.79 97.92 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -1151,7 +1139,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 96.56 43.31 97.92 ; + RECT 50.99 96.56 51.13 97.92 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -1159,7 +1147,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 96.56 70.45 97.92 ; + RECT 36.73 96.56 36.87 97.92 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -1167,7 +1155,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 96.56 48.37 97.92 ; + RECT 53.75 96.56 53.89 97.92 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -1175,7 +1163,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 96.56 71.37 97.92 ; + RECT 29.37 96.56 29.51 97.92 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -1183,7 +1171,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 96.56 27.67 97.92 ; + RECT 39.95 96.56 40.09 97.92 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -1191,7 +1179,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 96.56 60.33 97.92 ; + RECT 26.61 96.56 26.75 97.92 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -1199,7 +1187,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 96.56 46.07 97.92 ; + RECT 45.47 96.56 45.61 97.92 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -1207,15 +1195,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 96.56 61.25 97.92 ; + RECT 24.77 96.56 24.91 97.92 ; END END chany_top_out[16] PIN chany_top_out[17] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 41.25 96.56 41.55 97.92 ; + LAYER met2 ; + RECT 28.45 96.56 28.59 97.92 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1223,7 +1211,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 96.56 37.79 97.92 ; + RECT 42.25 96.56 42.39 97.92 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1231,7 +1219,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 96.56 46.99 97.92 ; + RECT 27.53 96.56 27.67 97.92 ; END END chany_top_out[19] PIN chany_bottom_out[0] @@ -1239,7 +1227,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + RECT 32.13 0 32.27 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -1247,7 +1235,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 79.05 0 79.19 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -1255,7 +1243,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 78.13 0 78.27 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -1263,7 +1251,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; + RECT 37.65 0 37.79 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -1271,7 +1259,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 0 66.77 1.36 ; + RECT 29.37 0 29.51 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -1279,7 +1267,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + RECT 22.93 0 23.07 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -1287,7 +1275,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; + RECT 23.85 0 23.99 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -1295,7 +1283,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1303,7 +1291,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 0 65.85 1.36 ; + RECT 43.17 0 43.31 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -1311,7 +1299,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 50.07 0 50.21 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1319,7 +1307,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; + RECT 34.43 0 34.57 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -1327,15 +1315,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; + RECT 28.45 0 28.59 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 56.89 0 57.19 1.36 ; + LAYER met2 ; + RECT 26.61 0 26.75 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -1343,7 +1331,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + RECT 24.77 0 24.91 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -1351,7 +1339,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 0 64.93 1.36 ; + RECT 30.29 0 30.43 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -1359,7 +1347,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 47.31 0 47.45 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1367,7 +1355,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 0 71.37 1.36 ; + RECT 27.53 0 27.67 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -1375,7 +1363,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 33.05 0 33.19 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -1383,7 +1371,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -1391,7 +1379,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_out[19] PIN chanx_left_out[0] @@ -1399,7 +1387,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; + RECT 0 45.41 1.38 45.71 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1407,7 +1395,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; + RECT 0 56.97 1.38 57.27 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -1415,7 +1403,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; + RECT 0 71.25 1.38 71.55 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1423,7 +1411,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; + RECT 0 27.73 1.38 28.03 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1431,7 +1419,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1439,7 +1427,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 46.77 1.38 47.07 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1447,7 +1435,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; + RECT 0 38.61 1.38 38.91 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1455,7 +1443,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 54.25 1.38 54.55 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1463,7 +1451,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; + RECT 0 44.05 1.38 44.35 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -1471,7 +1459,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1479,7 +1467,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 67.17 1.38 67.47 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1487,7 +1475,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1495,15 +1483,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; + RECT 0 26.37 1.38 26.67 ; END END chanx_left_out[12] PIN chanx_left_out[13] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; + LAYER met4 ; + RECT 6.29 16.32 6.59 17.68 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1511,7 +1499,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 23.65 1.38 23.95 ; + RECT 0 25.01 1.38 25.31 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1519,7 +1507,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1527,7 +1515,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; + RECT 0 59.69 1.38 59.99 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1535,7 +1523,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.97 1.38 74.27 ; + RECT 0 37.25 1.38 37.55 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1543,7 +1531,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 31.81 1.38 32.11 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1551,7 +1539,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 68.53 1.38 68.83 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1559,7 +1547,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; + RECT 0 63.09 1.38 63.39 ; END END ccff_tail[0] PIN VDD @@ -1667,53 +1655,53 @@ MACRO sb_2__1_ OBS LAYER li1 ; RECT 18.4 97.835 84.64 98.005 ; - RECT 83.72 95.115 84.64 95.285 ; + RECT 84.18 95.115 84.64 95.285 ; RECT 18.4 95.115 22.08 95.285 ; - RECT 83.72 92.395 84.64 92.565 ; + RECT 84.18 92.395 84.64 92.565 ; RECT 18.4 92.395 20.24 92.565 ; RECT 83.72 89.675 84.64 89.845 ; RECT 18.4 89.675 22.08 89.845 ; RECT 83.72 86.955 84.64 87.125 ; RECT 18.4 86.955 22.08 87.125 ; - RECT 83.72 84.235 84.64 84.405 ; - RECT 18.4 84.235 22.08 84.405 ; - RECT 83.72 81.515 84.64 81.685 ; - RECT 0 81.515 22.08 81.685 ; - RECT 83.72 78.795 84.64 78.965 ; + RECT 80.96 84.235 84.64 84.405 ; + RECT 18.4 84.235 20.24 84.405 ; + RECT 80.96 81.515 84.64 81.685 ; + RECT 0 81.515 20.24 81.685 ; + RECT 80.96 78.795 84.64 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 82.8 76.075 84.64 76.245 ; + RECT 80.96 76.075 84.64 76.245 ; RECT 0 76.075 1.84 76.245 ; - RECT 82.8 73.355 84.64 73.525 ; + RECT 83.72 73.355 84.64 73.525 ; RECT 0 73.355 1.84 73.525 ; - RECT 83.72 70.635 84.64 70.805 ; + RECT 80.96 70.635 84.64 70.805 ; RECT 0 70.635 1.84 70.805 ; RECT 80.96 67.915 84.64 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 80.96 65.195 84.64 65.365 ; + RECT 83.72 65.195 84.64 65.365 ; RECT 0 65.195 1.84 65.365 ; RECT 83.72 62.475 84.64 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 84.18 59.755 84.64 59.925 ; - RECT 0 59.755 1.84 59.925 ; + RECT 0 62.475 3.68 62.645 ; + RECT 83.72 59.755 84.64 59.925 ; + RECT 0 59.755 3.68 59.925 ; RECT 83.72 57.035 84.64 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 80.96 54.315 84.64 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 80.96 51.595 84.64 51.765 ; + RECT 0 57.035 3.68 57.205 ; + RECT 83.72 54.315 84.64 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 83.72 51.595 84.64 51.765 ; RECT 0 51.595 1.84 51.765 ; RECT 83.72 48.875 84.64 49.045 ; - RECT 0 48.875 3.68 49.045 ; + RECT 0 48.875 1.84 49.045 ; RECT 83.72 46.155 84.64 46.325 ; - RECT 0 46.155 3.68 46.325 ; + RECT 0 46.155 1.84 46.325 ; RECT 83.72 43.435 84.64 43.605 ; - RECT 0 43.435 1.84 43.605 ; + RECT 0 43.435 3.68 43.605 ; RECT 83.72 40.715 84.64 40.885 ; - RECT 0 40.715 1.84 40.885 ; + RECT 0 40.715 3.68 40.885 ; RECT 83.72 37.995 84.64 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 80.96 35.275 84.64 35.445 ; - RECT 0 35.275 1.84 35.445 ; - RECT 80.96 32.555 84.64 32.725 ; + RECT 0 37.995 3.68 38.165 ; + RECT 83.72 35.275 84.64 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 83.72 32.555 84.64 32.725 ; RECT 0 32.555 1.84 32.725 ; RECT 83.72 29.835 84.64 30.005 ; RECT 0 29.835 1.84 30.005 ; @@ -1721,55 +1709,52 @@ MACRO sb_2__1_ RECT 0 27.115 1.84 27.285 ; RECT 83.72 24.395 84.64 24.565 ; RECT 0 24.395 1.84 24.565 ; - RECT 82.8 21.675 84.64 21.845 ; - RECT 0 21.675 3.68 21.845 ; - RECT 82.8 18.955 84.64 19.125 ; + RECT 83.72 21.675 84.64 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 83.72 18.955 84.64 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 80.96 16.235 84.64 16.405 ; + RECT 83.72 16.235 84.64 16.405 ; RECT 0 16.235 22.08 16.405 ; - RECT 80.96 13.515 84.64 13.685 ; - RECT 18.4 13.515 22.08 13.685 ; + RECT 83.72 13.515 84.64 13.685 ; + RECT 18.4 13.515 20.24 13.685 ; RECT 83.72 10.795 84.64 10.965 ; - RECT 18.4 10.795 20.24 10.965 ; + RECT 18.4 10.795 22.08 10.965 ; RECT 83.72 8.075 84.64 8.245 ; - RECT 18.4 8.075 20.24 8.245 ; - RECT 83.72 5.355 84.64 5.525 ; + RECT 18.4 8.075 22.08 8.245 ; + RECT 84.18 5.355 84.64 5.525 ; RECT 18.4 5.355 20.24 5.525 ; - RECT 83.72 2.635 84.64 2.805 ; + RECT 84.18 2.635 84.64 2.805 ; RECT 18.4 2.635 22.08 2.805 ; RECT 18.4 -0.085 84.64 0.085 ; LAYER met2 ; RECT 73.46 97.735 73.74 98.105 ; RECT 44.02 97.735 44.3 98.105 ; - RECT 21.03 96.06 21.29 96.38 ; - RECT 4.93 79.74 5.19 80.06 ; - RECT 70.71 1.54 70.97 1.86 ; - RECT 52.31 1.54 52.57 1.86 ; + RECT 33.45 96.06 33.71 96.38 ; + RECT 41.73 1.54 41.99 1.86 ; + RECT 28.85 1.54 29.11 1.86 ; RECT 73.46 -0.185 73.74 0.185 ; RECT 44.02 -0.185 44.3 0.185 ; - POLYGON 84.36 97.64 84.36 0.28 80.85 0.28 80.85 1.64 80.15 1.64 80.15 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 18.68 0.28 18.68 16.6 4.03 16.6 4.03 17.96 3.33 17.96 3.33 16.6 2.65 16.6 2.65 17.96 1.95 17.96 1.95 16.6 0.28 16.6 0.28 81.32 2.41 81.32 2.41 79.96 3.11 79.96 3.11 81.32 3.33 81.32 3.33 79.96 4.03 79.96 4.03 81.32 4.25 81.32 4.25 79.96 4.95 79.96 4.95 81.32 5.17 81.32 5.17 79.96 5.87 79.96 5.87 81.32 6.09 81.32 6.09 79.96 6.79 79.96 6.79 81.32 7.47 81.32 7.47 79.96 8.17 79.96 8.17 81.32 8.39 81.32 8.39 79.96 9.09 79.96 9.09 81.32 18.68 81.32 18.68 97.64 20.35 97.64 20.35 96.28 21.05 96.28 21.05 97.64 21.27 97.64 21.27 96.28 21.97 96.28 21.97 97.64 22.19 97.64 22.19 96.28 22.89 96.28 22.89 97.64 23.11 97.64 23.11 96.28 23.81 96.28 23.81 97.64 24.03 97.64 24.03 96.28 24.73 96.28 24.73 97.64 27.25 97.64 27.25 96.28 27.95 96.28 27.95 97.64 37.37 97.64 37.37 96.28 38.07 96.28 38.07 97.64 38.29 97.64 38.29 96.28 38.99 96.28 38.99 97.64 39.21 97.64 39.21 96.28 39.91 96.28 39.91 97.64 40.13 97.64 40.13 96.28 40.83 96.28 40.83 97.64 41.05 97.64 41.05 96.28 41.75 96.28 41.75 97.64 41.97 97.64 41.97 96.28 42.67 96.28 42.67 97.64 42.89 97.64 42.89 96.28 43.59 96.28 43.59 97.64 44.73 97.64 44.73 96.28 45.43 96.28 45.43 97.64 45.65 97.64 45.65 96.28 46.35 96.28 46.35 97.64 46.57 97.64 46.57 96.28 47.27 96.28 47.27 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 48.87 97.64 48.87 96.28 49.57 96.28 49.57 97.64 49.79 97.64 49.79 96.28 50.49 96.28 50.49 97.64 50.71 97.64 50.71 96.28 51.41 96.28 51.41 97.64 51.63 97.64 51.63 96.28 52.33 96.28 52.33 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 53.93 97.64 53.93 96.28 54.63 96.28 54.63 97.64 54.85 97.64 54.85 96.28 55.55 96.28 55.55 97.64 55.77 97.64 55.77 96.28 56.47 96.28 56.47 97.64 56.69 97.64 56.69 96.28 57.39 96.28 57.39 97.64 57.61 97.64 57.61 96.28 58.31 96.28 58.31 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 60.83 97.64 60.83 96.28 61.53 96.28 61.53 97.64 64.51 97.64 64.51 96.28 65.21 96.28 65.21 97.64 65.43 97.64 65.43 96.28 66.13 96.28 66.13 97.64 66.35 97.64 66.35 96.28 67.05 96.28 67.05 97.64 67.27 97.64 67.27 96.28 67.97 96.28 67.97 97.64 68.19 97.64 68.19 96.28 68.89 96.28 68.89 97.64 69.11 97.64 69.11 96.28 69.81 96.28 69.81 97.64 70.03 97.64 70.03 96.28 70.73 96.28 70.73 97.64 70.95 97.64 70.95 96.28 71.65 96.28 71.65 97.64 80.15 97.64 80.15 96.28 80.85 96.28 80.85 97.64 ; + POLYGON 84.36 97.64 84.36 0.28 79.47 0.28 79.47 1.64 78.77 1.64 78.77 0.28 78.55 0.28 78.55 1.64 77.85 1.64 77.85 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 18.68 0.28 18.68 16.6 10.01 16.6 10.01 17.96 9.31 17.96 9.31 16.6 9.09 16.6 9.09 17.96 8.39 17.96 8.39 16.6 8.17 16.6 8.17 17.96 7.47 17.96 7.47 16.6 7.25 16.6 7.25 17.96 6.55 17.96 6.55 16.6 5.87 16.6 5.87 17.96 5.17 17.96 5.17 16.6 4.95 16.6 4.95 17.96 4.25 17.96 4.25 16.6 4.03 16.6 4.03 17.96 3.33 17.96 3.33 16.6 3.11 16.6 3.11 17.96 2.41 17.96 2.41 16.6 0.28 16.6 0.28 81.32 1.95 81.32 1.95 79.96 2.65 79.96 2.65 81.32 8.39 81.32 8.39 79.96 9.09 79.96 9.09 81.32 12.99 81.32 12.99 79.96 13.69 79.96 13.69 81.32 18.68 81.32 18.68 97.64 20.35 97.64 20.35 96.28 21.05 96.28 21.05 97.64 21.27 97.64 21.27 96.28 21.97 96.28 21.97 97.64 22.65 97.64 22.65 96.28 23.35 96.28 23.35 97.64 23.57 97.64 23.57 96.28 24.27 96.28 24.27 97.64 24.49 97.64 24.49 96.28 25.19 96.28 25.19 97.64 25.41 97.64 25.41 96.28 26.11 96.28 26.11 97.64 26.33 97.64 26.33 96.28 27.03 96.28 27.03 97.64 27.25 97.64 27.25 96.28 27.95 96.28 27.95 97.64 28.17 97.64 28.17 96.28 28.87 96.28 28.87 97.64 29.09 97.64 29.09 96.28 29.79 96.28 29.79 97.64 31.85 97.64 31.85 96.28 32.55 96.28 32.55 97.64 32.77 97.64 32.77 96.28 33.47 96.28 33.47 97.64 33.69 97.64 33.69 96.28 34.39 96.28 34.39 97.64 35.07 97.64 35.07 96.28 35.77 96.28 35.77 97.64 36.45 97.64 36.45 96.28 37.15 96.28 37.15 97.64 37.37 97.64 37.37 96.28 38.07 96.28 38.07 97.64 38.75 97.64 38.75 96.28 39.45 96.28 39.45 97.64 39.67 97.64 39.67 96.28 40.37 96.28 40.37 97.64 40.59 97.64 40.59 96.28 41.29 96.28 41.29 97.64 41.97 97.64 41.97 96.28 42.67 96.28 42.67 97.64 42.89 97.64 42.89 96.28 43.59 96.28 43.59 97.64 45.19 97.64 45.19 96.28 45.89 96.28 45.89 97.64 46.11 97.64 46.11 96.28 46.81 96.28 46.81 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 48.87 97.64 48.87 96.28 49.57 96.28 49.57 97.64 49.79 97.64 49.79 96.28 50.49 96.28 50.49 97.64 50.71 97.64 50.71 96.28 51.41 96.28 51.41 97.64 51.63 97.64 51.63 96.28 52.33 96.28 52.33 97.64 52.55 97.64 52.55 96.28 53.25 96.28 53.25 97.64 53.47 97.64 53.47 96.28 54.17 96.28 54.17 97.64 56.23 97.64 56.23 96.28 56.93 96.28 56.93 97.64 57.15 97.64 57.15 96.28 57.85 96.28 57.85 97.64 58.07 97.64 58.07 96.28 58.77 96.28 58.77 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 60.83 97.64 60.83 96.28 61.53 96.28 61.53 97.64 61.75 97.64 61.75 96.28 62.45 96.28 62.45 97.64 62.67 97.64 62.67 96.28 63.37 96.28 63.37 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 64.51 97.64 64.51 96.28 65.21 96.28 65.21 97.64 ; LAYER met4 ; - POLYGON 84.24 97.52 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 57.59 0.4 57.59 1.76 56.49 1.76 56.49 0.4 55.75 0.4 55.75 1.76 54.65 1.76 54.65 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 46.55 0.4 46.55 1.76 45.45 1.76 45.45 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 23.55 0.4 23.55 1.76 22.45 1.76 22.45 0.4 18.8 0.4 18.8 16.72 0.4 16.72 0.4 81.2 4.05 81.2 4.05 79.84 5.15 79.84 5.15 81.2 5.89 81.2 5.89 79.84 6.99 79.84 6.99 81.2 18.8 81.2 18.8 97.52 22.45 97.52 22.45 96.16 23.55 96.16 23.55 97.52 24.29 97.52 24.29 96.16 25.39 96.16 25.39 97.52 28.74 97.52 28.74 96.92 30.14 96.92 30.14 97.52 39.01 97.52 39.01 96.16 40.11 96.16 40.11 97.52 40.85 97.52 40.85 96.16 41.95 96.16 41.95 97.52 43.46 97.52 43.46 96.92 44.86 96.92 44.86 97.52 47.29 97.52 47.29 96.16 48.39 96.16 48.39 97.52 49.13 97.52 49.13 96.16 50.23 96.16 50.23 97.52 50.97 97.52 50.97 96.16 52.07 96.16 52.07 97.52 52.81 97.52 52.81 96.16 53.91 96.16 53.91 97.52 55.57 97.52 55.57 96.16 56.67 96.16 56.67 97.52 58.18 97.52 58.18 96.92 59.58 96.92 59.58 97.52 72.9 97.52 72.9 96.92 74.3 96.92 74.3 97.52 79.49 97.52 79.49 96.16 80.59 96.16 80.59 97.52 ; + POLYGON 84.24 97.52 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 25.39 0.4 25.39 1.76 24.29 1.76 24.29 0.4 23.55 0.4 23.55 1.76 22.45 1.76 22.45 0.4 18.8 0.4 18.8 16.72 6.99 16.72 6.99 18.08 5.89 18.08 5.89 16.72 5.15 16.72 5.15 18.08 4.05 18.08 4.05 16.72 0.4 16.72 0.4 81.2 18.8 81.2 18.8 97.52 22.45 97.52 22.45 96.16 23.55 96.16 23.55 97.52 24.29 97.52 24.29 96.16 25.39 96.16 25.39 97.52 28.74 97.52 28.74 96.92 30.14 96.92 30.14 97.52 34.41 97.52 34.41 96.16 35.51 96.16 35.51 97.52 36.25 97.52 36.25 96.16 37.35 96.16 37.35 97.52 43.46 97.52 43.46 96.92 44.86 96.92 44.86 97.52 45.45 97.52 45.45 96.16 46.55 96.16 46.55 97.52 48.21 97.52 48.21 96.16 49.31 96.16 49.31 97.52 56.49 97.52 56.49 96.16 57.59 96.16 57.59 97.52 58.18 97.52 58.18 96.92 59.58 96.92 59.58 97.52 72.9 97.52 72.9 96.92 74.3 96.92 74.3 97.52 ; LAYER met3 ; POLYGON 73.765 98.085 73.765 98.08 73.98 98.08 73.98 97.76 73.765 97.76 73.765 97.755 73.435 97.755 73.435 97.76 73.22 97.76 73.22 98.08 73.435 98.08 73.435 98.085 ; POLYGON 44.325 98.085 44.325 98.08 44.54 98.08 44.54 97.76 44.325 97.76 44.325 97.755 43.995 97.755 43.995 97.76 43.78 97.76 43.78 98.08 43.995 98.08 43.995 98.085 ; - POLYGON 14.87 70.19 14.87 69.89 1.78 69.89 1.78 69.91 1.23 69.91 1.23 70.19 ; - POLYGON 2.005 50.485 2.005 50.48 2.03 50.48 2.03 50.16 2.005 50.16 2.005 50.155 1.275 50.155 1.275 50.485 ; - POLYGON 4.29 41.63 4.29 41.33 1.99 41.33 1.99 40.65 1.78 40.65 1.78 41.35 1.69 41.35 1.69 41.63 ; - POLYGON 2.005 37.565 2.005 37.56 2.03 37.56 2.03 37.24 2.005 37.24 2.005 37.235 1.275 37.235 1.275 37.565 ; + POLYGON 2.03 68.16 2.03 68.15 4.75 68.15 4.75 67.85 2.03 67.85 2.03 67.84 1.65 67.84 1.65 68.16 ; + POLYGON 44.77 57.95 44.77 57.65 1.23 57.65 1.23 57.93 1.78 57.93 1.78 57.95 ; + POLYGON 39.71 55.23 39.71 54.93 1.23 54.93 1.23 55.21 1.78 55.21 1.78 55.23 ; + POLYGON 2.03 24.64 2.03 24.63 6.13 24.63 6.13 24.33 2.03 24.33 2.03 24.32 1.65 24.32 1.65 24.64 ; POLYGON 73.765 0.165 73.765 0.16 73.98 0.16 73.98 -0.16 73.765 -0.16 73.765 -0.165 73.435 -0.165 73.435 -0.16 73.22 -0.16 73.22 0.16 73.435 0.16 73.435 0.165 ; POLYGON 44.325 0.165 44.325 0.16 44.54 0.16 44.54 -0.16 44.325 -0.16 44.325 -0.165 43.995 -0.165 43.995 -0.16 43.78 -0.16 43.78 0.16 43.995 0.16 43.995 0.165 ; - POLYGON 84.24 97.52 84.24 0.4 18.8 0.4 18.8 4.89 20.18 4.89 20.18 5.99 18.8 5.99 18.8 6.25 20.18 6.25 20.18 7.35 18.8 7.35 18.8 7.61 20.18 7.61 20.18 8.71 18.8 8.71 18.8 16.72 0.4 16.72 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 77.65 1.78 77.65 1.78 78.75 0.4 78.75 0.4 81.2 18.8 81.2 18.8 97.52 ; + POLYGON 84.24 97.52 84.24 0.4 18.8 0.4 18.8 4.89 20.18 4.89 20.18 5.99 18.8 5.99 18.8 6.25 20.18 6.25 20.18 7.35 18.8 7.35 18.8 16.72 0.4 16.72 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 66.77 1.78 66.77 1.78 67.87 0.4 67.87 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 81.2 18.8 81.2 18.8 97.52 ; LAYER met5 ; - POLYGON 81.44 94.72 81.44 74.16 78.24 74.16 78.24 64.56 81.44 64.56 81.44 53.76 78.24 53.76 78.24 44.16 81.44 44.16 81.44 33.36 78.24 33.36 78.24 23.76 81.44 23.76 81.44 3.2 21.6 3.2 21.6 19.52 3.2 19.52 3.2 23.76 6.4 23.76 6.4 33.36 3.2 33.36 3.2 44.16 6.4 44.16 6.4 53.76 3.2 53.76 3.2 64.56 6.4 64.56 6.4 74.16 3.2 74.16 3.2 78.4 21.6 78.4 21.6 94.72 ; + POLYGON 83.04 96.32 83.04 72.56 79.84 72.56 79.84 66.16 83.04 66.16 83.04 52.16 79.84 52.16 79.84 45.76 83.04 45.76 83.04 31.76 79.84 31.76 79.84 25.36 83.04 25.36 83.04 1.6 20 1.6 20 17.92 1.6 17.92 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 80 20 80 20 96.32 ; LAYER met1 ; POLYGON 84.36 97.4 84.36 95.72 83.88 95.72 83.88 94.68 84.36 94.68 84.36 93 83.88 93 83.88 91.96 84.36 91.96 84.36 90.28 83.88 90.28 83.88 89.24 84.36 89.24 84.36 87.56 83.88 87.56 83.88 86.52 84.36 86.52 84.36 84.84 83.88 84.84 83.88 83.8 84.36 83.8 84.36 82.12 18.68 82.12 18.68 83.8 19.16 83.8 19.16 84.84 18.68 84.84 18.68 86.52 19.16 86.52 19.16 87.56 18.68 87.56 18.68 89.24 19.16 89.24 19.16 90.28 18.68 90.28 18.68 91.96 19.16 91.96 19.16 93 18.68 93 18.68 94.68 19.16 94.68 19.16 95.72 18.68 95.72 18.68 97.4 ; POLYGON 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 83.88 65.8 83.88 64.76 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; POLYGON 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 18.68 0.52 18.68 2.2 19.16 2.2 19.16 3.24 18.68 3.24 18.68 4.92 19.16 4.92 19.16 5.96 18.68 5.96 18.68 7.64 19.16 7.64 19.16 8.68 18.68 8.68 18.68 10.36 19.16 10.36 19.16 11.4 18.68 11.4 18.68 13.08 19.16 13.08 19.16 14.12 18.68 14.12 18.68 15.8 ; LAYER li1 ; - RECT 47.465 97.11 48.215 97.655 ; - RECT 47.465 0.265 48.215 0.81 ; - POLYGON 84.3 97.58 84.3 0.34 18.74 0.34 18.74 16.66 0.34 16.66 0.34 81.26 18.74 81.26 18.74 97.58 ; + POLYGON 84.47 97.75 84.47 0.17 18.57 0.17 18.57 16.49 0.17 16.49 0.17 81.43 18.57 81.43 18.57 97.75 ; LAYER mcon ; RECT 84.325 97.835 84.495 98.005 ; RECT 83.865 97.835 84.035 98.005 ; @@ -2563,134 +2548,34 @@ MACRO sb_2__1_ RECT 73.525 97.845 73.675 97.995 ; RECT 44.085 97.845 44.235 97.995 ; RECT 59.265 96.145 59.415 96.295 ; - RECT 49.145 96.145 49.295 96.295 ; + RECT 40.865 96.145 41.015 96.295 ; RECT 73.525 81.525 73.675 81.675 ; RECT 44.085 81.525 44.235 81.675 ; - RECT 6.365 79.825 6.515 79.975 ; + RECT 13.265 79.825 13.415 79.975 ; + RECT 5.445 17.945 5.595 18.095 ; RECT 73.525 16.245 73.675 16.395 ; RECT 44.085 16.245 44.235 16.395 ; - RECT 66.625 1.625 66.775 1.775 ; - RECT 50.985 1.625 51.135 1.775 ; - RECT 23.385 1.625 23.535 1.775 ; + RECT 37.645 1.625 37.795 1.775 ; + RECT 24.765 1.625 24.915 1.775 ; RECT 73.525 -0.075 73.675 0.075 ; RECT 44.085 -0.075 44.235 0.075 ; LAYER via2 ; RECT 73.5 97.82 73.7 98.02 ; RECT 44.06 97.82 44.26 98.02 ; - RECT 1.28 76.74 1.48 76.94 ; - RECT 1.74 74.02 1.94 74.22 ; - RECT 1.74 52.26 1.94 52.46 ; - RECT 1.28 31.86 1.48 32.06 ; - RECT 1.28 27.78 1.48 27.98 ; - RECT 19.68 6.7 19.88 6.9 ; + RECT 1.28 73.34 1.48 73.54 ; + RECT 1.74 61.1 1.94 61.3 ; + RECT 1.74 46.82 1.94 47.02 ; + RECT 1.28 25.06 1.48 25.26 ; + RECT 19.68 5.34 19.88 5.54 ; RECT 73.5 -0.1 73.7 0.1 ; RECT 44.06 -0.1 44.26 0.1 ; LAYER via3 ; RECT 73.5 97.82 73.7 98.02 ; RECT 44.06 97.82 44.26 98.02 ; - RECT 1.74 65.18 1.94 65.38 ; RECT 1.74 30.5 1.94 30.7 ; - RECT 20.14 8.06 20.34 8.26 ; + RECT 1.74 26.42 1.94 26.62 ; RECT 73.5 -0.1 73.7 0.1 ; RECT 44.06 -0.1 44.26 0.1 ; - LAYER fieldpoly ; - POLYGON 84.5 97.78 84.5 0.14 18.54 0.14 18.54 16.46 0.14 16.46 0.14 81.46 18.54 81.46 18.54 97.78 ; - LAYER diff ; - POLYGON 84.64 97.92 84.64 0 18.4 0 18.4 16.32 0 16.32 0 81.6 18.4 81.6 18.4 97.92 ; - LAYER nwell ; - POLYGON 84.83 96.615 84.83 93.785 83.53 93.785 83.53 95.39 83.99 95.39 83.99 96.615 ; - POLYGON 22.27 96.615 22.27 95.01 20.43 95.01 20.43 93.785 18.21 93.785 18.21 96.615 ; - RECT 83.53 88.345 84.83 91.175 ; - POLYGON 20.43 91.175 20.43 89.95 22.27 89.95 22.27 88.345 18.21 88.345 18.21 91.175 ; - RECT 83.53 82.905 84.83 85.735 ; - POLYGON 20.43 85.735 20.43 84.51 22.27 84.51 22.27 82.905 18.21 82.905 18.21 85.735 ; - RECT 83.53 77.465 84.83 80.295 ; - POLYGON 3.87 80.295 3.87 78.69 2.03 78.69 2.03 77.465 -0.19 77.465 -0.19 80.295 ; - POLYGON 84.83 74.855 84.83 72.025 83.53 72.025 83.53 73.25 82.61 73.25 82.61 74.855 ; - RECT -0.19 72.025 2.03 74.855 ; - POLYGON 84.83 69.415 84.83 66.585 80.77 66.585 80.77 68.19 83.53 68.19 83.53 69.415 ; - RECT -0.19 66.585 2.03 69.415 ; - POLYGON 84.83 63.975 84.83 61.145 83.99 61.145 83.99 62.37 83.53 62.37 83.53 63.975 ; - RECT -0.19 61.145 2.03 63.975 ; - POLYGON 84.83 58.535 84.83 55.705 83.53 55.705 83.53 57.31 83.99 57.31 83.99 58.535 ; - RECT -0.19 55.705 2.03 58.535 ; - POLYGON 84.83 53.095 84.83 50.265 83.53 50.265 83.53 51.49 80.77 51.49 80.77 53.095 ; - RECT -0.19 50.265 2.03 53.095 ; - POLYGON 84.83 47.655 84.83 44.825 83.53 44.825 83.53 46.43 83.99 46.43 83.99 47.655 ; - POLYGON 3.87 47.655 3.87 46.05 2.03 46.05 2.03 44.825 -0.19 44.825 -0.19 47.655 ; - POLYGON 84.83 42.215 84.83 39.385 83.53 39.385 83.53 40.99 83.99 40.99 83.99 42.215 ; - RECT -0.19 39.385 2.03 42.215 ; - POLYGON 84.83 36.775 84.83 33.945 80.77 33.945 80.77 35.55 83.99 35.55 83.99 36.775 ; - RECT -0.19 33.945 2.03 36.775 ; - POLYGON 84.83 31.335 84.83 28.505 83.99 28.505 83.99 29.73 83.53 29.73 83.53 31.335 ; - RECT -0.19 28.505 2.03 31.335 ; - POLYGON 84.83 25.895 84.83 23.065 83.99 23.065 83.99 24.29 83.53 24.29 83.53 25.895 ; - RECT -0.19 23.065 2.03 25.895 ; - POLYGON 84.83 20.455 84.83 17.625 83.53 17.625 83.53 18.85 82.61 18.85 82.61 20.455 ; - RECT -0.19 17.625 3.87 20.455 ; - POLYGON 84.83 15.015 84.83 12.185 83.53 12.185 83.53 13.41 80.77 13.41 80.77 15.015 ; - POLYGON 22.27 15.015 22.27 13.41 20.43 13.41 20.43 12.185 18.21 12.185 18.21 15.015 ; - POLYGON 84.83 9.575 84.83 6.745 83.99 6.745 83.99 7.97 83.53 7.97 83.53 9.575 ; - RECT 18.21 6.745 20.43 9.575 ; - POLYGON 84.83 4.135 84.83 1.305 83.99 1.305 83.99 2.53 83.53 2.53 83.53 4.135 ; - POLYGON 20.43 4.135 20.43 2.91 22.27 2.91 22.27 1.305 18.21 1.305 18.21 4.135 ; - POLYGON 84.64 97.92 84.64 0 18.4 0 18.4 16.32 0 16.32 0 81.6 18.4 81.6 18.4 97.92 ; - LAYER pwell ; - RECT 77.87 97.87 78.09 98.04 ; - RECT 74.19 97.87 74.41 98.04 ; - RECT 70.51 97.87 70.73 98.04 ; - RECT 66.83 97.87 67.05 98.04 ; - RECT 63.15 97.87 63.37 98.04 ; - RECT 59.47 97.87 59.69 98.04 ; - RECT 55.79 97.87 56.01 98.04 ; - RECT 52.11 97.87 52.33 98.04 ; - RECT 48.43 97.87 48.65 98.04 ; - RECT 40.61 97.87 40.83 98.04 ; - RECT 36.93 97.87 37.15 98.04 ; - RECT 33.25 97.87 33.47 98.04 ; - RECT 29.57 97.87 29.79 98.04 ; - RECT 25.89 97.87 26.11 98.04 ; - RECT 22.21 97.87 22.43 98.04 ; - RECT 18.53 97.87 18.75 98.04 ; - RECT 81.595 97.86 81.705 97.98 ; - RECT 44.335 97.86 44.445 97.98 ; - RECT 84.32 97.865 84.44 97.975 ; - RECT 47.06 97.865 47.18 97.975 ; - RECT 83.415 97.86 83.575 97.97 ; - RECT 46.155 97.86 46.315 97.97 ; - RECT 14.85 81.55 15.07 81.72 ; - RECT 11.17 81.55 11.39 81.72 ; - RECT 7.49 81.55 7.71 81.72 ; - RECT 3.81 81.55 4.03 81.72 ; - RECT 0.13 81.55 0.35 81.72 ; - RECT 14.85 16.2 15.07 16.37 ; - RECT 11.17 16.2 11.39 16.37 ; - RECT 7.49 16.2 7.71 16.37 ; - RECT 3.81 16.2 4.03 16.37 ; - RECT 0.13 16.2 0.35 16.37 ; - RECT 83.415 -0.05 83.575 0.06 ; - RECT 81.595 -0.06 81.705 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 84.32 -0.055 84.44 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 77.87 -0.12 78.09 0.05 ; - RECT 74.19 -0.12 74.41 0.05 ; - RECT 70.51 -0.12 70.73 0.05 ; - RECT 66.83 -0.12 67.05 0.05 ; - RECT 63.15 -0.12 63.37 0.05 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - POLYGON 84.64 97.92 84.64 0 18.4 0 18.4 16.32 0 16.32 0 81.6 18.4 81.6 18.4 97.92 ; LAYER OVERLAP ; POLYGON 18.4 0 18.4 16.32 0 16.32 0 81.6 18.4 81.6 18.4 97.92 84.64 97.92 84.64 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef index 2441fed..f57ed33 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef @@ -7,18 +7,6 @@ END UNITS MANUFACTURINGGRID 0.005 ; -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER fieldpoly - TYPE MASTERSLICE ; -END fieldpoly - LAYER li1 TYPE ROUTING ; DIRECTION VERTICAL ; @@ -81,13 +69,13 @@ LAYER met5 WIDTH 1.6 ; END met5 -LAYER diff +LAYER nwell TYPE MASTERSLICE ; -END diff +END nwell -LAYER licon1 +LAYER pwell TYPE MASTERSLICE ; -END licon1 +END pwell LAYER OVERLAP TYPE OVERLAP ; @@ -382,8 +370,8 @@ MACRO sb_2__2_ DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 55.05 0 55.35 1.36 ; + LAYER met2 ; + RECT 41.33 0 41.47 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -391,7 +379,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 49.15 0 49.29 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -399,7 +387,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 0 68.61 1.36 ; + RECT 50.99 0 51.13 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -407,7 +395,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.73 0 59.87 1.36 ; + RECT 42.25 0 42.39 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -415,7 +403,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.39 0 69.53 1.36 ; + RECT 22.01 0 22.15 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -423,7 +411,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; + RECT 38.57 0 38.71 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -431,7 +419,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 0 70.45 1.36 ; + RECT 39.49 0 39.63 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -439,7 +427,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.65 0 60.79 1.36 ; + RECT 62.95 0 63.09 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -447,7 +435,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 0 67.69 1.36 ; + RECT 61.57 0 61.71 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -455,15 +443,15 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.57 0 61.71 1.36 ; + RECT 64.79 0 64.93 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 45.85 0 46.15 1.36 ; + LAYER met2 ; + RECT 36.73 0 36.87 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -471,7 +459,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -479,7 +467,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + RECT 40.41 0 40.55 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -487,15 +475,15 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 31.21 0 31.35 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 52.29 0 52.59 1.36 ; + LAYER met2 ; + RECT 51.91 0 52.05 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -503,7 +491,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + RECT 59.73 0 59.87 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -511,7 +499,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 58.35 0 58.49 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -519,7 +507,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 60.65 0 60.79 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -527,7 +515,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; + RECT 63.87 0 64.01 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -535,7 +523,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 72.15 0 72.29 1.36 ; + RECT 56.51 0 56.65 1.36 ; END END chany_bottom_in[19] PIN bottom_right_grid_pin_1_[0] @@ -543,79 +531,79 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.43 0 80.57 1.36 ; + RECT 25.69 0 25.83 1.36 ; END END bottom_right_grid_pin_1_[0] - PIN bottom_left_grid_pin_34_[0] + PIN bottom_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 0 21.69 1.36 ; + RECT 3.61 16.32 3.75 17.68 ; END - END bottom_left_grid_pin_34_[0] - PIN bottom_left_grid_pin_35_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.47 0 22.61 1.36 ; - END - END bottom_left_grid_pin_35_[0] - PIN bottom_left_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; - END - END bottom_left_grid_pin_36_[0] - PIN bottom_left_grid_pin_37_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.97 16.32 11.11 17.68 ; - END - END bottom_left_grid_pin_37_[0] - PIN bottom_left_grid_pin_38_[0] + END bottom_left_grid_pin_42_[0] + PIN bottom_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met4 ; - RECT 10.89 16.32 11.19 17.68 ; + RECT 22.85 0 23.15 1.36 ; END - END bottom_left_grid_pin_38_[0] - PIN bottom_left_grid_pin_39_[0] + END bottom_left_grid_pin_43_[0] + PIN bottom_left_grid_pin_44_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 8.67 16.32 8.81 17.68 ; + LAYER met3 ; + RECT 18.4 8.01 19.78 8.31 ; END - END bottom_left_grid_pin_39_[0] - PIN bottom_left_grid_pin_40_[0] + END bottom_left_grid_pin_44_[0] + PIN bottom_left_grid_pin_45_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 6.83 16.32 6.97 17.68 ; + LAYER met3 ; + RECT 18.4 10.73 19.78 11.03 ; END - END bottom_left_grid_pin_40_[0] - PIN bottom_left_grid_pin_41_[0] + END bottom_left_grid_pin_45_[0] + PIN bottom_left_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 18.4 6.65 19.78 6.95 ; + END + END bottom_left_grid_pin_46_[0] + PIN bottom_left_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 18.4 9.37 19.78 9.67 ; + END + END bottom_left_grid_pin_47_[0] + PIN bottom_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; RECT 18.4 5.29 19.78 5.59 ; END - END bottom_left_grid_pin_41_[0] + END bottom_left_grid_pin_48_[0] + PIN bottom_left_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.37 16.32 6.51 17.68 ; + END + END bottom_left_grid_pin_49_[0] PIN chanx_left_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 27.05 1.38 27.35 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -623,7 +611,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 67.85 1.38 68.15 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -631,7 +619,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -639,7 +627,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -647,7 +635,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; + RECT 0 37.93 1.38 38.23 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -655,7 +643,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -663,7 +651,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -671,7 +659,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 25.69 1.38 25.99 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -679,7 +667,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -687,7 +675,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 60.37 1.38 60.67 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -695,7 +683,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; + RECT 0 63.77 1.38 64.07 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -703,7 +691,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 36.57 1.38 36.87 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -711,7 +699,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; + RECT 0 29.77 1.38 30.07 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -719,7 +707,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 20.25 1.38 20.55 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -727,7 +715,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 77.37 1.38 77.67 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -735,7 +723,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; + RECT 0 76.01 1.38 76.31 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -743,7 +731,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; + RECT 0 59.01 1.38 59.31 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -751,7 +739,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; + RECT 0 52.21 1.38 52.51 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -759,7 +747,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 40.65 1.38 40.95 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -767,23 +755,87 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 24.33 1.38 24.63 ; END END chanx_left_in[19] PIN left_top_grid_pin_1_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 3.61 80.24 3.75 81.6 ; + LAYER met3 ; + RECT 0 62.41 1.38 62.71 ; END END left_top_grid_pin_1_[0] + PIN left_bottom_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 6.29 16.32 6.59 17.68 ; + END + END left_bottom_grid_pin_34_[0] + PIN left_bottom_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 18.4 12.09 19.78 12.39 ; + END + END left_bottom_grid_pin_35_[0] + PIN left_bottom_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.67 16.32 8.81 17.68 ; + END + END left_bottom_grid_pin_36_[0] + PIN left_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.45 16.32 5.59 17.68 ; + END + END left_bottom_grid_pin_37_[0] + PIN left_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.63 0 20.77 1.36 ; + END + END left_bottom_grid_pin_38_[0] + PIN left_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.59 16.32 9.73 17.68 ; + END + END left_bottom_grid_pin_39_[0] + PIN left_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.97 16.32 11.11 17.68 ; + END + END left_bottom_grid_pin_40_[0] + PIN left_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.75 16.32 7.89 17.68 ; + END + END left_bottom_grid_pin_41_[0] PIN ccff_head[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 2.69 80.24 2.83 81.6 ; + RECT 2.23 80.24 2.37 81.6 ; END END ccff_head[0] PIN chany_bottom_out[0] @@ -791,7 +843,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + RECT 32.13 0 32.27 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -799,7 +851,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 79.05 0 79.19 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -807,7 +859,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 78.13 0 78.27 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -815,7 +867,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; + RECT 37.65 0 37.79 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -823,7 +875,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 0 66.77 1.36 ; + RECT 29.37 0 29.51 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -831,7 +883,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + RECT 22.93 0 23.07 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -839,7 +891,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; + RECT 23.85 0 23.99 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -847,7 +899,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -855,7 +907,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 0 65.85 1.36 ; + RECT 43.17 0 43.31 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -863,7 +915,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 50.07 0 50.21 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -871,7 +923,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; + RECT 34.43 0 34.57 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -879,15 +931,15 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; + RECT 28.45 0 28.59 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 56.89 0 57.19 1.36 ; + LAYER met2 ; + RECT 26.61 0 26.75 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -895,7 +947,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + RECT 24.77 0 24.91 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -903,7 +955,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 0 64.93 1.36 ; + RECT 30.29 0 30.43 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -911,7 +963,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 47.31 0 47.45 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -919,7 +971,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 0 71.37 1.36 ; + RECT 27.53 0 27.67 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -927,7 +979,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 33.05 0 33.19 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -935,7 +987,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -943,7 +995,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_out[19] PIN chanx_left_out[0] @@ -951,7 +1003,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 57.65 1.38 57.95 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -959,7 +1011,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 66.49 1.38 66.79 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -967,7 +1019,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + RECT 0 55.61 1.38 55.91 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -975,7 +1027,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -983,7 +1035,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; + RECT 0 50.85 1.38 51.15 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -991,7 +1043,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 28.41 1.38 28.71 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -999,7 +1051,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1007,7 +1059,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 31.13 1.38 31.43 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1015,15 +1067,15 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_out[8] PIN chanx_left_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + LAYER met4 ; + RECT 4.45 16.32 4.75 17.68 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1031,7 +1083,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 74.65 1.38 74.95 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1039,7 +1091,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 35.21 1.38 35.51 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1047,7 +1099,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 71.93 1.38 72.23 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1055,7 +1107,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; + RECT 0 53.57 1.38 53.87 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1063,7 +1115,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1071,7 +1123,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1079,7 +1131,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 33.85 1.38 34.15 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1087,7 +1139,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; + RECT 0 32.49 1.38 32.79 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1095,7 +1147,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1103,7 +1155,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1111,9 +1163,41 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 21.61 1.38 21.91 ; END END ccff_tail[0] + PIN SC_IN_TOP + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.53 16.32 4.67 17.68 ; + END + END SC_IN_TOP + PIN SC_IN_BOT + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.17 80.24 43.31 81.6 ; + END + END SC_IN_BOT + PIN SC_OUT_TOP + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.91 80.24 29.05 81.6 ; + END + END SC_OUT_TOP + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.25 80.24 42.39 81.6 ; + END + END SC_OUT_BOT PIN VDD DIRECTION INPUT ; USE POWER ; @@ -1210,90 +1294,90 @@ MACRO sb_2__2_ RECT 0 81.515 84.64 81.685 ; RECT 84.18 78.795 84.64 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 84.18 76.075 84.64 76.245 ; - RECT 0 76.075 1.84 76.245 ; - RECT 84.18 73.355 84.64 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 83.72 70.635 84.64 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 83.72 67.915 84.64 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 83.72 65.195 84.64 65.365 ; - RECT 0 65.195 1.84 65.365 ; + RECT 80.96 76.075 84.64 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 80.96 73.355 84.64 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 82.8 70.635 84.64 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 82.8 67.915 84.64 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 84.18 65.195 84.64 65.365 ; + RECT 0 65.195 3.68 65.365 ; RECT 82.8 62.475 84.64 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 80.96 59.755 84.64 59.925 ; + RECT 0 62.475 3.68 62.645 ; + RECT 82.8 59.755 84.64 59.925 ; RECT 0 59.755 1.84 59.925 ; - RECT 80.96 57.035 84.64 57.205 ; + RECT 84.18 57.035 84.64 57.205 ; RECT 0 57.035 1.84 57.205 ; - RECT 80.96 54.315 84.64 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 80.96 51.595 84.64 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 82.8 48.875 84.64 49.045 ; + RECT 84.18 54.315 84.64 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 83.72 51.595 84.64 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 83.72 48.875 84.64 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 82.8 46.155 84.64 46.325 ; - RECT 0 46.155 1.84 46.325 ; + RECT 80.96 46.155 84.64 46.325 ; + RECT 0 46.155 3.68 46.325 ; RECT 80.96 43.435 84.64 43.605 ; - RECT 0 43.435 1.84 43.605 ; + RECT 0 43.435 3.68 43.605 ; RECT 80.96 40.715 84.64 40.885 ; - RECT 0 40.715 1.84 40.885 ; + RECT 0 40.715 3.68 40.885 ; RECT 83.72 37.995 84.64 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 83.72 35.275 84.64 35.445 ; + RECT 0 37.995 3.68 38.165 ; + RECT 80.96 35.275 84.64 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 83.72 32.555 84.64 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 84.18 29.835 84.64 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 82.8 27.115 84.64 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 82.8 24.395 84.64 24.565 ; + RECT 80.96 32.555 84.64 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 83.72 29.835 84.64 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 84.18 27.115 84.64 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 84.18 24.395 84.64 24.565 ; RECT 0 24.395 1.84 24.565 ; - RECT 84.18 21.675 84.64 21.845 ; + RECT 83.72 21.675 84.64 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 82.8 18.955 84.64 19.125 ; + RECT 80.96 18.955 84.64 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 82.8 16.235 84.64 16.405 ; + RECT 80.96 16.235 84.64 16.405 ; RECT 0 16.235 22.08 16.405 ; - RECT 83.72 13.515 84.64 13.685 ; + RECT 84.18 13.515 84.64 13.685 ; RECT 18.4 13.515 22.08 13.685 ; - RECT 83.72 10.795 84.64 10.965 ; + RECT 80.96 10.795 84.64 10.965 ; RECT 18.4 10.795 22.08 10.965 ; - RECT 83.72 8.075 84.64 8.245 ; - RECT 18.4 8.075 22.08 8.245 ; - RECT 84.18 5.355 84.64 5.525 ; + RECT 80.96 8.075 84.64 8.245 ; + RECT 18.4 8.075 20.24 8.245 ; + RECT 80.96 5.355 84.64 5.525 ; RECT 18.4 5.355 22.08 5.525 ; - RECT 84.18 2.635 84.64 2.805 ; + RECT 80.96 2.635 84.64 2.805 ; RECT 18.4 2.635 22.08 2.805 ; RECT 18.4 -0.085 84.64 0.085 ; LAYER met2 ; RECT 73.46 81.415 73.74 81.785 ; RECT 44.02 81.415 44.3 81.785 ; + RECT 10.45 17.86 10.71 18.18 ; + RECT 52.31 1.54 52.57 1.86 ; + RECT 36.21 1.54 36.47 1.86 ; + RECT 21.49 1.54 21.75 1.86 ; RECT 73.46 -0.185 73.74 0.185 ; RECT 44.02 -0.185 44.3 0.185 ; - POLYGON 84.36 81.32 84.36 0.28 80.85 0.28 80.85 1.64 80.15 1.64 80.15 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 18.68 0.28 18.68 16.6 11.39 16.6 11.39 17.96 10.69 17.96 10.69 16.6 9.09 16.6 9.09 17.96 8.39 17.96 8.39 16.6 7.25 16.6 7.25 17.96 6.55 17.96 6.55 16.6 2.65 16.6 2.65 17.96 1.95 17.96 1.95 16.6 0.28 16.6 0.28 81.32 2.41 81.32 2.41 79.96 3.11 79.96 3.11 81.32 3.33 81.32 3.33 79.96 4.03 79.96 4.03 81.32 ; + POLYGON 84.36 81.32 84.36 0.28 79.47 0.28 79.47 1.64 78.77 1.64 78.77 0.28 78.55 0.28 78.55 1.64 77.85 1.64 77.85 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 18.68 0.28 18.68 16.6 11.39 16.6 11.39 17.96 10.69 17.96 10.69 16.6 10.01 16.6 10.01 17.96 9.31 17.96 9.31 16.6 9.09 16.6 9.09 17.96 8.39 17.96 8.39 16.6 8.17 16.6 8.17 17.96 7.47 17.96 7.47 16.6 6.79 16.6 6.79 17.96 6.09 17.96 6.09 16.6 5.87 16.6 5.87 17.96 5.17 17.96 5.17 16.6 4.95 16.6 4.95 17.96 4.25 17.96 4.25 16.6 4.03 16.6 4.03 17.96 3.33 17.96 3.33 16.6 2.65 16.6 2.65 17.96 1.95 17.96 1.95 16.6 0.28 16.6 0.28 81.32 1.95 81.32 1.95 79.96 2.65 79.96 2.65 81.32 28.63 81.32 28.63 79.96 29.33 79.96 29.33 81.32 41.97 81.32 41.97 79.96 42.67 79.96 42.67 81.32 42.89 81.32 42.89 79.96 43.59 79.96 43.59 81.32 ; LAYER met4 ; - POLYGON 84.24 81.2 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 57.59 0.4 57.59 1.76 56.49 1.76 56.49 0.4 55.75 0.4 55.75 1.76 54.65 1.76 54.65 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 46.55 0.4 46.55 1.76 45.45 1.76 45.45 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 18.8 0.4 18.8 16.72 11.59 16.72 11.59 18.08 10.49 18.08 10.49 16.72 0.4 16.72 0.4 81.2 28.74 81.2 28.74 80.6 30.14 80.6 30.14 81.2 43.46 81.2 43.46 80.6 44.86 80.6 44.86 81.2 58.18 81.2 58.18 80.6 59.58 80.6 59.58 81.2 72.9 81.2 72.9 80.6 74.3 80.6 74.3 81.2 ; + POLYGON 84.24 81.2 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 23.55 0.4 23.55 1.76 22.45 1.76 22.45 0.4 18.8 0.4 18.8 16.72 6.99 16.72 6.99 18.08 5.89 18.08 5.89 16.72 5.15 16.72 5.15 18.08 4.05 18.08 4.05 16.72 0.4 16.72 0.4 81.2 28.74 81.2 28.74 80.6 30.14 80.6 30.14 81.2 43.46 81.2 43.46 80.6 44.86 80.6 44.86 81.2 58.18 81.2 58.18 80.6 59.58 80.6 59.58 81.2 72.9 81.2 72.9 80.6 74.3 80.6 74.3 81.2 ; LAYER met3 ; POLYGON 73.765 81.765 73.765 81.76 73.98 81.76 73.98 81.44 73.765 81.44 73.765 81.435 73.435 81.435 73.435 81.44 73.22 81.44 73.22 81.76 73.435 81.76 73.435 81.765 ; POLYGON 44.325 81.765 44.325 81.76 44.54 81.76 44.54 81.44 44.325 81.44 44.325 81.435 43.995 81.435 43.995 81.44 43.78 81.44 43.78 81.76 43.995 81.76 43.995 81.765 ; - POLYGON 19.47 55.23 19.47 54.93 1.23 54.93 1.23 55.21 1.78 55.21 1.78 55.23 ; - POLYGON 26.83 52.51 26.83 52.21 1.23 52.21 1.23 52.49 1.78 52.49 1.78 52.51 ; - POLYGON 11.65 25.31 11.65 25.01 1.78 25.01 1.78 25.03 1.08 25.03 1.08 25.31 ; - POLYGON 2.03 19.88 2.03 19.87 13.49 19.87 13.49 19.57 2.03 19.57 2.03 19.56 1.65 19.56 1.65 19.88 ; + POLYGON 2.03 55.24 2.03 55.23 60.87 55.23 60.87 54.93 2.03 54.93 2.03 54.92 1.65 54.92 1.65 55.24 ; + POLYGON 2.005 21.245 2.005 21.23 3.83 21.23 3.83 20.93 2.005 20.93 2.005 20.915 1.675 20.915 1.675 21.245 ; POLYGON 73.765 0.165 73.765 0.16 73.98 0.16 73.98 -0.16 73.765 -0.16 73.765 -0.165 73.435 -0.165 73.435 -0.16 73.22 -0.16 73.22 0.16 73.435 0.16 73.435 0.165 ; POLYGON 44.325 0.165 44.325 0.16 44.54 0.16 44.54 -0.16 44.325 -0.16 44.325 -0.165 43.995 -0.165 43.995 -0.16 43.78 -0.16 43.78 0.16 43.995 0.16 43.995 0.165 ; - POLYGON 84.24 81.2 84.24 0.4 18.8 0.4 18.8 4.89 20.18 4.89 20.18 5.99 18.8 5.99 18.8 16.72 0.4 16.72 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 81.2 ; + POLYGON 84.24 81.2 84.24 0.4 18.8 0.4 18.8 4.89 20.18 4.89 20.18 5.99 18.8 5.99 18.8 6.25 20.18 6.25 20.18 7.35 18.8 7.35 18.8 7.61 20.18 7.61 20.18 8.71 18.8 8.71 18.8 8.97 20.18 8.97 20.18 10.07 18.8 10.07 18.8 10.33 20.18 10.33 20.18 11.43 18.8 11.43 18.8 11.69 20.18 11.69 20.18 12.79 18.8 12.79 18.8 16.72 0.4 16.72 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 81.2 ; LAYER met5 ; - POLYGON 81.44 78.4 81.44 74.16 78.24 74.16 78.24 64.56 81.44 64.56 81.44 53.76 78.24 53.76 78.24 44.16 81.44 44.16 81.44 33.36 78.24 33.36 78.24 23.76 81.44 23.76 81.44 3.2 21.6 3.2 21.6 19.52 3.2 19.52 3.2 23.76 6.4 23.76 6.4 33.36 3.2 33.36 3.2 44.16 6.4 44.16 6.4 53.76 3.2 53.76 3.2 64.56 6.4 64.56 6.4 74.16 3.2 74.16 3.2 78.4 ; + POLYGON 83.04 80 83.04 72.56 79.84 72.56 79.84 66.16 83.04 66.16 83.04 52.16 79.84 52.16 79.84 45.76 83.04 45.76 83.04 31.76 79.84 31.76 79.84 25.36 83.04 25.36 83.04 1.6 20 1.6 20 17.92 1.6 17.92 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 80 ; LAYER met1 ; POLYGON 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 83.88 65.8 83.88 64.76 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; POLYGON 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 18.68 0.52 18.68 2.2 19.16 2.2 19.16 3.24 18.68 3.24 18.68 4.92 19.16 4.92 19.16 5.96 18.68 5.96 18.68 7.64 19.16 7.64 19.16 8.68 18.68 8.68 18.68 10.36 19.16 10.36 19.16 11.4 18.68 11.4 18.68 13.08 19.16 13.08 19.16 14.12 18.68 14.12 18.68 15.8 ; LAYER li1 ; - RECT 47.465 80.79 48.215 81.335 ; - RECT 47.465 0.265 48.215 0.81 ; - POLYGON 84.3 81.26 84.3 0.34 18.74 0.34 18.74 16.66 0.34 16.66 0.34 81.26 ; + POLYGON 84.47 81.43 84.47 0.17 18.57 0.17 18.57 16.49 0.17 16.49 0.17 81.43 ; LAYER mcon ; RECT 84.325 81.515 84.495 81.685 ; RECT 83.865 81.515 84.035 81.685 ; @@ -1922,121 +2006,30 @@ MACRO sb_2__2_ LAYER via ; RECT 73.525 81.525 73.675 81.675 ; RECT 44.085 81.525 44.235 81.675 ; + RECT 42.245 79.825 42.395 79.975 ; + RECT 6.365 17.945 6.515 18.095 ; RECT 73.525 16.245 73.675 16.395 ; RECT 44.085 16.245 44.235 16.395 ; - RECT 80.425 1.625 80.575 1.775 ; - RECT 50.065 1.625 50.215 1.775 ; + RECT 61.565 1.625 61.715 1.775 ; + RECT 29.365 1.625 29.515 1.775 ; RECT 73.525 -0.075 73.675 0.075 ; RECT 44.085 -0.075 44.235 0.075 ; LAYER via2 ; RECT 73.5 81.5 73.7 81.7 ; RECT 44.06 81.5 44.26 81.7 ; - RECT 1.74 69.26 1.94 69.46 ; - RECT 1.28 62.46 1.48 62.66 ; - RECT 1.74 46.14 1.94 46.34 ; - RECT 1.28 42.06 1.48 42.26 ; - RECT 1.28 36.62 1.48 36.82 ; - RECT 19.68 5.34 19.88 5.54 ; + RECT 1.28 53.62 1.48 53.82 ; + RECT 1.28 52.26 1.48 52.46 ; + RECT 1.74 48.86 1.94 49.06 ; + RECT 1.28 32.54 1.48 32.74 ; + RECT 1.28 23.02 1.48 23.22 ; RECT 73.5 -0.1 73.7 0.1 ; RECT 44.06 -0.1 44.26 0.1 ; LAYER via3 ; RECT 73.5 81.5 73.7 81.7 ; RECT 44.06 81.5 44.26 81.7 ; - RECT 1.74 71.98 1.94 72.18 ; + RECT 1.74 60.42 1.94 60.62 ; RECT 73.5 -0.1 73.7 0.1 ; RECT 44.06 -0.1 44.26 0.1 ; - LAYER fieldpoly ; - POLYGON 84.5 81.46 84.5 0.14 18.54 0.14 18.54 16.46 0.14 16.46 0.14 81.46 ; - LAYER diff ; - POLYGON 84.64 81.6 84.64 0 18.4 0 18.4 16.32 0 16.32 0 81.6 ; - LAYER nwell ; - RECT 83.99 77.465 84.83 80.295 ; - POLYGON 3.87 80.295 3.87 78.69 2.03 78.69 2.03 77.465 -0.19 77.465 -0.19 80.295 ; - RECT 83.99 72.025 84.83 74.855 ; - RECT -0.19 72.025 2.03 74.855 ; - POLYGON 84.83 69.415 84.83 66.585 83.99 66.585 83.99 67.81 83.53 67.81 83.53 69.415 ; - RECT -0.19 66.585 2.03 69.415 ; - POLYGON 84.83 63.975 84.83 61.145 82.61 61.145 82.61 62.75 83.53 62.75 83.53 63.975 ; - RECT -0.19 61.145 2.03 63.975 ; - POLYGON 84.83 58.535 84.83 55.705 83.53 55.705 83.53 56.93 80.77 56.93 80.77 58.535 ; - RECT -0.19 55.705 2.03 58.535 ; - POLYGON 84.83 53.095 84.83 50.265 83.99 50.265 83.99 51.49 80.77 51.49 80.77 53.095 ; - RECT -0.19 50.265 2.03 53.095 ; - POLYGON 84.83 47.655 84.83 44.825 83.99 44.825 83.99 46.05 82.61 46.05 82.61 47.655 ; - RECT -0.19 44.825 2.03 47.655 ; - POLYGON 84.83 42.215 84.83 39.385 83.99 39.385 83.99 40.61 80.77 40.61 80.77 42.215 ; - RECT -0.19 39.385 2.03 42.215 ; - RECT 83.53 33.945 84.83 36.775 ; - RECT -0.19 33.945 2.03 36.775 ; - RECT 83.99 28.505 84.83 31.335 ; - RECT -0.19 28.505 2.03 31.335 ; - POLYGON 84.83 25.895 84.83 23.065 83.99 23.065 83.99 24.29 82.61 24.29 82.61 25.895 ; - RECT -0.19 23.065 2.03 25.895 ; - POLYGON 84.83 20.455 84.83 17.625 82.61 17.625 82.61 19.23 83.99 19.23 83.99 20.455 ; - POLYGON 2.03 20.455 2.03 19.23 3.87 19.23 3.87 17.625 -0.19 17.625 -0.19 20.455 ; - POLYGON 84.83 15.015 84.83 12.185 83.99 12.185 83.99 13.41 83.53 13.41 83.53 15.015 ; - POLYGON 20.43 15.015 20.43 13.79 22.27 13.79 22.27 12.185 18.21 12.185 18.21 15.015 ; - POLYGON 84.83 9.575 84.83 6.745 83.99 6.745 83.99 7.97 83.53 7.97 83.53 9.575 ; - POLYGON 20.43 9.575 20.43 8.35 22.27 8.35 22.27 6.745 18.21 6.745 18.21 9.575 ; - RECT 83.99 1.305 84.83 4.135 ; - RECT 18.21 1.305 22.27 4.135 ; - POLYGON 84.64 81.6 84.64 0 18.4 0 18.4 16.32 0 16.32 0 81.6 ; - LAYER pwell ; - RECT 77.87 81.55 78.09 81.72 ; - RECT 74.19 81.55 74.41 81.72 ; - RECT 70.51 81.55 70.73 81.72 ; - RECT 66.83 81.55 67.05 81.72 ; - RECT 63.15 81.55 63.37 81.72 ; - RECT 59.47 81.55 59.69 81.72 ; - RECT 55.79 81.55 56.01 81.72 ; - RECT 52.11 81.55 52.33 81.72 ; - RECT 48.43 81.55 48.65 81.72 ; - RECT 40.61 81.55 40.83 81.72 ; - RECT 36.93 81.55 37.15 81.72 ; - RECT 33.25 81.55 33.47 81.72 ; - RECT 29.57 81.55 29.79 81.72 ; - RECT 25.89 81.55 26.11 81.72 ; - RECT 22.21 81.55 22.43 81.72 ; - RECT 18.53 81.55 18.75 81.72 ; - RECT 14.85 81.55 15.07 81.72 ; - RECT 11.17 81.55 11.39 81.72 ; - RECT 7.49 81.55 7.71 81.72 ; - RECT 3.81 81.55 4.03 81.72 ; - RECT 0.13 81.55 0.35 81.72 ; - RECT 81.595 81.54 81.705 81.66 ; - RECT 44.335 81.54 44.445 81.66 ; - RECT 84.32 81.545 84.44 81.655 ; - RECT 47.06 81.545 47.18 81.655 ; - RECT 83.415 81.54 83.575 81.65 ; - RECT 46.155 81.54 46.315 81.65 ; - RECT 14.85 16.2 15.07 16.37 ; - RECT 11.17 16.2 11.39 16.37 ; - RECT 7.49 16.2 7.71 16.37 ; - RECT 3.81 16.2 4.03 16.37 ; - RECT 0.13 16.2 0.35 16.37 ; - RECT 83.415 -0.05 83.575 0.06 ; - RECT 81.595 -0.06 81.705 0.06 ; - RECT 46.155 -0.05 46.315 0.06 ; - RECT 44.335 -0.06 44.445 0.06 ; - RECT 84.32 -0.055 84.44 0.055 ; - RECT 47.06 -0.055 47.18 0.055 ; - RECT 77.87 -0.12 78.09 0.05 ; - RECT 74.19 -0.12 74.41 0.05 ; - RECT 70.51 -0.12 70.73 0.05 ; - RECT 66.83 -0.12 67.05 0.05 ; - RECT 63.15 -0.12 63.37 0.05 ; - RECT 59.47 -0.12 59.69 0.05 ; - RECT 55.79 -0.12 56.01 0.05 ; - RECT 52.11 -0.12 52.33 0.05 ; - RECT 48.43 -0.12 48.65 0.05 ; - RECT 40.61 -0.12 40.83 0.05 ; - RECT 36.93 -0.12 37.15 0.05 ; - RECT 33.25 -0.12 33.47 0.05 ; - RECT 29.57 -0.12 29.79 0.05 ; - RECT 25.89 -0.12 26.11 0.05 ; - RECT 22.21 -0.12 22.43 0.05 ; - RECT 18.53 -0.12 18.75 0.05 ; - POLYGON 84.64 81.6 84.64 0 18.4 0 18.4 16.32 0 16.32 0 81.6 ; LAYER OVERLAP ; POLYGON 18.4 0 18.4 16.32 0 16.32 0 81.6 84.64 81.6 84.64 0 ; END diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef index 9dbb8f7..429f16f 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ddc5e8d4021be888a42a0b6e1f08291b7aaa654b5984d9159d02a14fe1529f9e -size 1155406 +oid sha256:920e17dc24c8c4b732f6bbd636e73e5a2d052c3447b8861c38ccbca598c89f6b +size 726450 diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef index 97ee21b..6c68408 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a440102bfc4d03c26828df4db57a53409d01fa449982f532e1d9b624e10b05f0 -size 1116008 +oid sha256:d692d1e9a27e44a71862c2d1a53b3c01e7db59105a52d0d09be8bd6ca20340c6 +size 1108940 diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef index 4cc659d..b0f54b1 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e730bebac9a81516c00b69a69cc48778f42765f38578fe68c9a9c7e737a8c6e3 -size 268813 +oid sha256:904b12c4c3df99b3406d0774a5b2fd28957df83cb61a36e205d04208abd52e21 +size 1154636 diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef index 6f9b633..b9e879e 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version 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+4,601 @@ // // // -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__56 ( .A ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb15_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__70 ( .A ( mem_out[0] ) , + .X ( net_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_114 ( .A ( net_net_114 ) , + .X ( net_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_152 ( .A ( net_net_113 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb14_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( net_aps_67 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb11_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( net_aps_64 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__63 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb8_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_14__60 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_155 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module direct_interc_1 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb5_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( net_aps_58 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module direct_interc_0 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb2_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( net_aps_55 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; input [0:0] ccff_head ; +output [0:0] iopad_inpad ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output p_abuf0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module logical_tile_io_mode_io__0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; input [0:0] ccff_head ; +output [0:0] io_inpad ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output p_abuf0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) ) ; +direct_interc_0 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( io_outpad ) ) ; endmodule @@ -588,114 +618,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( net_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( net_net_69 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -716,7 +639,49 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -737,7 +702,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -758,12 +723,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_8 ( const1 ) ; +module const1 ( const1 ) ; output [0:0] const1 ; endmodule @@ -786,184 +751,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_5 const1_0_ ( +const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1004,7 +792,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1063,7 +851,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1122,7 +910,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1256,12 +1044,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1287,45 +1072,73 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , - top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , - top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , - top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , - top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , - top_grid_pin_30_ , top_grid_pin_31_ , bottom_grid_pin_0_ , ccff_tail ) ; + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , + top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , + top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , + top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , + top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , + top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , + top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_16_ ; -output [0:0] top_grid_pin_17_ ; -output [0:0] top_grid_pin_18_ ; -output [0:0] top_grid_pin_19_ ; -output [0:0] top_grid_pin_20_ ; -output [0:0] top_grid_pin_21_ ; -output [0:0] top_grid_pin_22_ ; -output [0:0] top_grid_pin_23_ ; -output [0:0] top_grid_pin_24_ ; -output [0:0] top_grid_pin_25_ ; -output [0:0] top_grid_pin_26_ ; -output [0:0] top_grid_pin_27_ ; -output [0:0] top_grid_pin_28_ ; -output [0:0] top_grid_pin_29_ ; -output [0:0] top_grid_pin_30_ ; -output [0:0] top_grid_pin_31_ ; output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; output [0:0] ccff_tail ; +input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +wire ropt_net_188 ; +wire ropt_net_186 ; +wire ropt_net_190 ; +wire ropt_net_184 ; +wire ropt_net_185 ; +wire ropt_net_183 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -1338,348 +1151,378 @@ wire [0:3] mux_tree_tapbuf_size10_4_sram ; wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_16_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_1 mux_bottom_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_177 ) ) ; +mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_4 mux_bottom_ipin_4 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_5 mux_bottom_ipin_5 ( + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( top_grid_pin_21_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_6 mux_bottom_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_7 mux_bottom_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_2 mux_bottom_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_3 mux_bottom_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_177 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , +mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , +mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( top_grid_pin_22_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_0 mux_bottom_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_1 mux_bottom_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_2 mux_bottom_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_92 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_672 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_673 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , +logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_12_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( ropt_net_188 ) ) ; +logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_206 } ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , + .p_abuf0 ( ropt_net_186 ) ) ; +logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_14_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , + .p_abuf0 ( ropt_net_190 ) ) ; +logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_15_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , + .p_abuf0 ( ropt_net_184 ) ) ; +logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_16_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , + .p_abuf0 ( ropt_net_185 ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_17_ } ) , + .ccff_tail ( { ropt_net_221 } ) , + .p_abuf0 ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_230 ) , .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_176 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_183 ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_184 ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_185 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_186 ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_187 ) , + .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_188 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_190 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( BUF_net_111 ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_110 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[12] ) , .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_231 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_194 ) , + .X ( ropt_net_247 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_232 ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( BUF_net_109 ) , + .X ( ropt_net_246 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_right_in[15] ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_1_ ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_76 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_77 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_78 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_82 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_233 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_197 ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_234 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_235 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_199 ) , + .X ( ropt_net_251 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_201 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_202 ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_236 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_237 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_238 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_205 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_43__42 ( .A ( aps_rename_14_ ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_44__43 ( .A ( aps_rename_15_ ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_206 ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_208 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_212 ) , + .X ( ropt_net_248 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_213 ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_214 ) , + .X ( ropt_net_243 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_239 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[14] ) , + .X ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_216 ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_242 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_right_in[9] ) , + .X ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( chanx_right_in[10] ) , + .X ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_243 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_244 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_245 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_246 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_218 ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( aps_rename_12_ ) , + .X ( BUF_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_110 ( .A ( aps_rename_13_ ) , + .X ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_111 ( .A ( aps_rename_16_ ) , + .X ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_219 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_220 ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_221 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_222 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_223 ) , + .X ( ropt_net_249 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_224 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_225 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_227 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_247 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_248 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_249 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_250 ) , .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_252 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_253 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_254 ) , .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_255 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_256 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_257 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_146 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_147 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_148 ( .A ( BUF_net_102 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_149 ( .A ( BUF_net_103 ) , + .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_158 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_159 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_161 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_162 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_163 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_164 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_92 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_167 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_173 ( .A ( aps_rename_17_ ) , + .X ( ropt_net_205 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v index f24b65f..361d4ae 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v @@ -4,13 +4,13 @@ // // // -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; input VDD ; input VSS ; @@ -18,29 +18,123 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb15_mem_outb_0_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__70 ( .A ( mem_out[0] ) , + .X ( net_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_114 ( .A ( net_net_114 ) , + .X ( net_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_152 ( .A ( net_net_113 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; input VDD ; input VSS ; @@ -48,29 +142,122 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb14_mem_outb_0_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( net_aps_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; input VDD ; input VSS ; @@ -78,29 +265,122 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb11_mem_outb_0_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( net_aps_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__63 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; input VDD ; input VSS ; @@ -108,29 +388,122 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb8_mem_outb_0_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_14__60 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_155 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; input VDD ; input VSS ; @@ -138,29 +511,122 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb5_mem_outb_0_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( net_aps_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; input VDD ; input VSS ; @@ -168,495 +634,104 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb2_mem_outb_0_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( net_aps_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; input [0:0] ccff_head ; +output [0:0] iopad_inpad ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; +output p_abuf0 ; +wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module logical_tile_io_mode_io__0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; input [0:0] ccff_head ; +output [0:0] io_inpad ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; +output p_abuf0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; endmodule @@ -685,159 +760,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( net_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( net_net_69 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -867,7 +790,67 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -897,7 +880,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -927,7 +910,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -994,6 +977,69 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; @@ -1120,258 +1166,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; @@ -1454,13 +1248,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1491,48 +1281,76 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , - top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , - top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , - top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , - top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , - top_grid_pin_30_ , top_grid_pin_31_ , bottom_grid_pin_0_ , ccff_tail , - VDD , VSS ) ; + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , + top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , + top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , + top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , + top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , + top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , + top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_16_ ; -output [0:0] top_grid_pin_17_ ; -output [0:0] top_grid_pin_18_ ; -output [0:0] top_grid_pin_19_ ; -output [0:0] top_grid_pin_20_ ; -output [0:0] top_grid_pin_21_ ; -output [0:0] top_grid_pin_22_ ; -output [0:0] top_grid_pin_23_ ; -output [0:0] top_grid_pin_24_ ; -output [0:0] top_grid_pin_25_ ; -output [0:0] top_grid_pin_26_ ; -output [0:0] top_grid_pin_27_ ; -output [0:0] top_grid_pin_28_ ; -output [0:0] top_grid_pin_29_ ; -output [0:0] top_grid_pin_30_ ; -output [0:0] top_grid_pin_31_ ; output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; output [0:0] ccff_tail ; +input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; input VDD ; input VSS ; +wire ropt_net_188 ; +wire ropt_net_186 ; +wire ropt_net_190 ; +wire ropt_net_184 ; +wire ropt_net_185 ; +wire ropt_net_183 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -1545,398 +1363,440 @@ wire [0:3] mux_tree_tapbuf_size10_4_sram ; wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_1 mux_bottom_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_177 ) ) ; +mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( top_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_4 mux_bottom_ipin_4 ( + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( top_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_5 mux_bottom_ipin_5 ( + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( top_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_6 mux_bottom_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( top_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_7 mux_bottom_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( top_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_2 mux_bottom_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( top_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_3 mux_bottom_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( top_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_177 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , +mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , +mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( top_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( top_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( top_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( top_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_0 mux_bottom_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( top_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_1 mux_bottom_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( top_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_2 mux_bottom_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( top_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( top_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2418 ( .VNB ( VSS ) , +logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_12_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_188 ) ) ; +logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_206 } ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_186 ) ) ; +logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_14_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_190 ) ) ; +logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_15_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_184 ) ) ; +logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_16_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_185 ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_17_ } ) , + .ccff_tail ( { ropt_net_221 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1420 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2419 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1421 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2420 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1422 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2421 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1423 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2422 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1424 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2423 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1425 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2424 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1426 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2425 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1427 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2426 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1428 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2427 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1429 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2428 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1430 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2429 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1431 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2430 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1432 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_92 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_672 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_230 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_673 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_183 ) , + .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_184 ) , + .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_185 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_186 ) , + .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_187 ) , + .X ( ropt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_188 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_190 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( BUF_net_111 ) , + .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_110 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_231 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_194 ) , + .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_232 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( BUF_net_109 ) , + .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_233 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_197 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_234 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_235 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_199 ) , + .X ( ropt_net_251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_201 ) , + .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_202 ) , + .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_236 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_237 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_238 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_205 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_43__42 ( .A ( aps_rename_14_ ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_44__43 ( .A ( aps_rename_15_ ) , + .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_206 ) , + .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_208 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_212 ) , + .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_213 ) , + .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_214 ) , + .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_239 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[14] ) , + .X ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_216 ) , + .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_242 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_right_in[9] ) , + .X ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( chanx_right_in[10] ) , + .X ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_243 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_244 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_245 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_246 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_218 ) , + .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( aps_rename_12_ ) , + .X ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_110 ( .A ( aps_rename_13_ ) , + .X ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_111 ( .A ( aps_rename_16_ ) , + .X ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_219 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_220 ) , + .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_221 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_222 ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_223 ) , + .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_224 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_225 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_227 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_247 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_248 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_249 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_250 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_252 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_253 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_254 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_255 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_256 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_257 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_146 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_147 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_148 ( .A ( BUF_net_102 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_149 ( .A ( BUF_net_103 ) , + .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_158 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_159 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_161 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_162 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_163 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_164 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_92 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_167 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_173 ( .A ( aps_rename_17_ ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( @@ -1947,38 +1807,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_1_ ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_76 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_77 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_78 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_82 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( aps_rename_2_ ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( @@ -2003,11 +1841,13 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2017,6 +1857,10 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y54400 ( @@ -2025,42 +1869,84 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x78200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y136000 ( @@ -2069,21 +1955,45 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2093,10 +2003,28 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y217600 ( @@ -2105,48 +2033,78 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y299200 ( @@ -2155,11 +2113,25 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2169,7 +2141,25 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2179,6 +2169,24 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y380800 ( @@ -2187,11 +2195,23 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2201,7 +2221,31 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2211,15 +2255,29 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2229,32 +2287,58 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y516800 ( @@ -2263,39 +2347,95 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x59800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2323,14 +2463,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v index b184d90..db949a5 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v @@ -4,515 +4,583 @@ // // // -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__56 ( .A ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb15_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__70 ( .A ( mem_out[0] ) , + .X ( net_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_114 ( .A ( net_net_114 ) , + .X ( net_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_152 ( .A ( net_net_113 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb14_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( net_aps_67 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb11_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( net_aps_64 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__63 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb8_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_14__60 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_155 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb5_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( net_aps_58 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:0] mem_out ; +output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb2_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( net_aps_55 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; input [0:0] ccff_head ; +output [0:0] iopad_inpad ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output p_abuf0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module logical_tile_io_mode_io__0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; input [0:0] ccff_head ; +output [0:0] io_inpad ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output p_abuf0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( p_abuf0 ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; endmodule @@ -532,114 +600,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( net_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( net_net_69 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -660,7 +621,49 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -681,7 +684,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -702,7 +705,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -759,6 +762,58 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -863,214 +918,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -1139,10 +986,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1168,45 +1012,73 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , - top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , - top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , - top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , - top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , - top_grid_pin_30_ , top_grid_pin_31_ , bottom_grid_pin_0_ , ccff_tail ) ; + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , + top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , + top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , + top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , + top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , + top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , + top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_16_ ; -output [0:0] top_grid_pin_17_ ; -output [0:0] top_grid_pin_18_ ; -output [0:0] top_grid_pin_19_ ; -output [0:0] top_grid_pin_20_ ; -output [0:0] top_grid_pin_21_ ; -output [0:0] top_grid_pin_22_ ; -output [0:0] top_grid_pin_23_ ; -output [0:0] top_grid_pin_24_ ; -output [0:0] top_grid_pin_25_ ; -output [0:0] top_grid_pin_26_ ; -output [0:0] top_grid_pin_27_ ; -output [0:0] top_grid_pin_28_ ; -output [0:0] top_grid_pin_29_ ; -output [0:0] top_grid_pin_30_ ; -output [0:0] top_grid_pin_31_ ; output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; output [0:0] ccff_tail ; +input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +wire ropt_net_188 ; +wire ropt_net_186 ; +wire ropt_net_190 ; +wire ropt_net_184 ; +wire ropt_net_185 ; +wire ropt_net_183 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -1219,348 +1091,378 @@ wire [0:3] mux_tree_tapbuf_size10_4_sram ; wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_16_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_1 mux_bottom_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_177 ) ) ; +mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_4 mux_bottom_ipin_4 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_5 mux_bottom_ipin_5 ( + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_176 ) ) ; +mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( top_grid_pin_21_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_6 mux_bottom_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_7 mux_bottom_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size10_2 mux_bottom_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_3 mux_bottom_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_177 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , +mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , +mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( top_grid_pin_22_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_0 mux_bottom_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_1 mux_bottom_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_91 ) ) ; -mux_tree_tapbuf_size8_2 mux_bottom_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_90 ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_92 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_672 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_673 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , +logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_12_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .p_abuf0 ( ropt_net_188 ) ) ; +logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_206 } ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , + .p_abuf0 ( ropt_net_186 ) ) ; +logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_14_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , + .p_abuf0 ( ropt_net_190 ) ) ; +logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_15_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , + .p_abuf0 ( ropt_net_184 ) ) ; +logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_16_ } ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , + .p_abuf0 ( ropt_net_185 ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_17_ } ) , + .ccff_tail ( { ropt_net_221 } ) , + .p_abuf0 ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_230 ) , .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_176 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_183 ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_184 ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_185 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_186 ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_187 ) , + .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_188 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_190 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( BUF_net_111 ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_110 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[12] ) , .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_231 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_194 ) , + .X ( ropt_net_247 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_232 ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( BUF_net_109 ) , + .X ( ropt_net_246 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_right_in[15] ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_1_ ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_76 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_77 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_78 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_82 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_233 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_197 ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_234 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_235 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_199 ) , + .X ( ropt_net_251 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_201 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_202 ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_236 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_237 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_238 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_205 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_43__42 ( .A ( aps_rename_14_ ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_44__43 ( .A ( aps_rename_15_ ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_206 ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_208 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_212 ) , + .X ( ropt_net_248 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_213 ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_214 ) , + .X ( ropt_net_243 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_239 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[14] ) , + .X ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_216 ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_242 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_right_in[9] ) , + .X ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( chanx_right_in[10] ) , + .X ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_243 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_244 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_245 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_246 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_218 ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( aps_rename_12_ ) , + .X ( BUF_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_110 ( .A ( aps_rename_13_ ) , + .X ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_111 ( .A ( aps_rename_16_ ) , + .X ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_219 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_220 ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_221 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_222 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_223 ) , + .X ( ropt_net_249 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_224 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_225 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_227 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_247 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_248 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_249 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_250 ) , .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_252 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_253 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_254 ) , .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_255 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_256 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_257 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_146 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_147 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_148 ( .A ( BUF_net_102 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_149 ( .A ( BUF_net_103 ) , + .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_158 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_159 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_161 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_162 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_163 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_164 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_92 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_167 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_173 ( .A ( aps_rename_17_ ) , + .X ( ropt_net_205 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v index daea3a4..d9024d5 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v @@ -20,9 +20,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( net_net_72 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -43,7 +41,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -64,28 +62,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -106,7 +83,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -127,7 +104,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -148,7 +125,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -169,7 +146,28 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -332,7 +330,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -383,53 +381,6 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -446,7 +397,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_10 const1_0_ ( +const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -476,7 +427,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_9 ( const1 ) ; +module const1_10 ( const1 ) ; output [0:0] const1 ; endmodule @@ -488,6 +439,53 @@ input [0:3] sram_inv ; output [0:0] out ; input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -532,7 +530,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -594,7 +592,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -615,91 +613,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -720,7 +634,91 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -741,7 +739,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -869,7 +867,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -928,7 +926,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -987,7 +985,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1046,7 +1044,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1105,7 +1103,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1219,35 +1217,43 @@ endmodule module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , - top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , - top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , - top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , - top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , - top_grid_pin_30_ , top_grid_pin_31_ , ccff_tail ) ; + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , CLB_SC_IN , CLB_SC_OUT , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_16_ ; -output [0:0] top_grid_pin_17_ ; -output [0:0] top_grid_pin_18_ ; -output [0:0] top_grid_pin_19_ ; -output [0:0] top_grid_pin_20_ ; -output [0:0] top_grid_pin_21_ ; -output [0:0] top_grid_pin_22_ ; -output [0:0] top_grid_pin_23_ ; -output [0:0] top_grid_pin_24_ ; -output [0:0] top_grid_pin_25_ ; -output [0:0] top_grid_pin_26_ ; -output [0:0] top_grid_pin_27_ ; -output [0:0] top_grid_pin_28_ ; -output [0:0] top_grid_pin_29_ ; -output [0:0] top_grid_pin_30_ ; -output [0:0] top_grid_pin_31_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; +input CLB_SC_IN ; +output CLB_SC_OUT ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1272,7 +1278,6 @@ wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; @@ -1296,316 +1301,318 @@ wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_16_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_1 mux_bottom_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_4 mux_bottom_ipin_4 ( + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_5 mux_bottom_ipin_5 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( top_grid_pin_21_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_6 mux_bottom_ipin_8 ( + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10 mux_bottom_ipin_9 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , + chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_2 mux_bottom_ipin_12 ( + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_3 mux_bottom_ipin_13 ( + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , + chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , +mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , +mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , +mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( top_grid_pin_22_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_0 mux_bottom_ipin_10 ( + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_1 mux_bottom_ipin_11 ( + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_2 mux_bottom_ipin_14 ( + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , +mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , +mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , +mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_97 } ) , +mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_105 ) , - .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( ropt_net_105 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( aps_rename_6_ ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_673 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_106 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_107 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_675 ( .A ( ropt_net_97 ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_108 ) , - .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_98 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( ropt_net_106 ) , + .X ( chanx_left_out[16] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_107 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_102 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_682 ( .A ( ropt_net_103 ) , - .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_108 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_109 ) , + .X ( chanx_right_out[15] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_104 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_59 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chanx_left_in[9] ) , - .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( BUF_net_61 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( aps_rename_3_ ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_82 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chanx_right_in[6] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( aps_rename_4_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[19] ) , + .X ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_2_ ) , - .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chanx_right_in[12] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chanx_right_in[16] ) , + .X ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( aps_rename_6_ ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( BUF_net_65 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( BUF_net_69 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_71 ) , + .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( CLB_SC_IN ) , + .X ( CLB_SC_OUT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( aps_rename_4_ ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v index 0f782fc..a3a7c08 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v @@ -29,9 +29,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( net_net_72 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61,7 +59,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -91,37 +89,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -151,7 +119,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -181,7 +149,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -211,7 +179,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -241,7 +209,37 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -405,7 +403,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -458,55 +456,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -569,6 +518,55 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -613,7 +611,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -691,7 +689,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -721,127 +719,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -871,7 +749,127 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -901,7 +899,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1032,6 +1030,69 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -1283,69 +1344,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; @@ -1410,35 +1408,43 @@ endmodule module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , - top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , - top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , - top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , - top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , - top_grid_pin_30_ , top_grid_pin_31_ , ccff_tail , VDD , VSS ) ; + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , CLB_SC_IN , CLB_SC_OUT , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_16_ ; -output [0:0] top_grid_pin_17_ ; -output [0:0] top_grid_pin_18_ ; -output [0:0] top_grid_pin_19_ ; -output [0:0] top_grid_pin_20_ ; -output [0:0] top_grid_pin_21_ ; -output [0:0] top_grid_pin_22_ ; -output [0:0] top_grid_pin_23_ ; -output [0:0] top_grid_pin_24_ ; -output [0:0] top_grid_pin_25_ ; -output [0:0] top_grid_pin_26_ ; -output [0:0] top_grid_pin_27_ ; -output [0:0] top_grid_pin_28_ ; -output [0:0] top_grid_pin_29_ ; -output [0:0] top_grid_pin_30_ ; -output [0:0] top_grid_pin_31_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; +input CLB_SC_IN ; +output CLB_SC_OUT ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; input VDD ; input VSS ; @@ -1465,7 +1471,6 @@ wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; @@ -1489,408 +1494,410 @@ wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_1 mux_bottom_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( top_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_4 mux_bottom_ipin_4 ( + .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( top_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_5 mux_bottom_ipin_5 ( + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( top_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_6 mux_bottom_ipin_8 ( + .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( top_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10 mux_bottom_ipin_9 ( + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , + chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( top_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_2 mux_bottom_ipin_12 ( + .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( top_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_3 mux_bottom_ipin_13 ( + .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , + chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( top_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , +mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , +mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , +mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( top_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( top_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( top_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( top_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_0 mux_bottom_ipin_10 ( + .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( top_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_1 mux_bottom_ipin_11 ( + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( top_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_2 mux_bottom_ipin_14 ( + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( top_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , + .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( top_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , +mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , +mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , +mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_97 } ) , +mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2432 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1434 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2433 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1435 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2434 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1436 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2435 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1437 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2436 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1438 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2437 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1439 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2438 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1440 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2439 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1441 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2440 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1442 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2441 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1443 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2442 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1444 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2443 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1445 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2444 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1446 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_105 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( ropt_net_105 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( aps_rename_6_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_673 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_106 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_107 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_675 ( .A ( ropt_net_97 ) , - .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_108 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_98 ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( ropt_net_106 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_107 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_102 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_682 ( .A ( ropt_net_103 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_108 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_109 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_104 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_59 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chanx_left_in[9] ) , - .X ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( aps_rename_4_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( BUF_net_61 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( aps_rename_3_ ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_82 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[19] ) , + .X ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_2_ ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chanx_right_in[12] ) , + .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chanx_right_in[16] ) , + .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( aps_rename_6_ ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( BUF_net_65 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( BUF_net_69 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_71 ) , + .X ( ropt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( CLB_SC_IN ) , + .X ( CLB_SC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( aps_rename_4_ ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( @@ -1913,26 +1920,42 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y81600 ( @@ -1941,11 +1964,9 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1955,10 +1976,14 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y136000 ( @@ -1967,21 +1992,9 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1991,36 +2004,56 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y244800 ( @@ -2029,10 +2062,8 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y272000 ( @@ -2041,11 +2072,13 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2055,24 +2088,18 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y353600 ( @@ -2081,22 +2108,26 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y408000 ( @@ -2105,21 +2136,23 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2129,29 +2162,13 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2161,27 +2178,25 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2191,24 +2206,22 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y571200 ( @@ -2217,8 +2230,10 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y598400 ( @@ -2245,14 +2260,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v index 8a008cc..0428a39 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v @@ -20,9 +20,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( net_net_72 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -43,7 +41,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -64,28 +62,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -106,7 +83,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -127,7 +104,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -148,7 +125,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -169,7 +146,28 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -306,7 +304,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -350,46 +348,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -441,6 +399,46 @@ input [0:3] sram_inv ; output [0:0] out ; input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -478,7 +476,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -538,7 +536,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -559,91 +557,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -664,7 +578,91 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -685,7 +683,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -794,6 +792,58 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -1002,58 +1052,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -1107,35 +1105,43 @@ endmodule module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , - top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , - top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , - top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , - top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , - top_grid_pin_30_ , top_grid_pin_31_ , ccff_tail ) ; + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , CLB_SC_IN , CLB_SC_OUT , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_16_ ; -output [0:0] top_grid_pin_17_ ; -output [0:0] top_grid_pin_18_ ; -output [0:0] top_grid_pin_19_ ; -output [0:0] top_grid_pin_20_ ; -output [0:0] top_grid_pin_21_ ; -output [0:0] top_grid_pin_22_ ; -output [0:0] top_grid_pin_23_ ; -output [0:0] top_grid_pin_24_ ; -output [0:0] top_grid_pin_25_ ; -output [0:0] top_grid_pin_26_ ; -output [0:0] top_grid_pin_27_ ; -output [0:0] top_grid_pin_28_ ; -output [0:0] top_grid_pin_29_ ; -output [0:0] top_grid_pin_30_ ; -output [0:0] top_grid_pin_31_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; +input CLB_SC_IN ; +output CLB_SC_OUT ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1160,7 +1166,6 @@ wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; @@ -1184,316 +1189,318 @@ wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_16_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_1 mux_bottom_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_4 mux_bottom_ipin_4 ( + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_5 mux_bottom_ipin_5 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( top_grid_pin_21_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_6 mux_bottom_ipin_8 ( + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10 mux_bottom_ipin_9 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , + chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_2 mux_bottom_ipin_12 ( + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size10_3 mux_bottom_ipin_13 ( + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , + chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , +mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , +mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , +mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( top_grid_pin_22_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_0 mux_bottom_ipin_10 ( + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_1 mux_bottom_ipin_11 ( + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size8_2 mux_bottom_ipin_14 ( + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , +mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , +mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , +mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_97 } ) , +mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_105 ) , - .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( ropt_net_105 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( aps_rename_6_ ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_673 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_106 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_107 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_675 ( .A ( ropt_net_97 ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_108 ) , - .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_98 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( ropt_net_106 ) , + .X ( chanx_left_out[16] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_107 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_102 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_682 ( .A ( ropt_net_103 ) , - .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_108 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_109 ) , + .X ( chanx_right_out[15] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_104 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_59 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chanx_left_in[9] ) , - .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( BUF_net_61 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( aps_rename_3_ ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_82 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chanx_right_in[6] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( aps_rename_4_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[19] ) , + .X ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_2_ ) , - .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chanx_right_in[12] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chanx_right_in[16] ) , + .X ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( aps_rename_6_ ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( BUF_net_65 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( BUF_net_69 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_71 ) , + .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( CLB_SC_IN ) , + .X ( CLB_SC_OUT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( aps_rename_4_ ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v index 0f002d3..cbe5341 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v @@ -4,6 +4,735 @@ // // // +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( net_aps_61 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( p_abuf0 ) , .X ( FPGA_IN ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf0 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -20,14 +749,294 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( net_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_115 ( .A ( net_net_74 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1 ( const1 ) ; +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -50,7 +1059,302 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1 const1_0_ ( +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -87,7 +1391,17 @@ endmodule module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_0_ , ccff_tail ) ; + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , + bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -95,217 +1409,404 @@ input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +wire p_abuf0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_143 ) ) ; -mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10 mux_top_ipin_8 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { ropt_net_181 } ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_144 ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_148 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_149 ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_152 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_155 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_167 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_172 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_44 ( .A ( chanx_left_in[8] ) , - .X ( BUF_net_44 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , +mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_197 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_198 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_199 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_200 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_203 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_204 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_207 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_209 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_211 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_216 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_103 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_104 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_116 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_44 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_132 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_119 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( p_abuf0 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_2_ ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_3_ ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v index 4259add..45f1f14 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v @@ -4,6 +4,874 @@ // // // +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( net_aps_61 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( p_abuf0 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf0 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -29,13 +897,350 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( net_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_115 ( .A ( net_net_74 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -98,9 +1303,333 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_0_ , ccff_tail , VDD , - VSS ) ; + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , + bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -108,17 +1637,94 @@ input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; input VDD ; input VSS ; +wire p_abuf0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , @@ -126,245 +1732,407 @@ mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; -mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10 mux_top_ipin_8 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { ropt_net_181 } ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2446 ( .VNB ( VSS ) , +mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1448 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2447 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1449 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2448 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1450 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2449 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1451 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2450 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1452 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2451 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1453 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2452 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1454 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2453 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1455 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2454 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1456 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2455 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1457 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2456 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1458 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2457 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1459 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2458 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1460 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_144 ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_148 ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_149 ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_152 ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_155 ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_167 ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_172 ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_44 ( .A ( chanx_left_in[8] ) , - .X ( BUF_net_44 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_197 ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_198 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_199 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_200 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_203 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_204 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_207 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_209 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_211 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_216 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_119 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( p_abuf0 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_103 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_104 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_2_ ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_3_ ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( @@ -373,18 +2141,8 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_116 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_44 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y0 ( @@ -393,56 +2151,16 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_132 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y27200 ( @@ -451,74 +2169,20 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y81600 ( @@ -527,30 +2191,8 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y108800 ( @@ -559,74 +2201,20 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y163200 ( @@ -635,35 +2223,9 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -673,44 +2235,6 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y217600 ( @@ -719,44 +2243,6 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y244800 ( @@ -765,43 +2251,7 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -811,40 +2261,12 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y299200 ( @@ -853,71 +2275,19 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -927,32 +2297,8 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y380800 ( @@ -961,184 +2307,36 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y489600 ( @@ -1147,40 +2345,6 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y516800 ( @@ -1189,81 +2353,17 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1273,31 +2373,13 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1325,14 +2407,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v index 9bec29d..bb10d5b 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v @@ -4,6 +4,679 @@ // // // +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( net_aps_61 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( p_abuf0 ) , .X ( FPGA_IN ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf0 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -20,13 +693,272 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( net_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_115 ( .A ( net_net_74 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -79,8 +1011,278 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_0_ , ccff_tail ) ; + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , + bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -88,217 +1290,404 @@ input [0:0] ccff_head ; output [0:19] chanx_left_out ; output [0:19] chanx_right_out ; output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +wire p_abuf0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_143 ) ) ; -mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10 mux_top_ipin_8 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { ropt_net_181 } ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_144 ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_148 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_149 ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_152 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_155 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_167 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_172 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_44 ( .A ( chanx_left_in[8] ) , - .X ( BUF_net_44 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , +mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_117 ) ) ; +mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_118 ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_197 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_198 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_199 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_200 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_203 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_204 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_207 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_209 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_211 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_216 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_103 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_104 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_116 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_44 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_132 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_119 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( p_abuf0 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_2_ ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_3_ ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v index 8872cc0..05bd39d 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v @@ -4,6 +4,114 @@ // // // +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +wire aps_rename_2_ ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , + .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -20,30 +128,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( net_net_76 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( net_net_76 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -107,302 +192,266 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , - ccff_tail ) ; + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , + right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chany_top_out ; -output [0:0] right_grid_pin_52_ ; output [0:0] left_grid_pin_0_ ; output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +wire ropt_net_162 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; // -mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( +mux_tree_tapbuf_size10 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_52_ ) , .p0 ( optlc_net_144 ) ) ; -mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_145 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_177 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_153 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_154 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_155 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_156 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_157 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_158 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_159 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , - .X ( chany_bottom_out[15] ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_163 } ) , + .p_abuf0 ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , + .X ( ropt_net_227 ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , - .X ( chany_bottom_out[19] ) ) ; + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , + .X ( ropt_net_210 ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_164 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_166 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_167 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_168 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_169 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_172 ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_175 ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_176 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_180 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_45 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_182 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_183 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_184 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_185 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_186 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_188 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_189 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_190 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_191 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_192 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_193 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_194 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_65 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chany_top_in[9] ) , - .X ( BUF_net_66 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_196 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_197 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_198 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_200 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_111 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_115 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_117 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_131 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_66 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chany_top_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) , + .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chany_top_in[15] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) , .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v index 8119b9c..01a2ce4 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v @@ -4,6 +4,137 @@ // // // +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; +input VDD ; +input VSS ; + +supply1 VDD ; +wire aps_rename_2_ ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , + .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -29,39 +160,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( net_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( net_net_76 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -128,308 +227,260 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , - ccff_tail , VDD , VSS ) ; + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , + right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chany_top_out ; -output [0:0] right_grid_pin_52_ ; output [0:0] left_grid_pin_0_ ; output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; input VDD ; input VSS ; +wire ropt_net_162 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( +mux_tree_tapbuf_size10 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_52_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; -mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2460 ( .VNB ( VSS ) , +logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_163 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1462 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2461 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1463 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2462 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1464 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2463 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1465 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2464 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1466 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2465 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1467 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2466 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1468 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2467 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1469 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2468 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1470 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2469 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1471 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2470 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1472 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2471 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1473 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2472 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1474 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2473 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1475 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2474 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1476 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_177 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_153 ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_154 ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_155 ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_156 ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_157 ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_158 ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_159 ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_164 ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_166 ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_167 ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_168 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_169 ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_172 ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_175 ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_176 ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_180 ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_45 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_182 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_183 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_184 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_185 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_186 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_188 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_189 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_190 ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_191 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_192 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_193 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_194 ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_65 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chany_top_in[9] ) , - .X ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_196 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_197 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_198 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_200 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_202 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) , + .X ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_203 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) , + .X ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_204 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( @@ -444,26 +495,24 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( @@ -472,74 +521,84 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_111 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_115 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_117 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y27200 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_131 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_66 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( @@ -550,15 +609,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -572,11 +625,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -588,36 +637,34 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( @@ -630,32 +677,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( @@ -672,30 +719,30 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( @@ -708,31 +755,29 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -742,35 +787,33 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -780,37 +823,43 @@ sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x87400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -820,36 +869,40 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( @@ -862,25 +915,25 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -910,20 +963,20 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( @@ -934,17 +987,17 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -952,19 +1005,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -980,63 +1033,63 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1044,24 +1097,36 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y462400 ( @@ -1082,29 +1147,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1122,31 +1189,29 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1158,68 +1223,66 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( @@ -1240,31 +1303,29 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1272,33 +1333,35 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1306,30 +1369,28 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( @@ -1356,14 +1417,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y734400 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v index ec06708..8457822 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v @@ -4,6 +4,114 @@ // // // +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR , p_abuf0 , p_abuf1 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +output p_abuf1 ; + +wire aps_rename_2_ ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , + .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , p_abuf0 , p_abuf1 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; + +wire [0:0] EMBEDDED_IO_0_en ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +output p_abuf0 ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -20,30 +128,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( net_net_76 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( net_net_76 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -100,295 +185,266 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , - ccff_tail ) ; + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , + right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chany_top_out ; -output [0:0] right_grid_pin_52_ ; output [0:0] left_grid_pin_0_ ; output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +wire ropt_net_162 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; // -mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( +mux_tree_tapbuf_size10 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_52_ ) , .p0 ( optlc_net_144 ) ) ; -mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_145 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_177 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_153 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_154 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_155 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_156 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_157 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_158 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_159 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , - .X ( chany_bottom_out[15] ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_163 } ) , + .p_abuf0 ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , + .X ( ropt_net_227 ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , - .X ( chany_bottom_out[19] ) ) ; + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , + .X ( ropt_net_210 ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_164 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_166 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_167 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_168 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_169 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_170 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_172 ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_175 ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_176 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_180 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_45 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_182 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_183 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_184 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_185 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_186 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_188 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_189 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_190 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_191 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_60 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_192 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_193 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_194 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_65 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chany_top_in[9] ) , - .X ( BUF_net_66 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_196 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_197 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_198 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_200 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_111 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_115 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_117 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_131 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_66 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chany_top_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) , + .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chany_top_in[15] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) , .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v index 85ec29c..d08666b 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v @@ -20,9 +20,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__56 ( .A ( mem_out[3] ) , - .X ( net_aps_56 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( net_aps_56 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -43,7 +41,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -64,28 +62,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -106,7 +83,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -127,7 +104,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -148,7 +125,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -169,7 +146,28 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -193,12 +191,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -218,61 +213,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -281,7 +224,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -332,7 +275,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -346,9 +289,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -368,9 +314,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -578,24 +525,54 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -616,90 +593,8 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( net_net_70 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_90 ( .A ( net_net_70 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -720,7 +615,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -741,7 +636,91 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -762,70 +741,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - module const1_7 ( const1 ) ; output [0:0] const1 ; endmodule @@ -890,7 +810,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -949,7 +869,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1008,7 +928,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1067,7 +987,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1126,7 +1046,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1185,7 +1105,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1299,35 +1219,34 @@ endmodule module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , - left_grid_pin_1_ , left_grid_pin_2_ , left_grid_pin_3_ , - left_grid_pin_4_ , left_grid_pin_5_ , left_grid_pin_6_ , - left_grid_pin_7_ , left_grid_pin_8_ , left_grid_pin_9_ , - left_grid_pin_10_ , left_grid_pin_11_ , left_grid_pin_12_ , - left_grid_pin_13_ , left_grid_pin_14_ , left_grid_pin_15_ , ccff_tail ) ; + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chany_top_out ; -output [0:0] right_grid_pin_52_ ; -output [0:0] left_grid_pin_0_ ; -output [0:0] left_grid_pin_1_ ; -output [0:0] left_grid_pin_2_ ; -output [0:0] left_grid_pin_3_ ; -output [0:0] left_grid_pin_4_ ; -output [0:0] left_grid_pin_5_ ; -output [0:0] left_grid_pin_6_ ; -output [0:0] left_grid_pin_7_ ; -output [0:0] left_grid_pin_8_ ; -output [0:0] left_grid_pin_9_ ; -output [0:0] left_grid_pin_10_ ; -output [0:0] left_grid_pin_11_ ; -output [0:0] left_grid_pin_12_ ; -output [0:0] left_grid_pin_13_ ; -output [0:0] left_grid_pin_14_ ; -output [0:0] left_grid_pin_15_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -1346,8 +1265,6 @@ wire [0:3] mux_tree_tapbuf_size10_6_sram ; wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1355,8 +1272,6 @@ wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; @@ -1380,320 +1295,326 @@ wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( +mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_52_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_2 mux_right_ipin_1 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_1_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_4_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_6 mux_right_ipin_5 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_5_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_7 mux_right_ipin_8 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_8_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10 mux_right_ipin_9 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_9_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_12_ ) , .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size10_4 mux_right_ipin_13 ( + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_98 ) ) ; +mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[14] , chany_top_in[14] , chany_bottom_in[18] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_13_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( +mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_2_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size8_5 mux_right_ipin_3 ( + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[16] , chany_top_in[16] } ) , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_3_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_6_ ) , .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size8 mux_right_ipin_7 ( + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_98 ) ) ; +mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[12] , chany_top_in[12] } ) , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_7_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_0 mux_right_ipin_10 ( + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_10_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size8_1 mux_right_ipin_11 ( + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[16] , chany_top_in[16] } ) , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_11_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size8_2 mux_right_ipin_14 ( + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_14_ ) , .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size8_3 mux_right_ipin_15 ( + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[12] , chany_top_in[12] } ) , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_15_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_right_ipin_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , +mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , +mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( - .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , + .X ( ropt_net_112 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_114 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( aps_rename_4_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( aps_rename_5_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chany_top_in[1] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_111 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_29__28 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__39 ( .A ( chany_top_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( + .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_top_in[16] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_1_ ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( aps_rename_2_ ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( aps_rename_4_ ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_5_ ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_112 ) , .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_113 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_114 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_115 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , + .X ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_116 ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_117 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_71 ) , - .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( aps_rename_1_ ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_59 ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v index d12633e..6a0c590 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v @@ -29,9 +29,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__56 ( .A ( mem_out[3] ) , - .X ( net_aps_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( net_aps_56 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61,7 +59,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -91,37 +89,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -151,7 +119,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -181,7 +149,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -211,7 +179,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -241,7 +209,37 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -262,13 +260,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -292,10 +286,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -405,55 +399,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -666,33 +611,56 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -722,126 +690,8 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( net_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_90 ( .A ( net_net_70 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -871,7 +721,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -901,7 +751,127 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -931,74 +901,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; @@ -1062,257 +969,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; @@ -1439,6 +1095,257 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; @@ -1503,36 +1410,34 @@ endmodule module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , - left_grid_pin_1_ , left_grid_pin_2_ , left_grid_pin_3_ , - left_grid_pin_4_ , left_grid_pin_5_ , left_grid_pin_6_ , - left_grid_pin_7_ , left_grid_pin_8_ , left_grid_pin_9_ , - left_grid_pin_10_ , left_grid_pin_11_ , left_grid_pin_12_ , - left_grid_pin_13_ , left_grid_pin_14_ , left_grid_pin_15_ , ccff_tail , - VDD , VSS ) ; + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chany_top_out ; -output [0:0] right_grid_pin_52_ ; -output [0:0] left_grid_pin_0_ ; -output [0:0] left_grid_pin_1_ ; -output [0:0] left_grid_pin_2_ ; -output [0:0] left_grid_pin_3_ ; -output [0:0] left_grid_pin_4_ ; -output [0:0] left_grid_pin_5_ ; -output [0:0] left_grid_pin_6_ ; -output [0:0] left_grid_pin_7_ ; -output [0:0] left_grid_pin_8_ ; -output [0:0] left_grid_pin_9_ ; -output [0:0] left_grid_pin_10_ ; -output [0:0] left_grid_pin_11_ ; -output [0:0] left_grid_pin_12_ ; -output [0:0] left_grid_pin_13_ ; -output [0:0] left_grid_pin_14_ ; -output [0:0] left_grid_pin_15_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; input VDD ; input VSS ; @@ -1553,8 +1458,6 @@ wire [0:3] mux_tree_tapbuf_size10_6_sram ; wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1562,8 +1465,6 @@ wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; @@ -1587,367 +1488,406 @@ wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( +mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_52_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_2 mux_right_ipin_1 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_6 mux_right_ipin_5 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_7 mux_right_ipin_8 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10 mux_right_ipin_9 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( + .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size10_4 mux_right_ipin_13 ( + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_98 ) ) ; +mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[14] , chany_top_in[14] , chany_bottom_in[18] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( +mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size8_5 mux_right_ipin_3 ( + .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[16] , chany_top_in[16] } ) , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size8 mux_right_ipin_7 ( + .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_98 ) ) ; +mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[12] , chany_top_in[12] } ) , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_0 mux_right_ipin_10 ( + .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size8_1 mux_right_ipin_11 ( + .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[16] , chany_top_in[16] } ) , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size8_2 mux_right_ipin_14 ( + .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size8_3 mux_right_ipin_15 ( + .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[12] , chany_top_in[12] } ) , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem mem_right_ipin_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , +mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , +mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2476 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1478 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2477 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1479 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2478 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1480 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2479 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1481 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2480 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1482 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2481 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1483 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2482 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1484 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2483 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1485 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2484 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1486 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2485 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1487 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2486 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1488 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2487 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1489 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2488 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1490 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2489 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1491 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2490 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1492 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( - .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , + .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_114 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( aps_rename_4_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( aps_rename_5_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chany_top_in[1] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_111 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__27 ( .A ( chany_top_in[7] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( + .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_111 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_29__28 ( .A ( chany_top_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , + .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_113 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_114 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_115 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , + .X ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_117 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( aps_rename_1_ ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_59 ) , + .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( @@ -1956,58 +1896,24 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_top_in[16] ) , - .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_1_ ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( aps_rename_2_ ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( aps_rename_4_ ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_5_ ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_71 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( @@ -2016,6 +1922,14 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( @@ -2024,32 +1938,22 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( @@ -2058,6 +1962,8 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( @@ -2066,8 +1972,6 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( @@ -2076,13 +1980,27 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2092,10 +2010,12 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( @@ -2104,11 +2024,9 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2118,45 +2036,47 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2174,15 +2094,33 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2192,14 +2130,36 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( @@ -2208,13 +2168,9 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2224,13 +2180,7 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x82800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2240,13 +2190,13 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2256,6 +2206,10 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x59800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( @@ -2264,13 +2218,15 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2280,7 +2236,7 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2290,9 +2246,9 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2302,7 +2258,9 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2330,14 +2288,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y734400 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v index 43b2d65..be65117 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v @@ -20,9 +20,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__56 ( .A ( mem_out[3] ) , - .X ( net_aps_56 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( net_aps_56 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -43,7 +41,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -64,28 +62,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -106,7 +83,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -127,7 +104,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -148,7 +125,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -169,7 +146,28 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -188,10 +186,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -211,10 +206,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -306,46 +300,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -522,24 +476,47 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -560,90 +537,8 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( net_net_70 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_90 ( .A ( net_net_70 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -664,7 +559,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -685,7 +580,91 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -706,63 +685,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -815,214 +742,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -1127,6 +846,214 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -1180,35 +1107,34 @@ endmodule module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , - left_grid_pin_1_ , left_grid_pin_2_ , left_grid_pin_3_ , - left_grid_pin_4_ , left_grid_pin_5_ , left_grid_pin_6_ , - left_grid_pin_7_ , left_grid_pin_8_ , left_grid_pin_9_ , - left_grid_pin_10_ , left_grid_pin_11_ , left_grid_pin_12_ , - left_grid_pin_13_ , left_grid_pin_14_ , left_grid_pin_15_ , ccff_tail ) ; + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chany_top_out ; -output [0:0] right_grid_pin_52_ ; -output [0:0] left_grid_pin_0_ ; -output [0:0] left_grid_pin_1_ ; -output [0:0] left_grid_pin_2_ ; -output [0:0] left_grid_pin_3_ ; -output [0:0] left_grid_pin_4_ ; -output [0:0] left_grid_pin_5_ ; -output [0:0] left_grid_pin_6_ ; -output [0:0] left_grid_pin_7_ ; -output [0:0] left_grid_pin_8_ ; -output [0:0] left_grid_pin_9_ ; -output [0:0] left_grid_pin_10_ ; -output [0:0] left_grid_pin_11_ ; -output [0:0] left_grid_pin_12_ ; -output [0:0] left_grid_pin_13_ ; -output [0:0] left_grid_pin_14_ ; -output [0:0] left_grid_pin_15_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -1227,8 +1153,6 @@ wire [0:3] mux_tree_tapbuf_size10_6_sram ; wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1236,8 +1160,6 @@ wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; @@ -1261,320 +1183,326 @@ wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( +mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_52_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_2 mux_right_ipin_1 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_1_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_4_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10_6 mux_right_ipin_5 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_5_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_7 mux_right_ipin_8 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_8_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size10 mux_right_ipin_9 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_9_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_12_ ) , .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size10_4 mux_right_ipin_13 ( + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_98 ) ) ; +mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[14] , chany_top_in[14] , chany_bottom_in[18] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_13_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( +mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_2_ ) , .p0 ( optlc_net_111 ) ) ; -mux_tree_tapbuf_size8_5 mux_right_ipin_3 ( + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[16] , chany_top_in[16] } ) , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_3_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_6_ ) , .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size8 mux_right_ipin_7 ( + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_98 ) ) ; +mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[12] , chany_top_in[12] } ) , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_7_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_0 mux_right_ipin_10 ( + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_10_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size8_1 mux_right_ipin_11 ( + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[16] , chany_top_in[16] } ) , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_11_ ) , .p0 ( optlc_net_109 ) ) ; -mux_tree_tapbuf_size8_2 mux_right_ipin_14 ( + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_14_ ) , .p0 ( optlc_net_110 ) ) ; -mux_tree_tapbuf_size8_3 mux_right_ipin_15 ( + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[12] , chany_top_in[12] } ) , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_15_ ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , +mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_right_ipin_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , +mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , +mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( - .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , + .X ( ropt_net_112 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_114 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( aps_rename_4_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( aps_rename_5_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chany_top_in[1] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_111 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_29__28 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__39 ( .A ( chany_top_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( + .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_top_in[16] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_1_ ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( aps_rename_2_ ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( aps_rename_4_ ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_5_ ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_112 ) , .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_113 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_114 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_115 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , + .X ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_116 ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_117 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_71 ) , - .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( aps_rename_1_ ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_59 ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v new file mode 100644 index 0000000..0f65450 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v @@ -0,0 +1,1778 @@ +// +// +// +// +// +// +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +assign ccff_tail[0] = mem_out[0] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +endmodule + + +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; + +assign FPGA_IN = SOC_IN ; +assign SOC_OUT = FPGA_OUT ; +assign SOC_DIR = FPGA_DIR ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_0_en ; +wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_15 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_12 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_11 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_10 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_9 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_8 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_7 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_3 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_2 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; + +assign const1[0] = 1'b1 ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; +// + +assign chany_bottom_out[0] = chany_top_in[0] ; +assign chany_bottom_out[1] = chany_top_in[1] ; +assign chany_bottom_out[2] = chany_top_in[2] ; +assign chany_bottom_out[3] = chany_top_in[3] ; +assign chany_bottom_out[4] = chany_top_in[4] ; +assign chany_bottom_out[5] = chany_top_in[5] ; +assign chany_bottom_out[6] = chany_top_in[6] ; +assign chany_bottom_out[7] = chany_top_in[7] ; +assign chany_bottom_out[8] = chany_top_in[8] ; +assign chany_bottom_out[9] = chany_top_in[9] ; +assign chany_bottom_out[10] = chany_top_in[10] ; +assign chany_bottom_out[11] = chany_top_in[11] ; +assign chany_bottom_out[12] = chany_top_in[12] ; +assign chany_bottom_out[13] = chany_top_in[13] ; +assign chany_bottom_out[14] = chany_top_in[14] ; +assign chany_bottom_out[15] = chany_top_in[15] ; +assign chany_bottom_out[16] = chany_top_in[16] ; +assign chany_bottom_out[17] = chany_top_in[17] ; +assign chany_bottom_out[18] = chany_top_in[18] ; +assign chany_bottom_out[19] = chany_top_in[19] ; +assign chany_top_out[0] = chany_bottom_in[0] ; +assign chany_top_out[1] = chany_bottom_in[1] ; +assign chany_top_out[2] = chany_bottom_in[2] ; +assign chany_top_out[3] = chany_bottom_in[3] ; +assign chany_top_out[4] = chany_bottom_in[4] ; +assign chany_top_out[5] = chany_bottom_in[5] ; +assign chany_top_out[6] = chany_bottom_in[6] ; +assign chany_top_out[7] = chany_bottom_in[7] ; +assign chany_top_out[8] = chany_bottom_in[8] ; +assign chany_top_out[9] = chany_bottom_in[9] ; +assign chany_top_out[10] = chany_bottom_in[10] ; +assign chany_top_out[11] = chany_bottom_in[11] ; +assign chany_top_out[12] = chany_bottom_in[12] ; +assign chany_top_out[13] = chany_bottom_in[13] ; +assign chany_top_out[14] = chany_bottom_in[14] ; +assign chany_top_out[15] = chany_bottom_in[15] ; +assign chany_top_out[16] = chany_bottom_in[16] ; +assign chany_top_out[17] = chany_bottom_in[17] ; +assign chany_top_out[18] = chany_bottom_in[18] ; +assign chany_top_out[19] = chany_bottom_in[19] ; + +mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( right_grid_pin_0_ ) ) ; +mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_16_ ) ) ; +mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_19_ ) ) ; +mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_20_ ) ) ; +mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_23_ ) ) ; +mux_tree_tapbuf_size10 mux_right_ipin_8 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_24_ ) ) ; +mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_27_ ) ) ; +mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_28_ ) ) ; +mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( left_grid_pin_31_ ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_17_ ) ) ; +mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_18_ ) ) ; +mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_21_ ) ) ; +mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_22_ ) ) ; +mux_tree_tapbuf_size8 mux_right_ipin_9 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_25_ ) ) ; +mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_26_ ) ) ; +mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_29_ ) ) ; +mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_30_ ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_41 } ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_42 } ) ) ; +sky130_fd_sc_hd__buf_4 FTB_41__40 ( + .A ( left_width_0_height_0__pin_1_upper[0] ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_731 ( .A ( ropt_net_41 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_732 ( .A ( ropt_net_42 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v new file mode 100644 index 0000000..f319bd8 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v @@ -0,0 +1,2600 @@ +// +// +// +// +// +// +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[0] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; + +assign FPGA_IN = SOC_IN ; +assign SOC_OUT = FPGA_OUT ; +assign SOC_DIR = FPGA_DIR ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_0_en ; +wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ; +supply1 VDD ; +supply0 VSS ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , + VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +assign chany_bottom_out[0] = chany_top_in[0] ; +assign chany_bottom_out[1] = chany_top_in[1] ; +assign chany_bottom_out[2] = chany_top_in[2] ; +assign chany_bottom_out[3] = chany_top_in[3] ; +assign chany_bottom_out[4] = chany_top_in[4] ; +assign chany_bottom_out[5] = chany_top_in[5] ; +assign chany_bottom_out[6] = chany_top_in[6] ; +assign chany_bottom_out[7] = chany_top_in[7] ; +assign chany_bottom_out[8] = chany_top_in[8] ; +assign chany_bottom_out[9] = chany_top_in[9] ; +assign chany_bottom_out[10] = chany_top_in[10] ; +assign chany_bottom_out[11] = chany_top_in[11] ; +assign chany_bottom_out[12] = chany_top_in[12] ; +assign chany_bottom_out[13] = chany_top_in[13] ; +assign chany_bottom_out[14] = chany_top_in[14] ; +assign chany_bottom_out[15] = chany_top_in[15] ; +assign chany_bottom_out[16] = chany_top_in[16] ; +assign chany_bottom_out[17] = chany_top_in[17] ; +assign chany_bottom_out[18] = chany_top_in[18] ; +assign chany_bottom_out[19] = chany_top_in[19] ; +assign chany_top_out[0] = chany_bottom_in[0] ; +assign chany_top_out[1] = chany_bottom_in[1] ; +assign chany_top_out[2] = chany_bottom_in[2] ; +assign chany_top_out[3] = chany_bottom_in[3] ; +assign chany_top_out[4] = chany_bottom_in[4] ; +assign chany_top_out[5] = chany_bottom_in[5] ; +assign chany_top_out[6] = chany_bottom_in[6] ; +assign chany_top_out[7] = chany_bottom_in[7] ; +assign chany_top_out[8] = chany_bottom_in[8] ; +assign chany_top_out[9] = chany_bottom_in[9] ; +assign chany_top_out[10] = chany_bottom_in[10] ; +assign chany_top_out[11] = chany_bottom_in[11] ; +assign chany_top_out[12] = chany_bottom_in[12] ; +assign chany_top_out[13] = chany_bottom_in[13] ; +assign chany_top_out[14] = chany_bottom_in[14] ; +assign chany_top_out[15] = chany_bottom_in[15] ; +assign chany_top_out[16] = chany_bottom_in[16] ; +assign chany_top_out[17] = chany_bottom_in[17] ; +assign chany_top_out[18] = chany_bottom_in[18] ; +assign chany_top_out[19] = chany_bottom_in[19] ; + +mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10 mux_right_ipin_8 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8 mux_right_ipin_9 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_41 } ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_42 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1494 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1495 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1496 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1497 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1498 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1499 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1500 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1501 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1502 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1503 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1504 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1505 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1506 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1507 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1508 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 FTB_41__40 ( + .A ( left_width_0_height_0__pin_1_upper[0] ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_731 ( .A ( ropt_net_41 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_732 ( .A ( ropt_net_42 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x69000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x87400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x69000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x87400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v new file mode 100644 index 0000000..4e481d0 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v @@ -0,0 +1,1642 @@ +// +// +// +// +// +// +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +assign ccff_tail[0] = mem_out[0] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +endmodule + + +module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , + FPGA_DIR ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; + +assign FPGA_IN = SOC_IN ; +assign SOC_OUT = FPGA_OUT ; +assign SOC_DIR = FPGA_DIR ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_0_en ; +wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ; + +EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) ) ; +EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , + gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , + io_outpad , ccff_head , io_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; + +wire [0:0] const1_0_const1 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , + .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; +// + +assign chany_bottom_out[0] = chany_top_in[0] ; +assign chany_bottom_out[1] = chany_top_in[1] ; +assign chany_bottom_out[2] = chany_top_in[2] ; +assign chany_bottom_out[3] = chany_top_in[3] ; +assign chany_bottom_out[4] = chany_top_in[4] ; +assign chany_bottom_out[5] = chany_top_in[5] ; +assign chany_bottom_out[6] = chany_top_in[6] ; +assign chany_bottom_out[7] = chany_top_in[7] ; +assign chany_bottom_out[8] = chany_top_in[8] ; +assign chany_bottom_out[9] = chany_top_in[9] ; +assign chany_bottom_out[10] = chany_top_in[10] ; +assign chany_bottom_out[11] = chany_top_in[11] ; +assign chany_bottom_out[12] = chany_top_in[12] ; +assign chany_bottom_out[13] = chany_top_in[13] ; +assign chany_bottom_out[14] = chany_top_in[14] ; +assign chany_bottom_out[15] = chany_top_in[15] ; +assign chany_bottom_out[16] = chany_top_in[16] ; +assign chany_bottom_out[17] = chany_top_in[17] ; +assign chany_bottom_out[18] = chany_top_in[18] ; +assign chany_bottom_out[19] = chany_top_in[19] ; +assign chany_top_out[0] = chany_bottom_in[0] ; +assign chany_top_out[1] = chany_bottom_in[1] ; +assign chany_top_out[2] = chany_bottom_in[2] ; +assign chany_top_out[3] = chany_bottom_in[3] ; +assign chany_top_out[4] = chany_bottom_in[4] ; +assign chany_top_out[5] = chany_bottom_in[5] ; +assign chany_top_out[6] = chany_bottom_in[6] ; +assign chany_top_out[7] = chany_bottom_in[7] ; +assign chany_top_out[8] = chany_bottom_in[8] ; +assign chany_top_out[9] = chany_bottom_in[9] ; +assign chany_top_out[10] = chany_bottom_in[10] ; +assign chany_top_out[11] = chany_bottom_in[11] ; +assign chany_top_out[12] = chany_bottom_in[12] ; +assign chany_top_out[13] = chany_bottom_in[13] ; +assign chany_top_out[14] = chany_bottom_in[14] ; +assign chany_top_out[15] = chany_bottom_in[15] ; +assign chany_top_out[16] = chany_bottom_in[16] ; +assign chany_top_out[17] = chany_bottom_in[17] ; +assign chany_top_out[18] = chany_bottom_in[18] ; +assign chany_top_out[19] = chany_bottom_in[19] ; + +mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( right_grid_pin_0_ ) ) ; +mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_16_ ) ) ; +mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_19_ ) ) ; +mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_20_ ) ) ; +mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_23_ ) ) ; +mux_tree_tapbuf_size10 mux_right_ipin_8 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_24_ ) ) ; +mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_27_ ) ) ; +mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_28_ ) ) ; +mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( left_grid_pin_31_ ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_17_ ) ) ; +mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_18_ ) ) ; +mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_21_ ) ) ; +mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_22_ ) ) ; +mux_tree_tapbuf_size8 mux_right_ipin_9 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[14] , chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_25_ ) ) ; +mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_26_ ) ) ; +mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , + chany_bottom_in[18] , chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_29_ ) ) ; +mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_30_ ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_41 } ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_42 } ) ) ; +sky130_fd_sc_hd__buf_4 FTB_41__40 ( + .A ( left_width_0_height_0__pin_1_upper[0] ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_731 ( .A ( ropt_net_41 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_732 ( .A ( ropt_net_42 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v index 9d60ce5..5d2854f 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v @@ -4,36 +4,78 @@ // // // -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__39 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -43,29 +85,103 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -74,273 +190,37 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -352,128 +232,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__33 ( .A ( mem_out[1] ) , - .X ( net_aps_33 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( net_aps_33 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , + .X ( net_aps_35 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -490,41 +251,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -541,17 +268,346 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_83 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + module const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -578,7 +634,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -605,7 +661,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -632,7 +688,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -659,7 +715,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -686,7 +742,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -713,7 +769,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -740,7 +796,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -767,7 +823,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -779,13 +835,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_81 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -802,13 +858,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -817,7 +877,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -844,7 +904,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -867,24 +927,20 @@ endmodule module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , - right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , - right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , - right_bottom_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - ccff_tail ) ; + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , + chany_top_out , chanx_right_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; @@ -896,6 +952,14 @@ wire [0:1] mux_tree_tapbuf_size2_10_sram ; wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; @@ -916,6 +980,10 @@ wire [0:1] mux_tree_tapbuf_size2_9_sram ; wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; @@ -925,93 +993,107 @@ wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; // -mux_tree_tapbuf_size2_8 mux_top_track_0 ( +mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_10 mux_top_track_4 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_9 mux_top_track_24 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( { ropt_net_107 } ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_10 ( - .in ( { chany_top_in[4] , right_top_grid_pin_43_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_11 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_12 ( - .in ( { chany_top_in[5] , right_top_grid_pin_44_[0] } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_14 ( - .in ( { chany_top_in[6] , right_top_grid_pin_45_[0] } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_16 ( - .in ( { chany_top_in[7] , right_top_grid_pin_46_[0] } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_18 ( - .in ( { chany_top_in[8] , right_top_grid_pin_47_[0] } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_20 ( - .in ( { chany_top_in[9] , right_top_grid_pin_48_[0] } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_22 ( - .in ( { chany_top_in[10] , right_top_grid_pin_49_[0] } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_26 ( - .in ( { chany_top_in[12] , right_top_grid_pin_43_[0] } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_106 } ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , @@ -1021,233 +1103,208 @@ mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , +mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_105 } ) , +mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size6_0 mux_right_track_0 ( - .in ( { chany_top_in[19] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size6 mux_right_track_4 ( - .in ( { chany_top_in[1] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , +mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( { ropt_net_110 } ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( { ropt_net_118 } ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_right_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size5 mux_right_track_6 ( - .in ( { chany_top_in[2] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3 mux_right_track_8 ( - .in ( { chany_top_in[3] , right_top_grid_pin_42_[0] , - right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_0 mux_right_track_24 ( - .in ( { chany_top_in[11] , right_top_grid_pin_42_[0] , - right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_right_in[7] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_697 ( .A ( ropt_net_113 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_114 ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_44 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_47 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , - .X ( BUF_net_49 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_115 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_116 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[17] ) , .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_117 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , - .X ( BUF_net_56 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_132 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_69 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_76 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_77 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( aps_rename_2_ ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( BUF_net_49 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_right_in[8] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_56 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_125 ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_127 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_110 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[4] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_78 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( BUF_net_58 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , + .X ( chanx_right_out[18] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v index 0faa575..02aaba8 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v @@ -4,117 +4,7 @@ // // // -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -136,12 +26,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__37 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -163,13 +53,67 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__36 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -181,173 +125,30 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -359,38 +160,99 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -409,177 +271,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__33 ( .A ( mem_out[1] ) , - .X ( net_aps_33 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( net_aps_33 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , + .X ( net_aps_35 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -603,55 +297,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -675,11 +321,402 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_83 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -888,55 +925,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_81 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -963,7 +952,88 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -990,24 +1060,20 @@ endmodule module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , - right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , - right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , - right_bottom_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - ccff_tail , VDD , VSS ) ; + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , + chany_top_out , chanx_right_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; @@ -1021,6 +1087,14 @@ wire [0:1] mux_tree_tapbuf_size2_10_sram ; wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; @@ -1041,6 +1115,10 @@ wire [0:1] mux_tree_tapbuf_size2_9_sram ; wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; @@ -1050,107 +1128,125 @@ wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size2_8 mux_top_track_0 ( +mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_10 mux_top_track_4 ( + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_102 ) ) ; mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_9 mux_top_track_24 ( + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( { ropt_net_107 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_10 ( - .in ( { chany_top_in[4] , right_top_grid_pin_43_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_11 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_12 ( - .in ( { chany_top_in[5] , right_top_grid_pin_44_[0] } ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_14 ( - .in ( { chany_top_in[6] , right_top_grid_pin_45_[0] } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_16 ( - .in ( { chany_top_in[7] , right_top_grid_pin_46_[0] } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_18 ( - .in ( { chany_top_in[8] , right_top_grid_pin_47_[0] } ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_20 ( - .in ( { chany_top_in[9] , right_top_grid_pin_48_[0] } ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_22 ( - .in ( { chany_top_in[10] , right_top_grid_pin_49_[0] } ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_26 ( - .in ( { chany_top_in[12] , right_top_grid_pin_43_[0] } ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_top_track_0 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_106 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , @@ -1162,300 +1258,274 @@ mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , +mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_105 } ) , +mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_0 mux_right_track_0 ( - .in ( { chany_top_in[19] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , +mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( { ropt_net_110 } ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size6 mux_right_track_4 ( - .in ( { chany_top_in[1] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( { ropt_net_118 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size5 mux_right_track_6 ( - .in ( { chany_top_in[2] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , +mux_tree_tapbuf_size4 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3 mux_right_track_8 ( - .in ( { chany_top_in[3] , right_top_grid_pin_42_[0] , - right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_0 mux_right_track_24 ( - .in ( { chany_top_in[11] , right_top_grid_pin_42_[0] , - right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2217 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1219 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2218 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1220 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2219 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1221 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2220 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1222 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2221 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1223 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2222 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1224 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2223 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1225 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2224 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1226 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2225 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1227 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2226 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1228 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2227 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1229 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2228 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1230 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2229 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1231 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2230 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1232 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2231 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1233 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2232 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1234 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_right_in[7] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_697 ( .A ( ropt_net_113 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_114 ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_44 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_47 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , - .X ( BUF_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_115 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_116 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[17] ) , .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_117 ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , - .X ( BUF_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_132 ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_69 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_76 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_77 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( aps_rename_2_ ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( BUF_net_49 ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_right_in[8] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_56 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_125 ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_127 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_110 ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , + .X ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[4] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_78 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( BUF_net_58 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( @@ -1464,14 +1534,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( @@ -1518,14 +1588,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y27200 ( @@ -1540,16 +1610,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( @@ -1592,13 +1662,13 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1618,14 +1688,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y81600 ( @@ -1634,66 +1704,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y108800 ( @@ -1720,38 +1794,36 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( @@ -1766,36 +1838,28 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( @@ -1816,32 +1880,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( @@ -1856,26 +1920,18 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y217600 ( @@ -1892,27 +1948,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1932,15 +1992,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1956,30 +2032,28 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( @@ -1992,39 +2066,33 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2040,33 +2108,29 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2082,36 +2146,34 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( @@ -2122,41 +2184,37 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2174,24 +2232,24 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( @@ -2200,30 +2258,38 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y462400 ( @@ -2236,26 +2302,42 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y489600 ( @@ -2266,64 +2348,68 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y544000 ( @@ -2332,231 +2418,249 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2584,14 +2688,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v index 53afb7d..2edde34 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v @@ -4,89 +4,7 @@ // // // -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -100,12 +18,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__37 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -119,13 +37,51 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__36 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -135,135 +91,25 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -273,32 +119,80 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -310,128 +204,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__33 ( .A ( mem_out[1] ) , - .X ( net_aps_33 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( net_aps_33 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , + .X ( net_aps_35 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -448,41 +223,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -499,11 +240,292 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_83 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -664,43 +686,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_81 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -720,7 +706,67 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -741,24 +787,20 @@ endmodule module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , - right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , - right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , - right_bottom_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - ccff_tail ) ; + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , + chany_top_out , chanx_right_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; @@ -770,6 +812,14 @@ wire [0:1] mux_tree_tapbuf_size2_10_sram ; wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; @@ -790,6 +840,10 @@ wire [0:1] mux_tree_tapbuf_size2_9_sram ; wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; @@ -799,93 +853,107 @@ wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; // -mux_tree_tapbuf_size2_8 mux_top_track_0 ( +mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_10 mux_top_track_4 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_9 mux_top_track_24 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( { ropt_net_107 } ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_10 ( - .in ( { chany_top_in[4] , right_top_grid_pin_43_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_11 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_12 ( - .in ( { chany_top_in[5] , right_top_grid_pin_44_[0] } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_14 ( - .in ( { chany_top_in[6] , right_top_grid_pin_45_[0] } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_16 ( - .in ( { chany_top_in[7] , right_top_grid_pin_46_[0] } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_18 ( - .in ( { chany_top_in[8] , right_top_grid_pin_47_[0] } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_20 ( - .in ( { chany_top_in[9] , right_top_grid_pin_48_[0] } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_22 ( - .in ( { chany_top_in[10] , right_top_grid_pin_49_[0] } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_26 ( - .in ( { chany_top_in[12] , right_top_grid_pin_43_[0] } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_106 } ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , @@ -895,233 +963,208 @@ mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , +mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_105 } ) , +mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size6_0 mux_right_track_0 ( - .in ( { chany_top_in[19] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size6 mux_right_track_4 ( - .in ( { chany_top_in[1] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , +mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( { ropt_net_110 } ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( { ropt_net_118 } ) , + .p0 ( optlc_net_103 ) ) ; +mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_right_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size4 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size5 mux_right_track_6 ( - .in ( { chany_top_in[2] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3 mux_right_track_8 ( - .in ( { chany_top_in[3] , right_top_grid_pin_42_[0] , - right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_0 mux_right_track_24 ( - .in ( { chany_top_in[11] , right_top_grid_pin_42_[0] , - right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_104 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_right_in[7] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_697 ( .A ( ropt_net_113 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_114 ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_44 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_47 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , - .X ( BUF_net_49 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_115 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_116 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[17] ) , .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_117 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , - .X ( BUF_net_56 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_132 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_69 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_76 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_77 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( aps_rename_2_ ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_83 ( .A ( BUF_net_49 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_right_in[8] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_56 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_125 ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_127 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_110 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[4] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_78 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( BUF_net_58 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , + .X ( chanx_right_out[18] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v index 9e5bf43..bb44fad 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v @@ -16,7 +16,92 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -48,6 +133,141 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -60,9 +280,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__57 ( .A ( mem_out[1] ) , - .X ( net_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( net_net_101 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , + .X ( net_net_82 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( net_net_82 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -79,7 +299,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -96,7 +316,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -113,7 +333,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -130,7 +350,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -304,7 +524,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -323,7 +543,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -342,7 +562,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -502,7 +722,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -521,7 +741,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -540,7 +760,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -559,7 +779,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -578,7 +798,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -597,7 +817,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -616,7 +836,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -710,8 +930,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -723,6 +941,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -880,7 +1100,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -899,7 +1119,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -918,7 +1138,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -937,7 +1157,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -956,7 +1176,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__38 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1170,7 +1390,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__37 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1189,7 +1409,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__36 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1208,7 +1428,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__35 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1227,7 +1447,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__34 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1246,7 +1466,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__33 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1265,7 +1485,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__32 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1284,7 +1504,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__31 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1591,23 +1811,24 @@ endmodule module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , - right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , - right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , - chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , - chanx_right_out , chany_bottom_out , ccff_tail ) ; + chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_left_grid_pin_1_ ; input [0:0] ccff_head ; @@ -1618,7 +1839,22 @@ output [0:0] ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -1706,44 +1942,44 @@ mux_tree_tapbuf_size6_4 mux_top_track_0 ( chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size6_3 mux_right_track_0 ( - .in ( { chany_top_in[2] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , chany_bottom_in[2] } ) , + .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_121 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_121 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1765,7 +2001,7 @@ mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; @@ -1784,31 +2020,31 @@ mux_tree_tapbuf_size5 mux_top_track_2 ( chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , @@ -1839,43 +2075,44 @@ mux_tree_tapbuf_size4_5 mux_top_track_24 ( chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size4_4 mux_right_track_8 ( - .in ( { chany_top_in[7] , chany_top_in[8] , right_top_grid_pin_42_[0] , + .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4_0 mux_right_track_10 ( - .in ( { chany_top_in[9] , chany_top_in[11] , right_top_grid_pin_43_[0] , - chany_bottom_in[9] } ) , + .in ( { chany_top_in[9] , chany_top_in[11] , + right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size4_1 mux_right_track_12 ( - .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_44_[0] , - chany_bottom_in[10] } ) , + .in ( { chany_top_in[10] , chany_top_in[15] , + right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( { ropt_net_130 } ) , + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size4_2 mux_right_track_14 ( - .in ( { chany_top_in[12] , chany_top_in[19] , right_top_grid_pin_45_[0] , - chany_bottom_in[12] } ) , + .in ( { chany_top_in[12] , chany_top_in[19] , + right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size4_3 mux_right_track_24 ( - .in ( { chany_top_in[18] , right_top_grid_pin_42_[0] , + .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -1912,26 +2149,26 @@ mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; mux_tree_tapbuf_size7_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[4] } ) , + .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size7_1 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , chany_bottom_in[5] } ) , + .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size7 mux_right_track_6 ( - .in ( { chany_top_in[3] , chany_top_in[6] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[6] } ) , + .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -1948,34 +2185,34 @@ mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; mux_tree_tapbuf_size3_1 mux_right_track_16 ( - .in ( { chany_top_in[13] , right_top_grid_pin_46_[0] , + .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size3_2 mux_right_track_18 ( - .in ( { chany_top_in[14] , right_top_grid_pin_47_[0] , + .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size3_3 mux_right_track_20 ( - .in ( { chany_top_in[16] , right_top_grid_pin_48_[0] , + .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size3 mux_right_track_22 ( - .in ( { chany_top_in[17] , right_top_grid_pin_49_[0] , + .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -1998,155 +2235,169 @@ mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_127 } ) , + .ccff_tail ( { ropt_net_131 } ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size2 mux_right_track_26 ( - .in ( { right_top_grid_pin_43_[0] , chany_bottom_in[15] } ) , +mux_tree_tapbuf_size2_0 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size2_mem mem_right_track_26 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_123 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_127 ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_129 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[4] ) , +mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_right_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[2] ) , .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_140 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_142 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_143 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[17] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_152 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_153 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_155 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_144 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chany_bottom_in[13] ) , +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_157 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( BUF_net_69 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[2] ) , .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_158 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_139 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_161 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_162 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_bottom_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[4] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_148 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[14] ) , + .X ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_149 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_150 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_151 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_152 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_153 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( BUF_net_69 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( chany_top_in[8] ) , .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_75 ) , + .X ( ropt_net_153 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v index 7e087e2..0af336e 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v @@ -23,7 +23,127 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54,6 +174,136 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -73,9 +323,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__57 ( .A ( mem_out[1] ) , - .X ( net_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( net_net_101 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , + .X ( net_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( net_net_82 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -99,7 +349,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -123,7 +373,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -147,7 +397,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -171,7 +421,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -353,7 +603,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -380,7 +630,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -407,7 +657,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -581,7 +831,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -608,7 +858,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -635,7 +885,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -662,7 +912,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -689,7 +939,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -716,7 +966,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -743,7 +993,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -834,9 +1084,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -850,6 +1097,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -1015,7 +1265,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1042,7 +1292,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1069,7 +1319,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1096,7 +1346,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1123,7 +1373,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__38 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1350,7 +1600,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__37 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1377,7 +1627,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__36 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1404,7 +1654,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__35 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1431,7 +1681,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__34 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1458,7 +1708,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__33 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1485,7 +1735,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__32 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1512,7 +1762,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__31 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1826,23 +2076,24 @@ endmodule module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , - right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , - right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , - chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , - chanx_right_out , chany_bottom_out , ccff_tail , VDD , VSS ) ; + chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_left_grid_pin_1_ ; input [0:0] ccff_head ; @@ -1855,7 +2106,22 @@ input VSS ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -1946,50 +2212,50 @@ mux_tree_tapbuf_size6_4 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size6_3 mux_right_track_0 ( - .in ( { chany_top_in[2] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , chany_bottom_in[2] } ) , + .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -2015,7 +2281,7 @@ mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) , .VDD ( VDD ) , @@ -2038,35 +2304,35 @@ mux_tree_tapbuf_size5 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , @@ -2103,49 +2369,49 @@ mux_tree_tapbuf_size4_5 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size4_4 mux_right_track_8 ( - .in ( { chany_top_in[7] , chany_top_in[8] , right_top_grid_pin_42_[0] , + .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4_0 mux_right_track_10 ( - .in ( { chany_top_in[9] , chany_top_in[11] , right_top_grid_pin_43_[0] , - chany_bottom_in[9] } ) , + .in ( { chany_top_in[9] , chany_top_in[11] , + right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size4_1 mux_right_track_12 ( - .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_44_[0] , - chany_bottom_in[10] } ) , + .in ( { chany_top_in[10] , chany_top_in[15] , + right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( { ropt_net_130 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size4_2 mux_right_track_14 ( - .in ( { chany_top_in[12] , chany_top_in[19] , right_top_grid_pin_45_[0] , - chany_bottom_in[12] } ) , + .in ( { chany_top_in[12] , chany_top_in[19] , + right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size4_3 mux_right_track_24 ( - .in ( { chany_top_in[18] , right_top_grid_pin_42_[0] , + .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -2189,29 +2455,29 @@ mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size7_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[4] } ) , + .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size7_1 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , chany_bottom_in[5] } ) , + .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size7 mux_right_track_6 ( - .in ( { chany_top_in[3] , chany_top_in[6] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[6] } ) , + .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -2231,39 +2497,39 @@ mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size3_1 mux_right_track_16 ( - .in ( { chany_top_in[13] , right_top_grid_pin_46_[0] , + .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size3_2 mux_right_track_18 ( - .in ( { chany_top_in[14] , right_top_grid_pin_47_[0] , + .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size3_3 mux_right_track_20 ( - .in ( { chany_top_in[16] , right_top_grid_pin_48_[0] , + .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size3 mux_right_track_22 ( - .in ( { chany_top_in[17] , right_top_grid_pin_49_[0] , + .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -2290,204 +2556,228 @@ mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_127 } ) , + .ccff_tail ( { ropt_net_131 } ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2 mux_right_track_26 ( - .in ( { right_top_grid_pin_43_[0] , chany_bottom_in[15] } ) , +mux_tree_tapbuf_size2_0 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size2_mem mem_right_track_26 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2234 ( .VNB ( VSS ) , +mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem mem_right_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1236 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2235 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1237 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2236 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1238 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2237 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1239 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2238 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1240 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2239 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1241 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2240 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1242 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2241 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1243 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2242 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1244 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2243 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1245 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2244 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1246 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2245 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1247 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2246 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1248 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2247 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1249 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2248 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1250 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2249 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1251 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2250 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1252 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2251 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1253 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2252 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1254 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_164 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_127 ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_129 ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[2] ) , .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_140 ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_142 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_143 ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[17] ) , - .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_152 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_153 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_155 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_144 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chany_bottom_in[13] ) , +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_157 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( BUF_net_69 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[2] ) , .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_158 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_139 ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_161 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_162 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[4] ) , + .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_148 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[14] ) , + .X ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_141 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_149 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_150 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_151 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_152 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_153 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( BUF_net_69 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_75 ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( @@ -2504,14 +2794,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( @@ -2526,365 +2816,383 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x64400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x64400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2892,223 +3200,229 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x96600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3118,139 +3432,151 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x69000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x105800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x69000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x87400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x96600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3258,59 +3584,61 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3318,280 +3646,262 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x59800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( @@ -3614,14 +3924,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y952000 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v index 56890ca..b7ded23 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v @@ -16,7 +16,92 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -41,6 +126,106 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -53,9 +238,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__57 ( .A ( mem_out[1] ) , - .X ( net_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( net_net_101 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , + .X ( net_net_82 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( net_net_82 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -72,7 +257,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -89,7 +274,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -106,7 +291,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -123,7 +308,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -262,7 +447,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -281,7 +466,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -300,7 +485,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -439,7 +624,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -458,7 +643,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -477,7 +662,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -496,7 +681,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -515,7 +700,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -534,7 +719,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -553,7 +738,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -626,8 +811,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -639,6 +822,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -768,7 +953,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -787,7 +972,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -806,7 +991,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -825,7 +1010,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -844,7 +1029,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__38 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1023,7 +1208,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__37 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1042,7 +1227,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__36 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1061,7 +1246,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__35 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1080,7 +1265,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__34 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1099,7 +1284,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__33 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1118,7 +1303,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__32 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1137,7 +1322,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__31 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1395,23 +1580,24 @@ endmodule module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , - right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , - right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , - chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , - chanx_right_out , chany_bottom_out , ccff_tail ) ; + chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_left_grid_pin_1_ ; input [0:0] ccff_head ; @@ -1422,7 +1608,22 @@ output [0:0] ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -1510,44 +1711,44 @@ mux_tree_tapbuf_size6_4 mux_top_track_0 ( chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size6_3 mux_right_track_0 ( - .in ( { chany_top_in[2] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , chany_bottom_in[2] } ) , + .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_121 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_121 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1569,7 +1770,7 @@ mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; @@ -1588,31 +1789,31 @@ mux_tree_tapbuf_size5 mux_top_track_2 ( chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , @@ -1643,43 +1844,44 @@ mux_tree_tapbuf_size4_5 mux_top_track_24 ( chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size4_4 mux_right_track_8 ( - .in ( { chany_top_in[7] , chany_top_in[8] , right_top_grid_pin_42_[0] , + .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4_0 mux_right_track_10 ( - .in ( { chany_top_in[9] , chany_top_in[11] , right_top_grid_pin_43_[0] , - chany_bottom_in[9] } ) , + .in ( { chany_top_in[9] , chany_top_in[11] , + right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size4_1 mux_right_track_12 ( - .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_44_[0] , - chany_bottom_in[10] } ) , + .in ( { chany_top_in[10] , chany_top_in[15] , + right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( { ropt_net_130 } ) , + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size4_2 mux_right_track_14 ( - .in ( { chany_top_in[12] , chany_top_in[19] , right_top_grid_pin_45_[0] , - chany_bottom_in[12] } ) , + .in ( { chany_top_in[12] , chany_top_in[19] , + right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size4_3 mux_right_track_24 ( - .in ( { chany_top_in[18] , right_top_grid_pin_42_[0] , + .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -1716,26 +1918,26 @@ mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; mux_tree_tapbuf_size7_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[4] } ) , + .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size7_1 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , chany_bottom_in[5] } ) , + .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size7 mux_right_track_6 ( - .in ( { chany_top_in[3] , chany_top_in[6] , right_top_grid_pin_43_[0] , - right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[6] } ) , + .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -1752,34 +1954,34 @@ mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; mux_tree_tapbuf_size3_1 mux_right_track_16 ( - .in ( { chany_top_in[13] , right_top_grid_pin_46_[0] , + .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size3_2 mux_right_track_18 ( - .in ( { chany_top_in[14] , right_top_grid_pin_47_[0] , + .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size3_3 mux_right_track_20 ( - .in ( { chany_top_in[16] , right_top_grid_pin_48_[0] , + .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size3 mux_right_track_22 ( - .in ( { chany_top_in[17] , right_top_grid_pin_49_[0] , + .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -1802,155 +2004,169 @@ mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_127 } ) , + .ccff_tail ( { ropt_net_131 } ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size2 mux_right_track_26 ( - .in ( { right_top_grid_pin_43_[0] , chany_bottom_in[15] } ) , +mux_tree_tapbuf_size2_0 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_123 ) ) ; -mux_tree_tapbuf_size2_mem mem_right_track_26 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size2 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_123 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_127 ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_129 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[4] ) , +mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_right_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[2] ) , .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_140 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_142 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_143 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[17] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_152 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_153 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_155 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_144 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chany_bottom_in[13] ) , +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_157 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( BUF_net_69 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[2] ) , .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_158 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_139 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_161 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_162 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_bottom_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[4] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_148 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[14] ) , + .X ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_149 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_150 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_151 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_152 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_153 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( BUF_net_69 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( chany_top_in[8] ) , .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_75 ) , + .X ( ropt_net_153 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v index 8a3e3b9..6d15198 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v @@ -16,9 +16,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__39 ( .A ( mem_out[1] ) , - .X ( net_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_71 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_59 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( net_net_59 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -35,7 +35,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -52,7 +52,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -69,24 +69,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -103,7 +86,177 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -120,7 +273,24 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -137,7 +307,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -169,7 +339,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_6 ( const1 ) ; +module const1_22 ( const1 ) ; output [0:0] const1 ; endmodule @@ -184,6 +354,440 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_75 ( .A ( BUF_net_43 ) , + .X ( out[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( @@ -196,13 +800,47 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + module const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; @@ -210,16 +848,20 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; endmodule @@ -228,8 +870,8 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; @@ -237,16 +879,58 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -255,25 +939,37 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; endmodule @@ -282,25 +978,75 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -309,25 +1055,41 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule @@ -336,43 +1098,91 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , - chany_bottom_out , ccff_tail ) ; + right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_left_grid_pin_1_ ; input [0:0] ccff_head ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; @@ -387,253 +1197,373 @@ wire [0:1] mux_tree_tapbuf_size2_6_sram ; wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; // -mux_tree_tapbuf_size2_4 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[18] } ) , +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size6_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size6 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size5 mux_right_track_6 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size3_0 mux_right_track_24 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[16] } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_12 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[14] } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_24 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_8 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_9 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size2_10 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_12 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_13 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_14 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_15 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_16 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( + .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_103 } ) , +mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_133 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_135 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_136 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_102 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_103 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[3] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_702 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chany_bottom_in[5] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_113 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_114 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_116 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_117 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_118 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_120 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_121 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_122 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( .A ( chanx_right_in[2] ) , - .X ( BUF_net_42 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_140 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_123 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_143 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_124 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_145 ) , +mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_right_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( { ropt_net_106 } ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_146 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_57 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_148 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_125 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_126 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_127 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_128 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_129 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( BUF_net_42 ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_83 ( .A ( chanx_right_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( ropt_net_98 ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[7] ) , + .X ( BUF_net_52 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_115 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_101 ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_102 ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_106 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_72 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_78 ( .A ( BUF_net_52 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_79 ( .A ( chanx_right_in[11] ) , .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_91 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_92 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_80 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , + .X ( ropt_net_114 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v index f516f6a..6946ab3 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v @@ -23,9 +23,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__39 ( .A ( mem_out[1] ) , - .X ( net_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_71 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( net_net_59 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49,7 +49,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -73,7 +73,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -97,31 +97,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -145,7 +121,247 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -169,7 +385,31 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -193,7 +433,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -302,32 +542,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -354,6 +568,273 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -368,6 +849,34 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_43 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_75 ( .A ( BUF_net_43 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -406,23 +915,441 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , - chany_bottom_out , ccff_tail , VDD , VSS ) ; + right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_left_grid_pin_1_ ; input [0:0] ccff_head ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; input VDD ; input VSS ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; @@ -437,311 +1364,461 @@ wire [0:1] mux_tree_tapbuf_size2_6_sram ; wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size2_4 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[18] } ) , +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size6_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size6 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_0 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size5 mux_right_track_6 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size3_0 mux_right_track_24 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[16] } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_12 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[14] } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_24 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_8 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_9 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size2_10 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_12 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_13 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_14 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_15 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_16 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( + .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_103 } ) , +mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2254 ( .VNB ( VSS ) , +mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem mem_right_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( { ropt_net_106 } ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1256 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2255 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1257 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2256 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1258 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2257 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1259 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2258 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1260 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2259 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1261 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2260 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1262 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2261 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1263 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2262 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1264 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2263 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1265 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2264 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1266 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2265 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1267 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2266 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1268 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2267 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1269 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2268 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1270 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2269 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1271 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_133 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_135 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_154 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_136 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_102 ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_103 ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[3] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_702 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_152 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chany_bottom_in[5] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_113 ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_114 ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_116 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_117 ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_118 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_120 ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_121 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_122 ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( .A ( chanx_right_in[2] ) , - .X ( BUF_net_42 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_140 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_123 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_143 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_124 ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_145 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_146 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_57 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_148 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_125 ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_126 ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_127 ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_128 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_129 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( BUF_net_42 ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_83 ( .A ( chanx_right_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( ropt_net_98 ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[7] ) , + .X ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_115 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_101 ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_102 ) , + .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , + .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , + .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_106 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_72 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_78 ( .A ( BUF_net_52 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_79 ( .A ( chanx_right_in[11] ) , .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_80 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , + .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_91 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_92 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( @@ -758,14 +1835,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( @@ -784,46 +1861,46 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( @@ -832,85 +1909,83 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -918,139 +1993,109 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1058,29 +2103,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1088,46 +2135,20 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( @@ -1136,35 +2157,39 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1172,42 +2197,36 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y353600 ( @@ -1218,33 +2237,27 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1260,81 +2273,63 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1350,39 +2345,37 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1392,193 +2385,177 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1598,29 +2575,27 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1640,35 +2615,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1688,32 +2659,36 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( @@ -1736,32 +2711,36 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( @@ -1796,13 +2775,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1830,14 +2815,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y734400 ( @@ -1852,16 +2837,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( @@ -1930,14 +2915,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v index a6e4689..d2ca854 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v @@ -16,9 +16,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__39 ( .A ( mem_out[1] ) , - .X ( net_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_71 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_59 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( net_net_59 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -35,7 +35,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -52,7 +52,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -69,24 +69,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -103,7 +86,177 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -120,7 +273,24 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -137,7 +307,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -222,26 +392,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -262,6 +412,206 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -272,6 +622,28 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_75 ( .A ( BUF_net_43 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -302,21 +674,347 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , - chany_bottom_out , ccff_tail ) ; + right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_left_grid_pin_1_ ; input [0:0] ccff_head ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; @@ -331,253 +1029,373 @@ wire [0:1] mux_tree_tapbuf_size2_6_sram ; wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; // -mux_tree_tapbuf_size2_4 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[18] } ) , +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size6_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size6 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size5 mux_right_track_6 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size3_0 mux_right_track_24 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[16] } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_12 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[14] } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_24 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_8 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_9 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ; +mux_tree_tapbuf_size2_10 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; +mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_97 ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_12 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_13 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_14 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2_15 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_16 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; +mux_tree_tapbuf_size2 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( + .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_103 } ) , +mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_133 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_134 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_135 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_136 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_102 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_103 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[3] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_702 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chany_bottom_in[5] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_113 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_114 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_116 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_117 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_118 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_120 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_121 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_122 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( .A ( chanx_right_in[2] ) , - .X ( BUF_net_42 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_140 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_123 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_143 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_124 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_145 ) , +mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_right_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( { ropt_net_106 } ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_146 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_57 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_148 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_125 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_126 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_127 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_128 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_129 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_151 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( BUF_net_42 ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_83 ( .A ( chanx_right_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( ropt_net_98 ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[7] ) , + .X ( BUF_net_52 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_115 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_101 ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_102 ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_106 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_72 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_78 ( .A ( BUF_net_52 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_79 ( .A ( chanx_right_in[11] ) , .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_91 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_92 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_80 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , + .X ( ropt_net_114 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v index 9557bb9..3fed6b9 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v @@ -4,13 +4,13 @@ // // // -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; @@ -18,9 +18,28 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( net_net_105 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -30,10 +49,10 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; @@ -42,45 +61,64 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; endmodule @@ -98,7 +136,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__58 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -117,12 +155,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_31 ( const1 ) ; +module const1_25 ( const1 ) ; output [0:0] const1 ; endmodule @@ -139,12 +177,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_31 const1_0_ ( +const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -158,14 +193,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule -module const1_30 ( const1 ) ; +module const1_24 ( const1 ) ; output [0:0] const1 ; endmodule @@ -182,9 +216,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_30 const1_0_ ( +const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -199,64 +232,124 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_29 ( const1 ) ; +module const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; +module mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; @@ -264,9 +357,6 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -277,10 +367,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_29 const1_0_ ( +const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -289,262 +379,30 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module const1_28 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; endmodule @@ -560,193 +418,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - module const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -780,24 +462,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -814,7 +479,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -831,7 +496,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -848,7 +513,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -865,7 +530,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -882,7 +547,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -899,7 +564,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -940,7 +605,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -971,7 +636,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1002,7 +667,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1015,6 +680,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -1023,8 +690,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1033,7 +698,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1064,7 +729,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1095,37 +760,6 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -1137,7 +771,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_13 const1_0_ ( +const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -1166,7 +800,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1185,17 +819,52 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + module const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1225,60 +894,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -1293,26 +908,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1331,12 +927,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1350,26 +946,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1388,17 +965,159 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + module const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1445,7 +1164,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1492,7 +1211,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1539,7 +1258,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1586,7 +1305,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1603,6 +1322,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1623,10 +1344,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_104 ( .A ( BUF_net_61 ) , - .X ( out[0] ) ) ; endmodule @@ -1635,7 +1352,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1682,7 +1399,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1724,24 +1441,50 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; + +module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule @@ -1761,12 +1504,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1782,7 +1525,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1803,62 +1546,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - module const1_2 ( const1 ) ; output [0:0] const1 ; endmodule @@ -1915,7 +1607,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2012,77 +1704,61 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , - right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , - right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , - right_top_grid_pin_49_ , right_bottom_grid_pin_1_ , chanx_left_in , - left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , - left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , - left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , - ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail ) ; +module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , + left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , + left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , + left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -2097,8 +1773,6 @@ wire [0:1] mux_tree_tapbuf_size3_5_sram ; wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_6_sram ; wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_7_sram ; -wire [0:1] mux_tree_tapbuf_size3_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -2106,18 +1780,23 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; @@ -2132,6 +1811,10 @@ wire [0:2] mux_tree_tapbuf_size7_5_sram ; wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -2139,132 +1822,127 @@ wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; // +assign SC_IN_TOP = SC_IN_BOT ; + mux_tree_tapbuf_size8 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size8_2 mux_right_track_8 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , - right_bottom_grid_pin_1_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size8_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_3 ( - .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[13] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size8_1 mux_left_track_9 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - chanx_right_in[6] , chanx_right_in[16] , left_top_grid_pin_42_[0] , - left_top_grid_pin_46_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_126 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , +mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_4 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size7_6 mux_top_track_2 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size7_5 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_7 mux_top_track_4 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_130 ) ) ; mux_tree_tapbuf_size7 mux_top_track_6 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_2 mux_right_track_16 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , - chanx_left_in[8] , chanx_left_in[17] } ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_3 mux_right_track_0 ( + .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_3 mux_right_track_24 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , - chanx_left_in[9] , chanx_left_in[18] } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size7_5 mux_right_track_8 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , + chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_0 mux_left_track_17 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_47_[0] } ) , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , + chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_1 mux_left_track_25 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - chanx_right_in[9] , chanx_right_in[18] , left_top_grid_pin_44_[0] , - left_top_grid_pin_48_[0] } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_1 mux_left_track_3 ( + .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[13] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_2 mux_left_track_9 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_0 mux_left_track_17 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , @@ -2274,38 +1952,48 @@ mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_right_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , +mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , +mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) ) ; mux_tree_tapbuf_size4 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , chanx_right_in[8] , + .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4_0 mux_top_track_10 ( - .in ( { top_left_grid_pin_35_[0] , chanx_right_in[9] , + .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_127 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -2317,53 +2005,47 @@ mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; mux_tree_tapbuf_size3_0 mux_top_track_12 ( - .in ( { top_left_grid_pin_36_[0] , chanx_right_in[10] , + .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_37_[0] , chanx_right_in[12] , + .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_2 mux_top_track_16 ( - .in ( { top_left_grid_pin_38_[0] , chanx_right_in[13] , + .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_3 mux_top_track_18 ( - .in ( { top_left_grid_pin_39_[0] , chanx_right_in[14] , + .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_4 mux_top_track_20 ( - .in ( { top_left_grid_pin_40_[0] , chanx_right_in[16] , + .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( { ropt_net_134 } ) , - .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_5 mux_top_track_22 ( - .in ( { top_left_grid_pin_41_[0] , chanx_right_in[17] , + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3_6 mux_top_track_24 ( - .in ( { top_left_grid_pin_34_[0] , chanx_right_in[18] , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size3 mux_top_track_24 ( + .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3 mux_top_track_38 ( - .in ( { top_left_grid_pin_41_[0] , chanx_right_in[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size3_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_7_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -2394,291 +2076,231 @@ mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_0 mux_top_track_28 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[19] } ) , +mux_tree_tapbuf_size2 mux_top_track_38 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_1 mux_top_track_30 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[15] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_2 mux_top_track_32 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_3 mux_top_track_34 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[17] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_36 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_36 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size9_0 mux_right_track_0 ( - .in ( { chany_top_in[6] , chany_top_in[13] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size9 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; -mux_tree_tapbuf_size14 mux_right_track_4 ( +mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , - right_bottom_grid_pin_1_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size14_0 mux_left_track_5 ( + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , + chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - chanx_right_in[5] , chanx_right_in[14] , left_top_grid_pin_42_[0] , - left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , - left_top_grid_pin_49_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size6 mux_right_track_32 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - right_top_grid_pin_45_[0] , right_top_grid_pin_49_[0] , - chanx_left_in[10] } ) , + chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) ) ; +mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) ) ; +mux_tree_tapbuf_size6 mux_right_track_24 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_129 } ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size6_0 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - chanx_right_in[10] , left_top_grid_pin_45_[0] , - left_top_grid_pin_49_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size6_0 mux_left_track_25 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_131 } ) , +mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size10 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - chanx_right_in[2] , chanx_right_in[12] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5 mux_right_track_32 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size5_0 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_35_[0] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[16] ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( { ropt_net_139 } ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_129 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_163 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[7] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_156 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_157 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_134 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_136 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_158 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_159 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_160 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_161 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_162 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_145 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_146 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_164 ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_147 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_148 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_149 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_150 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_168 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_169 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_170 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_171 ) , .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_172 ) , - .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , + .X ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( + .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_153 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_176 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_154 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_155 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_107 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_157 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_114 ( .A ( BUF_net_70 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , + .X ( ropt_net_164 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v index 76d0052..2cfb214 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v @@ -4,13 +4,13 @@ // // // -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; input VDD ; input VSS ; @@ -26,18 +26,44 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( net_net_105 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -48,16 +74,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , @@ -65,34 +86,57 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -118,7 +162,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__58 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -145,7 +189,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -164,13 +208,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -187,10 +227,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -208,7 +248,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; @@ -228,17 +267,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -263,12 +299,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -293,14 +329,14 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:13] in ; +input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; @@ -310,9 +346,6 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -326,7 +359,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , @@ -340,47 +373,37 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:13] in ; +module mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; @@ -390,8 +413,6 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -404,6 +425,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -416,218 +440,32 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -650,103 +488,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -777,110 +519,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -900,31 +538,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -948,7 +562,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -972,7 +586,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -996,7 +610,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1020,7 +634,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1044,7 +658,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1068,7 +682,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1104,37 +718,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -1181,6 +764,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1191,9 +777,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -1343,7 +926,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1370,7 +953,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1445,33 +1028,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -1494,34 +1050,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1548,12 +1077,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1575,34 +1104,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1629,57 +1131,143 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; input VDD ; input VSS ; -input p0 ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1732,55 +1320,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; @@ -1830,58 +1369,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_61 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_104 ( .A ( BUF_net_61 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1979,33 +1467,248 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2034,12 +1737,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -2064,7 +1767,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2094,64 +1797,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -2205,7 +1855,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2311,80 +1961,63 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , - right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , - right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , - right_top_grid_pin_49_ , right_bottom_grid_pin_1_ , chanx_left_in , - left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , - left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , - left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , - ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , - VDD , VSS ) ; +module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , + left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , + left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , + left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; input VDD ; input VSS ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -2399,8 +2032,6 @@ wire [0:1] mux_tree_tapbuf_size3_5_sram ; wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_6_sram ; wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_7_sram ; -wire [0:1] mux_tree_tapbuf_size3_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -2408,18 +2039,23 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; @@ -2434,6 +2070,10 @@ wire [0:2] mux_tree_tapbuf_size7_5_sram ; wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -2441,149 +2081,145 @@ wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; supply1 VDD ; supply0 VSS ; // +assign SC_IN_TOP = SC_IN_BOT ; + mux_tree_tapbuf_size8 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size8_2 mux_right_track_8 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , - right_bottom_grid_pin_1_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , + .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size8_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_3 ( - .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[13] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size8_1 mux_left_track_9 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - chanx_right_in[6] , chanx_right_in[16] , left_top_grid_pin_42_[0] , - left_top_grid_pin_46_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , +mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_4 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size7_6 mux_top_track_2 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size7_5 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_7 mux_top_track_4 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .p0 ( optlc_net_130 ) ) ; mux_tree_tapbuf_size7 mux_top_track_6 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( { ropt_net_169 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_2 mux_right_track_16 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , - chanx_left_in[8] , chanx_left_in[17] } ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_3 mux_right_track_0 ( + .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_3 mux_right_track_24 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , - chanx_left_in[9] , chanx_left_in[18] } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size7_5 mux_right_track_8 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , + chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_0 mux_left_track_17 ( + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_47_[0] } ) , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , + chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_1 mux_left_track_25 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - chanx_right_in[9] , chanx_right_in[18] , left_top_grid_pin_44_[0] , - left_top_grid_pin_48_[0] } ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_1 mux_left_track_3 ( + .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[13] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_2 mux_left_track_9 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_0 mux_left_track_17 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , @@ -2595,44 +2231,56 @@ mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_right_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , +mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , +mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; mux_tree_tapbuf_size4 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , chanx_right_in[8] , + .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4_0 mux_top_track_10 ( - .in ( { top_left_grid_pin_35_[0] , chanx_right_in[9] , + .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -2646,60 +2294,54 @@ mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size3_0 mux_top_track_12 ( - .in ( { top_left_grid_pin_36_[0] , chanx_right_in[10] , + .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_37_[0] , chanx_right_in[12] , + .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_2 mux_top_track_16 ( - .in ( { top_left_grid_pin_38_[0] , chanx_right_in[13] , + .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_3 mux_top_track_18 ( - .in ( { top_left_grid_pin_39_[0] , chanx_right_in[14] , + .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_4 mux_top_track_20 ( - .in ( { top_left_grid_pin_40_[0] , chanx_right_in[16] , + .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( { ropt_net_134 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_5 mux_top_track_22 ( - .in ( { top_left_grid_pin_41_[0] , chanx_right_in[17] , + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3_6 mux_top_track_24 ( - .in ( { top_left_grid_pin_34_[0] , chanx_right_in[18] , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size3 mux_top_track_24 ( + .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3 mux_top_track_38 ( - .in ( { top_left_grid_pin_41_[0] , chanx_right_in[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size3_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_7_sram_inv ) , - .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -2736,385 +2378,317 @@ mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_0 mux_top_track_28 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[19] } ) , +mux_tree_tapbuf_size2 mux_top_track_38 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_1 mux_top_track_30 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_2 mux_top_track_32 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( { ropt_net_130 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_3 mux_top_track_34 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_36 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_36 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9_0 mux_right_track_0 ( - .in ( { chany_top_in[6] , chany_top_in[13] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size9 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size14 mux_right_track_4 ( +mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , - right_bottom_grid_pin_1_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , + chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - chanx_right_in[5] , chanx_right_in[14] , left_top_grid_pin_42_[0] , - left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , - left_top_grid_pin_49_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6 mux_right_track_32 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - right_top_grid_pin_45_[0] , right_top_grid_pin_49_[0] , - chanx_left_in[10] } ) , +mux_tree_tapbuf_size6 mux_right_track_24 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_129 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size6_0 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - chanx_right_in[10] , left_top_grid_pin_45_[0] , - left_top_grid_pin_49_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size6_0 mux_left_track_25 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_131 } ) , +mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - chanx_right_in[2] , chanx_right_in[12] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5 mux_right_track_32 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size5_0 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2271 ( .VNB ( VSS ) , +mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( { ropt_net_139 } ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1273 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2272 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1274 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2273 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1275 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2274 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1276 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2275 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1277 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2276 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1278 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2277 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1279 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2278 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1280 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2279 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1281 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2280 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1282 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2281 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1283 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2282 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1284 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2283 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1285 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2284 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1286 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2285 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1287 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2286 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1288 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2287 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1289 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2288 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1290 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2289 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1291 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2290 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1292 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2291 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1293 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2292 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1294 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2293 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1295 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2294 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1296 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2295 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1297 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2296 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1298 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2297 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1299 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2298 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1300 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2299 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1301 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_35_[0] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[16] ) , +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_129 ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_163 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_156 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_157 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_134 ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_136 ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_158 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_159 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_160 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_161 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_162 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_145 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_146 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_164 ) , .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_147 ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_148 ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_149 ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_150 ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_168 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_169 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_170 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_171 ) , .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_172 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , + .X ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( + .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_173 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_153 ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_176 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_154 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_155 ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_107 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_157 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_114 ( .A ( BUF_net_70 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( @@ -3125,14 +2699,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( @@ -3157,7 +2731,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3165,33 +2739,45 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x837200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3201,68 +2787,76 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y81600 ( @@ -3271,77 +2865,71 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x124200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3351,72 +2939,62 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y190400 ( @@ -3425,77 +3003,105 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1012000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x772800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3505,17 +3111,33 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3525,54 +3147,80 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y353600 ( @@ -3581,51 +3229,81 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3635,36 +3313,82 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y462400 ( @@ -3673,16 +3397,34 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y489600 ( @@ -3691,32 +3433,32 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y516800 ( @@ -3725,74 +3467,122 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x138000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x82800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x772800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y598400 ( @@ -3811,31 +3601,39 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3843,94 +3641,112 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y761600 ( @@ -3947,14 +3763,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v index 01a9af2..f1ce1ea 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v @@ -4,13 +4,13 @@ // // // -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; @@ -18,17 +18,36 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( net_net_105 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; @@ -37,43 +56,55 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; endmodule @@ -91,7 +122,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__58 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -110,7 +141,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -127,10 +158,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -144,10 +172,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -163,7 +190,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -178,59 +204,112 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; +module mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; @@ -238,9 +317,6 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -252,7 +328,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -261,241 +337,30 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; endmodule @@ -511,75 +376,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -604,86 +401,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -696,24 +413,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -730,7 +430,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -747,7 +447,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -764,7 +464,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -781,7 +481,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -798,7 +498,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -815,7 +515,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -844,30 +544,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -903,6 +579,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -911,8 +589,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1026,7 +702,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1045,7 +721,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1106,25 +782,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -1139,26 +796,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1177,12 +815,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1196,26 +834,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1234,48 +853,103 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -1319,46 +993,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; @@ -1399,49 +1033,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_104 ( .A ( BUF_net_61 ) , - .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1521,24 +1113,203 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule @@ -1558,12 +1329,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1579,7 +1350,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1600,55 +1371,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; @@ -1693,7 +1420,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1781,77 +1508,61 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , - right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , - right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , - right_top_grid_pin_49_ , right_bottom_grid_pin_1_ , chanx_left_in , - left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , - left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , - left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , - ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail ) ; +module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , + left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , + left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , + left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , + SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -1866,8 +1577,6 @@ wire [0:1] mux_tree_tapbuf_size3_5_sram ; wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_6_sram ; wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_7_sram ; -wire [0:1] mux_tree_tapbuf_size3_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -1875,18 +1584,23 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; @@ -1901,6 +1615,10 @@ wire [0:2] mux_tree_tapbuf_size7_5_sram ; wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -1908,132 +1626,127 @@ wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; // +assign SC_IN_TOP = SC_IN_BOT ; + mux_tree_tapbuf_size8 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size8_2 mux_right_track_8 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , - right_bottom_grid_pin_1_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size8_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_3 ( - .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[13] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size8_1 mux_left_track_9 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - chanx_right_in[6] , chanx_right_in[16] , left_top_grid_pin_42_[0] , - left_top_grid_pin_46_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_126 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , +mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , +mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_4 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size7_6 mux_top_track_2 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size7_5 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_7 mux_top_track_4 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_124 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_130 ) ) ; mux_tree_tapbuf_size7 mux_top_track_6 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_2 mux_right_track_16 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , - chanx_left_in[8] , chanx_left_in[17] } ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_3 mux_right_track_0 ( + .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_3 mux_right_track_24 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , - chanx_left_in[9] , chanx_left_in[18] } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size7_5 mux_right_track_8 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , + chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_0 mux_left_track_17 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_47_[0] } ) , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , + chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_1 mux_left_track_25 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - chanx_right_in[9] , chanx_right_in[18] , left_top_grid_pin_44_[0] , - left_top_grid_pin_48_[0] } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size7_1 mux_left_track_3 ( + .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[13] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_2 mux_left_track_9 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_0 mux_left_track_17 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , @@ -2043,38 +1756,48 @@ mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_right_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , +mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , +mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , +mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , +mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) ) ; mux_tree_tapbuf_size4 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , chanx_right_in[8] , + .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4_0 mux_top_track_10 ( - .in ( { top_left_grid_pin_35_[0] , chanx_right_in[9] , + .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_127 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -2086,53 +1809,47 @@ mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; mux_tree_tapbuf_size3_0 mux_top_track_12 ( - .in ( { top_left_grid_pin_36_[0] , chanx_right_in[10] , + .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_37_[0] , chanx_right_in[12] , + .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_131 ) ) ; mux_tree_tapbuf_size3_2 mux_top_track_16 ( - .in ( { top_left_grid_pin_38_[0] , chanx_right_in[13] , + .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_3 mux_top_track_18 ( - .in ( { top_left_grid_pin_39_[0] , chanx_right_in[14] , + .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_4 mux_top_track_20 ( - .in ( { top_left_grid_pin_40_[0] , chanx_right_in[16] , + .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( { ropt_net_134 } ) , - .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size3_5 mux_top_track_22 ( - .in ( { top_left_grid_pin_41_[0] , chanx_right_in[17] , + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3_6 mux_top_track_24 ( - .in ( { top_left_grid_pin_34_[0] , chanx_right_in[18] , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size3 mux_top_track_24 ( + .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_124 ) ) ; -mux_tree_tapbuf_size3 mux_top_track_38 ( - .in ( { top_left_grid_pin_41_[0] , chanx_right_in[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size3_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_7_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -2163,291 +1880,231 @@ mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_0 mux_top_track_28 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[19] } ) , +mux_tree_tapbuf_size2 mux_top_track_38 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_1 mux_top_track_30 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[15] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_2 mux_top_track_32 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_3 mux_top_track_34 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[17] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_36 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_36 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size9_0 mux_right_track_0 ( - .in ( { chany_top_in[6] , chany_top_in[13] , right_top_grid_pin_42_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , - right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size9 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; -mux_tree_tapbuf_size14 mux_right_track_4 ( +mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , - right_bottom_grid_pin_1_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size14_0 mux_left_track_5 ( + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , + chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; +mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - chanx_right_in[5] , chanx_right_in[14] , left_top_grid_pin_42_[0] , - left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , - left_top_grid_pin_49_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size6 mux_right_track_32 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - right_top_grid_pin_45_[0] , right_top_grid_pin_49_[0] , - chanx_left_in[10] } ) , + chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) ) ; +mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) ) ; +mux_tree_tapbuf_size6 mux_right_track_24 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_129 } ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size6_0 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - chanx_right_in[10] , left_top_grid_pin_45_[0] , - left_top_grid_pin_49_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size6_0 mux_left_track_25 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( { ropt_net_131 } ) , +mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size10 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - chanx_right_in[2] , chanx_right_in[12] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5 mux_right_track_32 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size5_0 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_128 ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_35_[0] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[16] ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( { ropt_net_139 } ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_129 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_163 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[7] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_156 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_157 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_134 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_136 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_158 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_159 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_160 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_161 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_162 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[14] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_145 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_146 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_164 ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_147 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_148 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_149 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_150 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_168 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_169 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_170 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_171 ) , .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_172 ) , - .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , + .X ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( + .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_153 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_176 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_154 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_155 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_107 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_157 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_114 ( .A ( BUF_net_70 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , + .X ( ropt_net_164 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v index c7d0e13..e14db9d 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v @@ -18,7 +18,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_28__79 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__79 ( .A ( mem_out[2] ) , + .X ( net_net_87 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -326,7 +328,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__73 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2232,6 +2234,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -2244,6 +2247,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -2275,9 +2280,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; endmodule @@ -2348,58 +2354,60 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , - right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , - right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , - right_top_grid_pin_49_ , chany_bottom_in , bottom_left_grid_pin_34_ , - bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , - bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , - bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , - bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , - left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , - left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , - left_top_grid_pin_49_ , ccff_head , chany_top_out , chanx_right_out , +module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , + right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , + bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; @@ -2493,77 +2501,77 @@ wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; // mux_tree_tapbuf_size12_6 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size12 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , - right_top_grid_pin_42_[0] , right_top_grid_pin_44_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_48_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , - right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , - bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , - chany_bottom_in[12] , chany_bottom_in[19] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] } ) , + chany_bottom_in[12] , chany_bottom_in[19] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[4] , chany_bottom_in[13] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[4] , chany_bottom_in[13] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -2605,49 +2613,49 @@ mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; mux_tree_tapbuf_size16 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , - top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , - top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , + top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , - right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , - chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_40_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[5] , chanx_left_in[7] , + chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[5] , chany_bottom_in[14] , left_top_grid_pin_42_[0] , - left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[5] , chany_bottom_in[14] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -2669,101 +2677,101 @@ mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; mux_tree_tapbuf_size10 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_9 mux_top_track_16 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_10 mux_top_track_24 ( - .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , - right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , - right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , - chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_38_[0] , chanx_left_in[6] , chanx_left_in[11] , + chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_39_[0] , chanx_left_in[8] , chanx_left_in[15] , + chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[9] , chanx_left_in[18] , + chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , - chany_bottom_in[6] , chany_bottom_in[16] , left_top_grid_pin_42_[0] , - left_top_grid_pin_46_[0] } ) , + chany_bottom_in[6] , chany_bottom_in[16] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , - chany_bottom_in[8] , chany_bottom_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_47_[0] } ) , + chany_bottom_in[8] , chany_bottom_in[17] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , - chany_bottom_in[11] , chany_bottom_in[18] , left_top_grid_pin_44_[0] , - left_top_grid_pin_48_[0] } ) , + chany_bottom_in[11] , chany_bottom_in[18] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -2825,33 +2833,33 @@ mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; mux_tree_tapbuf_size7 mux_top_track_32 ( - .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size7_2 mux_right_track_32 ( - .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_45_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[10] , - chany_bottom_in[19] , chanx_left_in[10] } ) , + .in ( { chany_top_in[10] , chany_top_in[15] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , - chany_bottom_in[10] , chany_bottom_in[15] , left_top_grid_pin_45_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[10] , chany_bottom_in[15] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -2868,147 +2876,132 @@ mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( { ropt_net_130 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__2 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chany_top_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_top_in[16] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_148 ) , - .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[6] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , .X ( chanx_left_out[13] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_130 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_132 ) , + .X ( ropt_net_133 ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_152 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_153 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_155 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_42__41 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_158 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_41__40 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_159 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_44__43 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_87 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[6] ) , - .X ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_100 ( .A ( chany_top_in[6] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_105 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_106 ( .A ( BUF_net_90 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_115 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_121 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_123 ( .A ( aps_rename_3_ ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_112 ( .A ( aps_rename_1_ ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[6] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v index 9d3ea93..bba0c8d 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v @@ -26,7 +26,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_28__79 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__79 ( .A ( mem_out[2] ) , + .X ( net_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -393,7 +395,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__73 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2593,6 +2595,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -2605,6 +2608,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2642,10 +2648,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2721,58 +2727,60 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , - right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , - right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , - right_top_grid_pin_49_ , chany_bottom_in , bottom_left_grid_pin_34_ , - bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , - bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , - bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , - bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , - left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , - left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , - left_top_grid_pin_49_ , ccff_head , chany_top_out , chanx_right_out , +module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , + right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , + bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; @@ -2870,85 +2878,85 @@ supply0 VSS ; // mux_tree_tapbuf_size12_6 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size12 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , - right_top_grid_pin_42_[0] , right_top_grid_pin_44_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_48_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , - right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , - bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , - chany_bottom_in[12] , chany_bottom_in[19] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] } ) , + chany_bottom_in[12] , chany_bottom_in[19] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[4] , chany_bottom_in[13] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[4] , chany_bottom_in[13] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -2998,53 +3006,53 @@ mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size16 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , - top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , - top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , + top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , - right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , - chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_40_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[5] , chanx_left_in[7] , + chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[5] , chany_bottom_in[14] , left_top_grid_pin_42_[0] , - left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[5] , chany_bottom_in[14] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -3070,113 +3078,113 @@ mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size10 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_9 mux_top_track_16 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_10 mux_top_track_24 ( - .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , - right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , - right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , - chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_38_[0] , chanx_left_in[6] , chanx_left_in[11] , + chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_39_[0] , chanx_left_in[8] , chanx_left_in[15] , + chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[9] , chanx_left_in[18] , + chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , - chany_bottom_in[6] , chany_bottom_in[16] , left_top_grid_pin_42_[0] , - left_top_grid_pin_46_[0] } ) , + chany_bottom_in[6] , chany_bottom_in[16] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , - chany_bottom_in[8] , chany_bottom_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_47_[0] } ) , + chany_bottom_in[8] , chany_bottom_in[17] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , - chany_bottom_in[11] , chany_bottom_in[18] , left_top_grid_pin_44_[0] , - left_top_grid_pin_48_[0] } ) , + chany_bottom_in[11] , chany_bottom_in[18] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -3250,37 +3258,37 @@ mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size7 mux_top_track_32 ( - .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size7_2 mux_right_track_32 ( - .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_45_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[10] , - chany_bottom_in[19] , chanx_left_in[10] } ) , + .in ( { chany_top_in[10] , chany_top_in[15] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , - chany_bottom_in[10] , chany_bottom_in[15] , left_top_grid_pin_45_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[10] , chany_bottom_in[15] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -3300,234 +3308,219 @@ mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( { ropt_net_130 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2301 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1303 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2302 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1304 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2303 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1305 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2304 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1306 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2305 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1307 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2306 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1308 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2307 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1309 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2308 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1310 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2309 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1311 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2310 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1312 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2311 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1313 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2312 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1314 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2313 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1315 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2314 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1316 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2315 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1317 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2316 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1318 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2317 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1319 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2318 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1320 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2319 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1321 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2320 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1322 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2321 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1323 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2322 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1324 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2323 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1325 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2324 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1326 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2325 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1327 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2326 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1328 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2327 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1329 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2328 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1330 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2329 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1331 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2330 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1332 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2331 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1333 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2332 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1334 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__2 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chany_top_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_top_in[16] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_148 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[6] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_130 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_132 ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_152 ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_153 ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_155 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_42__41 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_158 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_41__40 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_159 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_44__43 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_87 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[6] ) , - .X ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_100 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_105 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_106 ( .A ( BUF_net_90 ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_115 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_121 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_123 ( .A ( aps_rename_3_ ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_112 ( .A ( aps_rename_1_ ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( @@ -3554,11 +3547,15 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3568,8 +3565,8 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( @@ -3578,19 +3575,21 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3600,11 +3599,11 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3620,65 +3619,55 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x82800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x78200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x901600y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3688,83 +3677,73 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x878600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3774,43 +3753,71 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3820,16 +3827,22 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y408000 ( @@ -3838,37 +3851,47 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3878,50 +3901,42 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y516800 ( @@ -3930,29 +3945,29 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3962,11 +3977,13 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3976,14 +3993,14 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y625600 ( @@ -3992,67 +4009,67 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x864800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x59800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x69000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4062,11 +4079,21 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4088,30 +4115,24 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y788800 ( @@ -4122,52 +4143,64 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y924800 ( @@ -4184,14 +4217,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y952000 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v index 159b596..bee694a 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v @@ -18,7 +18,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_28__79 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__79 ( .A ( mem_out[2] ) , + .X ( net_net_87 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -298,7 +300,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__73 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2045,6 +2047,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -2055,6 +2058,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -2086,9 +2091,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; endmodule @@ -2152,58 +2158,60 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , - right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , - right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , - right_top_grid_pin_49_ , chany_bottom_in , bottom_left_grid_pin_34_ , - bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , - bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , - bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , - bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , - left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , - left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , - left_top_grid_pin_49_ , ccff_head , chany_top_out , chanx_right_out , +module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , + right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , + bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_42_ ; -input [0:0] right_top_grid_pin_43_ ; -input [0:0] right_top_grid_pin_44_ ; -input [0:0] right_top_grid_pin_45_ ; -input [0:0] right_top_grid_pin_46_ ; -input [0:0] right_top_grid_pin_47_ ; -input [0:0] right_top_grid_pin_48_ ; -input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_right_out ; @@ -2297,77 +2305,77 @@ wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; // mux_tree_tapbuf_size12_6 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size12 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , - right_top_grid_pin_42_[0] , right_top_grid_pin_44_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_48_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , - right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , - bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , - chany_bottom_in[12] , chany_bottom_in[19] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] } ) , + chany_bottom_in[12] , chany_bottom_in[19] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[4] , chany_bottom_in[13] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[4] , chany_bottom_in[13] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -2409,49 +2417,49 @@ mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; mux_tree_tapbuf_size16 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , - top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , - top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , + top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , - right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , - right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , - right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , - right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , - chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_40_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[5] , chanx_left_in[7] , + chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[5] , chany_bottom_in[14] , left_top_grid_pin_42_[0] , - left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[5] , chany_bottom_in[14] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , @@ -2473,101 +2481,101 @@ mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; mux_tree_tapbuf_size10 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_9 mux_top_track_16 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_10 mux_top_track_24 ( - .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , - right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , - right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , - chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_38_[0] , chanx_left_in[6] , chanx_left_in[11] , + chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_39_[0] , chanx_left_in[8] , chanx_left_in[15] , + chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[9] , chanx_left_in[18] , + chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , - chany_bottom_in[6] , chany_bottom_in[16] , left_top_grid_pin_42_[0] , - left_top_grid_pin_46_[0] } ) , + chany_bottom_in[6] , chany_bottom_in[16] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , - chany_bottom_in[8] , chany_bottom_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_47_[0] } ) , + chany_bottom_in[8] , chany_bottom_in[17] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , - chany_bottom_in[11] , chany_bottom_in[18] , left_top_grid_pin_44_[0] , - left_top_grid_pin_48_[0] } ) , + chany_bottom_in[11] , chany_bottom_in[18] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -2629,33 +2637,33 @@ mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; mux_tree_tapbuf_size7 mux_top_track_32 ( - .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size7_2 mux_right_track_32 ( - .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_45_[0] , - right_top_grid_pin_49_[0] , chany_bottom_in[10] , - chany_bottom_in[19] , chanx_left_in[10] } ) , + .in ( { chany_top_in[10] , chany_top_in[15] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_125 ) ) ; mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , - chany_bottom_in[10] , chany_bottom_in[15] , left_top_grid_pin_45_[0] , - left_top_grid_pin_49_[0] } ) , + chany_bottom_in[10] , chany_bottom_in[15] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -2672,147 +2680,132 @@ mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( { ropt_net_130 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__2 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chany_top_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_top_in[16] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_148 ) , - .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[6] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , .X ( chanx_left_out[13] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_130 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_132 ) , + .X ( ropt_net_133 ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_152 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_153 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_155 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_42__41 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_158 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_41__40 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_159 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_44__43 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_87 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[6] ) , - .X ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_100 ( .A ( chany_top_in[6] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_105 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_106 ( .A ( BUF_net_90 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_115 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_121 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_123 ( .A ( aps_rename_3_ ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_112 ( .A ( aps_rename_1_ ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[6] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v index 0677bd9..ea3ca3a 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v @@ -4,6 +4,70 @@ // // // +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( net_net_89 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -16,114 +80,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1 ( const1 ) ; +module const1_26 ( const1 ) ; output [0:0] const1 ; endmodule @@ -138,7 +100,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1 const1_0_ ( +const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -150,187 +112,294 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_32 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_32 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_31 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_31 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_30 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_30 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_29 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_29 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_28 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +output [0:1] mem_out ; +output [0:1] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__52 ( .A ( mem_out[2] ) , - .X ( net_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_95 ( .A ( net_net_95 ) , - .X ( net_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_130 ( .A ( net_net_94 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -345,7 +414,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -364,12 +433,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -383,47 +452,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module const1_25 ( const1 ) ; +module const1_19 ( const1 ) ; output [0:0] const1 ; endmodule @@ -440,7 +474,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_25 const1_0_ ( +const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -458,7 +492,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_24 ( const1 ) ; +module const1_18 ( const1 ) ; output [0:0] const1 ; endmodule @@ -475,42 +509,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -const1_23 const1_0_ ( +const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -528,7 +527,42 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , +module const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -542,7 +576,103 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -561,7 +691,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -580,7 +710,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -599,17 +729,55 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_22 ( const1 ) ; +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -624,7 +792,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_22 const1_0_ ( +const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -646,14 +814,106 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_136 ( .A ( BUF_net_69 ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_21 ( const1 ) ; +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; output [0:0] const1 ; endmodule @@ -673,7 +933,54 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_21 const1_0_ ( +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -695,57 +1002,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_68 ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_19 ( const1 ) ; +module const1_10 ( const1 ) ; output [0:0] const1 ; endmodule @@ -765,8 +1027,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_19 const1_0_ ( +const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -787,555 +1051,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__44 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__43 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__42 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__41 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__32 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__31 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; endmodule @@ -1344,8 +1059,8 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -1356,25 +1071,33 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule @@ -1383,8 +1106,8 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; +module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -1395,25 +1118,75 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -1422,10 +1195,10 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -1434,25 +1207,37 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -1461,10 +1246,10 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -1473,25 +1258,79 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -1500,10 +1339,223 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -1512,8 +1564,66 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -const1_5 const1_0_ ( +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1523,234 +1633,23 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__30 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__29 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__28 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__27 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__26 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -1759,49 +1658,10 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -1811,11 +1671,91 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1826,64 +1766,96 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; endmodule module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - chany_bottom_in , bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , - bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , - bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , - bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , - left_top_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , - chanx_left_out , ccff_tail ) ; + right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -1896,62 +1868,26 @@ wire [0:1] mux_tree_tapbuf_size3_4_sram ; wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_5_sram ; -wire [0:2] mux_tree_tapbuf_size5_5_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_6_sram ; -wire [0:2] mux_tree_tapbuf_size5_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; @@ -1960,301 +1896,279 @@ wire [0:2] mux_tree_tapbuf_size7_2_sram ; wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; // -mux_tree_tapbuf_size6_2 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[5] , +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_3 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[3] , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size9 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size9_0 mux_left_track_1 ( + .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , + chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size9_1 mux_left_track_3 ( + .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[7] , chany_bottom_in[14] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; +mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; +mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) ) ; +mux_tree_tapbuf_size14 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[2] , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; +mux_tree_tapbuf_size8 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_0 mux_left_track_5 ( - .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size6_1 mux_left_track_9 ( + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_3 mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; -mux_tree_tapbuf_size5_5 mux_right_track_2 ( - .in ( { chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_172 } ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size5_4 mux_right_track_16 ( - .in ( { chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , + chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size8_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_6 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , + chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size5 mux_right_track_24 ( - .in ( { chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size5_0 mux_left_track_1 ( - .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , - chany_bottom_in[13] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size5_3 mux_left_track_3 ( - .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[7] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size5_1 mux_left_track_17 ( - .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_5_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size5_2 mux_left_track_25 ( - .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , - chany_bottom_in[11] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_6_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size5_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_5_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_6_sram_inv ) ) ; -mux_tree_tapbuf_size3 mux_right_track_32 ( - .in ( { chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( - .in ( { chanx_right_in[10] , bottom_left_grid_pin_36_[0] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( - .in ( { chanx_right_in[12] , bottom_left_grid_pin_37_[0] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( - .in ( { chanx_right_in[13] , bottom_left_grid_pin_38_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_39_[0] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_40_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_5 mux_bottom_track_23 ( - .in ( { chanx_right_in[17] , bottom_left_grid_pin_41_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_5 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[2] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( { ropt_net_175 } ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( - .in ( { chanx_right_in[4] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , + chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[5] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( + .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( { ropt_net_207 } ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7 mux_bottom_track_7 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_175 } ) , + .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_4 mux_left_track_17 ( + .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_5 mux_left_track_25 ( + .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , + chany_bottom_in[11] , chany_bottom_in[18] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( { ropt_net_165 } ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , +mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size4_2 mux_bottom_track_9 ( - .in ( { chanx_right_in[8] , bottom_left_grid_pin_34_[0] , +mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; +mux_tree_tapbuf_size5 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size4 mux_bottom_track_9 ( + .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_164 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ; mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( - .in ( { chanx_right_in[9] , bottom_left_grid_pin_35_[0] , + .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_176 } ) , - .p0 ( optlc_net_164 ) ) ; + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_158 ) ) ; mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , - bottom_left_grid_pin_34_[0] , chanx_left_in[18] } ) , + bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size4 mux_left_track_33 ( - .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , - chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; @@ -2264,219 +2178,261 @@ mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_27 ( - .in ( { chanx_right_in[15] , bottom_left_grid_pin_35_[0] } ) , +mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( + .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( + .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size3 mux_bottom_track_23 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( { ropt_net_176 } ) , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; +mux_tree_tapbuf_size2 mux_bottom_track_27 ( + .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_29 ( - .in ( { chanx_right_in[11] , bottom_left_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_31 ( - .in ( { chanx_right_in[7] , bottom_left_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_33 ( - .in ( { chanx_right_in[3] , bottom_left_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_4 mux_bottom_track_35 ( - .in ( { chanx_right_in[1] , bottom_left_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_5 mux_bottom_track_37 ( - .in ( { chanx_right_in[0] , bottom_left_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size2 mux_bottom_track_39 ( - .in ( { bottom_left_grid_pin_41_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_162 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_164 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_169 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_172 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_left_in[5] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_173 ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_175 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_176 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_197 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_198 ) , +mux_tree_tapbuf_size6 mux_left_track_33 ( + .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , + chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_181 } ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_199 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( chanx_left_in[4] ) , - .X ( BUF_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_185 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_187 ) , +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_165 ) , .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , - .X ( BUF_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_188 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[10] ) , .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_190 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_191 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_192 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_204 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( BUF_net_83 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_115 ( .A ( aps_rename_2_ ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_116 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_205 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_206 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_166 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[12] ) , .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_92 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_170 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_172 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_175 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_176 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_200 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[14] ) , + .X ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[17] ) , + .X ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[9] ) , + .X ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_181 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_182 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_183 ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_184 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_186 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_187 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_188 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_189 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_190 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_205 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_206 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_207 ) , .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_208 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_212 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( BUF_net_77 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_79 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_184 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v index 6746dfc..e22ee70 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v @@ -4,6 +4,79 @@ // // // +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( net_net_89 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -23,151 +96,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -198,715 +127,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__52 ( .A ( mem_out[2] ) , - .X ( net_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_95 ( .A ( net_net_95 ) , - .X ( net_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_130 ( .A ( net_net_94 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_69 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_136 ( .A ( BUF_net_69 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_68 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_68 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -925,7 +146,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -949,7 +170,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -973,7 +194,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__42 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -997,7 +218,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__41 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1021,7 +242,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1045,36 +266,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__39 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1089,9 +286,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1102,6 +296,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -1260,10 +457,91 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -1272,130 +550,96 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1421,225 +665,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__33 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__32 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__31 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; @@ -1680,8 +710,224 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -1694,11 +940,884 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , @@ -1710,20 +1829,34 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -1734,6 +1867,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; @@ -1747,158 +1883,34 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__30 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__29 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__28 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__27 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__26 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -1910,11 +1922,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , @@ -1922,27 +1937,68 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; @@ -1954,11 +2010,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , @@ -1973,190 +2033,100 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - chany_bottom_in , bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , - bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , - bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , - bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , - left_top_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , - chanx_left_out , ccff_tail , VDD , VSS ) ; + right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; input VDD ; input VSS ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -2169,62 +2139,26 @@ wire [0:1] mux_tree_tapbuf_size3_4_sram ; wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_5_sram ; -wire [0:2] mux_tree_tapbuf_size5_5_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_6_sram ; -wire [0:2] mux_tree_tapbuf_size5_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; @@ -2233,349 +2167,316 @@ wire [0:2] mux_tree_tapbuf_size7_2_sram ; wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size6_2 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[5] , +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_3 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[3] , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size9 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size9_0 mux_left_track_1 ( + .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , + chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size9_1 mux_left_track_3 ( + .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[7] , chany_bottom_in[14] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size14 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[2] , + .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_0 mux_left_track_5 ( - .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size6_1 mux_left_track_9 ( + .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size8_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_3 mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_5 mux_right_track_2 ( - .in ( { chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_172 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size5_4 mux_right_track_16 ( - .in ( { chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , +mux_tree_tapbuf_size7_6 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , + chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size5 mux_right_track_24 ( - .in ( { chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size5_0 mux_left_track_1 ( - .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , - chany_bottom_in[13] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size5_3 mux_left_track_3 ( - .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[7] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size5_1 mux_left_track_17 ( - .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_5_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size5_2 mux_left_track_25 ( - .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , - chany_bottom_in[11] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_6_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size5_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3 mux_right_track_32 ( - .in ( { chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( - .in ( { chanx_right_in[10] , bottom_left_grid_pin_36_[0] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( - .in ( { chanx_right_in[12] , bottom_left_grid_pin_37_[0] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( - .in ( { chanx_right_in[13] , bottom_left_grid_pin_38_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_39_[0] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_40_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_5 mux_bottom_track_23 ( - .in ( { chanx_right_in[17] , bottom_left_grid_pin_41_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_5 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[2] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( { ropt_net_175 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( - .in ( { chanx_right_in[4] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , + chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[5] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( + .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( { ropt_net_207 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7 mux_bottom_track_7 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_175 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_4 mux_left_track_17 ( + .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_5 mux_left_track_25 ( + .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , + chany_bottom_in[11] , chany_bottom_in[18] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( { ropt_net_165 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , +mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_2 mux_bottom_track_9 ( - .in ( { chanx_right_in[8] , bottom_left_grid_pin_34_[0] , +mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4 mux_bottom_track_9 ( + .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; + .p0 ( optlc_net_158 ) ) ; mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( - .in ( { chanx_right_in[9] , bottom_left_grid_pin_35_[0] , + .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_176 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_164 ) ) ; + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , - bottom_left_grid_pin_34_[0] , chanx_left_in[18] } ) , + bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size4 mux_left_track_33 ( - .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , - chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , @@ -2587,292 +2488,335 @@ mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( + .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( + .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size3 mux_bottom_track_23 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( { ropt_net_176 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_27 ( - .in ( { chanx_right_in[15] , bottom_left_grid_pin_35_[0] } ) , +mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2 mux_bottom_track_27 ( + .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_169 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_29 ( - .in ( { chanx_right_in[11] , bottom_left_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_31 ( - .in ( { chanx_right_in[7] , bottom_left_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_33 ( - .in ( { chanx_right_in[3] , bottom_left_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_4 mux_bottom_track_35 ( - .in ( { chanx_right_in[1] , bottom_left_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_5 mux_bottom_track_37 ( - .in ( { chanx_right_in[0] , bottom_left_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size2 mux_bottom_track_39 ( - .in ( { bottom_left_grid_pin_41_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size6 mux_left_track_33 ( + .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , + chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_181 } ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2334 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1336 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2335 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1337 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2336 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1338 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2337 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1339 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2338 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1340 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2339 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1341 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2340 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1342 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2341 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1343 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2342 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1344 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2343 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1345 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2344 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1346 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2345 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1347 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2346 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1348 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2347 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1349 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2348 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1350 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2349 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1351 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2350 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1352 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2351 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1353 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2352 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1354 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2353 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1355 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2354 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1356 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2355 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1357 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2356 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1358 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2357 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1359 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2358 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1360 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2359 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1361 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2360 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1362 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2361 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1363 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2362 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1364 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_169 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_172 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_left_in[5] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_173 ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_175 ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_176 ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_197 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_198 ) , +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_199 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( chanx_left_in[4] ) , - .X ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_185 ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_187 ) , +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_165 ) , .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , - .X ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_188 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[10] ) , .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_190 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_191 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_192 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_204 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( BUF_net_83 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_115 ( .A ( aps_rename_2_ ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_116 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_205 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_206 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_166 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[12] ) , .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_92 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_170 ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_172 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_175 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_176 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_200 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[14] ) , + .X ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[17] ) , + .X ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[9] ) , + .X ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_181 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_182 ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_183 ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_184 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_186 ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_187 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_188 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_189 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_190 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_205 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_206 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_207 ) , .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_208 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_212 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( BUF_net_77 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_79 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( @@ -2885,14 +2829,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( @@ -2917,104 +2861,58 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y108800 ( @@ -3023,34 +2921,30 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( @@ -3065,27 +2959,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3093,11 +2981,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3109,29 +2997,37 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x55200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3141,74 +3037,66 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y244800 ( @@ -3217,31 +3105,25 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x818800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3251,29 +3133,27 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x864800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3283,62 +3163,70 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x133400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y353600 ( @@ -3347,63 +3235,65 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x864800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3413,129 +3303,135 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x809600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3545,35 +3441,23 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3583,100 +3467,124 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x96600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y625600 ( @@ -3685,15 +3593,39 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3703,33 +3635,29 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3739,116 +3667,80 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x809600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x87400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( @@ -3871,14 +3763,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( @@ -3903,7 +3795,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v index d2d6ddd..1f771c2 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v @@ -4,6 +4,63 @@ // // // +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( net_net_89 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -16,109 +73,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -143,551 +98,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__52 ( .A ( mem_out[2] ) , - .X ( net_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_95 ( .A ( net_net_95 ) , - .X ( net_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_130 ( .A ( net_net_94 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_136 ( .A ( BUF_net_69 ) , - .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_68 ) , - .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -699,7 +110,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -716,7 +127,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -733,7 +144,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__42 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -750,7 +161,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__41 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -767,7 +178,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -784,29 +195,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__39 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -817,8 +211,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -827,6 +219,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -950,103 +344,144 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule @@ -1064,177 +499,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__33 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__32 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__31 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; @@ -1267,8 +536,160 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; output [0:0] out ; @@ -1279,9 +700,704 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1290,19 +1406,31 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -1311,6 +1439,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1320,116 +1451,30 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__30 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__29 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__28 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__27 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__26 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -1439,33 +1484,66 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; output [0:0] out ; input p0 ; @@ -1475,9 +1553,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1488,164 +1570,96 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; endmodule module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - chany_bottom_in , bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , - bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , - bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , - bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , - left_top_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , - chanx_left_out , ccff_tail ) ; + right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , + bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , + SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_34_ ; +input [0:0] right_bottom_grid_pin_35_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -1658,62 +1672,26 @@ wire [0:1] mux_tree_tapbuf_size3_4_sram ; wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_5_sram ; -wire [0:2] mux_tree_tapbuf_size5_5_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_6_sram ; -wire [0:2] mux_tree_tapbuf_size5_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; @@ -1722,301 +1700,279 @@ wire [0:2] mux_tree_tapbuf_size7_2_sram ; wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; // -mux_tree_tapbuf_size6_2 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[5] , +assign SC_IN_TOP = SC_IN_BOT ; + +mux_tree_tapbuf_size10 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_3 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[3] , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size9 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size9_0 mux_left_track_1 ( + .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , + chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size9_1 mux_left_track_3 ( + .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[7] , chany_bottom_in[14] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; +mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; +mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) ) ; +mux_tree_tapbuf_size14 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , + right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[2] , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; +mux_tree_tapbuf_size8 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size6_0 mux_left_track_5 ( - .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size6_1 mux_left_track_9 ( + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_3 mem_right_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; -mux_tree_tapbuf_size5_5 mux_right_track_2 ( - .in ( { chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_172 } ) , - .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size5_4 mux_right_track_16 ( - .in ( { chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , + chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size8_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_6 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , + chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size5 mux_right_track_24 ( - .in ( { chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size5_0 mux_left_track_1 ( - .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , - chany_bottom_in[13] , left_top_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size5_3 mux_left_track_3 ( - .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[7] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size5_1 mux_left_track_17 ( - .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_5_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size5_2 mux_left_track_25 ( - .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , - chany_bottom_in[11] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_6_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size5_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_5_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_6_sram_inv ) ) ; -mux_tree_tapbuf_size3 mux_right_track_32 ( - .in ( { chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( - .in ( { chanx_right_in[10] , bottom_left_grid_pin_36_[0] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( - .in ( { chanx_right_in[12] , bottom_left_grid_pin_37_[0] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( - .in ( { chanx_right_in[13] , bottom_left_grid_pin_38_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_39_[0] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_40_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_5 mux_bottom_track_23 ( - .in ( { chanx_right_in[17] , bottom_left_grid_pin_41_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_5 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[2] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( { ropt_net_175 } ) , - .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( - .in ( { chanx_right_in[4] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , + chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[5] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( + .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( { ropt_net_207 } ) , - .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7 mux_bottom_track_7 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_175 } ) , + .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_158 ) ) ; +mux_tree_tapbuf_size7_4 mux_left_track_17 ( + .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size7_5 mux_left_track_25 ( + .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , + chany_bottom_in[11] , chany_bottom_in[18] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( { ropt_net_165 } ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , +mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size4_2 mux_bottom_track_9 ( - .in ( { chanx_right_in[8] , bottom_left_grid_pin_34_[0] , +mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; +mux_tree_tapbuf_size5 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , + chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size4 mux_bottom_track_9 ( + .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_164 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ; mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( - .in ( { chanx_right_in[9] , bottom_left_grid_pin_35_[0] , + .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_176 } ) , - .p0 ( optlc_net_164 ) ) ; + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_158 ) ) ; mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , - bottom_left_grid_pin_34_[0] , chanx_left_in[18] } ) , + bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size4 mux_left_track_33 ( - .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , - chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_164 ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; @@ -2026,219 +1982,261 @@ mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_27 ( - .in ( { chanx_right_in[15] , bottom_left_grid_pin_35_[0] } ) , +mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( + .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( + .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size3 mux_bottom_track_23 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( { ropt_net_176 } ) , + .p0 ( optlc_net_160 ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; +mux_tree_tapbuf_size2 mux_bottom_track_27 ( + .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_29 ( - .in ( { chanx_right_in[11] , bottom_left_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_165 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_31 ( - .in ( { chanx_right_in[7] , bottom_left_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_33 ( - .in ( { chanx_right_in[3] , bottom_left_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_4 mux_bottom_track_35 ( - .in ( { chanx_right_in[1] , bottom_left_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_163 ) ) ; -mux_tree_tapbuf_size2_5 mux_bottom_track_37 ( - .in ( { chanx_right_in[0] , bottom_left_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size2 mux_bottom_track_39 ( - .in ( { bottom_left_grid_pin_41_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_162 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_157 ) ) ; +mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_162 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_164 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_169 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_172 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_left_in[5] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_173 ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_175 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_176 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_197 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_198 ) , +mux_tree_tapbuf_size6 mux_left_track_33 ( + .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , + chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_159 ) ) ; +mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_181 } ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_199 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( chanx_left_in[4] ) , - .X ( BUF_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_185 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_187 ) , +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_165 ) , .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , - .X ( BUF_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_188 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[10] ) , .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_190 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_191 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_192 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_204 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( BUF_net_83 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_115 ( .A ( aps_rename_2_ ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_116 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_205 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_206 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_166 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[12] ) , .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_92 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_170 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_172 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_175 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_176 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_200 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[14] ) , + .X ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[17] ) , + .X ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[9] ) , + .X ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_181 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_182 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_183 ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_184 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_186 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_187 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_188 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_189 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_190 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_205 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_206 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_207 ) , .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_208 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_212 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( BUF_net_77 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_79 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_184 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v index e9e9315..aac13eb 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v @@ -4,330 +4,219 @@ // // // -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , - .X ( net_net_49 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_49 ( .A ( net_net_49 ) , - .X ( net_net_48 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( net_net_48 ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; +module const1 ( const1 ) ; +output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; +module const1_28 ( const1 ) ; +output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; +module const1_27 ( const1 ) ; +output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; +module const1_26 ( const1 ) ; +output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; +const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule @@ -343,7 +232,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__35 ( .A ( mem_out[1] ) , + .X ( net_net_71 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( net_net_71 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -360,7 +251,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -377,224 +268,297 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1 ( const1 ) ; -output [0:0] const1 ; +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module const1_32 ( const1 ) ; -output [0:0] const1 ; +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_32 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module const1_31 ( const1 ) ; -output [0:0] const1 ; +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_31 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module const1_30 ( const1 ) ; -output [0:0] const1 ; +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_30 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module const1_29 ( const1 ) ; -output [0:0] const1 ; +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_29 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module const1_28 ( const1 ) ; -output [0:0] const1 ; +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module const1_27 ( const1 ) ; -output [0:0] const1 ; +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module const1_26 ( const1 ) ; -output [0:0] const1 ; +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule -const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -603,7 +567,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -630,7 +594,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -657,7 +621,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -684,7 +648,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -692,17 +656,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -711,7 +671,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -723,13 +683,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -738,7 +698,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -765,7 +725,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -792,7 +752,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -819,7 +779,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -846,7 +806,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -873,7 +833,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -900,7 +860,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -927,7 +887,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -954,7 +914,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -976,6 +936,168 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -988,41 +1110,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1039,12 +1127,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_11 ( const1 ) ; +module const1_5 ( const1 ) ; output [0:0] const1 ; endmodule @@ -1060,7 +1148,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_11 const1_0_ ( +const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -1075,69 +1163,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module const1_8 ( const1 ) ; +module const1_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -1153,8 +1179,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_8 const1_0_ ( +const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -1163,14 +1191,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_65 ( .A ( BUF_net_41 ) , - .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1184,7 +1208,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1203,128 +1227,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module const1_5 ( const1 ) ; +module const1_3 ( const1 ) ; output [0:0] const1 ; endmodule @@ -1342,7 +1250,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_5 const1_0_ ( +const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1363,12 +1271,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1381,7 +1289,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_4 const1_0_ ( +const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1402,7 +1310,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1416,7 +1324,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1435,135 +1343,11 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - module const1_1 ( const1 ) ; output [0:0] const1 ; endmodule @@ -1612,7 +1396,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1624,6 +1408,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; @@ -1640,41 +1425,41 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule -module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , top_right_grid_pin_1_ , chanx_left_in , - left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , - left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , - left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , - ccff_head , chany_top_out , chanx_left_out , ccff_tail ) ; +module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , + chany_top_out , chanx_left_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:0] top_right_grid_pin_1_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_left_out ; @@ -1704,10 +1489,6 @@ wire [0:1] mux_tree_tapbuf_size2_19_sram ; wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; @@ -1734,9 +1515,7 @@ wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; @@ -1749,69 +1528,50 @@ wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; // -mux_tree_tapbuf_size6_2 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , +mux_tree_tapbuf_size6_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_109 } ) , + .p0 ( optlc_net_100 ) ) ; mux_tree_tapbuf_size6 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size6_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size6_1 mux_left_track_5 ( - .in ( { chany_top_in[18] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , @@ -1821,45 +1581,21 @@ mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_2 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size5_0 mux_top_track_2 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_80 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; mux_tree_tapbuf_size5 mux_top_track_6 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size5_0 mux_left_track_3 ( - .in ( { chany_top_in[19] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_1 mux_left_track_7 ( - .in ( { chany_top_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , @@ -1869,321 +1605,342 @@ mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; mux_tree_tapbuf_size3 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( { ropt_net_89 } ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size3_2 mux_top_track_24 ( - .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size3_0 mux_top_track_24 ( + .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size3_1 mux_left_track_9 ( - .in ( { chany_top_in[16] , left_top_grid_pin_42_[0] , - left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_0 mux_left_track_25 ( - .in ( { chany_top_in[8] , left_top_grid_pin_42_[0] , - left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_81 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_100 ) ) ; mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_8 mux_top_track_10 ( - .in ( { top_left_grid_pin_35_[0] , chanx_left_in[15] } ) , +mux_tree_tapbuf_size2_12 mux_top_track_10 ( + .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size2_9 mux_top_track_12 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[14] } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size2_10 mux_top_track_14 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[13] } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_11 mux_top_track_16 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[12] } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_15 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_12 mux_top_track_18 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_16 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_20 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[10] } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_17 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_22 ( - .in ( { top_left_grid_pin_41_[0] , chanx_left_in[9] } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_18 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_15 mux_top_track_26 ( - .in ( { top_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_26 ( + .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_16 mux_top_track_28 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[6] } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_11 mux_left_track_9 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_17 mux_top_track_30 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[5] } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_0 mux_left_track_11 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chany_top_out[15] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_32 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[4] } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_1 mux_left_track_13 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_19 mux_top_track_34 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[3] } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_2 mux_left_track_15 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chany_top_out[17] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_20 mux_top_track_36 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[2] } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_3 mux_left_track_17 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_38 ( - .in ( { top_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_4 mux_left_track_19 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_0 mux_left_track_11 ( - .in ( { chany_top_in[15] , left_top_grid_pin_43_[0] } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_5 mux_left_track_25 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_1 mux_left_track_13 ( - .in ( { chany_top_in[14] , left_top_grid_pin_44_[0] } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_6 mux_left_track_27 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_2 mux_left_track_15 ( - .in ( { chany_top_in[13] , left_top_grid_pin_45_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( { ropt_net_108 } ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_7 mux_left_track_29 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_3 mux_left_track_17 ( - .in ( { chany_top_in[12] , left_top_grid_pin_46_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( { ropt_net_103 } ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_8 mux_left_track_31 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_4 mux_left_track_19 ( - .in ( { chany_top_in[11] , left_top_grid_pin_47_[0] } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_9 mux_left_track_33 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_5 mux_left_track_21 ( - .in ( { chany_top_in[10] , left_top_grid_pin_48_[0] } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size2_10 mux_left_track_35 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_6 mux_left_track_23 ( - .in ( { chany_top_in[9] , left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_7 mux_left_track_27 ( - .in ( { chany_top_in[7] , left_top_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_top_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_top_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_top_track_16 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_18 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_20 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_top_track_26 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_top_track_28 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , +mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_top_track_30 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_32 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_top_track_34 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_top_track_36 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , +mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_left_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , +mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( { ropt_net_105 } ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_left_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_left_track_27 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( { ropt_net_88 } ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_676 ( .A ( ropt_net_91 ) , +mux_tree_tapbuf_size4_0 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_1 mux_left_track_3 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_2 mux_left_track_5 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size4 mux_left_track_7 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_118 ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_79 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_678 ( .A ( ropt_net_93 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_679 ( .A ( ropt_net_94 ) , +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_119 ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_95 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_93 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_84 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_63 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_85 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_85 ) , +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_103 ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_left_in[4] ) , + .X ( BUF_net_56 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_left_in[5] ) , + .X ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_66 ( .A ( BUF_net_56 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_84 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( BUF_net_57 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_86 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_67 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_672 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_88 ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_89 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_90 ) , - .X ( ropt_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_123 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_125 ) , + .X ( chanx_left_out[10] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v index 253e419..b049ff9 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v @@ -4,13 +4,13 @@ // // // -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; input VDD ; input VSS ; @@ -23,22 +23,21 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , - .X ( net_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_49 ( .A ( net_net_49 ) , - .X ( net_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( net_net_48 ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; input VDD ; input VSS ; @@ -51,18 +50,21 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; input VDD ; input VSS ; @@ -75,18 +77,21 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; input VDD ; input VSS ; @@ -99,368 +104,151 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -483,7 +271,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__35 ( .A ( mem_out[1] ) , + .X ( net_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( net_net_71 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -507,7 +297,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -531,12 +321,421 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -562,6 +761,80 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -576,15 +849,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -744,6 +1017,33 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -770,60 +1070,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -1013,112 +1259,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -1138,55 +1278,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1210,7 +1302,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1246,68 +1338,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -1323,6 +1353,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1333,15 +1366,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_65 ( .A ( BUF_net_41 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1363,7 +1391,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1390,66 +1418,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1529,87 +1503,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1631,7 +1525,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1658,66 +1552,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1779,9 +1619,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1802,122 +1639,38 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , top_right_grid_pin_1_ , chanx_left_in , - left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , - left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , - left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , - ccff_head , chany_top_out , chanx_left_out , ccff_tail , VDD , VSS ) ; +module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , + chany_top_out , chanx_left_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:0] top_right_grid_pin_1_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_left_out ; @@ -1949,10 +1702,6 @@ wire [0:1] mux_tree_tapbuf_size2_19_sram ; wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; @@ -1979,9 +1728,7 @@ wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; @@ -1994,75 +1741,53 @@ wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size6_2 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , +mux_tree_tapbuf_size6_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_109 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_100 ) ) ; mux_tree_tapbuf_size6 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size6_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size6_1 mux_left_track_5 ( - .in ( { chany_top_in[18] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , @@ -2074,51 +1799,23 @@ mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_2 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size5_0 mux_top_track_2 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; + .p0 ( optlc_net_100 ) ) ; mux_tree_tapbuf_size5 mux_top_track_6 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size5_0 mux_left_track_3 ( - .in ( { chany_top_in[19] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_1 mux_left_track_7 ( - .in ( { chany_top_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , @@ -2130,406 +1827,424 @@ mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; mux_tree_tapbuf_size3 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( { ropt_net_89 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size3_2 mux_top_track_24 ( - .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size3_0 mux_top_track_24 ( + .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size3_1 mux_left_track_9 ( - .in ( { chany_top_in[16] , left_top_grid_pin_42_[0] , - left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_0 mux_left_track_25 ( - .in ( { chany_top_in[8] , left_top_grid_pin_42_[0] , - left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; + .p0 ( optlc_net_100 ) ) ; mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_8 mux_top_track_10 ( - .in ( { top_left_grid_pin_35_[0] , chanx_left_in[15] } ) , +mux_tree_tapbuf_size2_12 mux_top_track_10 ( + .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size2_9 mux_top_track_12 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[14] } ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size2_10 mux_top_track_14 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[13] } ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_11 mux_top_track_16 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[12] } ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_15 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_12 mux_top_track_18 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_16 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_20 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[10] } ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_17 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_22 ( - .in ( { top_left_grid_pin_41_[0] , chanx_left_in[9] } ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_18 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_15 mux_top_track_26 ( - .in ( { top_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_26 ( + .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_16 mux_top_track_28 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[6] } ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_11 mux_left_track_9 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_17 mux_top_track_30 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[5] } ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_0 mux_left_track_11 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_32 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[4] } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_1 mux_left_track_13 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_19 mux_top_track_34 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[3] } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_2 mux_left_track_15 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_20 mux_top_track_36 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[2] } ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_3 mux_left_track_17 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_38 ( - .in ( { top_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_4 mux_left_track_19 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_0 mux_left_track_11 ( - .in ( { chany_top_in[15] , left_top_grid_pin_43_[0] } ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_5 mux_left_track_25 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_1 mux_left_track_13 ( - .in ( { chany_top_in[14] , left_top_grid_pin_44_[0] } ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_6 mux_left_track_27 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_2 mux_left_track_15 ( - .in ( { chany_top_in[13] , left_top_grid_pin_45_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( { ropt_net_108 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_7 mux_left_track_29 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_3 mux_left_track_17 ( - .in ( { chany_top_in[12] , left_top_grid_pin_46_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( { ropt_net_103 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_8 mux_left_track_31 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_4 mux_left_track_19 ( - .in ( { chany_top_in[11] , left_top_grid_pin_47_[0] } ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_9 mux_left_track_33 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_5 mux_left_track_21 ( - .in ( { chany_top_in[10] , left_top_grid_pin_48_[0] } ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size2_10 mux_left_track_35 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_6 mux_left_track_23 ( - .in ( { chany_top_in[9] , left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_7 mux_left_track_27 ( - .in ( { chany_top_in[7] , left_top_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_top_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_top_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_top_track_16 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_18 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_20 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_top_track_26 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_top_track_28 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , +mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_top_track_30 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_32 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_top_track_34 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_top_track_36 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , +mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_left_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , +mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( { ropt_net_105 } ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_left_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size4_0 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_1 mux_left_track_3 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_2 mux_left_track_5 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size4 mux_left_track_7 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_left_track_27 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( { ropt_net_88 } ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2364 ( .VNB ( VSS ) , +mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1366 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2365 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1367 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2366 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1368 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2367 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1369 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2368 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1370 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2369 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1371 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2370 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1372 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2371 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1373 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2372 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1374 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2373 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1375 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2374 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1376 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2375 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1377 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2376 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1378 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2377 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1379 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2378 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1380 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2379 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1381 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_676 ( .A ( ropt_net_91 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_118 ) , .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_678 ( .A ( ropt_net_93 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_679 ( .A ( ropt_net_94 ) , +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_119 ) , .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_95 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_84 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_63 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_85 ) , +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_103 ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_left_in[4] ) , + .X ( BUF_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_left_in[5] ) , + .X ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_66 ( .A ( BUF_net_56 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_84 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( BUF_net_57 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_86 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_67 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_672 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_88 ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_89 ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_90 ) , - .X ( ropt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_123 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_125 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( @@ -2552,14 +2267,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( @@ -2586,111 +2301,127 @@ sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2698,35 +2429,37 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2734,159 +2467,169 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x87400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2894,68 +2637,74 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( @@ -2964,41 +2713,33 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3006,33 +2747,39 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3042,21 +2789,33 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3066,71 +2825,79 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x96600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x59800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3140,57 +2907,57 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x78200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3198,166 +2965,182 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x92000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x64400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x87400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( @@ -3372,188 +3155,156 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( @@ -3570,14 +3321,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v index 8bab6a6..d0a9d2b 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v @@ -4,330 +4,191 @@ // // // -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , - .X ( net_net_49 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_49 ( .A ( net_net_49 ) , - .X ( net_net_48 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( net_net_48 ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +output [0:2] mem_out ; +output [0:2] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule @@ -343,7 +204,9 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__35 ( .A ( mem_out[1] ) , + .X ( net_net_71 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( net_net_71 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -360,7 +223,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -377,12 +240,301 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -402,6 +554,62 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -412,13 +620,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -542,6 +750,26 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -562,46 +790,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -742,86 +930,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -834,41 +942,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -885,7 +959,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -914,54 +988,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -973,6 +999,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -981,14 +1009,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_65 ( .A ( BUF_net_41 ) , - .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1002,7 +1026,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1021,50 +1045,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1128,71 +1114,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1206,7 +1128,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1225,50 +1147,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1318,8 +1202,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1337,106 +1219,37 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , top_right_grid_pin_1_ , chanx_left_in , - left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , - left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , - left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , - ccff_head , chany_top_out , chanx_left_out , ccff_tail ) ; +module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , + chany_top_out , chanx_left_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:0] top_right_grid_pin_1_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chanx_left_out ; @@ -1466,10 +1279,6 @@ wire [0:1] mux_tree_tapbuf_size2_19_sram ; wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; @@ -1496,9 +1305,7 @@ wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; @@ -1511,69 +1318,50 @@ wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; // -mux_tree_tapbuf_size6_2 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , +mux_tree_tapbuf_size6_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_109 } ) , + .p0 ( optlc_net_100 ) ) ; mux_tree_tapbuf_size6 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size6_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size6_1 mux_left_track_5 ( - .in ( { chany_top_in[18] , left_top_grid_pin_42_[0] , - left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , - left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , @@ -1583,45 +1371,21 @@ mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_2 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , +mux_tree_tapbuf_size5_0 mux_top_track_2 ( + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_80 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; mux_tree_tapbuf_size5 mux_top_track_6 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size5_0 mux_left_track_3 ( - .in ( { chany_top_in[19] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_1 mux_left_track_7 ( - .in ( { chany_top_in[17] , left_top_grid_pin_43_[0] , - left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , - left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , @@ -1631,321 +1395,342 @@ mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; mux_tree_tapbuf_size3 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( { ropt_net_89 } ) , - .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size3_2 mux_top_track_24 ( - .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size3_0 mux_top_track_24 ( + .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size3_1 mux_left_track_9 ( - .in ( { chany_top_in[16] , left_top_grid_pin_42_[0] , - left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_0 mux_left_track_25 ( - .in ( { chany_top_in[8] , left_top_grid_pin_42_[0] , - left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_81 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_100 ) ) ; mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_8 mux_top_track_10 ( - .in ( { top_left_grid_pin_35_[0] , chanx_left_in[15] } ) , +mux_tree_tapbuf_size2_12 mux_top_track_10 ( + .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size2_9 mux_top_track_12 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[14] } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_81 ) ) ; -mux_tree_tapbuf_size2_10 mux_top_track_14 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[13] } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_11 mux_top_track_16 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[12] } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_15 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_12 mux_top_track_18 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_16 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_20 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[10] } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_17 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_22 ( - .in ( { top_left_grid_pin_41_[0] , chanx_left_in[9] } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_18 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_15 mux_top_track_26 ( - .in ( { top_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_26 ( + .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_16 mux_top_track_28 ( - .in ( { top_left_grid_pin_36_[0] , chanx_left_in[6] } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_11 mux_left_track_9 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_17 mux_top_track_30 ( - .in ( { top_left_grid_pin_37_[0] , chanx_left_in[5] } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_0 mux_left_track_11 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chany_top_out[15] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_32 ( - .in ( { top_left_grid_pin_38_[0] , chanx_left_in[4] } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size2_1 mux_left_track_13 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_19 mux_top_track_34 ( - .in ( { top_left_grid_pin_39_[0] , chanx_left_in[3] } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_2 mux_left_track_15 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chany_top_out[17] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_20 mux_top_track_36 ( - .in ( { top_left_grid_pin_40_[0] , chanx_left_in[2] } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_3 mux_left_track_17 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_38 ( - .in ( { top_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size2_4 mux_left_track_19 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_79 ) ) ; -mux_tree_tapbuf_size2_0 mux_left_track_11 ( - .in ( { chany_top_in[15] , left_top_grid_pin_43_[0] } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_5 mux_left_track_25 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_1 mux_left_track_13 ( - .in ( { chany_top_in[14] , left_top_grid_pin_44_[0] } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_6 mux_left_track_27 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_2 mux_left_track_15 ( - .in ( { chany_top_in[13] , left_top_grid_pin_45_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( { ropt_net_108 } ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_7 mux_left_track_29 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_3 mux_left_track_17 ( - .in ( { chany_top_in[12] , left_top_grid_pin_46_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( { ropt_net_103 } ) , + .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_8 mux_left_track_31 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_4 mux_left_track_19 ( - .in ( { chany_top_in[11] , left_top_grid_pin_47_[0] } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_99 ) ) ; +mux_tree_tapbuf_size2_9 mux_left_track_33 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_5 mux_left_track_21 ( - .in ( { chany_top_in[10] , left_top_grid_pin_48_[0] } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size2_10 mux_left_track_35 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_6 mux_left_track_23 ( - .in ( { chany_top_in[9] , left_top_grid_pin_49_[0] } ) , - .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_7 mux_left_track_27 ( - .in ( { chany_top_in[7] , left_top_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_80 ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_top_track_12 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_top_track_14 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_top_track_16 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_18 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_20 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_22 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_top_track_26 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_top_track_28 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , +mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_top_track_30 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_32 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_top_track_34 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_top_track_36 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , +mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_left_track_21 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , +mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( { ropt_net_105 } ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_left_track_23 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_left_track_27 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( { ropt_net_88 } ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_676 ( .A ( ropt_net_91 ) , +mux_tree_tapbuf_size4_0 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_1 mux_left_track_3 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_2 mux_left_track_5 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_102 ) ) ; +mux_tree_tapbuf_size4 mux_left_track_7 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_101 ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_118 ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_92 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_79 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_678 ( .A ( ropt_net_93 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_679 ( .A ( ropt_net_94 ) , +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_119 ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_95 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_93 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_84 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_63 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_85 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_85 ) , +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_103 ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_left_in[4] ) , + .X ( BUF_net_56 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_left_in[5] ) , + .X ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_66 ( .A ( BUF_net_56 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_84 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( BUF_net_57 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_86 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_67 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_672 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_88 ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_89 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_90 ) , - .X ( ropt_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_123 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_125 ) , + .X ( chanx_left_out[10] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v index cb2208a..2b9876d 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v @@ -4,6 +4,272 @@ // // // +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , + .X ( net_net_91 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_91 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -16,9 +282,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , - .X ( net_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( net_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -35,7 +299,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -52,7 +316,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -69,7 +333,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -86,12 +350,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1 ( const1 ) ; +module const1_26 ( const1 ) ; output [0:0] const1 ; endmodule @@ -107,10 +371,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1 const1_0_ ( +const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -119,6 +381,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -260,7 +524,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -279,7 +543,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -298,7 +562,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -317,7 +581,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -411,6 +675,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -422,8 +688,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -478,7 +742,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -507,6 +771,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -533,8 +799,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_104 ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -552,7 +816,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -571,7 +835,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -590,7 +854,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -738,7 +1002,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -757,7 +1021,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -776,7 +1040,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -795,7 +1059,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -814,7 +1078,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -833,7 +1097,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -852,7 +1116,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -926,8 +1190,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -948,6 +1210,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1202,7 +1466,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1223,7 +1487,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1394,7 +1658,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1415,7 +1679,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1436,7 +1700,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1610,7 +1874,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1631,7 +1895,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1661,8 +1925,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1692,6 +1954,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_61 ) , + .X ( out[0] ) ) ; endmodule @@ -1754,49 +2020,50 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , top_right_grid_pin_1_ , chany_bottom_in , - bottom_right_grid_pin_1_ , bottom_left_grid_pin_34_ , - bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , - bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , - bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , - bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , - left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , - left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , - left_top_grid_pin_49_ , ccff_head , chany_top_out , chany_bottom_out , +module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , + bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , chanx_left_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:0] top_right_grid_pin_1_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chany_bottom_out ; @@ -1815,6 +2082,23 @@ wire [0:3] mux_tree_tapbuf_size14_1_sram ; wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -1829,6 +2113,7 @@ wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; @@ -1886,21 +2171,22 @@ wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; // mux_tree_tapbuf_size10 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_166 } ) , + .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1912,27 +2198,27 @@ mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; mux_tree_tapbuf_size8_1 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size8 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -1949,25 +2235,25 @@ mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; mux_tree_tapbuf_size14 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , - top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , - top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , + top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_40_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -1979,54 +2265,55 @@ mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; mux_tree_tapbuf_size7_5 mux_top_track_16 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size7 mux_top_track_24 ( - .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_38_[0] , chanx_left_in[5] , chanx_left_in[12] , + .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , - left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , - left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , - left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_125 ) ) ; + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( { ropt_net_158 } ) , + .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , - left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -2063,25 +2350,25 @@ mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; mux_tree_tapbuf_size6 mux_top_track_32 ( - .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_39_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , + .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[0] , chanx_left_in[7] , + .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -2098,14 +2385,13 @@ mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; mux_tree_tapbuf_size9 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[2] , chanx_left_in[9] , + .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , @@ -2113,29 +2399,28 @@ mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , - left_top_grid_pin_42_[0] } ) , + left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , - left_top_grid_pin_43_[0] } ) , + left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_129 } ) , - .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , - left_top_grid_pin_44_[0] } ) , + left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , - left_top_grid_pin_45_[0] } ) , + left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -2158,34 +2443,35 @@ mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , - left_top_grid_pin_46_[0] } ) , + left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , - left_top_grid_pin_47_[0] } ) , + left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , - left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , - left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , - left_top_grid_pin_42_[0] } ) , + left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_123 ) ) ; + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( { ropt_net_155 } ) , + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -2207,160 +2493,185 @@ mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( { ropt_net_127 } ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_155 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_156 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_126 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( ropt_net_127 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[1] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_129 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_157 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_top_in[4] ) , +mux_tree_tapbuf_size2_0 mux_left_track_29 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( { ropt_net_156 } ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_1 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_2 mux_left_track_33 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_3 mux_left_track_35 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_4 mux_left_track_37 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2 mux_left_track_39 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( { ropt_net_154 } ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( - .A ( chany_bottom_in[13] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_136 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( left_top_grid_pin_43_[0] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_158 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_140 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_160 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_141 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_142 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_143 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_144 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_162 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_145 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_146 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_151 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_152 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_153 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_164 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_167 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_168 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_170 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_154 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_155 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_156 ) , .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( + .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_158 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_161 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_162 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chany_top_in[16] ) , + .X ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_165 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_168 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_169 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_170 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_179 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_180 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_80 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_89 ) , + .X ( chanx_left_out[13] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v index 1ecb02d..dd4256c 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v @@ -4,6 +4,308 @@ // // // +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , + .X ( net_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_91 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -23,9 +325,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , - .X ( net_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( net_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49,7 +349,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -73,7 +373,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -97,7 +397,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -121,7 +421,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -141,9 +441,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -154,6 +451,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -303,7 +603,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -330,7 +630,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -357,7 +657,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -384,7 +684,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -475,6 +775,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -488,9 +791,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -554,7 +854,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -580,6 +880,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -611,9 +914,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_104 ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -639,7 +939,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -666,7 +966,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -693,7 +993,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -852,7 +1152,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -879,7 +1179,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -906,7 +1206,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -933,7 +1233,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -960,7 +1260,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -987,7 +1287,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1014,7 +1314,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1087,9 +1387,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1114,6 +1411,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -1387,7 +1687,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1417,7 +1717,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1608,7 +1908,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1638,7 +1938,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1668,7 +1968,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1857,7 +2157,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1887,7 +2187,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1915,9 +2215,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1952,6 +2249,11 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_61 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_61 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2017,49 +2319,50 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , top_right_grid_pin_1_ , chany_bottom_in , - bottom_right_grid_pin_1_ , bottom_left_grid_pin_34_ , - bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , - bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , - bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , - bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , - left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , - left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , - left_top_grid_pin_49_ , ccff_head , chany_top_out , chany_bottom_out , +module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , + bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:0] top_right_grid_pin_1_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chany_bottom_out ; @@ -2080,6 +2383,23 @@ wire [0:3] mux_tree_tapbuf_size14_1_sram ; wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -2094,6 +2414,7 @@ wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; @@ -2153,23 +2474,23 @@ supply0 VSS ; // mux_tree_tapbuf_size10 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_166 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -2183,30 +2504,30 @@ mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size8_1 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size8 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -2226,27 +2547,27 @@ mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size14 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , - top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , - top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , + top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_40_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -2260,61 +2581,61 @@ mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size7_5 mux_top_track_16 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size7 mux_top_track_24 ( - .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_38_[0] , chanx_left_in[5] , chanx_left_in[12] , + .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , - left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , - left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , - left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( { ropt_net_158 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , - left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -2358,28 +2679,28 @@ mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size6 mux_top_track_32 ( - .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_39_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , + .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[0] , chanx_left_in[7] , + .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -2399,14 +2720,14 @@ mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size9 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[2] , chanx_left_in[9] , + .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( { ropt_net_130 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , @@ -2415,32 +2736,32 @@ mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , - left_top_grid_pin_42_[0] } ) , + left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , - left_top_grid_pin_43_[0] } ) , + left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_129 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , - left_top_grid_pin_44_[0] } ) , + left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , - left_top_grid_pin_45_[0] } ) , + left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -2467,39 +2788,39 @@ mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , - left_top_grid_pin_46_[0] } ) , + left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , - left_top_grid_pin_47_[0] } ) , + left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , - left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , - left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , - left_top_grid_pin_42_[0] } ) , + left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( { ropt_net_155 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -2525,201 +2846,239 @@ mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( { ropt_net_127 } ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2381 ( .VNB ( VSS ) , +mux_tree_tapbuf_size2_0 mux_left_track_29 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( { ropt_net_156 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_1 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_2 mux_left_track_33 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_3 mux_left_track_35 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_4 mux_left_track_37 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2 mux_left_track_39 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( { ropt_net_154 } ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1383 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2382 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1384 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2383 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1385 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2384 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1386 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2385 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1387 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2386 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1388 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2387 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1389 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2388 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1390 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2389 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1391 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2390 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1392 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2391 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1393 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2392 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1394 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2393 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1395 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2394 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1396 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2395 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1397 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2396 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1398 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2397 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1399 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2398 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1400 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2399 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1401 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_155 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_156 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_126 ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( ropt_net_127 ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[1] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_129 ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_157 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( - .A ( chany_bottom_in[13] ) , .X ( chany_top_out[14] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_136 ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( left_top_grid_pin_43_[0] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_158 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_140 ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_160 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_141 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_142 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_143 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_144 ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_162 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_145 ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_146 ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_151 ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_152 ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_153 ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_164 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_167 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_168 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_170 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_154 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_155 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_156 ) , .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( + .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_158 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_161 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_162 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chany_top_in[16] ) , + .X ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( BUF_net_89 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_173 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_165 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_168 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_169 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_170 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_179 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_180 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_80 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_89 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( @@ -2732,14 +3091,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( @@ -2768,34 +3127,44 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y81600 ( @@ -2808,43 +3177,27 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2856,198 +3209,156 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x87400y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( @@ -3056,93 +3367,93 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x69000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3150,32 +3461,36 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y408000 ( @@ -3186,231 +3501,213 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x138000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x82800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x101200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x92000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x138000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x78200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x96600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3422,34 +3719,20 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y625600 ( @@ -3458,153 +3741,135 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3620,78 +3885,66 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y870400 ( @@ -3700,22 +3953,40 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( @@ -3728,14 +3999,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y952000 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v index 317da6a..35225a7 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v @@ -4,6 +4,230 @@ // // // +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , + .X ( net_net_91 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_91 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -16,9 +240,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , - .X ( net_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( net_net_80 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -35,7 +257,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -52,7 +274,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -69,7 +291,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -86,7 +308,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -102,8 +324,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -112,6 +332,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -225,7 +447,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -244,7 +466,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -263,7 +485,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -282,7 +504,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -355,6 +577,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -366,8 +590,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -415,7 +637,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -437,6 +659,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -463,8 +687,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_104 ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -482,7 +704,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -501,7 +723,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -520,7 +742,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -647,7 +869,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -666,7 +888,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -685,7 +907,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -704,7 +926,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -723,7 +945,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -742,7 +964,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -761,7 +983,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -821,8 +1043,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -843,6 +1063,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1062,7 +1284,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1083,7 +1305,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1240,7 +1462,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1261,7 +1483,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1282,7 +1504,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1435,7 +1657,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1456,7 +1678,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1479,8 +1701,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1510,6 +1730,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_61 ) , + .X ( out[0] ) ) ; endmodule @@ -1565,49 +1789,50 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , - top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , - top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , - top_left_grid_pin_41_ , top_right_grid_pin_1_ , chany_bottom_in , - bottom_right_grid_pin_1_ , bottom_left_grid_pin_34_ , - bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , - bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , - bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , - bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , - left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , - left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , - left_top_grid_pin_49_ , ccff_head , chany_top_out , chany_bottom_out , +module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , + top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , + top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , + top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , + bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , chanx_left_out , ccff_tail ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_34_ ; -input [0:0] top_left_grid_pin_35_ ; -input [0:0] top_left_grid_pin_36_ ; -input [0:0] top_left_grid_pin_37_ ; -input [0:0] top_left_grid_pin_38_ ; -input [0:0] top_left_grid_pin_39_ ; -input [0:0] top_left_grid_pin_40_ ; -input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_left_grid_pin_42_ ; +input [0:0] top_left_grid_pin_43_ ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; input [0:0] top_right_grid_pin_1_ ; input [0:19] chany_bottom_in ; input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_42_ ; -input [0:0] left_top_grid_pin_43_ ; -input [0:0] left_top_grid_pin_44_ ; -input [0:0] left_top_grid_pin_45_ ; -input [0:0] left_top_grid_pin_46_ ; -input [0:0] left_top_grid_pin_47_ ; -input [0:0] left_top_grid_pin_48_ ; -input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_top_out ; output [0:19] chany_bottom_out ; @@ -1626,6 +1851,23 @@ wire [0:3] mux_tree_tapbuf_size14_1_sram ; wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; @@ -1640,6 +1882,7 @@ wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; @@ -1697,21 +1940,22 @@ wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; // mux_tree_tapbuf_size10 mux_top_track_0 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_166 } ) , + .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -1723,27 +1967,27 @@ mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; mux_tree_tapbuf_size8_1 mux_top_track_2 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size8 mux_top_track_8 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -1760,25 +2004,25 @@ mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; mux_tree_tapbuf_size14 mux_top_track_4 ( - .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , - top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , - top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , - top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , + top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , + top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_37_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_40_[0] , bottom_left_grid_pin_41_[0] , + bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , @@ -1790,54 +2034,55 @@ mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; mux_tree_tapbuf_size7_5 mux_top_track_16 ( - .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size7 mux_top_track_24 ( - .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_38_[0] , chanx_left_in[5] , chanx_left_in[12] , + .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , - left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , - left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , - left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , - left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_125 ) ) ; + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( { ropt_net_158 } ) , + .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , - left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , - left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -1874,25 +2119,25 @@ mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; mux_tree_tapbuf_size6 mux_top_track_32 ( - .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_39_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , + .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[0] , chanx_left_in[7] , + .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_150 ) ) ; mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -1909,14 +2154,13 @@ mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; mux_tree_tapbuf_size9 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_34_[0] , - bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , - bottom_left_grid_pin_40_[0] , chanx_left_in[2] , chanx_left_in[9] , + .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_124 ) ) ; + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_151 ) ) ; mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , @@ -1924,29 +2168,28 @@ mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , - left_top_grid_pin_42_[0] } ) , + left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , - left_top_grid_pin_43_[0] } ) , + left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_129 } ) , - .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , - left_top_grid_pin_44_[0] } ) , + left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_122 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , - left_top_grid_pin_45_[0] } ) , + left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -1969,34 +2212,35 @@ mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , - left_top_grid_pin_46_[0] } ) , + left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , - left_top_grid_pin_47_[0] } ) , + left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , - left_top_grid_pin_48_[0] } ) , + left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_125 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , - left_top_grid_pin_49_[0] } ) , + left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_123 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , - left_top_grid_pin_42_[0] } ) , + left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_123 ) ) ; + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( { ropt_net_155 } ) , + .p0 ( optlc_net_149 ) ) ; mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -2018,160 +2262,185 @@ mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( { ropt_net_127 } ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_155 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_156 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_126 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( ropt_net_127 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[1] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_129 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_157 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_top_in[4] ) , +mux_tree_tapbuf_size2_0 mux_left_track_29 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( { ropt_net_156 } ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_1 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_2 mux_left_track_33 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_3 mux_left_track_35 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2_4 mux_left_track_37 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size2 mux_left_track_39 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( { ropt_net_154 } ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( - .A ( chany_bottom_in[13] ) , .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_136 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( left_top_grid_pin_43_[0] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_158 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_140 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_160 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_141 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_142 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_143 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_144 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_162 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_145 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_146 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_151 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_152 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_153 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_164 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_167 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_168 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_170 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_154 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_155 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_156 ) , .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( + .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_158 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_161 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_162 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chany_top_in[16] ) , + .X ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_165 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_168 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_169 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_170 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_179 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_180 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_80 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_89 ) , + .X ( chanx_left_out[13] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v index 6d242d9..3271d55 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16,13 +16,138 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__39 ( .A ( mem_out[1] ) , - .X ( net_net_59 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( net_net_59 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -35,7 +160,111 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( net_net_48 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_48 ( .A ( net_net_48 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -52,7 +281,24 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -69,7 +315,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -86,7 +332,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -103,7 +349,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -120,7 +366,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -137,24 +383,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -171,7 +400,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -188,7 +417,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -205,7 +434,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -222,7 +451,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -239,7 +468,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -256,7 +485,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -273,7 +502,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -290,7 +519,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -307,12 +536,245 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1 ( const1 ) ; +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_23 ( const1 ) ; output [0:0] const1 ; endmodule @@ -327,7 +789,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1 const1_0_ ( +const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -344,7 +806,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -356,13 +818,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -371,7 +833,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -398,7 +860,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -425,7 +887,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -452,7 +914,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -475,7 +937,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -502,7 +964,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -510,17 +972,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -529,7 +987,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -541,33 +999,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -578,12 +1009,35 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + module const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -610,7 +1064,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -637,7 +1091,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -664,7 +1118,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -691,7 +1145,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -718,7 +1172,7 @@ output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -740,158 +1194,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( BUF_net_41 ) , - .X ( out[0] ) ) ; -endmodule - - -module const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -906,7 +1208,45 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -925,12 +1265,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_3 ( const1 ) ; +module const1_7 ( const1 ) ; output [0:0] const1 ; endmodule @@ -948,7 +1288,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_3 const1_0_ ( +const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -969,7 +1309,85 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_2 ( const1 ) ; +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; output [0:0] const1 ; endmodule @@ -987,8 +1405,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_2 const1_0_ ( +const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1003,8 +1423,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_87 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1022,7 +1440,45 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1041,17 +1497,103 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + module const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1133,29 +1675,45 @@ endmodule module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , - bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , - bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , - bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , - bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , - left_top_grid_pin_1_ , ccff_head , chany_bottom_out , chanx_left_out , - ccff_tail ) ; + bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; @@ -1175,8 +1733,20 @@ wire [0:1] mux_tree_tapbuf_size2_16_sram ; wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; @@ -1201,7 +1771,13 @@ wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; @@ -1214,355 +1790,462 @@ wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; // +assign SC_IN_TOP = SC_IN_BOT ; + mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size6 mux_bottom_track_5 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[3] } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_114 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6_2 mux_left_track_1 ( + .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_74 ) ) ; mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( - .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_123 } ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size5 mux_bottom_track_7 ( - .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( + .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_114 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size5_2 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size5 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_78 ) ) ; mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3 mux_bottom_track_9 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , - chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( - .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[6] } ) , +mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( - .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( - .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[8] } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( + .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( - .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[9] } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( - .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[10] } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( - .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( - .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[12] } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( - .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[14] } ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( { ropt_net_83 } ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( - .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_9 mux_bottom_track_31 ( - .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[16] } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( + .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( { ropt_net_120 } ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_10 mux_bottom_track_33 ( - .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[17] } ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_10 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_11 mux_bottom_track_35 ( - .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[18] } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_11 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_12 mux_bottom_track_37 ( - .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[19] } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size2_12 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_13 mux_bottom_track_39 ( - .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[0] } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_13 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_14 mux_left_track_1 ( - .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_14 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_16 mux_left_track_5 ( - .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_81 } ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_15 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2 mux_left_track_9 ( - .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size2_16 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_15 mux_left_track_25 ( - .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_17 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_18 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_19 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_20 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_21 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_22 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , +mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , +mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , +mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_left_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_left_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_128 } ) , +mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_113 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chany_bottom_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( - .A ( chany_bottom_in[16] ) , .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_120 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( - .A ( chany_bottom_in[17] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( chany_bottom_in[8] ) , +mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( { ropt_net_84 } ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size3 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size3_1 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_87 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_92 ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( ropt_net_123 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( - .A ( chany_bottom_in[15] ) , .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_bottom_in[0] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( - .A ( chany_bottom_in[12] ) , .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( - .A ( chany_bottom_in[18] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_128 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_129 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chany_bottom_in[4] ) , - .X ( BUF_net_46 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[9] ) , - .X ( BUF_net_51 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chany_bottom_in[10] ) , - .X ( BUF_net_52 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_136 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chany_bottom_in[13] ) , - .X ( BUF_net_54 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[14] ) , - .X ( BUF_net_55 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_131 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_137 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_93 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_88 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_82 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_94 ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chanx_left_in[18] ) , + .X ( BUF_net_46 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( ropt_net_95 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_60 ( .A ( BUF_net_46 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_75 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_76 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_77 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_78 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_667 ( .A ( ropt_net_81 ) , + .X ( ropt_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( ropt_net_82 ) , + .X ( ropt_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_83 ) , + .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_84 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_46 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_98 ( .A ( BUF_net_51 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_99 ( .A ( BUF_net_52 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_54 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_55 ) , - .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_672 ( .A ( ropt_net_86 ) , + .X ( ropt_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_87 ) , + .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_88 ) , + .X ( ropt_net_93 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( ropt_net_96 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_97 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_98 ) , + .X ( chany_bottom_out[16] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v index f05cd29..e427a0f 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -23,13 +23,152 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__39 ( .A ( mem_out[1] ) , - .X ( net_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( net_net_59 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; @@ -49,7 +188,153 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( net_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_48 ( .A ( net_net_48 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -73,7 +358,31 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -97,7 +406,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -121,7 +430,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -145,7 +454,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -169,7 +478,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -193,31 +502,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -241,7 +526,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -265,7 +550,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -289,7 +574,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -313,7 +598,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -337,7 +622,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -361,7 +646,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -385,7 +670,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -409,7 +694,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -433,12 +718,62 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -465,7 +800,116 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -518,7 +962,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -545,6 +989,33 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -583,15 +1054,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -633,45 +1108,15 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -711,19 +1156,15 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -763,19 +1204,15 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -909,56 +1346,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; @@ -968,56 +1357,18 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( BUF_net_41 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1043,7 +1394,61 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1070,7 +1475,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1115,6 +1520,86 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; @@ -1132,6 +1617,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1149,9 +1637,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_87 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -1177,7 +1662,61 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1204,7 +1743,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1253,6 +1792,94 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; @@ -1298,29 +1925,45 @@ endmodule module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , - bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , - bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , - bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , - bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , - left_top_grid_pin_1_ , ccff_head , chany_bottom_out , chanx_left_out , - ccff_tail , VDD , VSS ) ; + bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; input VDD ; input VSS ; @@ -1342,8 +1985,20 @@ wire [0:1] mux_tree_tapbuf_size2_16_sram ; wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; @@ -1368,7 +2023,13 @@ wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; @@ -1381,427 +2042,564 @@ wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; supply1 VDD ; supply0 VSS ; // +assign SC_IN_TOP = SC_IN_BOT ; + mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size6 mux_bottom_track_5 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[3] } ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6_2 mux_left_track_1 ( + .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_74 ) ) ; mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( - .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_123 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size5 mux_bottom_track_7 ( - .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( + .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size5_2 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size5 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3 mux_bottom_track_9 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , - chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( { ropt_net_130 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , +mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( - .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[6] } ) , +mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( - .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( - .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[8] } ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( + .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( - .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[9] } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( - .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[10] } ) , + .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( - .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( - .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[12] } ) , + .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( - .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[14] } ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( { ropt_net_83 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( - .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_9 mux_bottom_track_31 ( - .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[16] } ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( + .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( { ropt_net_120 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_10 mux_bottom_track_33 ( - .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[17] } ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_10 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_11 mux_bottom_track_35 ( - .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[18] } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_11 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_12 mux_bottom_track_37 ( - .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[19] } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size2_12 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_13 mux_bottom_track_39 ( - .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[0] } ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_13 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_14 mux_left_track_1 ( - .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] } ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_14 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_16 mux_left_track_5 ( - .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_81 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_15 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2 mux_left_track_9 ( - .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size2_16 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_15 mux_left_track_25 ( - .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] } ) , + .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_17 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_18 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_19 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_20 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_21 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_22 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , + .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , +mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , +mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , +mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_left_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_left_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_128 } ) , +mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2401 ( .VNB ( VSS ) , +mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( { ropt_net_84 } ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size3 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size3_1 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1403 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2402 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1404 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2403 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1405 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2404 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1406 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2405 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1407 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2406 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1408 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2407 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1409 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2408 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1410 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2409 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1411 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2410 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1412 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2411 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1413 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2412 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1414 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2413 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1415 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2414 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1416 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2415 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1417 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2416 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1418 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chany_bottom_in[2] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( - .A ( chany_bottom_in[16] ) , .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_120 ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( - .A ( chany_bottom_in[17] ) , .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_92 ) , .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( ropt_net_123 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( - .A ( chany_bottom_in[15] ) , .X ( ropt_net_135 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_bottom_in[0] ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( - .A ( chany_bottom_in[12] ) , .X ( ropt_net_134 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( - .A ( chany_bottom_in[18] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_128 ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_129 ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chany_bottom_in[4] ) , - .X ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[9] ) , - .X ( BUF_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chany_bottom_in[10] ) , - .X ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_136 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chany_bottom_in[13] ) , - .X ( BUF_net_54 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[14] ) , - .X ( BUF_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_131 ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_137 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_93 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_94 ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chanx_left_in[18] ) , + .X ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( ropt_net_95 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_60 ( .A ( BUF_net_46 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_667 ( .A ( ropt_net_81 ) , + .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( ropt_net_82 ) , + .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_83 ) , + .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_84 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_672 ( .A ( ropt_net_86 ) , + .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_87 ) , + .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_88 ) , + .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( ropt_net_96 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_97 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_98 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( @@ -1814,36 +2612,24 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_46 ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_98 ( .A ( BUF_net_51 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_99 ( .A ( BUF_net_52 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_54 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_55 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( @@ -1860,154 +2646,116 @@ sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( @@ -2018,113 +2766,89 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2132,775 +2856,699 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x82800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x87400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x87400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x55200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x55200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x82800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x87400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x55200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x138000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2926,14 +3574,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v index df453dd..7aac881 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16,13 +16,117 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__39 ( .A ( mem_out[1] ) , - .X ( net_net_59 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( net_net_59 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; @@ -35,7 +139,111 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( net_net_48 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_48 ( .A ( net_net_48 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -52,7 +260,24 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -69,7 +294,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -86,7 +311,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -103,7 +328,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -120,7 +345,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -137,24 +362,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -171,7 +379,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -188,7 +396,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -205,7 +413,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -222,7 +430,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -239,7 +447,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -256,7 +464,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -273,7 +481,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -290,7 +498,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -307,12 +515,29 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -332,7 +557,107 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -372,7 +697,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -392,6 +717,26 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -420,11 +765,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -456,35 +805,11 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -516,15 +841,11 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -556,15 +877,11 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -668,42 +985,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; @@ -711,44 +994,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( BUF_net_41 ) , - .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -766,7 +1019,45 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -785,7 +1076,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -822,6 +1113,70 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; @@ -835,6 +1190,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -849,8 +1206,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_87 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -868,7 +1223,45 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -887,7 +1280,7 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -928,6 +1321,78 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; @@ -965,29 +1430,45 @@ endmodule module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , - bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , - bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , - bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , - bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , - left_top_grid_pin_1_ , ccff_head , chany_bottom_out , chanx_left_out , - ccff_tail ) ; + bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , + left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_34_ ; -input [0:0] bottom_left_grid_pin_35_ ; -input [0:0] bottom_left_grid_pin_36_ ; -input [0:0] bottom_left_grid_pin_37_ ; -input [0:0] bottom_left_grid_pin_38_ ; -input [0:0] bottom_left_grid_pin_39_ ; -input [0:0] bottom_left_grid_pin_40_ ; -input [0:0] bottom_left_grid_pin_41_ ; +input [0:0] bottom_left_grid_pin_42_ ; +input [0:0] bottom_left_grid_pin_43_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; input [0:19] chanx_left_in ; input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_34_ ; +input [0:0] left_bottom_grid_pin_35_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; input [0:0] ccff_head ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; @@ -1007,8 +1488,20 @@ wire [0:1] mux_tree_tapbuf_size2_16_sram ; wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; @@ -1033,7 +1526,13 @@ wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; @@ -1046,355 +1545,462 @@ wire [0:1] mux_tree_tapbuf_size3_0_sram ; wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; // +assign SC_IN_TOP = SC_IN_BOT ; + mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size6 mux_bottom_track_5 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , - bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , - bottom_left_grid_pin_41_[0] , chanx_left_in[3] } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_114 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6_2 mux_left_track_1 ( + .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size6 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_74 ) ) ; mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( - .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_123 } ) , - .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size5 mux_bottom_track_7 ( - .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , - bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( + .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_114 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size5_2 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size5 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_78 ) ) ; mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3 mux_bottom_track_9 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , - chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( - .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[6] } ) , +mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( - .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( - .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[8] } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( + .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( - .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[9] } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( - .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[10] } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( - .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( - .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[12] } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( - .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[14] } ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( { ropt_net_83 } ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( - .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_9 mux_bottom_track_31 ( - .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[16] } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( + .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( { ropt_net_120 } ) , - .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_10 mux_bottom_track_33 ( - .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[17] } ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_10 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_11 mux_bottom_track_35 ( - .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[18] } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_11 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_112 ) ) ; -mux_tree_tapbuf_size2_12 mux_bottom_track_37 ( - .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[19] } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size2_12 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_115 ) ) ; -mux_tree_tapbuf_size2_13 mux_bottom_track_39 ( - .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[0] } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_13 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_114 ) ) ; -mux_tree_tapbuf_size2_14 mux_left_track_1 ( - .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_14 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_16 mux_left_track_5 ( - .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] } ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_81 } ) , + .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_15 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2 mux_left_track_9 ( - .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size2_16 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_15 mux_left_track_25 ( - .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_17 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_113 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_18 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_19 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_20 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_76 ) ) ; +mux_tree_tapbuf_size2_21 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2_22 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_74 ) ) ; +mux_tree_tapbuf_size2 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_77 ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , +mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , +mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , +mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_left_track_1 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_left_track_5 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , +mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_left_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_128 } ) , +mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_113 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( chany_bottom_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( - .A ( chany_bottom_in[16] ) , .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_120 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( - .A ( chany_bottom_in[17] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( chany_bottom_in[8] ) , +mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( { ropt_net_84 } ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_75 ) ) ; +mux_tree_tapbuf_size3 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size3_1 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_78 ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_87 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_92 ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( ropt_net_123 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( - .A ( chany_bottom_in[15] ) , .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_bottom_in[0] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( - .A ( chany_bottom_in[12] ) , .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( - .A ( chany_bottom_in[18] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_128 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_129 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chany_bottom_in[4] ) , - .X ( BUF_net_46 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[9] ) , - .X ( BUF_net_51 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chany_bottom_in[10] ) , - .X ( BUF_net_52 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( ropt_net_136 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chany_bottom_in[13] ) , - .X ( BUF_net_54 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[14] ) , - .X ( BUF_net_55 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_131 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_137 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_93 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_88 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_82 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_94 ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chanx_left_in[18] ) , + .X ( BUF_net_46 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( ropt_net_95 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_60 ( .A ( BUF_net_46 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_74 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_75 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_76 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_77 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_78 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_667 ( .A ( ropt_net_81 ) , + .X ( ropt_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( ropt_net_82 ) , + .X ( ropt_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_83 ) , + .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_84 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_46 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_98 ( .A ( BUF_net_51 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_99 ( .A ( BUF_net_52 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_54 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_55 ) , - .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_672 ( .A ( ropt_net_86 ) , + .X ( ropt_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_87 ) , + .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_88 ) , + .X ( ropt_net_93 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( ropt_net_96 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_97 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_98 ) , + .X ( chany_bottom_out[16] ) ) ; endmodule